From cfee81c7ce51a8601ddf3af8451ecee2b4cf1711 Mon Sep 17 00:00:00 2001
From: Jamie Smith <smit109@usc.edu>
Date: Sat, 21 Sep 2024 23:13:52 -0700
Subject: [PATCH] Update STM32H7 HAL driver to v1.11.3 (#353)

* Update STM32H5 HAL driver, fix some DMA bugs

* Disable LL driver

* Add scancode ignore rules

* Update STM32H7 HAL driver to v1.11.3

* Fix some license issues
---
 .../TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c   |     6 +
 .../common/greentea_get_network_interface.h   |     2 +
 .../TARGET_STM/TARGET_STM32H7/CMakeLists.txt  |     5 +-
 .../STM32Cube_FW/CMSIS/stm32h723xx.h          |   666 +-
 .../STM32Cube_FW/CMSIS/stm32h725xx.h          |   666 +-
 .../STM32Cube_FW/CMSIS/stm32h730xx.h          |   670 +-
 .../STM32Cube_FW/CMSIS/stm32h730xxq.h         |   670 +-
 .../STM32Cube_FW/CMSIS/stm32h733xx.h          |   670 +-
 .../STM32Cube_FW/CMSIS/stm32h735xx.h          |   670 +-
 .../STM32Cube_FW/CMSIS/stm32h742xx.h          |   843 +-
 .../STM32Cube_FW/CMSIS/stm32h743xx.h          |   845 +-
 .../STM32Cube_FW/CMSIS/stm32h745xg.h          | 27361 ++++++++++++++
 .../STM32Cube_FW/CMSIS/stm32h745xx.h          |   861 +-
 .../STM32Cube_FW/CMSIS/stm32h747xg.h          | 30534 ++++++++++++++++
 .../STM32Cube_FW/CMSIS/stm32h747xx.h          |   889 +-
 .../STM32Cube_FW/CMSIS/stm32h750xx.h          |   849 +-
 .../STM32Cube_FW/CMSIS/stm32h753xx.h          |   849 +-
 .../STM32Cube_FW/CMSIS/stm32h755xx.h          |   865 +-
 .../STM32Cube_FW/CMSIS/stm32h757xx.h          |   889 +-
 .../STM32Cube_FW/CMSIS/stm32h7a3xx.h          |   523 +-
 .../STM32Cube_FW/CMSIS/stm32h7a3xxq.h         |   523 +-
 .../STM32Cube_FW/CMSIS/stm32h7b0xx.h          |   527 +-
 .../STM32Cube_FW/CMSIS/stm32h7b0xxq.h         |   527 +-
 .../STM32Cube_FW/CMSIS/stm32h7b3xx.h          |   527 +-
 .../STM32Cube_FW/CMSIS/stm32h7b3xxq.h         |   527 +-
 .../STM32Cube_FW/CMSIS/stm32h7xx.h            |    87 +-
 .../STM32Cube_FW/CMSIS/system_stm32h7xx.h     |    12 +-
 .../STM32Cube_FW/CMakeLists.txt               |     9 +-
 .../TARGET_STM32H7/STM32Cube_FW/LICENSE.md    |    27 +
 .../Legacy/stm32_hal_legacy.h                 |   742 +-
 .../Legacy/stm32h7xx_hal_eth.c                |  3028 ++
 .../Legacy/stm32h7xx_hal_eth_ex.c             |   556 +
 .../Legacy/stm32h7xx_hal_eth_ex_legacy.h      |   354 +
 .../Legacy/stm32h7xx_hal_eth_legacy.h         |  1682 +
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal.c      |    63 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal.h      |    82 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c  |   144 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h  |    41 +-
 .../stm32h7xx_hal_adc_ex.c                    |   206 +-
 .../stm32h7xx_hal_adc_ex.h                    |    62 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c  |   108 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h  |   164 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c |    51 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.h |    13 +-
 .../stm32h7xx_hal_cordic.c                    |    91 +-
 .../stm32h7xx_hal_cordic.h                    |    29 +-
 .../stm32h7xx_hal_cortex.c                    |    97 +-
 .../stm32h7xx_hal_cortex.h                    |    14 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.c  |    48 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.h  |    67 +-
 .../stm32h7xx_hal_crc_ex.c                    |   101 +-
 .../stm32h7xx_hal_crc_ex.h                    |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c |  1495 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h |    52 +-
 .../stm32h7xx_hal_cryp_ex.c                   |    48 +-
 .../stm32h7xx_hal_cryp_ex.h                   |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c  |   238 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h  |    51 +-
 .../stm32h7xx_hal_dac_ex.c                    |   150 +-
 .../stm32h7xx_hal_dac_ex.h                    |    26 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c |    40 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.h |    19 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h  |    17 +-
 .../stm32h7xx_hal_dfsdm.c                     |    47 +-
 .../stm32h7xx_hal_dfsdm.h                     |    40 +-
 .../stm32h7xx_hal_dfsdm_ex.c                  |    14 +-
 .../stm32h7xx_hal_dfsdm_ex.h                  |    14 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c  |   107 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h  |    20 +-
 .../stm32h7xx_hal_dma2d.c                     |    46 +-
 .../stm32h7xx_hal_dma2d.h                     |    23 +-
 .../stm32h7xx_hal_dma_ex.c                    |    25 +-
 .../stm32h7xx_hal_dma_ex.h                    |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c  |   539 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h  |   304 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c  |   246 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.h  |    71 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c  |  2289 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h  |  1598 +-
 .../stm32h7xx_hal_eth_ex.c                    |   311 +-
 .../stm32h7xx_hal_eth_ex.h                    |   239 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c |    68 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.h |    12 +-
 .../stm32h7xx_hal_fdcan.c                     |   479 +-
 .../stm32h7xx_hal_fdcan.h                     |   351 +-
 .../stm32h7xx_hal_flash.c                     |   119 +-
 .../stm32h7xx_hal_flash.h                     |    13 +-
 .../stm32h7xx_hal_flash_ex.c                  |   282 +-
 .../stm32h7xx_hal_flash_ex.h                  |    86 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.c |   961 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.h |   295 +-
 .../stm32h7xx_hal_gfxmmu.c                    |    25 +-
 .../stm32h7xx_hal_gfxmmu.h                    |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c |    88 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.h |    69 +-
 .../stm32h7xx_hal_gpio_ex.h                   |    19 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c |  1093 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.h |   163 +-
 .../stm32h7xx_hal_hash_ex.c                   |   173 +-
 .../stm32h7xx_hal_hash_ex.h                   |   100 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c  |   939 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h  |    57 +-
 .../stm32h7xx_hal_hrtim.c                     |   195 +-
 .../stm32h7xx_hal_hrtim.h                     |   127 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.c |    26 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.h |    17 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c  |  2099 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h  |   147 +-
 .../stm32h7xx_hal_i2c_ex.c                    |    73 +-
 .../stm32h7xx_hal_i2c_ex.h                    |    45 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.c  |   348 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.h  |    76 +-
 .../stm32h7xx_hal_i2s_ex.c                    |    16 +-
 .../stm32h7xx_hal_i2s_ex.h                    |    14 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c |   137 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h |    26 +-
 .../stm32h7xx_hal_irda_ex.h                   |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c |    33 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c |    23 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h |    16 +-
 .../stm32h7xx_hal_lptim.c                     |   204 +-
 .../stm32h7xx_hal_lptim.h                     |    61 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.c |   130 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.h |   127 +-
 .../stm32h7xx_hal_ltdc_ex.c                   |    45 +-
 .../stm32h7xx_hal_ltdc_ex.h                   |    13 +-
 .../stm32h7xx_hal_mdios.c                     |    45 +-
 .../stm32h7xx_hal_mdios.h                     |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c |    26 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c  |   627 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h  |    59 +-
 .../stm32h7xx_hal_mmc_ex.c                    |    24 +-
 .../stm32h7xx_hal_mmc_ex.h                    |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c |   106 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h |    60 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c  |   293 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h  |    15 +-
 .../stm32h7xx_hal_opamp.c                     |   446 +-
 .../stm32h7xx_hal_opamp.h                     |    20 +-
 .../stm32h7xx_hal_opamp_ex.c                  |    18 +-
 .../stm32h7xx_hal_opamp_ex.h                  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c |   802 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h |   106 +-
 .../stm32h7xx_hal_otfdec.c                    |   174 +-
 .../stm32h7xx_hal_otfdec.h                    |    39 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c  |   319 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h  |    79 +-
 .../stm32h7xx_hal_pcd_ex.c                    |    63 +-
 .../stm32h7xx_hal_pcd_ex.h                    |    17 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.c |   319 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h |   131 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c  |    27 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.h  |    12 +-
 .../stm32h7xx_hal_pwr_ex.c                    |    52 +-
 .../stm32h7xx_hal_pwr_ex.h                    |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c |   275 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.h |    47 +-
 .../stm32h7xx_hal_ramecc.c                    |   207 +-
 .../stm32h7xx_hal_ramecc.h                    |   180 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c  |   684 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h  |    46 +-
 .../stm32h7xx_hal_rcc_ex.c                    |  3335 +-
 .../stm32h7xx_hal_rcc_ex.h                    |   230 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c  |   138 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h  |    18 +-
 .../stm32h7xx_hal_rng_ex.c                    |    42 +-
 .../stm32h7xx_hal_rng_ex.h                    |    50 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.c  |   399 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.h  |   240 +-
 .../stm32h7xx_hal_rtc_ex.c                    |   506 +-
 .../stm32h7xx_hal_rtc_ex.h                    |   503 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c  |    68 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.h  |    16 +-
 .../stm32h7xx_hal_sai_ex.c                    |    15 +-
 .../stm32h7xx_hal_sai_ex.h                    |    15 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c   |   312 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h   |    25 +-
 .../stm32h7xx_hal_sd_ex.c                     |    28 +-
 .../stm32h7xx_hal_sd_ex.h                     |    13 +-
 .../stm32h7xx_hal_sdram.c                     |    74 +-
 .../stm32h7xx_hal_sdram.h                     |    13 +-
 .../stm32h7xx_hal_smartcard.c                 |    85 +-
 .../stm32h7xx_hal_smartcard.h                 |    24 +-
 .../stm32h7xx_hal_smartcard_ex.c              |    23 +-
 .../stm32h7xx_hal_smartcard_ex.h              |    12 +-
 .../stm32h7xx_hal_smbus.c                     |   387 +-
 .../stm32h7xx_hal_smbus.h                     |   194 +-
 .../stm32h7xx_hal_smbus_ex.c                  |   258 +
 .../stm32h7xx_hal_smbus_ex.h                  |   152 +
 .../stm32h7xx_hal_spdifrx.c                   |   242 +-
 .../stm32h7xx_hal_spdifrx.h                   |   156 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c  |  1579 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h  |   210 +-
 .../stm32h7xx_hal_spi_ex.c                    |    18 +-
 .../stm32h7xx_hal_spi_ex.h                    |    48 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c |    78 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h |    15 +-
 .../stm32h7xx_hal_swpmi.c                     |   377 +-
 .../stm32h7xx_hal_swpmi.h                     |    41 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c  |  1374 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h  |   384 +-
 .../stm32h7xx_hal_tim_ex.c                    |   684 +-
 .../stm32h7xx_hal_tim_ex.h                    |   227 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c |   643 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h |    85 +-
 .../stm32h7xx_hal_uart_ex.c                   |   115 +-
 .../stm32h7xx_hal_uart_ex.h                   |    14 +-
 .../stm32h7xx_hal_usart.c                     |   190 +-
 .../stm32h7xx_hal_usart.h                     |    33 +-
 .../stm32h7xx_hal_usart_ex.c                  |    23 +-
 .../stm32h7xx_hal_usart_ex.h                  |    14 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c |    26 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h |    15 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c   |    75 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h   |   311 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.c  |   111 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h  |   202 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_bus.h   |   193 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h  |   104 +-
 .../stm32h7xx_ll_cordic.c                     |    15 +-
 .../stm32h7xx_ll_cordic.h                     |    55 +-
 .../stm32h7xx_ll_cortex.h                     |    18 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.c   |    20 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.h   |    37 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.c   |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h   |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c   |   102 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h   |    95 +-
 .../stm32h7xx_ll_delayblock.c                 |    36 +-
 .../stm32h7xx_ll_delayblock.h                 |    27 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.c   |   152 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.h   |   208 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c |    14 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h |    13 +-
 .../stm32h7xx_ll_dmamux.h                     |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.h  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.c  |    57 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.h  |   292 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c   |    37 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h   |    17 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.c  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.c |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h |   295 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_hsem.h  |    18 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.c   |    21 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h   |   373 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h  |    13 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c |    30 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h |   146 +-
 .../stm32h7xx_ll_lpuart.c                     |    23 +-
 .../stm32h7xx_ll_lpuart.h                     |   275 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.c  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h  |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.c |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h |    15 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.c   |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h   |    12 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c   |   110 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h   |   282 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c   |    39 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h   |    89 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.c   |    50 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.h   |   335 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c |    55 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h |    89 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c   |   455 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h   |   389 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.c |    22 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.h |    13 +-
 .../stm32h7xx_ll_system.h                     |    28 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.c   |   188 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h   |   838 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c |    34 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h |   359 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c   |   653 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h   |   309 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c |    40 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.h |    24 +-
 .../STM32H7xx_HAL_Driver/stm32h7xx_ll_wwdg.h  |    13 +-
 .../STM32Cube_FW/stm32h7xx_hal_conf.h         |    10 +-
 .../system_init_files/CMakeLists.txt          |    15 +
 .../system_stm32h7xx_dualcore_boot_cm4_cm7.c  |    82 +-
 .../system_stm32h7xx_singlecore.c             |    49 +-
 targets/TARGET_STM/stm_spi_api.c              |     8 -
 targets/targets.json5                         |     3 +-
 targets/upload_method_cfg/NUCLEO_H723ZG.cmake |     2 +-
 291 files changed, 98955 insertions(+), 25719 deletions(-)
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xg.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xg.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/LICENSE.md
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth.c
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex.c
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex_legacy.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_legacy.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.c
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.h
 create mode 100644 targets/TARGET_STM/TARGET_STM32H7/system_init_files/CMakeLists.txt
 rename targets/TARGET_STM/TARGET_STM32H7/{STM32Cube_FW => system_init_files}/system_stm32h7xx_dualcore_boot_cm4_cm7.c (80%)
 rename targets/TARGET_STM/TARGET_STM32H7/{STM32Cube_FW => system_init_files}/system_stm32h7xx_singlecore.c (88%)

diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c
index 0690d7bf67..b0fc334712 100644
--- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c
+++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_NUCLEO_H723ZG/stm32h7_eth_init.c
@@ -1,6 +1,8 @@
 /* mbed Microcontroller Library
  * Copyright (c) 2018, STMicroelectronics
  * All rights reserved.
+ * 
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -160,4 +162,8 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
     }
 }
 
+// Blank, non-weak-override function to make sure the linker pulls in this file
+void stm32_eth_init_weak_symbol_helper()
+{}
+
 #endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */
diff --git a/connectivity/netsocket/tests/TESTS/common/greentea_get_network_interface.h b/connectivity/netsocket/tests/TESTS/common/greentea_get_network_interface.h
index 9aa166e3d7..9910640ea4 100644
--- a/connectivity/netsocket/tests/TESTS/common/greentea_get_network_interface.h
+++ b/connectivity/netsocket/tests/TESTS/common/greentea_get_network_interface.h
@@ -28,6 +28,7 @@
 #error [NOT_SUPPORTED] No network configuration found for this target.
 #endif
 
+#if MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == WIFI
 /*
  * Read the MBED_GREENTEA_WIFI_SECURE_PROTOCOL define from CMake and get the type of wifi
  * security in use
@@ -58,6 +59,7 @@ inline WiFiInterface *get_wifi_interface()
 
     return wifi_interface;
 }
+#endif
 
 /*
  * Get the default network interface for this board.
diff --git a/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt
index 74f95d48d1..4a62501b9e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt
+++ b/targets/TARGET_STM/TARGET_STM32H7/CMakeLists.txt
@@ -44,5 +44,6 @@ elseif("STM32H7_280MHZ" IN_LIST MBED_TARGET_LABELS)
     target_sources(mbed-stm32h7 INTERFACE clock_cfg/TARGET_STM32H7_280MHZ/system_clock.c)
 endif()
 
-# Add linker scripts
-add_subdirectory(linker_scripts)
\ No newline at end of file
+# Add linker scripts & system init files
+add_subdirectory(linker_scripts)
+add_subdirectory(system_init_files)
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h
index 610abfdc5e..170fa48195 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -212,13 +211,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -248,10 +247,10 @@ typedef struct
   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
-  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
+  __IO uint32_t PCSEL_RES0;       /*!< Reserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
   __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
   __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
-  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
+  __IO uint32_t RES1_TR3;         /*!< Reserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
@@ -928,8 +927,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2700,6 +2699,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2749,6 +2757,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3853,6 +3864,10 @@ typedef struct
 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC3_AWD2CR_AWD2CH_Msk             (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD2CR_AWD2CH                  ADC3_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+
 /********************  Bit definition for ADC_AWD3CR register  ********************/
 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
@@ -3878,6 +3893,10 @@ typedef struct
 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC3_AWD3CR_AWD3CH_Msk             (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD3CR_AWD3CH                  ADC3_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 3 channel selection */
+
 /********************  Bit definition for ADC_DIFSEL register  ********************/
 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
@@ -4120,7 +4139,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6138,10 +6157,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6896,7 +6915,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6915,14 +6934,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7033,7 +7052,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7069,21 +7088,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7102,7 +7121,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7127,7 +7146,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7183,7 +7202,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7219,7 +7238,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7252,7 +7271,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7454,7 +7473,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7478,7 +7497,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7635,7 +7654,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7790,12 +7809,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8293,14 +8312,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8335,10 +8354,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8385,10 +8404,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8411,7 +8430,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8424,7 +8443,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8456,14 +8475,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8503,7 +8522,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8525,7 +8544,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8549,11 +8568,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8562,12 +8581,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8585,12 +8604,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10803,7 +10822,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10813,6 +10832,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10821,12 +10848,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11706,7 +11727,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -14580,7 +14601,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -14614,7 +14635,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -14636,7 +14657,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -14671,7 +14692,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -14693,7 +14714,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -14716,7 +14737,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -14736,7 +14757,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18123,10 +18144,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18187,6 +18208,7 @@ typedef struct
 /*                   Serial Peripheral Interface (SPI/I2S)                    */
 /*                                                                            */
 /******************************************************************************/
+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define SPI_CR1_SPE_Pos             (0U)
 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
@@ -18623,57 +18645,57 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -18691,56 +18713,56 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -18759,58 +18781,58 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -18828,55 +18850,55 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19268,8 +19290,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -19546,8 +19568,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -19571,12 +19593,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -19782,6 +19804,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -19816,8 +19850,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -19835,12 +19869,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20326,9 +20360,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -20342,6 +20373,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -21437,7 +21473,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -21605,7 +21641,7 @@ typedef struct
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (25U)
 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk
 /********************  Bit definition for APB2FZ1 register  ************/
@@ -21876,6 +21912,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -21901,7 +21940,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -21912,13 +21951,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -21988,6 +22035,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -22105,7 +22158,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -23968,6 +24021,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -23980,6 +24034,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24231,4 +24286,3 @@ typedef struct
 
 #endif /* STM32H723xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h725xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h725xx.h
index d4d22d953b..24aeb690f0 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h725xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h725xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -213,13 +212,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -249,10 +248,10 @@ typedef struct
   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
-  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
+  __IO uint32_t PCSEL_RES0;       /*!< Reserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
   __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
   __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
-  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
+  __IO uint32_t RES1_TR3;         /*!< Reserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
@@ -929,8 +928,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2701,6 +2700,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2750,6 +2758,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3854,6 +3865,10 @@ typedef struct
 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC3_AWD2CR_AWD2CH_Msk             (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD2CR_AWD2CH                  ADC3_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+
 /********************  Bit definition for ADC_AWD3CR register  ********************/
 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
@@ -3879,6 +3894,10 @@ typedef struct
 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC3_AWD3CR_AWD3CH_Msk             (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD3CR_AWD3CH                  ADC3_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 3 channel selection */
+
 /********************  Bit definition for ADC_DIFSEL register  ********************/
 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
@@ -4121,7 +4140,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6139,10 +6158,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6897,7 +6916,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6916,14 +6935,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7034,7 +7053,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7070,21 +7089,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7103,7 +7122,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7128,7 +7147,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7184,7 +7203,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7220,7 +7239,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7253,7 +7272,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7455,7 +7474,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7479,7 +7498,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7636,7 +7655,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7791,12 +7810,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8294,14 +8313,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8336,10 +8355,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8386,10 +8405,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8412,7 +8431,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8425,7 +8444,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8457,14 +8476,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8504,7 +8523,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8526,7 +8545,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8550,11 +8569,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8563,12 +8582,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8586,12 +8605,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10804,7 +10823,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10814,6 +10833,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10822,12 +10849,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11707,7 +11728,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -14592,7 +14613,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -14626,7 +14647,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -14648,7 +14669,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -14683,7 +14704,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -14705,7 +14726,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -14728,7 +14749,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -14748,7 +14769,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18135,10 +18156,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18199,6 +18220,7 @@ typedef struct
 /*                   Serial Peripheral Interface (SPI/I2S)                    */
 /*                                                                            */
 /******************************************************************************/
+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define SPI_CR1_SPE_Pos             (0U)
 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
@@ -18635,57 +18657,57 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -18703,56 +18725,56 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -18771,58 +18793,58 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -18840,55 +18862,55 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19280,8 +19302,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -19558,8 +19580,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -19583,12 +19605,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -19794,6 +19816,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -19828,8 +19862,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -19847,12 +19881,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20338,9 +20372,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -20354,6 +20385,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -21449,7 +21485,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -21617,7 +21653,7 @@ typedef struct
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (25U)
 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk
 /********************  Bit definition for APB2FZ1 register  ************/
@@ -21888,6 +21924,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -21913,7 +21952,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -21924,13 +21963,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -22000,6 +22047,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -22117,7 +22170,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -23980,6 +24033,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -23992,6 +24046,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24243,4 +24298,3 @@ typedef struct
 
 #endif /* STM32H725xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xx.h
index 624714f4a9..3785a4cdfc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -215,13 +214,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -251,10 +250,10 @@ typedef struct
   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
-  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
+  __IO uint32_t PCSEL_RES0;       /*!< Reserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
   __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
   __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
-  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
+  __IO uint32_t RES1_TR3;         /*!< Reserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
@@ -931,8 +930,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2835,6 +2834,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2884,6 +2892,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3988,6 +3999,10 @@ typedef struct
 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC3_AWD2CR_AWD2CH_Msk             (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD2CR_AWD2CH                  ADC3_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+
 /********************  Bit definition for ADC_AWD3CR register  ********************/
 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
@@ -4013,6 +4028,10 @@ typedef struct
 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC3_AWD3CR_AWD3CH_Msk             (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD3CR_AWD3CH                  ADC3_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 3 channel selection */
+
 /********************  Bit definition for ADC_DIFSEL register  ********************/
 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
@@ -4255,7 +4274,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6033,7 +6052,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -6084,7 +6103,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6392,10 +6411,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -7150,7 +7169,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -7169,14 +7188,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7287,7 +7306,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7323,21 +7342,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7356,7 +7375,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7381,7 +7400,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7437,7 +7456,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7473,7 +7492,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7506,7 +7525,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7708,7 +7727,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7732,7 +7751,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7889,7 +7908,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -8044,12 +8063,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8547,14 +8566,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8589,10 +8608,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8639,10 +8658,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8665,7 +8684,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8678,7 +8697,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8710,14 +8729,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8757,7 +8776,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8779,7 +8798,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8803,11 +8822,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8816,12 +8835,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8839,12 +8858,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -11057,7 +11076,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -11067,6 +11086,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -11075,12 +11102,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11960,7 +11981,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -15031,7 +15052,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -15065,7 +15086,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -15087,7 +15108,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -15122,7 +15143,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -15144,7 +15165,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -15167,7 +15188,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -15187,7 +15208,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18610,10 +18631,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18674,6 +18695,7 @@ typedef struct
 /*                   Serial Peripheral Interface (SPI/I2S)                    */
 /*                                                                            */
 /******************************************************************************/
+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define SPI_CR1_SPE_Pos             (0U)
 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
@@ -19110,57 +19132,57 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19178,56 +19200,56 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19246,58 +19268,58 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19315,55 +19337,55 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19755,8 +19777,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -20033,8 +20055,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -20058,12 +20080,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20269,6 +20291,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -20303,8 +20337,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20322,12 +20356,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20813,9 +20847,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -20829,6 +20860,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -21924,7 +21960,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -22092,7 +22128,7 @@ typedef struct
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (25U)
 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk
 /********************  Bit definition for APB2FZ1 register  ************/
@@ -22363,6 +22399,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -22388,7 +22427,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -22399,13 +22438,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -22475,6 +22522,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -22592,7 +22645,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -24459,6 +24512,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24471,6 +24525,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24722,4 +24777,3 @@ typedef struct
 
 #endif /* STM32H730xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xxq.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xxq.h
index cac92b30bb..ce80012efa 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xxq.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xxq.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -216,13 +215,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -252,10 +251,10 @@ typedef struct
   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
-  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
+  __IO uint32_t PCSEL_RES0;       /*!< Reserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
   __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
   __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
-  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
+  __IO uint32_t RES1_TR3;         /*!< Reserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
@@ -932,8 +931,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2836,6 +2835,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2885,6 +2893,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3989,6 +4000,10 @@ typedef struct
 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC3_AWD2CR_AWD2CH_Msk             (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD2CR_AWD2CH                  ADC3_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+
 /********************  Bit definition for ADC_AWD3CR register  ********************/
 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
@@ -4014,6 +4029,10 @@ typedef struct
 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC3_AWD3CR_AWD3CH_Msk             (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD3CR_AWD3CH                  ADC3_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 3 channel selection */
+
 /********************  Bit definition for ADC_DIFSEL register  ********************/
 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
@@ -4256,7 +4275,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6034,7 +6053,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -6085,7 +6104,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6393,10 +6412,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -7151,7 +7170,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -7170,14 +7189,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7288,7 +7307,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7324,21 +7343,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7357,7 +7376,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7382,7 +7401,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7438,7 +7457,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7474,7 +7493,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7507,7 +7526,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7709,7 +7728,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7733,7 +7752,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7890,7 +7909,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -8045,12 +8064,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8548,14 +8567,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8590,10 +8609,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8640,10 +8659,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8666,7 +8685,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8679,7 +8698,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8711,14 +8730,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8758,7 +8777,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8780,7 +8799,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8804,11 +8823,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8817,12 +8836,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8840,12 +8859,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -11058,7 +11077,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -11068,6 +11087,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -11076,12 +11103,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11961,7 +11982,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -15043,7 +15064,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -15077,7 +15098,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -15099,7 +15120,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -15134,7 +15155,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -15156,7 +15177,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -15179,7 +15200,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -15199,7 +15220,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18622,10 +18643,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18686,6 +18707,7 @@ typedef struct
 /*                   Serial Peripheral Interface (SPI/I2S)                    */
 /*                                                                            */
 /******************************************************************************/
+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define SPI_CR1_SPE_Pos             (0U)
 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
@@ -19122,57 +19144,57 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19190,56 +19212,56 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19258,58 +19280,58 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19327,55 +19349,55 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19767,8 +19789,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -20045,8 +20067,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -20070,12 +20092,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20281,6 +20303,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -20315,8 +20349,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20334,12 +20368,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20825,9 +20859,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -20841,6 +20872,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -21936,7 +21972,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -22104,7 +22140,7 @@ typedef struct
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (25U)
 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk
 /********************  Bit definition for APB2FZ1 register  ************/
@@ -22375,6 +22411,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -22400,7 +22439,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -22411,13 +22450,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -22487,6 +22534,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -22604,7 +22657,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -24471,6 +24524,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24483,6 +24537,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24734,4 +24789,3 @@ typedef struct
 
 #endif /* STM32H730xxQ_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h733xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h733xx.h
index 39404cbf22..be28e7fcd6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h733xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h733xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -215,13 +214,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -251,10 +250,10 @@ typedef struct
   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
-  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
+  __IO uint32_t PCSEL_RES0;       /*!< Reserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
   __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
   __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
-  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
+  __IO uint32_t RES1_TR3;         /*!< Reserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
@@ -931,8 +930,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2835,6 +2834,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2884,6 +2892,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3988,6 +3999,10 @@ typedef struct
 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC3_AWD2CR_AWD2CH_Msk             (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD2CR_AWD2CH                  ADC3_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+
 /********************  Bit definition for ADC_AWD3CR register  ********************/
 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
@@ -4013,6 +4028,10 @@ typedef struct
 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC3_AWD3CR_AWD3CH_Msk             (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD3CR_AWD3CH                  ADC3_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 3 channel selection */
+
 /********************  Bit definition for ADC_DIFSEL register  ********************/
 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
@@ -4255,7 +4274,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6033,7 +6052,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -6084,7 +6103,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6392,10 +6411,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -7150,7 +7169,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -7169,14 +7188,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7287,7 +7306,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7323,21 +7342,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7356,7 +7375,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7381,7 +7400,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7437,7 +7456,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7473,7 +7492,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7506,7 +7525,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7708,7 +7727,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7732,7 +7751,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7889,7 +7908,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -8044,12 +8063,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8547,14 +8566,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8589,10 +8608,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8639,10 +8658,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8665,7 +8684,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8678,7 +8697,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8710,14 +8729,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8757,7 +8776,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8779,7 +8798,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8803,11 +8822,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8816,12 +8835,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8839,12 +8858,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -11057,7 +11076,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -11067,6 +11086,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -11075,12 +11102,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11960,7 +11981,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -15031,7 +15052,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -15065,7 +15086,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -15087,7 +15108,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -15122,7 +15143,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -15144,7 +15165,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -15167,7 +15188,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -15187,7 +15208,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18610,10 +18631,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18674,6 +18695,7 @@ typedef struct
 /*                   Serial Peripheral Interface (SPI/I2S)                    */
 /*                                                                            */
 /******************************************************************************/
+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define SPI_CR1_SPE_Pos             (0U)
 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
@@ -19110,57 +19132,57 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19178,56 +19200,56 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19246,58 +19268,58 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19315,55 +19337,55 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19755,8 +19777,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -20033,8 +20055,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -20058,12 +20080,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20269,6 +20291,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -20303,8 +20337,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20322,12 +20356,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20813,9 +20847,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -20829,6 +20860,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -21924,7 +21960,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -22092,7 +22128,7 @@ typedef struct
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (25U)
 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk
 /********************  Bit definition for APB2FZ1 register  ************/
@@ -22363,6 +22399,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -22388,7 +22427,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -22399,13 +22438,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -22475,6 +22522,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -22592,7 +22645,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -24459,6 +24512,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24471,6 +24525,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24722,4 +24777,3 @@ typedef struct
 
 #endif /* STM32H733xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h735xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h735xx.h
index e8272e8758..5bab7a1a33 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h735xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h735xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -216,13 +215,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -252,10 +251,10 @@ typedef struct
   __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
   __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
   __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
-  __IO uint32_t PCSEL_RES0;       /*!< Rserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
+  __IO uint32_t PCSEL_RES0;       /*!< Reserved for ADC3, ADC1/2 pre-channel selection,             Address offset: 0x1C */
   __IO uint32_t LTR1_TR1;         /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
   __IO uint32_t HTR1_TR2;         /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
-  __IO uint32_t RES1_TR3;         /*!< Rserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
+  __IO uint32_t RES1_TR3;         /*!< Reserved for ADC1/2, ADC3 threshold register,                Address offset: 0x28 */
   uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
   __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
   __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
@@ -932,8 +931,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2836,6 +2835,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2885,6 +2893,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3989,6 +4000,10 @@ typedef struct
 #define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC3_AWD2CR_AWD2CH_Msk             (0x7FFFFUL << ADC3_AWD2CR_AWD2CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD2CR_AWD2CH                  ADC3_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+
 /********************  Bit definition for ADC_AWD3CR register  ********************/
 #define ADC_AWD3CR_AWD3CH_Pos             (0U)
 #define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
@@ -4014,6 +4029,10 @@ typedef struct
 #define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
 #define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
 
+#define ADC3_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC3_AWD3CR_AWD3CH_Msk             (0x7FFFFUL << ADC3_AWD3CR_AWD3CH_Pos)  /*!< 0x0007FFFF */
+#define ADC3_AWD3CR_AWD3CH                  ADC3_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 3 channel selection */
+
 /********************  Bit definition for ADC_DIFSEL register  ********************/
 #define ADC_DIFSEL_DIFSEL_Pos             (0U)
 #define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
@@ -4256,7 +4275,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6034,7 +6053,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -6085,7 +6104,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6393,10 +6412,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -7151,7 +7170,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -7170,14 +7189,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7288,7 +7307,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7324,21 +7343,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7357,7 +7376,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7382,7 +7401,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7438,7 +7457,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7474,7 +7493,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7507,7 +7526,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7709,7 +7728,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7733,7 +7752,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7890,7 +7909,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -8045,12 +8064,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8548,14 +8567,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8590,10 +8609,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8640,10 +8659,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8666,7 +8685,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8679,7 +8698,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8711,14 +8730,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8758,7 +8777,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8780,7 +8799,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8804,11 +8823,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8817,12 +8836,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8840,12 +8859,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -11058,7 +11077,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -11068,6 +11087,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -11076,12 +11103,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11961,7 +11982,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -15043,7 +15064,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -15077,7 +15098,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -15099,7 +15120,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -15134,7 +15155,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -15156,7 +15177,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -15179,7 +15200,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -15199,7 +15220,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18622,10 +18643,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18686,6 +18707,7 @@ typedef struct
 /*                   Serial Peripheral Interface (SPI/I2S)                    */
 /*                                                                            */
 /******************************************************************************/
+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */
 /*******************  Bit definition for SPI_CR1 register  ********************/
 #define SPI_CR1_SPE_Pos             (0U)
 #define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
@@ -19122,57 +19144,57 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19190,56 +19212,56 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19258,58 +19280,58 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19327,55 +19349,55 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19767,8 +19789,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -20045,8 +20067,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -20070,12 +20092,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20281,6 +20303,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -20315,8 +20349,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20334,12 +20368,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20825,9 +20859,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -20841,6 +20872,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -21936,7 +21972,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -22104,7 +22140,7 @@ typedef struct
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Pos     (24U)
 #define DBGMCU_APB1HFZ1_DBG_TIM23_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM23_Pos) /*!< 0x01000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM23          DBGMCU_APB1HFZ1_DBG_TIM23_Msk
-#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (24U)
+#define DBGMCU_APB1HFZ1_DBG_TIM24_Pos     (25U)
 #define DBGMCU_APB1HFZ1_DBG_TIM24_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_TIM24_Pos) /*!< 0x02000000 */
 #define DBGMCU_APB1HFZ1_DBG_TIM24          DBGMCU_APB1HFZ1_DBG_TIM24_Msk
 /********************  Bit definition for APB2FZ1 register  ************/
@@ -22375,6 +22411,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -22400,7 +22439,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -22411,13 +22450,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -22487,6 +22534,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -22604,7 +22657,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -24471,6 +24524,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24483,6 +24537,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15)   || \
    ((INSTANCE) == TIM23)   || \
    ((INSTANCE) == TIM24))
@@ -24734,4 +24789,3 @@ typedef struct
 
 #endif /* STM32H735xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h742xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h742xx.h
index 5d67a52dec..de01dee934 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h742xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h742xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -211,13 +210,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -226,7 +225,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -885,8 +883,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1638,7 +1636,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2618,6 +2616,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2667,6 +2674,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3917,7 +3927,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5874,10 +5884,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6632,7 +6642,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6651,14 +6661,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -6769,7 +6779,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -6805,21 +6815,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -6838,7 +6848,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -6863,7 +6873,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -6919,7 +6929,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -6955,7 +6965,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -6988,7 +6998,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7190,7 +7200,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7214,7 +7224,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7371,7 +7381,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7526,12 +7536,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8029,14 +8039,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8071,10 +8081,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8121,10 +8131,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8147,7 +8157,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8160,7 +8170,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8192,14 +8202,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8239,7 +8249,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8261,7 +8271,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8285,11 +8295,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8298,12 +8308,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8321,12 +8331,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10568,7 +10578,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10578,6 +10588,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10586,12 +10604,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11356,7 +11368,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -13926,7 +13938,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -13960,7 +13972,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -13982,7 +13994,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -14017,7 +14029,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -14039,7 +14051,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -14062,7 +14074,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -14082,7 +14094,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -17413,10 +17425,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17862,12 +17874,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -18142,61 +18155,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -18214,60 +18227,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -18286,62 +18299,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -18359,59 +18372,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -18698,8 +18711,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -18976,8 +18989,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -19001,12 +19014,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -19246,8 +19259,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -19265,12 +19278,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -20379,7 +20392,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20646,7 +20659,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -20855,7 +20868,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -21742,6 +21755,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -21782,6 +21796,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -23465,6 +23643,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -23490,7 +23671,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -23501,13 +23682,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -23577,6 +23766,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -23694,7 +23889,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -25293,7 +25488,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -25490,6 +25686,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -25500,6 +25697,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -25730,4 +25928,3 @@ typedef struct
 
 #endif /* STM32H742xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h743xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h743xx.h
index a9e5f4c024..ec21ef97d5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h743xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h743xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -214,13 +213,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -229,7 +228,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -888,8 +886,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1725,7 +1723,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2713,6 +2711,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2762,6 +2769,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4012,7 +4022,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5969,10 +5979,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6727,7 +6737,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6746,14 +6756,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -6864,7 +6874,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -6900,21 +6910,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -6933,7 +6943,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -6958,7 +6968,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7014,7 +7024,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7050,7 +7060,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7083,7 +7093,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7285,7 +7295,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7309,7 +7319,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7466,7 +7476,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7621,12 +7631,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8124,14 +8134,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8166,10 +8176,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8216,10 +8226,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8242,7 +8252,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8255,7 +8265,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8287,14 +8297,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8334,7 +8344,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8356,7 +8366,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8380,11 +8390,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8393,12 +8403,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8416,12 +8426,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10663,7 +10673,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10673,6 +10683,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10681,12 +10699,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11451,7 +11463,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -13198,7 +13210,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -14556,7 +14568,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -14590,7 +14602,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -14612,7 +14624,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -14647,7 +14659,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -14669,7 +14681,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -14692,7 +14704,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -14712,7 +14724,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18061,10 +18073,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18510,12 +18522,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -18790,61 +18803,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -18862,60 +18875,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -18934,62 +18947,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19007,59 +19020,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19346,8 +19359,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -19624,8 +19637,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -19649,12 +19662,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -19894,8 +19907,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -19913,12 +19926,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -21027,7 +21040,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -21294,7 +21307,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -21503,7 +21516,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -22390,6 +22403,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -22430,6 +22444,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -24113,6 +24291,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -24138,7 +24319,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -24149,13 +24330,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -24225,6 +24414,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -24342,7 +24537,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -25943,7 +26138,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -26140,6 +26336,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -26150,6 +26347,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -26380,4 +26578,3 @@ typedef struct
 
 #endif /* STM32H743xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xg.h
new file mode 100644
index 0000000000..fa504d22a9
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xg.h
@@ -0,0 +1,27361 @@
+/**
+  ******************************************************************************
+  * @file    stm32h745xg.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H745xG Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32h745xg
+  * @{
+  */
+
+#ifndef STM32H745xG_H
+#define STM32H745xG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
+  CM7_SEV_IRQn                = 64,     /*!< CM7 Send event interrupt for CM4                                  */
+  CM4_SEV_IRQn                = 65,     /*!< CM4 Send event interrupt for CM7                                  */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */
+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */
+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */
+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */
+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */
+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */
+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */
+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */
+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */
+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */
+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */
+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */
+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
+  HSEM2_IRQn                  = 126,    /*!< HSEM2 global Interrupt                                            */
+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */
+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */
+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */
+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */
+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */
+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */
+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */
+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */
+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */
+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */
+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */
+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */
+  HOLD_CORE_IRQn              = 148,    /*!< Hold core interrupt                                               */
+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+#define DUAL_CORE  /*!< Dual core line feature */
+
+#define SMPS       /*!< Switched mode power supply feature */
+
+
+
+/**
+  * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
+   */
+#ifdef CORE_CM4
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< CM4 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM4 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+
+#include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */
+#else  /* CORE_CM7 */
+#ifdef CORE_CM7
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */
+#else  /* UNKNOWN_CORE */
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM7 */
+#endif /* CORE_CM4 */
+
+/**
+  * @}
+  */
+
+
+
+
+#include "system_stm32h7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+/**
+  * @brief ART
+  */
+
+typedef struct
+{
+  __IO uint32_t  CTR;        /*!< ART accelerator - control register */
+}ART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+
+/**
+  * @brief Consumer Electronics Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
+                                   short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
+  __IO uint32_t  RESERVED4[11]; /*!< Reserved,                               Address offset: 0x08 */
+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
+  __IO uint32_t APB3FZ2;     /*!< Debug MCU APB3FZ2 freeze register,    Address offset: 0x38 */
+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
+  __IO uint32_t APB1LFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x40 */
+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
+  __IO uint32_t APB1HFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x48 */
+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
+  __IO uint32_t APB2FZ2;     /*!< Debug MCU APB2FZ2 freeze register,    Address offset: 0x50 */
+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
+  __IO uint32_t APB4FZ2;     /*!< Debug MCU APB4FZ2 freeze register,    Address offset: 0x58 */
+
+}DBGMCU_TypeDef;
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
+} BDMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} BDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief MDMA Controller
+  */
+typedef struct
+{
+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
+}MDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
+  uint32_t       RESERVED0; /*!< Reserved, 0x6C                                                             */
+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACECR;
+  __IO uint32_t MACPFR;
+  __IO uint32_t MACWTR;
+  __IO uint32_t MACHT0R;
+  __IO uint32_t MACHT1R;
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTR;
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVHTR;
+  uint32_t      RESERVED3;
+  __IO uint32_t MACVIR;
+  __IO uint32_t MACIVIR;
+  uint32_t      RESERVED4[2];
+  __IO uint32_t MACTFCR;
+  uint32_t      RESERVED5[7];
+  __IO uint32_t MACRFCR;
+  uint32_t      RESERVED6[7];
+  __IO uint32_t MACISR;
+  __IO uint32_t MACIER;
+  __IO uint32_t MACRXTXSR;
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;
+  __IO uint32_t MACRWKPFR;
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;
+  __IO uint32_t MACLTCR;
+  __IO uint32_t MACLETR;
+  __IO uint32_t MAC1USTCR;
+  uint32_t      RESERVED9[12];
+  __IO uint32_t MACVR;
+  __IO uint32_t MACDR;
+  uint32_t      RESERVED10;
+  __IO uint32_t MACHWF0R;
+  __IO uint32_t MACHWF1R;
+  __IO uint32_t MACHWF2R;
+  uint32_t      RESERVED11[54];
+  __IO uint32_t MACMDIOAR;
+  __IO uint32_t MACMDIODR;
+  uint32_t      RESERVED12[2];
+  __IO uint32_t MACARPAR;
+  uint32_t      RESERVED13[59];
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+  uint32_t      RESERVED14[248];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+  uint32_t      RESERVED15[14];
+  __IO uint32_t MMCTSCGPR;
+  __IO uint32_t MMCTMCGPR;
+  uint32_t      RESERVED16[5];
+  __IO uint32_t MMCTPCGR;
+  uint32_t      RESERVED17[10];
+  __IO uint32_t MMCRCRCEPR;
+  __IO uint32_t MMCRAEPR;
+  uint32_t      RESERVED18[10];
+  __IO uint32_t MMCRUPGR;
+  uint32_t      RESERVED19[9];
+  __IO uint32_t MMCTLPIMSTR;
+  __IO uint32_t MMCTLPITCR;
+  __IO uint32_t MMCRLPIMSTR;
+  __IO uint32_t MMCRLPITCR;
+  uint32_t      RESERVED20[65];
+  __IO uint32_t MACL3L4C0R;
+  __IO uint32_t MACL4A0R;
+  uint32_t      RESERVED21[2];
+  __IO uint32_t MACL3A0R0R;
+  __IO uint32_t MACL3A1R0R;
+  __IO uint32_t MACL3A2R0R;
+  __IO uint32_t MACL3A3R0R;
+  uint32_t      RESERVED22[4];
+  __IO uint32_t MACL3L4C1R;
+  __IO uint32_t MACL4A1R;
+  uint32_t      RESERVED23[2];
+  __IO uint32_t MACL3A0R1R;
+  __IO uint32_t MACL3A1R1R;
+  __IO uint32_t MACL3A2R1R;
+  __IO uint32_t MACL3A3R1R;
+  uint32_t      RESERVED24[108];
+  __IO uint32_t MACTSCR;
+  __IO uint32_t MACSSIR;
+  __IO uint32_t MACSTSR;
+  __IO uint32_t MACSTNR;
+  __IO uint32_t MACSTSUR;
+  __IO uint32_t MACSTNUR;
+  __IO uint32_t MACTSAR;
+  uint32_t      RESERVED25;
+  __IO uint32_t MACTSSR;
+  uint32_t      RESERVED26[3];
+  __IO uint32_t MACTTSSNR;
+  __IO uint32_t MACTTSSSR;
+  uint32_t      RESERVED27[2];
+  __IO uint32_t MACACR;
+  uint32_t      RESERVED28;
+  __IO uint32_t MACATSNR;
+  __IO uint32_t MACATSSR;
+  __IO uint32_t MACTSIACR;
+  __IO uint32_t MACTSEACR;
+  __IO uint32_t MACTSICNR;
+  __IO uint32_t MACTSECNR;
+  uint32_t      RESERVED29[4];
+  __IO uint32_t MACPPSCR;
+  uint32_t      RESERVED30[3];
+  __IO uint32_t MACPPSTTSR;
+  __IO uint32_t MACPPSTTNR;
+  __IO uint32_t MACPPSIR;
+  __IO uint32_t MACPPSWR;
+  uint32_t      RESERVED31[12];
+  __IO uint32_t MACPOCR;
+  __IO uint32_t MACSPI0R;
+  __IO uint32_t MACSPI1R;
+  __IO uint32_t MACSPI2R;
+  __IO uint32_t MACLMIR;
+  uint32_t      RESERVED32[11];
+  __IO uint32_t MTLOMR;
+  uint32_t      RESERVED33[7];
+  __IO uint32_t MTLISR;
+  uint32_t      RESERVED34[55];
+  __IO uint32_t MTLTQOMR;
+  __IO uint32_t MTLTQUR;
+  __IO uint32_t MTLTQDR;
+  uint32_t      RESERVED35[8];
+  __IO uint32_t MTLQICSR;
+  __IO uint32_t MTLRQOMR;
+  __IO uint32_t MTLRQMPOCR;
+  __IO uint32_t MTLRQDR;
+  uint32_t      RESERVED36[177];
+  __IO uint32_t DMAMR;
+  __IO uint32_t DMASBMR;
+  __IO uint32_t DMAISR;
+  __IO uint32_t DMADSR;
+  uint32_t      RESERVED37[60];
+  __IO uint32_t DMACCR;
+  __IO uint32_t DMACTCR;
+  __IO uint32_t DMACRCR;
+  uint32_t      RESERVED38[2];
+  __IO uint32_t DMACTDLAR;
+  uint32_t      RESERVED39;
+  __IO uint32_t DMACRDLAR;
+  __IO uint32_t DMACTDTPR;
+  uint32_t      RESERVED40;
+  __IO uint32_t DMACRDTPR;
+  __IO uint32_t DMACTDRLR;
+  __IO uint32_t DMACRDRLR;
+  __IO uint32_t DMACIER;
+  __IO uint32_t DMACRIWTR;
+__IO uint32_t DMACSFCSR;
+  uint32_t      RESERVED41;
+  __IO uint32_t DMACCATDR;
+  uint32_t      RESERVED42;
+  __IO uint32_t DMACCARDR;
+  uint32_t      RESERVED43;
+  __IO uint32_t DMACCATBR;
+  uint32_t      RESERVED44;
+  __IO uint32_t DMACCARBR;
+  __IO uint32_t DMACSR;
+uint32_t      RESERVED45[2];
+__IO uint32_t DMACMFCR;
+}ETH_TypeDef;
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
+uint32_t      RESERVED6[5];        /*!< Reserved,                                        0xAC to 0xBC         */
+__IO uint32_t C2IMR1;              /*!< EXTI Interrupt mask register,                    Address offset: 0xC0 */
+__IO uint32_t C2EMR1;              /*!< EXTI Event mask register,                        Address offset: 0xC4 */
+__IO uint32_t C2PR1;               /*!< EXTI Pending register,                           Address offset: 0xC8 */
+uint32_t      RESERVED7;           /*!< Reserved,                                        0xCC                 */
+__IO uint32_t C2IMR2;              /*!< EXTI Interrupt mask register,                    Address offset: 0xD0 */
+__IO uint32_t C2EMR2;              /*!< EXTI Event mask register,                        Address offset: 0xD4 */
+__IO uint32_t C2PR2;               /*!< EXTI Pending register,                           Address offset: 0xD8 */
+uint32_t      RESERVED8;           /*!< Reserved,                                        0xDC                 */
+__IO uint32_t C2IMR3;              /*!< EXTI Interrupt mask register,                    Address offset: 0xE0 */
+__IO uint32_t C2EMR3;              /*!< EXTI Event mask register,                        Address offset: 0xE4 */
+__IO uint32_t C2PR3;               /*!< EXTI Pending register,                           Address offset: 0xE8 */
+
+}EXTI_TypeDef;
+
+/**
+  * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+  *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+  *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
+  *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+  */
+
+typedef struct
+{
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
+}EXTI_Core_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
+  __IO uint32_t BOOT7_CUR;       /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
+  __IO uint32_t BOOT7_PRG;       /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
+  __IO uint32_t BOOT4_CUR;       /*!< Flash Current Boot Address for M4 Core Register,          Address offset: 0x48  */
+  __IO uint32_t BOOT4_PRG;       /*!< Flash Boot Address to Program for M4 Core Register,       Address offset: 0x4C  */
+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */
+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5 and 6
+  */
+
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */
+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */
+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */
+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */
+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */
+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */
+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */
+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */
+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */
+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */
+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */
+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */
+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */
+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */
+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */
+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */
+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */
+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */
+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */
+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */
+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */
+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */
+
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
+  __IO uint32_t CPU2CR;    /*!< PWR CPU2 control register,               Address offset: 0x14 */
+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */
+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */
+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */
+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */
+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */
+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */
+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
+
+} RCC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t RSR;          /*!< RCC Reset status register,                                               Address offset: 0x00 */
+  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clock  register,                            Address offset: 0x04 */
+  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clock  register,                            Address offset: 0x08 */
+  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clock  register,                            Address offset: 0x0C */
+  __IO uint32_t AHB4ENR;      /*!< RCC AHB4 peripheral clock  register,                            Address offset: 0x10 */
+  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clock  register,                            Address offset: 0x14 */
+  __IO uint32_t APB1LENR;     /*!< RCC APB1 peripheral clock  Low Word register,                   Address offset: 0x18 */
+  __IO uint32_t APB1HENR;     /*!< RCC APB1 peripheral clock  High Word register,                  Address offset: 0x1C */
+  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clock  register,                            Address offset: 0x20 */
+  __IO uint32_t APB4ENR;      /*!< RCC APB4 peripheral clock  register,                            Address offset: 0x24 */
+  uint32_t      RESERVED9;    /*!< Reserved,                                                       Address offset: 0x28 */
+  __IO uint32_t AHB3LPENR;    /*!< RCC AHB3 peripheral sleep clock  register,                      Address offset: 0x3C */
+  __IO uint32_t AHB1LPENR;    /*!< RCC AHB1 peripheral sleep clock  register,                      Address offset: 0x40 */
+  __IO uint32_t AHB2LPENR;    /*!< RCC AHB2 peripheral sleep clock  register,                      Address offset: 0x44 */
+  __IO uint32_t AHB4LPENR;    /*!< RCC AHB4 peripheral sleep clock  register,                      Address offset: 0x48 */
+  __IO uint32_t APB3LPENR;    /*!< RCC APB3 peripheral sleep clock  register,                      Address offset: 0x4C */
+  __IO uint32_t APB1LLPENR;   /*!< RCC APB1 peripheral sleep clock  Low Word register,             Address offset: 0x50 */
+  __IO uint32_t APB1HLPENR;   /*!< RCC APB1 peripheral sleep clock  High Word register,            Address offset: 0x54 */
+  __IO uint32_t APB2LPENR;    /*!< RCC APB2 peripheral sleep clock  register,                      Address offset: 0x58 */
+  __IO uint32_t APB4LPENR;    /*!< RCC APB4 peripheral sleep clock  register,                      Address offset: 0x5C */
+  uint32_t     RESERVED10[4]; /*!< Reserved, 0x60-0x6C                                             Address offset: 0x60 */
+
+} RCC_Core_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Delay Block DLYB
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief HW Semaphore HSEM
+  */
+
+typedef struct
+{
+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
+  __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */
+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */
+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */
+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */
+  __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */
+  __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */
+  __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */
+  __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */
+   uint32_t  Reserved[8];   /* Reserved                                         Address offset: 120h-13Ch*/
+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
+
+} HSEM_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
+} HSEM_Common_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+
+} SPI_TypeDef;
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+typedef struct
+{
+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RAM_ECC_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
+} RAMECC_MonitorTypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
+} RAMECC_TypeDef;
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief High resolution Timer (HRTIM)
+  */
+/* HRTIM master registers definition */
+typedef struct
+{
+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interrupt clear register,             Address offset: 0x08 */
+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */
+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM Timer A to E registers definition */
+typedef struct
+{
+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */
+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */
+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */
+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */
+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */
+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */
+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */
+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */
+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */
+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */
+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */
+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */
+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */
+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */
+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM  register definition */
+typedef struct {
+  HRTIM_Master_TypeDef sMasterRegs;
+  HRTIM_Timerx_TypeDef sTimerxRegs[5];
+  uint32_t             RESERVED0[32];
+  HRTIM_Common_TypeDef sCommonRegs;
+}HRTIM_TypeDef;
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+/**
+  * @brief Global Programmer View
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2036];     /*!< Reserved,                                                                           Address offset: 0x00-0x1FCC     */
+  __IO uint32_t AXI_PERIPH_ID_4;     /*!< AXI interconnect - peripheral ID4 register,                                         Address offset: 0x1FD0          */
+  uint32_t      AXI_PERIPH_ID_5;     /*!< Reserved,                                                                           Address offset: 0x1FD4          */
+  uint32_t      AXI_PERIPH_ID_6;     /*!< Reserved,                                                                           Address offset: 0x1FD8          */
+  uint32_t      AXI_PERIPH_ID_7;     /*!< Reserved,                                                                           Address offset: 0x1FDC          */
+  __IO uint32_t AXI_PERIPH_ID_0;     /*!< AXI interconnect - peripheral ID0 register,                                         Address offset: 0x1FE0          */
+  __IO uint32_t AXI_PERIPH_ID_1;     /*!< AXI interconnect - peripheral ID1 register,                                         Address offset: 0x1FE4          */
+  __IO uint32_t AXI_PERIPH_ID_2;     /*!< AXI interconnect - peripheral ID2 register,                                         Address offset: 0x1FE8          */
+  __IO uint32_t AXI_PERIPH_ID_3;     /*!< AXI interconnect - peripheral ID3 register,                                         Address offset: 0x1FEC          */
+  __IO uint32_t AXI_COMP_ID_0;       /*!< AXI interconnect - component ID0 register,                                          Address offset: 0x1FF0          */
+  __IO uint32_t AXI_COMP_ID_1;       /*!< AXI interconnect - component ID1 register,                                          Address offset: 0x1FF4          */
+  __IO uint32_t AXI_COMP_ID_2;       /*!< AXI interconnect - component ID2 register,                                          Address offset: 0x1FF8          */
+  __IO uint32_t AXI_COMP_ID_3;       /*!< AXI interconnect - component ID3 register,                                          Address offset: 0x1FFC          */
+  uint32_t      RESERVED1[2];        /*!< Reserved,                                                                           Address offset: 0x2000-0x2004   */
+  __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register,           Address offset: 0x2008          */
+  uint32_t      RESERVED2[6];        /*!< Reserved,                                                                           Address offset: 0x200C-0x2020   */
+  __IO uint32_t AXI_TARG1_FN_MOD2;   /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register,                      Address offset: 0x2024          */
+  uint32_t      RESERVED3;           /*!< Reserved,                                                                           Address offset: 0x2028          */
+  __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register,           Address offset: 0x202C          */
+  uint32_t      RESERVED4[54];       /*!< Reserved,                                                                           Address offset: 0x2030-0x2104   */
+  __IO uint32_t AXI_TARG1_FN_MOD;    /*!< AXI interconnect - TARG 1 issuing functionality modification register,              Address offset: 0x2108          */
+  uint32_t      RESERVED5[959];      /*!< Reserved,                                                                           Address offset: 0x210C-0x3004   */
+  __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register,           Address offset: 0x3008          */
+  uint32_t      RESERVED6[6];        /*!< Reserved,                                                                           Address offset: 0x300C-0x3020   */
+  __IO uint32_t AXI_TARG2_FN_MOD2;   /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register,                      Address offset: 0x3024          */
+  uint32_t      RESERVED7;           /*!< Reserved,                                                                           Address offset: 0x3028          */
+  __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register,           Address offset: 0x302C          */
+  uint32_t      RESERVED8[54];       /*!< Reserved,                                                                           Address offset: 0x3030-0x3104   */
+  __IO uint32_t AXI_TARG2_FN_MOD;    /*!< AXI interconnect - TARG 2 issuing functionality modification register,              Address offset: 0x3108          */
+  uint32_t      RESERVED9[959];      /*!< Reserved,                                                                           Address offset: 0x310C-0x4004   */
+  __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;   /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register,          Address offset: 0x4008          */
+  uint32_t      RESERVED10[1023];    /*!< Reserved,                                                                           Address offset: 0x400C-0x5004   */
+  __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register,           Address offset: 0x5008          */
+  uint32_t      RESERVED11[1023];    /*!< Reserved,                                                                           Address offset: 0x500C-0x6004   */
+  __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register,           Address offset: 0x6008          */
+  uint32_t      RESERVED12[1023];    /*!< Reserved,                                                                           Address offset: 0x600C-0x7004   */
+  __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register,           Address offset: 0x7008          */
+  uint32_t      RESERVED13[1023];    /*!< Reserved,                                                                           Address offset: 0x700C-0x8004   */
+  __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register,           Address offset: 0x8008          */
+  uint32_t      RESERVED14[6];       /*!< Reserved,                                                                           Address offset: 0x800C-0x8020   */
+  __IO uint32_t AXI_TARG7_FN_MOD2;   /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register,                      Address offset: 0x8024          */
+  uint32_t      RESERVED15;          /*!< Reserved,                                                                           Address offset: 0x8028          */
+  __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register,           Address offset: 0x802C          */
+  uint32_t      RESERVED16[54];      /*!< Reserved,                                                                           Address offset: 0x8030-0x8104   */
+  __IO uint32_t AXI_TARG7_FN_MOD;    /*!< AXI interconnect - TARG 7 issuing functionality modification register,              Address offset: 0x8108          */
+  uint32_t      RESERVED17[59334];    /*!< Reserved,                                                                          Address offset: 0x810C-0x42020  */
+  __IO uint32_t AXI_INI1_FN_MOD2;    /*!< AXI interconnect - INI 1 functionality modification 2 register,                     Address offset: 0x42024         */
+  __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register,                   Address offset: 0x42028         */
+  uint32_t      RESERVED18[53];      /*!< Reserved,                                                                           Address offset: 0x4202C-0x420FC */
+  __IO uint32_t AXI_INI1_READ_QOS;   /*!< AXI interconnect - INI 1 read QoS register,                                         Address offset: 0x42100         */
+  __IO uint32_t AXI_INI1_WRITE_QOS;  /*!< AXI interconnect - INI 1 write QoS register,                                        Address offset: 0x42104         */
+  __IO uint32_t AXI_INI1_FN_MOD;     /*!< AXI interconnect - INI 1 issuing functionality modification register,               Address offset: 0x42108         */
+  uint32_t      RESERVED19[1021];    /*!< Reserved,                                                                           Address offset: 0x4210C-0x430FC */
+  __IO uint32_t AXI_INI2_READ_QOS;   /*!< AXI interconnect - INI 2 read QoS register,                                         Address offset: 0x43100         */
+  __IO uint32_t AXI_INI2_WRITE_QOS;  /*!< AXI interconnect - INI 2 write QoS register,                                        Address offset: 0x43104         */
+  __IO uint32_t AXI_INI2_FN_MOD;     /*!< AXI interconnect - INI 2 issuing functionality modification register,               Address offset: 0x43108         */
+  uint32_t      RESERVED20[966];     /*!< Reserved,                                                                           Address offset: 0x4310C-0x44020 */
+  __IO uint32_t AXI_INI3_FN_MOD2;    /*!< AXI interconnect - INI 3 functionality modification 2 register,                     Address offset: 0x44024         */
+  __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register,                   Address offset: 0x44028         */
+  uint32_t      RESERVED21[53];      /*!< Reserved,                                                                           Address offset: 0x4402C-0x440FC */
+  __IO uint32_t AXI_INI3_READ_QOS;   /*!< AXI interconnect - INI 3 read QoS register,                                         Address offset: 0x44100         */
+  __IO uint32_t AXI_INI3_WRITE_QOS;  /*!< AXI interconnect - INI 3 write QoS register,                                        Address offset: 0x44104         */
+  __IO uint32_t AXI_INI3_FN_MOD;     /*!< AXI interconnect - INI 3 issuing functionality modification register,               Address offset: 0x44108         */
+  uint32_t      RESERVED22[1021];    /*!< Reserved,                                                                           Address offset: 0x4410C-0x450FC */
+  __IO uint32_t AXI_INI4_READ_QOS;   /*!< AXI interconnect - INI 4 read QoS register,                                         Address offset: 0x45100         */
+  __IO uint32_t AXI_INI4_WRITE_QOS;  /*!< AXI interconnect - INI 4 write QoS register,                                        Address offset: 0x45104         */
+  __IO uint32_t AXI_INI4_FN_MOD;     /*!< AXI interconnect - INI 4 issuing functionality modification register,               Address offset: 0x45108         */
+  uint32_t      RESERVED23[1021];    /*!< Reserved,                                                                           Address offset: 0x4510C-0x460FC */
+  __IO uint32_t AXI_INI5_READ_QOS;   /*!< AXI interconnect - INI 5 read QoS register,                                         Address offset: 0x46100         */
+  __IO uint32_t AXI_INI5_WRITE_QOS;  /*!< AXI interconnect - INI 5 write QoS register,                                        Address offset: 0x46104         */
+  __IO uint32_t AXI_INI5_FN_MOD;     /*!< AXI interconnect - INI 5 issuing functionality modification register,               Address offset: 0x46108         */
+  uint32_t      RESERVED24[1021];    /*!< Reserved,                                                                           Address offset: 0x4610C-0x470FC */
+  __IO uint32_t AXI_INI6_READ_QOS;   /*!< AXI interconnect - INI 6 read QoS register,                                         Address offset: 0x47100         */
+  __IO uint32_t AXI_INI6_WRITE_QOS;  /*!< AXI interconnect - INI 6 write QoS register,                                        Address offset: 0x47104         */
+  __IO uint32_t AXI_INI6_FN_MOD;     /*!< AXI interconnect - INI 6 issuing functionality modification register,               Address offset: 0x47108         */
+  uint32_t      RESERVED25[1021];    /*!< Reserved,                                                                           Address offset: 0x4710C-0x480FC */
+  __IO uint32_t AXI_INI7_READ_QOS;   /*!< AXI interconnect - INI 7 read QoS register,                                         Address offset: 0x48100         */
+  __IO uint32_t AXI_INI7_WRITE_QOS;  /*!< AXI interconnect - INI 7 write QoS register,                                        Address offset: 0x48104         */
+  __IO uint32_t AXI_INI7_FN_MOD;     /*!< AXI interconnect - INI 7 issuing functionality modification register,               Address offset: 0x48108         */
+
+} GPV_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */
+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */
+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */
+
+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */
+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */
+
+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */
+
+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */
+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+
+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
+
+/* Legacy define */
+#define FLASH_BASE                FLASH_BANK1_BASE
+
+/*!< Device electronic signature memory map */
+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */
+
+
+/*!< Peripheral memory map */
+#define D2_APB1PERIPH_BASE        PERIPH_BASE
+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
+
+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)
+
+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)
+
+/*!< Legacy Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< D1_AHB1PERIPH peripherals */
+
+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)
+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)
+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)
+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)
+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)
+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)
+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)
+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)
+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)
+
+/*!< D2_AHB1PERIPH peripherals */
+
+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)
+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)
+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)
+#define ART_BASE                (D2_AHB1PERIPH_BASE + 0x4400UL)
+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE            (ETH_BASE)
+
+/*!< USB registers base address */
+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
+
+/*!< D2_AHB2PERIPH peripherals */
+
+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)
+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)
+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)
+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)
+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)
+
+/*!< D3_AHB1PERIPH peripherals */
+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)
+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)
+#define RCC_C1_BASE           (RCC_BASE + 0x130UL)
+#define RCC_C2_BASE           (RCC_BASE + 0x190UL)
+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)
+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)
+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)
+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)
+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)
+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)
+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)
+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)
+
+/*!< D1_APB1PERIPH peripherals */
+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)
+
+/*!< D2_APB1PERIPH peripherals */
+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)
+
+#define WWDG2_BASE            (D2_APB1PERIPH_BASE + 0x2C00UL)
+
+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)
+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)
+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)
+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)
+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)
+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)
+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)
+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)
+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)
+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)
+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)
+
+/*!< D2_APB2PERIPH peripherals */
+
+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)
+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)
+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)
+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)
+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)
+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)
+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
+
+
+/*!< D3_APB1PERIPH peripherals */
+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)
+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)
+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)
+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)
+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)
+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)
+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)
+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)
+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)
+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)
+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)
+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)
+#define COMP2_BASE            (COMP12_BASE + 0x10UL)
+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)
+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)
+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)
+
+#define IWDG2_BASE            (D3_APB1PERIPH_BASE + 0x4C00UL)
+
+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)
+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)
+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)
+
+
+
+
+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)
+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)
+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)
+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)
+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)
+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)
+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)
+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)
+
+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
+
+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
+
+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
+
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
+
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0x5C001000UL)
+
+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
+
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
+
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
+
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+
+
+#define GPV_BASE       (PERIPH_BASE + 0x11000000UL)   /*!<  GPV_BASE       (PERIPH_BASE + 0x11000000UL)                    */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
+
+#define WWDG2               ((WWDG_TypeDef *) WWDG2_BASE)
+#define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)
+
+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define RCC_C1              ((RCC_Core_TypeDef *) RCC_C1_BASE)
+#define RCC_C2              ((RCC_Core_TypeDef *) RCC_C2_BASE)
+
+#define ART                 ((ART_TypeDef *)  ART_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+
+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)
+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
+
+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)
+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
+
+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)
+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
+
+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)
+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
+
+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
+
+
+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
+
+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+
+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
+#if defined(CORE_CM4)
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
+#else  /* CORE_CM7 */
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
+#endif /* CORE_CM4 */
+
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH                 ((ETH_TypeDef *)ETH_BASE)
+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+
+
+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
+
+/* Legacy defines */
+#define USB_OTG_HS                   USB1_OTG_HS
+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
+#define USB_OTG_FS                   USB2_OTG_FS
+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE
+
+#define GPV                ((GPV_TypeDef *) GPV_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  ADC VERSION  ********************************/
+#define ADC_VER_V5_X
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos                 (0U)
+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP_Pos                 (1U)
+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos                   (2U)
+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos                   (3U)
+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos                   (4U)
+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos                  (5U)
+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos                  (6U)
+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos                  (7U)
+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos                  (8U)
+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos                  (9U)
+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos                 (10U)
+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos               (0U)
+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos               (1U)
+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos                 (2U)
+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos                 (3U)
+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos                 (4U)
+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos                (5U)
+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos                (6U)
+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos                (7U)
+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos                (8U)
+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos                (9U)
+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos               (10U)
+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                   (0U)
+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos                  (1U)
+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos                (2U)
+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos               (3U)
+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos                  (4U)
+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos                 (5U)
+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos                  (8U)
+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
+#define ADC_CR_ADCALLIN_Pos               (16U)
+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos            (22U)
+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos            (23U)
+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos            (24U)
+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos            (25U)
+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos            (26U)
+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos            (27U)
+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos               (28U)
+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos                (29U)
+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos               (30U)
+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos                  (31U)
+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMNGT_Pos                (0U)
+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos                  (2U)
+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos               (5U)
+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos                (10U)
+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos               (12U)
+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos                 (13U)
+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos               (14U)
+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos               (16U)
+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos              (17U)
+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos              (20U)
+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos                  (21U)
+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos              (22U)
+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos               (23U)
+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos              (24U)
+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos                (25U)
+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos               (26U)
+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos                (31U)
+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  ********************/
+#define ADC_CFGR2_ROVSE_Pos               (0U)
+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos               (1U)
+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos                (5U)
+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos               (9U)
+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos               (10U)
+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos             (11U)
+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos             (12U)
+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos             (13U)
+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos             (14U)
+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OVSR_Pos                (16U)
+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos              (28U)
+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0_Pos                (0U)
+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos                (3U)
+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos                (6U)
+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos                (9U)
+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos                (12U)
+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos                (15U)
+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos                (18U)
+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos                (21U)
+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos                (24U)
+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos                (27U)
+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10_Pos               (0U)
+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos               (3U)
+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos               (6U)
+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos               (9U)
+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos               (12U)
+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos               (15U)
+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos               (18U)
+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos               (21U)
+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos               (24U)
+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos               (27U)
+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  ********************/
+#define ADC_PCSEL_PCSEL_Pos               (0U)
+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos                    (0U)
+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
+#define ADC_HTR_HT_Pos                    (0U)
+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L_Pos                    (0U)
+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence length */
+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos                  (6U)
+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos                  (12U)
+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos                  (18U)
+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos                  (24U)
+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5_Pos                  (0U)
+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos                  (6U)
+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos                  (12U)
+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos                  (18U)
+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos                  (24U)
+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10_Pos                 (0U)
+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos                 (6U)
+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos                 (12U)
+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos                 (18U)
+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos                 (24U)
+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR4_SQ15_Pos                 (0U)
+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos                 (6U)
+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos                  (0U)
+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL_Pos                   (0U)
+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos              (2U)
+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos               (7U)
+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos                 (9U)
+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos                 (15U)
+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos                 (21U)
+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos                 (27U)
+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1_Pos              (0U)
+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos                (31U)
+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2_Pos              (0U)
+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos                (31U)
+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3_Pos              (0U)
+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos                (31U)
+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4_Pos              (0U)
+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos                (31U)
+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA_Pos                (0U)
+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos                (0U)
+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos                (0U)
+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos                (0U)
+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL_Pos             (0U)
+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S_Pos         (0U)
+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos         (16U)
+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_CALFACT2 register  ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_ADRDY_MST_Pos             (0U)
+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos             (1U)
+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos               (2U)
+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos               (3U)
+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos               (4U)
+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos              (5U)
+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos              (6U)
+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos              (7U)
+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos              (8U)
+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos              (9U)
+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos             (10U)
+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos             (16U)
+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos             (17U)
+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos               (18U)
+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos               (19U)
+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos               (20U)
+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos              (21U)
+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos              (22U)
+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos              (23U)
+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos              (24U)
+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos              (25U)
+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos             (26U)
+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_DUAL_Pos                  (0U)
+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos                 (8U)
+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
+
+
+#define ADC_CCR_DAMDF_Pos                 (14U)
+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos                (16U)
+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos                 (18U)
+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos                (22U)
+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
+#define ADC_CCR_TSEN_Pos                  (23U)
+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos                (24U)
+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos             (0U)
+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos             (16U)
+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos            (0U)
+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        ART accelerator                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for ART_CTR register  ********************/
+#define ART_CTR_EN_Pos              (0U)
+#define ART_CTR_EN_Msk              (0x1UL << ART_CTR_EN_Pos)                /*!< 0x00000001 */
+#define ART_CTR_EN                  ART_CTR_EN_Msk                           /*!< Cache enable*/
+
+#define ART_CTR_PCACHEADDR_Pos      (8U)
+#define ART_CTR_PCACHEADDR_Msk      (0xFFFUL << ART_CTR_PCACHEADDR_Pos)      /*!< 0x000FFF00 */
+#define ART_CTR_PCACHEADDR          ART_CTR_PCACHEADDR_Msk                   /*!< Cacheable page index */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   VREFBUF                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos        (0U)
+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos         (1U)
+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos         (3U)
+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos         (4U)
+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
+
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
+
+/*******************  Bit definition for VREFBUF_CCR register  ****************/
+#define VREFBUF_CCR_TRIM_Pos        (0U)
+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x000000FF */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos         (1U)
+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos         (2U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (3U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (4U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos         (5U)
+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos         (6U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (7U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (8U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (9U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (10U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (11U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (12U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos         (13U)
+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos         (14U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (15U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (16U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (17U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (18U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos          (19U)
+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos          (22U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (23U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (24U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (25U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (26U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (27U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (28U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (29U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
+#define FDCAN_IE_RF0WE_Pos        (1U)
+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos        (2U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
+#define FDCAN_IE_RF0LE_Pos        (3U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
+#define FDCAN_IE_RF1NE_Pos        (4U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
+#define FDCAN_IE_RF1WE_Pos        (5U)
+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos        (6U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
+#define FDCAN_IE_RF1LE_Pos        (7U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
+#define FDCAN_IE_HPME_Pos         (8U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
+#define FDCAN_IE_TCE_Pos          (9U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
+#define FDCAN_IE_TCFE_Pos         (10U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos         (11U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
+#define FDCAN_IE_TEFNE_Pos        (12U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
+#define FDCAN_IE_TEFWE_Pos        (13U)
+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos        (14U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
+#define FDCAN_IE_TEFLE_Pos        (15U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
+#define FDCAN_IE_TSWE_Pos         (16U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
+#define FDCAN_IE_MRAFE_Pos        (17U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
+#define FDCAN_IE_TOOE_Pos         (18U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
+#define FDCAN_IE_DRXE_Pos         (19U)
+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos         (20U)
+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos         (21U)
+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos         (22U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
+#define FDCAN_IE_EPE_Pos          (23U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
+#define FDCAN_IE_EWE_Pos          (24U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
+#define FDCAN_IE_BOE_Pos          (25U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
+#define FDCAN_IE_WDIE_Pos         (26U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
+#define FDCAN_IE_PEAE_Pos         (27U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos         (28U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
+#define FDCAN_IE_ARAE_Pos         (29U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RF0NL_Pos       (0U)
+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos       (1U)
+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos       (2U)
+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos       (3U)
+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos       (4U)
+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos       (5U)
+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos       (6U)
+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos       (7U)
+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos        (8U)
+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos         (9U)
+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos        (10U)
+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos        (11U)
+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos       (12U)
+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos       (13U)
+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos       (14U)
+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos       (15U)
+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos        (16U)
+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFE_Pos       (17U)
+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOE_Pos        (18U)
+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXE_Pos        (19U)
+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_BECE_Pos        (20U)
+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
+#define FDCAN_ILS_BEUE_Pos        (21U)
+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
+#define FDCAN_ILS_ELOE_Pos        (22U)
+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPE_Pos         (23U)
+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWE_Pos         (24U)
+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOE_Pos         (25U)
+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIE_Pos        (26U)
+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAE_Pos        (27U)
+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDE_Pos        (28U)
+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAE_Pos        (29U)
+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
+
+/*****************  Bit definition for FDCAN_GFC register  **********************/
+#define FDCAN_GFC_RRFE_Pos        (0U)
+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos        (1U)
+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos        (2U)
+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos        (4U)
+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos     (2U)
+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos       (16U)
+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos     (2U)
+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos       (16U)
+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos       (0U)
+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos       (1U)
+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos       (2U)
+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos       (3U)
+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos       (4U)
+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos       (5U)
+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos       (6U)
+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos       (7U)
+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos       (8U)
+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos       (9U)
+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos      (10U)
+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos      (11U)
+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos      (12U)
+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos      (13U)
+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos      (14U)
+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos      (15U)
+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos      (16U)
+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos      (17U)
+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos      (18U)
+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos      (19U)
+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos      (20U)
+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos      (21U)
+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos      (22U)
+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos      (23U)
+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos      (24U)
+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos      (25U)
+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos      (26U)
+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos      (27U)
+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos      (28U)
+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos      (29U)
+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos      (30U)
+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos      (31U)
+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos      (0U)
+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos      (1U)
+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos      (2U)
+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos      (3U)
+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos      (4U)
+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos      (5U)
+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos      (6U)
+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos      (7U)
+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos      (8U)
+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos      (9U)
+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos      (10U)
+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos      (11U)
+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos      (12U)
+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos      (13U)
+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos      (14U)
+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos      (15U)
+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos      (16U)
+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos      (17U)
+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos      (18U)
+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos      (19U)
+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos      (20U)
+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos      (21U)
+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos      (22U)
+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos      (23U)
+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos      (24U)
+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos      (25U)
+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos      (26U)
+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos      (27U)
+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos      (28U)
+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos      (29U)
+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos      (30U)
+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos      (31U)
+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos      (2U)
+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos       (16U)
+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos      (24U)
+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos      (31U)
+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos       (2U)
+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ********************/
+#define FDCAN_RXF1C_F1SA_Pos      (2U)
+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos       (16U)
+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos      (24U)
+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos      (31U)
+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXESC register  ********************/
+#define FDCAN_RXESC_F0DS_Pos      (0U)
+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos      (4U)
+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos      (8U)
+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TBSA_Pos       (2U)
+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos       (16U)
+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos       (24U)
+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos       (30U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  *********************/
+#define FDCAN_TXESC_TBDS_Pos      (0U)
+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
+
+/*****************  Bit definition for FDCAN_TXEFC register  *********************/
+#define FDCAN_TXEFC_EFSA_Pos      (2U)
+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos       (16U)
+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos      (24U)
+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TTTMC register  *********************/
+#define FDCAN_TTTMC_TMSA_Pos      (2U)
+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos       (16U)
+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  *********************/
+#define FDCAN_TTRMC_RID_Pos       (0U)
+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos       (30U)
+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos      (31U)
+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  *********************/
+#define FDCAN_TTOCF_OM_Pos        (0U)
+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos       (3U)
+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos        (4U)
+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos     (5U)
+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos      (8U)
+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos      (15U)
+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos       (16U)
+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos      (24U)
+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos       (25U)
+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos      (26U)
+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  *********************/
+#define FDCAN_TTMLM_CCM_Pos       (0U)
+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos       (6U)
+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos      (8U)
+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos      (16U)
+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  *********************/
+#define FDCAN_TURCF_NCL_Pos       (0U)
+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos        (16U)
+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos       (31U)
+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ********************/
+#define FDCAN_TTOCN_SGT_Pos       (0U)
+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos       (1U)
+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos       (2U)
+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos       (3U)
+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos      (5U)
+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos       (6U)
+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos      (8U)
+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos       (9U)
+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos       (10U)
+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos       (11U)
+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos       (12U)
+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos      (13U)
+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos      (15U)
+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ********************/
+#define FDCAN_TTGTP_TP_Pos        (0U)
+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos       (16U)
+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ********************/
+#define FDCAN_TTTMK_TM_Pos        (0U)
+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos      (16U)
+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos      (31U)
+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  ********************/
+#define FDCAN_TTIR_SBC_Pos        (0U)
+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos        (1U)
+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos        (2U)
+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos        (3U)
+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos       (4U)
+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos       (5U)
+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos        (6U)
+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos        (7U)
+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos        (8U)
+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos        (9U)
+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos        (10U)
+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos        (11U)
+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos        (12U)
+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos        (13U)
+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos        (14U)
+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos        (15U)
+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos         (16U)
+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos         (17U)
+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos        (18U)
+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  ********************/
+#define FDCAN_TTIE_SBCE_Pos       (0U)
+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos       (1U)
+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos       (2U)
+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos       (3U)
+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos      (4U)
+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos      (5U)
+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos       (6U)
+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos       (7U)
+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos       (8U)
+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos       (9U)
+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos       (10U)
+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos       (11U)
+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos       (12U)
+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos       (13U)
+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos       (14U)
+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos       (15U)
+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos        (16U)
+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos        (17U)
+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos       (18U)
+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ********************/
+#define FDCAN_TTILS_SBCS_Pos      (0U)
+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos      (1U)
+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos      (2U)
+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos      (3U)
+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos     (4U)
+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos     (5U)
+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos      (6U)
+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos      (7U)
+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos      (8U)
+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos      (9U)
+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos      (10U)
+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos      (11U)
+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos      (12U)
+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos      (13U)
+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos      (14U)
+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos      (15U)
+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos       (16U)
+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos       (17U)
+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos      (18U)
+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ********************/
+#define FDCAN_TTOST_EL_Pos        (0U)
+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos        (2U)
+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos       (4U)
+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos      (6U)
+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos       (7U)
+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos       (8U)
+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos      (22U)
+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos       (23U)
+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos       (24U)
+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos       (27U)
+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos       (28U)
+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos       (29U)
+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos      (30U)
+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos       (31U)
+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ********************/
+#define FDCAN_TURNA_NAV_Pos       (0U)
+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ********************/
+#define FDCAN_TTLGT_LT_Pos        (0U)
+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos        (16U)
+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ********************/
+#define FDCAN_TTCTC_CT_Pos        (0U)
+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos        (16U)
+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ********************/
+#define FDCAN_TTCPT_CCV_Pos       (0U)
+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos       (16U)
+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ********************/
+#define FDCAN_TTCSM_CSM_Pos       (0U)
+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *********************/
+#define FDCAN_TTTS_SWTSEL_Pos     (0U)
+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos     (4U)
+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
+
+/********************************************************************************/
+/*                                                                              */
+/*                      FDCANCCU (Clock Calibration unit)                       */
+/*                                                                              */
+/********************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ******************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ******************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *******************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *******************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define CEC_CR_CECEN_Pos         (0U)
+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
+#define CEC_CR_TXSOM_Pos         (1U)
+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
+#define CEC_CR_TXEOM_Pos         (2U)
+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define CEC_CFGR_SFT_Pos         (0U)
+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
+#define CEC_CFGR_RXTOL_Pos       (3U)
+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
+#define CEC_CFGR_BRESTP_Pos      (4U)
+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
+#define CEC_CFGR_BREGEN_Pos      (5U)
+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
+#define CEC_CFGR_LBPEGEN_Pos     (6U)
+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
+#define CEC_CFGR_SFTOPT_Pos      (8U)
+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
+#define CEC_CFGR_BRDNOGEN_Pos    (7U)
+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
+#define CEC_CFGR_OAR_Pos         (16U)
+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
+#define CEC_CFGR_LSTN_Pos        (31U)
+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define CEC_TXDR_TXD_Pos         (0U)
+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define CEC_RXDR_RXD_Pos         (0U)
+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define CEC_ISR_RXBR_Pos         (0U)
+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
+#define CEC_ISR_RXEND_Pos        (1U)
+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
+#define CEC_ISR_RXOVR_Pos        (2U)
+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
+#define CEC_ISR_BRE_Pos          (3U)
+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
+#define CEC_ISR_SBPE_Pos         (4U)
+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
+#define CEC_ISR_LBPE_Pos         (5U)
+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
+#define CEC_ISR_RXACKE_Pos       (6U)
+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
+#define CEC_ISR_ARBLST_Pos       (7U)
+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
+#define CEC_ISR_TXBR_Pos         (8U)
+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
+#define CEC_ISR_TXEND_Pos        (9U)
+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
+#define CEC_ISR_TXUDR_Pos        (10U)
+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
+#define CEC_ISR_TXERR_Pos        (11U)
+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
+#define CEC_ISR_TXACKE_Pos       (12U)
+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define CEC_IER_RXBRIE_Pos       (0U)
+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
+#define CEC_IER_RXENDIE_Pos      (1U)
+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
+#define CEC_IER_RXOVRIE_Pos      (2U)
+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
+#define CEC_IER_BREIE_Pos        (3U)
+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
+#define CEC_IER_SBPEIE_Pos       (4U)
+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
+#define CEC_IER_LBPEIE_Pos       (5U)
+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
+#define CEC_IER_RXACKEIE_Pos     (6U)
+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define CEC_IER_ARBLSTIE_Pos     (7U)
+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
+#define CEC_IER_TXBRIE_Pos       (8U)
+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
+#define CEC_IER_TXENDIE_Pos      (9U)
+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
+#define CEC_IER_TXUDRIE_Pos      (10U)
+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define CEC_IER_TXERRIE_Pos      (11U)
+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
+#define CEC_IER_TXACKEIE_Pos     (12U)
+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos             (1U)
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos           (2U)
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos           (3U)
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos            (4U)
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos         (5U)
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos          (6U)
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos          (7U)
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
+#define DCMI_CR_CRE_Pos            (12U)
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos         (14U)
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos            (16U)
+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos           (18U)
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos            (19U)
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos           (20U)
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos          (1U)
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos            (2U)
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos       (1U)
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos       (2U)
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos      (4U)
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos        (1U)
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos        (2U)
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos      (3U)
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos       (4U)
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos       (1U)
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos       (2U)
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos      (4U)
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos       (1U)
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos       (2U)
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos      (4U)
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos          (8U)
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos          (16U)
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos          (24U)
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos          (8U)
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos          (16U)
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos          (24U)
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos        (16U)
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos      (16U)
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos          (0U)
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos          (8U)
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos          (16U)
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos          (24U)
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
+
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           BDMA Controller                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BDMA_ISR register  ********************/
+#define BDMA_ISR_GIF0_Pos       (0U)
+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
+#define BDMA_ISR_TCIF0_Pos      (1U)
+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
+#define BDMA_ISR_HTIF0_Pos      (2U)
+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
+#define BDMA_ISR_TEIF0_Pos      (3U)
+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
+#define BDMA_ISR_GIF1_Pos       (4U)
+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
+#define BDMA_ISR_TCIF1_Pos      (5U)
+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
+#define BDMA_ISR_HTIF1_Pos      (6U)
+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
+#define BDMA_ISR_TEIF1_Pos      (7U)
+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
+#define BDMA_ISR_GIF2_Pos       (8U)
+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
+#define BDMA_ISR_TCIF2_Pos      (9U)
+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
+#define BDMA_ISR_HTIF2_Pos      (10U)
+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
+#define BDMA_ISR_TEIF2_Pos      (11U)
+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
+#define BDMA_ISR_GIF3_Pos       (12U)
+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
+#define BDMA_ISR_TCIF3_Pos      (13U)
+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
+#define BDMA_ISR_HTIF3_Pos      (14U)
+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
+#define BDMA_ISR_TEIF3_Pos      (15U)
+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
+#define BDMA_ISR_GIF4_Pos       (16U)
+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
+#define BDMA_ISR_TCIF4_Pos      (17U)
+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
+#define BDMA_ISR_HTIF4_Pos      (18U)
+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
+#define BDMA_ISR_TEIF4_Pos      (19U)
+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
+#define BDMA_ISR_GIF5_Pos       (20U)
+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
+#define BDMA_ISR_TCIF5_Pos      (21U)
+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
+#define BDMA_ISR_HTIF5_Pos      (22U)
+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
+#define BDMA_ISR_TEIF5_Pos      (23U)
+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
+#define BDMA_ISR_GIF6_Pos       (24U)
+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
+#define BDMA_ISR_TCIF6_Pos      (25U)
+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
+#define BDMA_ISR_HTIF6_Pos      (26U)
+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
+#define BDMA_ISR_TEIF6_Pos      (27U)
+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
+#define BDMA_ISR_GIF7_Pos       (28U)
+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
+#define BDMA_ISR_TCIF7_Pos      (29U)
+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
+#define BDMA_ISR_HTIF7_Pos      (30U)
+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
+#define BDMA_ISR_TEIF7_Pos      (31U)
+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for BDMA_IFCR register  *******************/
+#define BDMA_IFCR_CGIF0_Pos     (0U)
+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
+#define BDMA_IFCR_CTCIF0_Pos    (1U)
+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF0_Pos    (2U)
+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
+#define BDMA_IFCR_CTEIF0_Pos    (3U)
+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
+#define BDMA_IFCR_CGIF1_Pos     (4U)
+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
+#define BDMA_IFCR_CTCIF1_Pos    (5U)
+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF1_Pos    (6U)
+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
+#define BDMA_IFCR_CTEIF1_Pos    (7U)
+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
+#define BDMA_IFCR_CGIF2_Pos     (8U)
+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
+#define BDMA_IFCR_CTCIF2_Pos    (9U)
+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF2_Pos    (10U)
+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
+#define BDMA_IFCR_CTEIF2_Pos    (11U)
+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
+#define BDMA_IFCR_CGIF3_Pos     (12U)
+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
+#define BDMA_IFCR_CTCIF3_Pos    (13U)
+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF3_Pos    (14U)
+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
+#define BDMA_IFCR_CTEIF3_Pos    (15U)
+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
+#define BDMA_IFCR_CGIF4_Pos     (16U)
+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
+#define BDMA_IFCR_CTCIF4_Pos    (17U)
+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF4_Pos    (18U)
+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
+#define BDMA_IFCR_CTEIF4_Pos    (19U)
+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
+#define BDMA_IFCR_CGIF5_Pos     (20U)
+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
+#define BDMA_IFCR_CTCIF5_Pos    (21U)
+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF5_Pos    (22U)
+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
+#define BDMA_IFCR_CTEIF5_Pos    (23U)
+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
+#define BDMA_IFCR_CGIF6_Pos     (24U)
+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
+#define BDMA_IFCR_CTCIF6_Pos    (25U)
+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF6_Pos    (26U)
+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
+#define BDMA_IFCR_CTEIF6_Pos    (27U)
+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
+#define BDMA_IFCR_CGIF7_Pos     (28U)
+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
+#define BDMA_IFCR_CTCIF7_Pos    (29U)
+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF7_Pos    (30U)
+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
+#define BDMA_IFCR_CTEIF7_Pos    (31U)
+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for BDMA_CCR register  ********************/
+#define BDMA_CCR_EN_Pos         (0U)
+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
+#define BDMA_CCR_TCIE_Pos       (1U)
+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
+#define BDMA_CCR_HTIE_Pos       (2U)
+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
+#define BDMA_CCR_TEIE_Pos       (3U)
+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
+#define BDMA_CCR_DIR_Pos        (4U)
+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
+#define BDMA_CCR_CIRC_Pos       (5U)
+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
+#define BDMA_CCR_PINC_Pos       (6U)
+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
+#define BDMA_CCR_MINC_Pos       (7U)
+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
+
+#define BDMA_CCR_PSIZE_Pos      (8U)
+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
+
+#define BDMA_CCR_MSIZE_Pos      (10U)
+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
+
+#define BDMA_CCR_PL_Pos         (12U)
+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
+
+#define BDMA_CCR_MEM2MEM_Pos    (14U)
+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
+#define BDMA_CCR_DBM_Pos        (15U)
+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
+#define BDMA_CCR_CT_Pos         (16U)
+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
+
+/******************  Bit definition for BDMA_CNDTR register  *******************/
+#define BDMA_CNDTR_NDT_Pos      (0U)
+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
+
+/******************  Bit definition for BDMA_CPAR register  ********************/
+#define BDMA_CPAR_PA_Pos        (0U)
+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
+
+/******************  Bit definition for BDMA_CM0AR register  ********************/
+#define BDMA_CM0AR_MA_Pos        (0U)
+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************  Bit definition for BDMA_CM1AR register  ********************/
+#define BDMA_CM1AR_MA_Pos        (0U)
+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Configuration Register register */
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Extended Configuration Register register */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/* Bit definition for Ethernet MAC Packet Filter Register */
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTR_EIVLS_Pos                          (28U)
+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTR_EDVLP_Pos                          (26U)
+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTR_VTHM_Pos                           (25U)
+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_EVLS_Pos                           (21U)
+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTR_ESVL_Pos                           (18U)
+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTR_VTIM_Pos                           (17U)
+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ETV_Pos                            (16U)
+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VL_Pos                             (0U)
+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_UP_Pos                          (13U)
+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVTR_VL_VID_Pos                         (0U)
+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/* Bit definition for Ethernet MAC VLAN Incl Register */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
+#define ETH_MACTFCR_PT_Pos                            (16U)
+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
+#define ETH_MACTFCR_DZPQ_Pos                          (7U)
+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACTFCR_PLT_Pos                           (4U)
+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACTFCR_TFE_Pos                           (1U)
+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACTFCR_FCB_Pos                           (0U)
+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
+#define ETH_MACRFCR_UP_Pos                            (1U)
+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRFCR_RFE_Pos                           (0U)
+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/* Bit definition for Ethernet MAC Interrupt Status Register */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+
+/* Bit definition for Ethernet MAC Interrupt Enable Register */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+
+/* Bit definition for Ethernet MAC Rx Tx Status Register */
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/* Bit definition for Ethernet MAC PMT Control Status Register */
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
+#define ETH_MACRWUPFR_D_Pos                           (0U)
+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
+
+/* Bit definition for Ethernet MAC LPI Control Status Register */
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/* Bit definition for Ethernet MAC LPI Timers Control Register */
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/* Bit definition for Ethernet MAC Version Register */
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/* Bit definition for Ethernet MAC Debug Register */
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/* Bit definition for Ethernet MAC HW Feature0 Register */
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/* Bit definition for Ethernet MAC HW Feature1 Register */
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/* Bit definition for Ethernet MAC HW Feature2 Register */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+
+/* Bit definition for Ethernet MAC MDIO Address Register */
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_MOC_Pos                         (2U)
+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_MB_Pos                          (0U)
+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
+
+/* Bit definition for Ethernet MAC MDIO Data Register */
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_MD_Pos                          (0U)
+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
+
+/* Bit definition for Ethernet ARP Address Register */
+#define ETH_MACARPAR_ARPPA_Pos                         (0U)
+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/* Bit definition for Ethernet MAC Address 0 High Register */
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 0 Low Register */
+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
+#define ETH_MACA1HR_SA_Pos                            (30U)
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 1 Low Register */
+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
+#define ETH_MACA2HR_SA_Pos                            (30U)
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 Low Register */
+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
+
+/* Bit definition for Ethernet MAC Address 3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
+#define ETH_MACA3HR_SA_Pos                            (30U)
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 3 Low Register */
+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
+
+/* Bit definition for Ethernet MAC Address High Register */
+#define ETH_MACAHR_AE_Pos                             (31U)
+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
+#define ETH_MACAHR_SA_Pos                             (30U)
+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
+#define ETH_MACAHR_MBC_Pos                            (24U)
+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MACAH_Pos                          (0U)
+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
+
+/* Bit definition for Ethernet MAC Address Low Register */
+#define ETH_MACALR_MACAL_Pos                          (0U)
+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Rx Interrupt Register */
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Register */
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/* Bit definition for Ethernet MMC Rx alignment error packets register */
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/* Bit definition for Ethernet MAC L3 L4 Control Register */
+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
+
+/* Bit definition for Ethernet MAC L4 Address Register */
+#define ETH_MACL4AR_L4DP_Pos                          (16U)
+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4AR_L4SP_Pos                          (0U)
+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
+
+/* Bit definition for Ethernet MAC L3 Address0 Register */
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/* Bit definition for Ethernet MAC L4 Address1 Register */
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/* Bit definition for Ethernet MAC L4 Address2 Register */
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/* Bit definition for Ethernet MAC L4 Address3 Register */
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/* Bit definition for Ethernet MAC Timestamp Control Register */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_CSC_Pos                           (19U)
+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/* Bit definition for Ethernet MAC Sub-second Increment Register */
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
+
+/* Bit definition for Ethernet MAC System Time Seconds Register */
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/* Bit definition for Ethernet MAC Timestamp Status Register */
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/* Bit definition for Ethernet MAC PPS Control Register */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/* Bit definition for Ethernet MAC PPS Interval Register */
+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/* Bit definition for Ethernet MAC PPS Width Register */
+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/* Bit definition for Ethernet MAC PTP Offload Control Register */
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
+#define ETH_MACSPI1R_SPI1_Pos                         (0U)
+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
+#define ETH_MACSPI2R_SPI2_Pos                         (0U)
+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/* Bit definition for Ethernet MAC Log Message Interval Register */
+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                           (0U)
+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/* Bit definition for Ethernet MTL Operation Mode Register */
+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/* Bit definition for Ethernet MTL Interrupt Status Register */
+#define ETH_MTLISR_MACIS_Pos                          (16U)
+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_MTLISR_QIS_Pos                            (0U)
+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
+
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
+#define ETH_MTLTQOMR_TTC_Pos                          (4U)
+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TSF_Pos                          (1U)
+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */
+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
+#define ETH_MTLRQOMR_RQS_Pos                          (20U)
+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRQOMR_RFD_Pos                          (14U)
+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRQOMR_RFA_Pos                          (8U)
+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRQOMR_RSF_Pos                          (5U)
+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRQOMR_FEP_Pos                          (4U)
+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRQOMR_FUP_Pos                          (3U)
+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRQOMR_RTC_Pos                          (0U)
+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
+
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */
+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Control Register */
+#define ETH_MTLRQCR_RQPA_Pos                          (3U)
+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRQCR_RQW_Pos                           (0U)
+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
+
+/* Bit definition for Ethernet DMA Mode Register */
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_PR_Pos                              (12U)
+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
+#define ETH_DMAMR_DA_Pos                              (1U)
+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
+
+/* Bit definition for Ethernet DMA SysBus Mode Register */
+#define ETH_DMASBMR_RB_Pos                            (15U)
+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
+#define ETH_DMASBMR_MB_Pos                            (14U)
+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/* Bit definition for Ethernet DMA Interrupt Status Register */
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMACIS_Pos                         (0U)
+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
+
+/* Bit definition for Ethernet DMA Debug Status Register */
+#define ETH_DMADSR_TPS_Pos                            (12U)
+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS_Pos                            (8U)
+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+
+/* Bit definition for Ethernet DMA Channel Control Register */
+#define ETH_DMACCR_DSL_Pos                            (18U)
+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
+#define ETH_DMACCR_MSS_Pos                            (0U)
+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
+
+/* Bit definition for Ethernet DMA Channel Tx Control Register */
+#define ETH_DMACTCR_TPBL_Pos                          (16U)
+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TSE_Pos                           (12U)
+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
+#define ETH_DMACTCR_OSP_Pos                           (4U)
+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
+#define ETH_DMACTCR_ST_Pos                            (0U)
+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/* Bit definition for Ethernet DMA Channel Rx Control Register */
+#define ETH_DMACRCR_RPF_Pos                           (31U)
+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
+#define ETH_DMACRCR_RPBL_Pos                          (16U)
+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RBSZ_Pos                          (1U)
+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
+#define ETH_DMACRCR_SR_Pos                            (0U)
+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
+
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
+
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
+#define ETH_DMACTDTPR_TDT_Pos                         (2U)
+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
+#define ETH_DMACRDTPR_RDT_Pos                         (2U)
+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
+#define ETH_DMACIER_NIE_Pos                           (15U)
+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACIER_AIE_Pos                           (14U)
+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACIER_CDEE_Pos                          (13U)
+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACIER_FBEE_Pos                          (12U)
+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACIER_ERIE_Pos                          (11U)
+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACIER_ETIE_Pos                          (10U)
+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACIER_RWTE_Pos                          (9U)
+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACIER_RSE_Pos                           (8U)
+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACIER_RBUE_Pos                          (7U)
+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACIER_RIE_Pos                           (6U)
+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACIER_TBUE_Pos                          (2U)
+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACIER_TXSE_Pos                          (1U)
+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACIER_TIE_Pos                           (0U)
+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
+#define ETH_DMACRIWTR_RWT_Pos                         (0U)
+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Status Register */
+#define ETH_DMACSR_REB_Pos                            (19U)
+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACSR_TEB_Pos                            (16U)
+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACSR_NIS_Pos                            (15U)
+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACSR_AIS_Pos                            (14U)
+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACSR_CDE_Pos                            (13U)
+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACSR_FBE_Pos                            (12U)
+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACSR_ERI_Pos                            (11U)
+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACSR_ETI_Pos                            (10U)
+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACSR_RWT_Pos                            (9U)
+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACSR_RPS_Pos                            (8U)
+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACSR_RBU_Pos                            (7U)
+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACSR_RI_Pos                             (6U)
+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACSR_TBU_Pos                            (2U)
+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACSR_TPS_Pos                            (1U)
+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACSR_TI_Pos                             (0U)
+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
+
+/* Bit definition for Ethernet DMA Channel missed frame count register */
+#define ETH_DMACMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACMFCR_MFC_Pos                          (0U)
+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_MBURST_Pos      (23U)
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_TRBUFF_Pos      (20U)
+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
+#define DMA_SxCR_CT_Pos          (19U)
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
+#define DMA_SxCR_DBM_Pos         (18U)
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
+#define DMA_SxCR_PL_Pos          (16U)
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
+#define DMA_SxCR_MSIZE_Pos       (13U)
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
+#define DMA_SxCR_PINC_Pos        (9U)
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
+#define DMA_SxCR_CIRC_Pos        (8U)
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
+#define DMA_SxCR_DIR_Pos         (6U)
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
+#define DMA_SxCR_TCIE_Pos        (4U)
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
+#define DMA_SxCR_HTIE_Pos        (3U)
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
+#define DMA_SxCR_TEIE_Pos        (2U)
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
+#define DMA_SxCR_DMEIE_Pos       (1U)
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
+#define DMA_SxCR_EN_Pos          (0U)
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/
+#define DMA_SxFCR_FEIE_Pos       (7U)
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
+#define DMA_SxFCR_FS_Pos         (3U)
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
+#define DMA_SxFCR_FTH_Pos        (0U)
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/
+#define DMA_LISR_TCIF3_Pos       (27U)
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
+#define DMA_LISR_HTIF3_Pos       (26U)
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
+#define DMA_LISR_TEIF3_Pos       (25U)
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
+#define DMA_LISR_DMEIF3_Pos      (24U)
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
+#define DMA_LISR_FEIF3_Pos       (22U)
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
+#define DMA_LISR_TCIF2_Pos       (21U)
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
+#define DMA_LISR_HTIF2_Pos       (20U)
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
+#define DMA_LISR_TEIF2_Pos       (19U)
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
+#define DMA_LISR_DMEIF2_Pos      (18U)
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
+#define DMA_LISR_FEIF2_Pos       (16U)
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
+#define DMA_LISR_TCIF1_Pos       (11U)
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
+#define DMA_LISR_HTIF1_Pos       (10U)
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
+#define DMA_LISR_TEIF1_Pos       (9U)
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
+#define DMA_LISR_DMEIF1_Pos      (8U)
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
+#define DMA_LISR_FEIF1_Pos       (6U)
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
+#define DMA_LISR_TCIF0_Pos       (5U)
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
+#define DMA_LISR_HTIF0_Pos       (4U)
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
+#define DMA_LISR_TEIF0_Pos       (3U)
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
+#define DMA_LISR_DMEIF0_Pos      (2U)
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
+#define DMA_LISR_FEIF0_Pos       (0U)
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HISR register  *****************/
+#define DMA_HISR_TCIF7_Pos       (27U)
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
+#define DMA_HISR_HTIF7_Pos       (26U)
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
+#define DMA_HISR_TEIF7_Pos       (25U)
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
+#define DMA_HISR_DMEIF7_Pos      (24U)
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
+#define DMA_HISR_FEIF7_Pos       (22U)
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
+#define DMA_HISR_TCIF6_Pos       (21U)
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
+#define DMA_HISR_HTIF6_Pos       (20U)
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
+#define DMA_HISR_TEIF6_Pos       (19U)
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
+#define DMA_HISR_DMEIF6_Pos      (18U)
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
+#define DMA_HISR_FEIF6_Pos       (16U)
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
+#define DMA_HISR_TCIF5_Pos       (11U)
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
+#define DMA_HISR_HTIF5_Pos       (10U)
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
+#define DMA_HISR_TEIF5_Pos       (9U)
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
+#define DMA_HISR_DMEIF5_Pos      (8U)
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
+#define DMA_HISR_FEIF5_Pos       (6U)
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
+#define DMA_HISR_TCIF4_Pos       (5U)
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
+#define DMA_HISR_HTIF4_Pos       (4U)
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
+#define DMA_HISR_TEIF4_Pos       (3U)
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
+#define DMA_HISR_DMEIF4_Pos      (2U)
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
+#define DMA_HISR_FEIF4_Pos       (0U)
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_LIFCR register  ****************/
+#define DMA_LIFCR_CTCIF3_Pos     (27U)
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF3_Pos     (26U)
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF3_Pos     (25U)
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF3_Pos     (22U)
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF2_Pos     (21U)
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF2_Pos     (20U)
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF2_Pos     (19U)
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF2_Pos     (16U)
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF1_Pos     (11U)
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF1_Pos     (10U)
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF1_Pos     (9U)
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF1_Pos     (6U)
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF0_Pos     (5U)
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF0_Pos     (4U)
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF0_Pos     (3U)
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF0_Pos     (0U)
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/
+#define DMA_HIFCR_CTCIF7_Pos     (27U)
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF7_Pos     (26U)
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF7_Pos     (25U)
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF7_Pos     (22U)
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF6_Pos     (21U)
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF6_Pos     (20U)
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF6_Pos     (19U)
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF6_Pos     (16U)
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF5_Pos     (11U)
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF5_Pos     (10U)
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF5_Pos     (9U)
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF5_Pos     (6U)
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF4_Pos     (5U)
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF4_Pos     (4U)
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF4_Pos     (3U)
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF4_Pos     (0U)
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos           (8U)
+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos            (9U)
+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
+#define DMAMUX_CxCR_SE_Pos             (16U)
+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos           (17U)
+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos          (19U)
+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  **************/
+#define DMAMUX_CSR_SOF0_Pos            (0U)
+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF1_Pos            (1U)
+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF2_Pos            (2U)
+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF3_Pos            (3U)
+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF4_Pos            (4U)
+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF5_Pos            (5U)
+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF6_Pos            (6U)
+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF7_Pos            (7U)
+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF8_Pos            (8U)
+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF9_Pos            (9U)
+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF10_Pos           (10U)
+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF11_Pos           (11U)
+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF12_Pos           (12U)
+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF13_Pos           (13U)
+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF14_Pos           (14U)
+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF15_Pos           (15U)
+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_CFR register  **************/
+#define DMAMUX_CFR_CSOF0_Pos           (0U)
+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF1_Pos           (1U)
+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF2_Pos           (2U)
+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF3_Pos           (3U)
+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF4_Pos           (4U)
+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF5_Pos           (5U)
+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF6_Pos           (6U)
+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF7_Pos           (7U)
+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF8_Pos           (8U)
+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF9_Pos           (9U)
+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF10_Pos          (10U)
+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF11_Pos          (11U)
+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF12_Pos          (12U)
+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF13_Pos          (13U)
+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF14_Pos          (14U)
+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF15_Pos          (15U)
+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos           (8U)
+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos            (16U)
+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
+#define DMAMUX_RGxCR_GPOL_Pos          (17U)
+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos            (0U)
+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF1_Pos            (1U)
+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF2_Pos            (2U)
+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF3_Pos            (3U)
+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF4_Pos            (4U)
+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF5_Pos            (5U)
+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF6_Pos            (6U)
+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF7_Pos            (7U)
+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGCFR register  **************/
+#define DMAMUX_RGCFR_COF0_Pos          (0U)
+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF1_Pos          (1U)
+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF2_Pos          (2U)
+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF3_Pos          (3U)
+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF4_Pos          (4U)
+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF5_Pos          (5U)
+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF6_Pos          (6U)
+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF7_Pos          (7U)
+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)
+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_1_Pos      (16U)
+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_2_Pos      (11U)
+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_3_Pos      (10U)
+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)
+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_4_Pos      (8U)
+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for EXTI_RTSR1 register  *******************/
+#define EXTI_RTSR1_TR_Pos          (0U)
+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR1_TR0_Pos         (0U)
+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos         (1U)
+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos         (2U)
+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos         (3U)
+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos         (4U)
+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos         (5U)
+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos         (6U)
+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos         (7U)
+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos         (8U)
+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos         (9U)
+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos        (10U)
+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos        (11U)
+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos        (12U)
+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos        (13U)
+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos        (14U)
+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos        (15U)
+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos        (16U)
+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos        (17U)
+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos        (18U)
+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos        (19U)
+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos        (20U)
+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos        (21U)
+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_FTSR1 register  *******************/
+#define EXTI_FTSR1_TR_Pos          (0U)
+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR1_TR0_Pos         (0U)
+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos         (1U)
+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos         (2U)
+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos         (3U)
+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos         (4U)
+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos         (5U)
+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos         (6U)
+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos         (7U)
+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos         (8U)
+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos         (9U)
+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos        (10U)
+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos        (11U)
+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos        (12U)
+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos        (13U)
+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos        (14U)
+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos        (15U)
+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos        (16U)
+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos        (17U)
+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos        (18U)
+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos        (19U)
+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos        (20U)
+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos        (21U)
+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_SWIER1 register  ******************/
+#define EXTI_SWIER1_SWIER0_Pos     (0U)
+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos     (1U)
+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos     (2U)
+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos     (3U)
+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos     (4U)
+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos     (5U)
+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos     (6U)
+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos     (7U)
+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos     (8U)
+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos     (9U)
+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos    (10U)
+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos    (11U)
+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos    (12U)
+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos    (13U)
+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos    (14U)
+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos    (15U)
+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos    (16U)
+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos    (17U)
+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos    (18U)
+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos    (19U)
+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos    (20U)
+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos    (21U)
+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
+
+/******************  Bit definition for EXTI_D3PMR1 register  ******************/
+#define EXTI_D3PMR1_MR0_Pos        (0U)
+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
+#define EXTI_D3PMR1_MR1_Pos        (1U)
+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
+#define EXTI_D3PMR1_MR2_Pos        (2U)
+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
+#define EXTI_D3PMR1_MR3_Pos        (3U)
+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
+#define EXTI_D3PMR1_MR4_Pos        (4U)
+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
+#define EXTI_D3PMR1_MR5_Pos        (5U)
+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
+#define EXTI_D3PMR1_MR6_Pos        (6U)
+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
+#define EXTI_D3PMR1_MR7_Pos        (7U)
+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
+#define EXTI_D3PMR1_MR8_Pos        (8U)
+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
+#define EXTI_D3PMR1_MR9_Pos        (9U)
+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
+#define EXTI_D3PMR1_MR10_Pos       (10U)
+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
+#define EXTI_D3PMR1_MR11_Pos       (11U)
+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
+#define EXTI_D3PMR1_MR12_Pos       (12U)
+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
+#define EXTI_D3PMR1_MR13_Pos       (13U)
+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
+#define EXTI_D3PMR1_MR14_Pos       (14U)
+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
+#define EXTI_D3PMR1_MR15_Pos       (15U)
+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
+#define EXTI_D3PMR1_MR19_Pos       (19U)
+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
+#define EXTI_D3PMR1_MR20_Pos       (20U)
+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
+#define EXTI_D3PMR1_MR21_Pos       (21U)
+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
+#define EXTI_D3PMR1_MR25_Pos       (24U)
+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
+
+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/
+#define EXTI_D3PCR1L_PCS0_Pos       (0U)
+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
+#define EXTI_D3PCR1L_PCS1_Pos       (2U)
+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
+#define EXTI_D3PCR1L_PCS2_Pos       (4U)
+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
+#define EXTI_D3PCR1L_PCS3_Pos       (6U)
+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
+#define EXTI_D3PCR1L_PCS4_Pos       (8U)
+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
+#define EXTI_D3PCR1L_PCS5_Pos       (10U)
+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
+#define EXTI_D3PCR1L_PCS6_Pos       (12U)
+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
+#define EXTI_D3PCR1L_PCS7_Pos       (14U)
+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
+#define EXTI_D3PCR1L_PCS8_Pos       (16U)
+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
+#define EXTI_D3PCR1L_PCS9_Pos       (18U)
+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
+#define EXTI_D3PCR1L_PCS10_Pos      (20U)
+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
+#define EXTI_D3PCR1L_PCS11_Pos      (22U)
+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
+#define EXTI_D3PCR1L_PCS12_Pos      (24U)
+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
+#define EXTI_D3PCR1L_PCS13_Pos      (26U)
+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
+#define EXTI_D3PCR1L_PCS14_Pos      (28U)
+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
+#define EXTI_D3PCR1L_PCS15_Pos      (30U)
+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
+
+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/
+#define EXTI_D3PCR1H_PCS19_Pos       (6U)
+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
+#define EXTI_D3PCR1H_PCS20_Pos       (8U)
+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
+#define EXTI_D3PCR1H_PCS21_Pos       (10U)
+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
+#define EXTI_D3PCR1H_PCS25_Pos       (18U)
+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
+
+/******************  Bit definition for EXTI_RTSR2 register  *******************/
+#define EXTI_RTSR2_TR_Pos          (17U)
+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR2_TR49_Pos        (17U)
+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos        (19U)
+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_FTSR2 register  *******************/
+#define EXTI_FTSR2_TR_Pos          (17U)
+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR2_TR49_Pos        (17U)
+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos        (19U)
+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_SWIER2 register  ******************/
+#define EXTI_SWIER2_SWIER49_Pos    (17U)
+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos    (19U)
+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
+
+/******************  Bit definition for EXTI_D3PMR2 register  ******************/
+#define EXTI_D3PMR2_MR34_Pos       (2U)
+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
+#define EXTI_D3PMR2_MR35_Pos       (3U)
+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
+#define EXTI_D3PMR2_MR41_Pos       (9U)
+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
+#define EXTI_D3PMR2_MR48_Pos       (16U)
+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
+#define EXTI_D3PMR2_MR49_Pos       (17U)
+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
+#define EXTI_D3PMR2_MR50_Pos       (18U)
+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
+#define EXTI_D3PMR2_MR51_Pos       (19U)
+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
+#define EXTI_D3PMR2_MR52_Pos       (20U)
+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */
+#define EXTI_D3PMR2_MR53_Pos       (21U)
+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */
+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/
+#define EXTI_D3PCR2L_PCS34_Pos       (4U)
+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
+#define EXTI_D3PCR2L_PCS35_Pos       (6U)
+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
+#define EXTI_D3PCR2L_PCS41_Pos       (18U)
+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
+
+
+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/
+#define EXTI_D3PCR2H_PCS48_Pos       (0U)
+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
+#define EXTI_D3PCR2H_PCS49_Pos       (2U)
+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
+#define EXTI_D3PCR2H_PCS50_Pos       (4U)
+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
+#define EXTI_D3PCR2H_PCS51_Pos       (6U)
+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
+#define EXTI_D3PCR2H_PCS52_Pos       (8U)
+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */
+#define EXTI_D3PCR2H_PCS53_Pos       (10U)
+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */
+/******************  Bit definition for EXTI_RTSR3 register  *******************/
+#define EXTI_RTSR3_TR_Pos          (18U)
+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR3_TR82_Pos        (18U)
+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
+#define EXTI_RTSR3_TR84_Pos        (20U)
+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */
+#define EXTI_RTSR3_TR85_Pos        (21U)
+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos        (22U)
+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_FTSR3 register  *******************/
+#define EXTI_FTSR3_TR_Pos          (18U)
+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR3_TR82_Pos        (18U)
+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
+#define EXTI_FTSR3_TR84_Pos        (20U)
+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */
+#define EXTI_FTSR3_TR85_Pos        (21U)
+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos        (22U)
+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_SWIER3 register  ******************/
+#define EXTI_SWIER3_SWI_Pos        (18U)
+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */
+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
+#define EXTI_SWIER3_SWIER82_Pos    (18U)
+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
+#define EXTI_SWIER3_SWIER84_Pos    (20U)
+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */
+#define EXTI_SWIER3_SWIER85_Pos    (21U)
+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos    (22U)
+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
+
+/*******************  Bit definition for EXTI_IMR1 register  *******************/
+#define EXTI_IMR1_IM_Pos           (0U)
+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR1_IM0_Pos          (0U)
+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos          (1U)
+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos          (2U)
+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos          (3U)
+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos          (4U)
+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos          (5U)
+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos          (6U)
+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos          (7U)
+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos          (8U)
+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos          (9U)
+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos         (10U)
+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos         (11U)
+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos         (12U)
+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos         (13U)
+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos         (14U)
+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos         (15U)
+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos         (16U)
+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos         (17U)
+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos         (18U)
+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos         (19U)
+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos         (20U)
+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos         (21U)
+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos         (22U)
+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos         (23U)
+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos         (24U)
+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos         (25U)
+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos         (26U)
+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos         (27U)
+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos         (28U)
+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos         (29U)
+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos         (30U)
+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos         (31U)
+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
+
+/*******************  Bit definition for EXTI_EMR1 register  *******************/
+#define EXTI_EMR1_EM_Pos           (0U)
+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR1_EM0_Pos          (0U)
+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos          (1U)
+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos          (2U)
+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos          (3U)
+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos          (4U)
+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos          (5U)
+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos          (6U)
+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos          (7U)
+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos          (8U)
+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos          (9U)
+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos         (10U)
+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos         (11U)
+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos         (12U)
+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos         (13U)
+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos         (14U)
+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos         (15U)
+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos         (16U)
+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos         (17U)
+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos         (18U)
+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos         (20U)
+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos         (21U)
+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos         (22U)
+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos         (23U)
+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos         (24U)
+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos         (25U)
+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos         (26U)
+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos         (27U)
+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos         (28U)
+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos         (29U)
+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos         (30U)
+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos         (31U)
+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_PR1 register  ********************/
+#define EXTI_PR1_PR_Pos            (0U)
+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR1_PR0_Pos           (0U)
+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos           (1U)
+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos           (2U)
+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos           (3U)
+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos           (4U)
+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos           (5U)
+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos           (6U)
+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos           (7U)
+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos           (8U)
+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos           (9U)
+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos          (10U)
+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos          (11U)
+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos          (12U)
+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos          (13U)
+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos          (14U)
+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos          (15U)
+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos          (16U)
+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
+#define EXTI_PR1_PR17_Pos          (17U)
+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
+#define EXTI_PR1_PR18_Pos          (18U)
+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
+#define EXTI_PR1_PR19_Pos          (19U)
+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
+#define EXTI_PR1_PR20_Pos          (20U)
+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
+#define EXTI_PR1_PR21_Pos          (21U)
+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
+
+/*******************  Bit definition for EXTI_IMR2 register  *******************/
+#define EXTI_IMR2_IM_Pos           (0U)
+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR2_IM32_Pos         (0U)
+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos         (1U)
+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos         (2U)
+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos         (3U)
+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos         (4U)
+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos         (5U)
+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos         (6U)
+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos         (7U)
+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos         (8U)
+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos         (9U)
+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos         (10U)
+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos         (11U)
+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos         (12U)
+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM46_Pos         (14U)
+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos         (15U)
+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos         (16U)
+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos         (17U)
+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos         (18U)
+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos         (19U)
+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos         (20U)
+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos         (21U)
+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos         (22U)
+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos         (23U)
+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos         (24U)
+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos         (25U)
+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos         (26U)
+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos         (27U)
+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos         (28U)
+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos         (29U)
+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos         (30U)
+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos         (31U)
+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
+
+/*******************  Bit definition for EXTI_EMR2 register  *******************/
+#define EXTI_EMR2_EM_Pos           (0U)
+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR2_EM32_Pos         (0U)
+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos         (1U)
+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos         (2U)
+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos         (3U)
+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos         (4U)
+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos         (5U)
+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos         (6U)
+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos         (7U)
+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos         (8U)
+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos         (9U)
+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos         (10U)
+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos         (11U)
+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos         (12U)
+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM46_Pos         (14U)
+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos         (15U)
+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos         (16U)
+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos         (17U)
+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos         (18U)
+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos         (19U)
+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos         (20U)
+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos         (21U)
+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos         (22U)
+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos         (23U)
+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos         (24U)
+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos         (25U)
+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos         (26U)
+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos         (27U)
+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos         (28U)
+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos         (29U)
+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos         (30U)
+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos         (31U)
+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
+
+/*******************  Bit definition for EXTI_PR2 register  ********************/
+#define EXTI_PR2_PR_Pos            (17U)
+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR2_PR49_Pos          (17U)
+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
+#define EXTI_PR2_PR51_Pos          (19U)
+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
+
+/*******************  Bit definition for EXTI_IMR3 register  *******************/
+#define EXTI_IMR3_IM_Pos           (0U)
+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR3_IM64_Pos         (0U)
+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos         (1U)
+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos         (2U)
+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos         (3U)
+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos         (4U)
+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos         (5U)
+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos         (6U)
+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos         (7U)
+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos         (8U)
+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos         (9U)
+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos         (10U)
+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos         (11U)
+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos         (12U)
+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos         (13U)
+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos         (14U)
+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos         (15U)
+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos         (16U)
+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM82_Pos         (18U)
+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos         (20U)
+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos         (21U)
+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos         (22U)
+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos         (23U)
+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
+
+
+/*******************  Bit definition for EXTI_EMR3 register  *******************/
+#define EXTI_EMR3_EM_Pos           (0U)
+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
+#define EXTI_EMR3_EM64_Pos         (0U)
+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos         (1U)
+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos         (2U)
+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos         (3U)
+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos         (4U)
+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos         (5U)
+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos         (6U)
+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos         (7U)
+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos         (8U)
+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos         (9U)
+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos         (10U)
+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos         (11U)
+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos         (12U)
+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos         (13U)
+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos         (14U)
+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos         (15U)
+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos         (16U)
+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos         (17U)
+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos         (18U)
+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos         (20U)
+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos         (21U)
+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos         (22U)
+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos         (23U)
+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
+
+/*******************  Bit definition for EXTI_PR3 register  ********************/
+#define EXTI_PR3_PR_Pos            (18U)
+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */
+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR3_PR82_Pos          (18U)
+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
+#define EXTI_PR3_PR84_Pos          (20U)
+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */
+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */
+#define EXTI_PR3_PR85_Pos          (21U)
+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
+#define EXTI_PR3_PR86_Pos          (22U)
+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */
+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Global Defines
+*/
+#if defined(CORE_CM4)
+#define FLASH_SIZE                           0x100000UL            /* 1 MB   */
+#else
+#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
+#define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+                                             (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
+#endif /* CORE_CM4 */
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */
+#define DUAL_BANK                                                  /* Dual-bank Flash */
+
+/*******************  Bits definition for FLASH_ACR register  **********************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
+/*******************  Bits definition for FLASH_CR register  ***********************/
+#define FLASH_CR_LOCK_Pos                    (0U)
+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
+#define FLASH_CR_PG_Pos                      (1U)
+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
+#define FLASH_CR_SER_Pos                     (2U)
+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
+#define FLASH_CR_BER_Pos                     (3U)
+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
+#define FLASH_CR_PSIZE_Pos                   (4U)
+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */
+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */
+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */
+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */
+#define FLASH_CR_FW_Pos                      (6U)
+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */
+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
+#define FLASH_CR_START_Pos                   (7U)
+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */
+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
+#define FLASH_CR_SNB_Pos                     (8U)
+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */
+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */
+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */
+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */
+#define FLASH_CR_CRC_EN_Pos                  (15U)
+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
+#define FLASH_CR_EOPIE_Pos                   (16U)
+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
+#define FLASH_CR_WRPERRIE_Pos                (17U)
+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
+#define FLASH_CR_PGSERRIE_Pos                (18U)
+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
+#define FLASH_CR_STRBERRIE_Pos               (19U)
+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
+#define FLASH_CR_INCERRIE_Pos                (21U)
+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
+#define FLASH_CR_OPERRIE_Pos                 (22U)
+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */
+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */
+#define FLASH_CR_RDPERRIE_Pos                (23U)
+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
+#define FLASH_CR_RDSERRIE_Pos                (24U)
+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
+#define FLASH_CR_SNECCERRIE_Pos              (25U)
+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
+#define FLASH_CR_DBECCERRIE_Pos              (26U)
+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
+#define FLASH_CR_CRCENDIE_Pos                (27U)
+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
+#define FLASH_CR_CRCRDERRIE_Pos              (28U)
+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
+
+/*******************  Bits definition for FLASH_SR register  ***********************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
+#define FLASH_SR_WBNE_Pos                    (1U)
+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
+#define FLASH_SR_QW_Pos                      (2U)
+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
+#define FLASH_SR_CRC_BUSY_Pos                (3U)
+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
+#define FLASH_SR_EOP_Pos                     (16U)
+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
+#define FLASH_SR_WRPERR_Pos                  (17U)
+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
+#define FLASH_SR_PGSERR_Pos                  (18U)
+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
+#define FLASH_SR_STRBERR_Pos                 (19U)
+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
+#define FLASH_SR_INCERR_Pos                  (21U)
+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
+#define FLASH_SR_OPERR_Pos                   (22U)
+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */
+#define FLASH_SR_RDPERR_Pos                  (23U)
+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
+#define FLASH_SR_RDSERR_Pos                  (24U)
+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
+#define FLASH_SR_SNECCERR_Pos                (25U)
+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
+#define FLASH_SR_DBECCERR_Pos                (26U)
+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
+#define FLASH_SR_CRCEND_Pos                  (27U)
+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
+#define FLASH_SR_CRCRDERR_Pos                (28U)
+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
+
+/*******************  Bits definition for FLASH_CCR register  *******************/
+#define FLASH_CCR_CLR_EOP_Pos                (16U)
+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)
+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)
+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)
+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
+#define FLASH_CCR_CLR_INCERR_Pos             (21U)
+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
+#define FLASH_CCR_CLR_OPERR_Pos              (22U)
+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */
+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)
+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)
+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)
+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
+
+/*******************  Bits definition for FLASH_OPTCR register  *******************/
+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
+#define FLASH_OPTCR_OPTSTART_Pos             (1U)
+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
+#define FLASH_OPTCR_MER_Pos                  (4U)
+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
+
+/*******************  Bits definition for FLASH_OPTSR register  ***************/
+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)
+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
+#define FLASH_OPTSR_IWDG2_SW_Pos             (5U)
+#define FLASH_OPTSR_IWDG2_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTSR_IWDG2_SW                 FLASH_OPTSR_IWDG2_SW_Msk            /*!< IWDG2 control mode option status bit */
+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_RDP_Pos                  (8U)
+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
+#define FLASH_OPTSR_SECURITY_Pos             (21U)
+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
+#define FLASH_OPTSR_BCM4_Pos                 (22U)
+#define FLASH_OPTSR_BCM4_Msk                 (0x1UL << FLASH_OPTSR_BCM4_Pos)   /*!< 0x00400000 */
+#define FLASH_OPTSR_BCM4                     FLASH_OPTSR_BCM4_Msk              /*!< Arm Cortex-M4 boot option status bit */
+#define FLASH_OPTSR_BCM7_Pos                 (23U)
+#define FLASH_OPTSR_BCM7_Msk                 (0x1UL << FLASH_OPTSR_BCM7_Pos)   /*!< 0x00800000 */
+#define FLASH_OPTSR_BCM7                     FLASH_OPTSR_BCM7_Msk              /*!< Arm Cortex-M7 boot option status bit */
+#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)
+#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */
+#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)
+#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */
+#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)
+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
+
+/*******************  Bits definition for FLASH_OPTCCR register  *******************/
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
+
+/*******************  Bits definition for FLASH_PRAR register  *********************/
+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
+#define FLASH_PRAR_DMEP_Pos                  (31U)
+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_SCAR register  *********************/
+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
+#define FLASH_SCAR_DMES_Pos                  (31U)
+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_WPSN register  *********************/
+#define FLASH_WPSN_WRPSN_Pos                 (0U)
+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */
+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
+
+/*******************  Bits definition for FLASH_BOOT7_CUR register  ****************/
+#define FLASH_BOOT7_BCM7_ADD0_Pos            (0U)
+#define FLASH_BOOT7_BCM7_ADD0_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT7_BCM7_ADD0                FLASH_BOOT7_BCM7_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
+#define FLASH_BOOT7_BCM7_ADD1_Pos            (16U)
+#define FLASH_BOOT7_BCM7_ADD1_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT7_BCM7_ADD1                FLASH_BOOT7_BCM7_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
+
+/*******************  Bits definition for FLASH_BOOT4 register  ********************/
+#define FLASH_BOOT4_BCM4_ADD0_Pos            (0U)
+#define FLASH_BOOT4_BCM4_ADD0_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT4_BCM4_ADD0                FLASH_BOOT4_BCM4_ADD0_Msk               /*!< Arm Cortex-M4 boot address 0 */
+#define FLASH_BOOT4_BCM4_ADD1_Pos            (16U)
+#define FLASH_BOOT4_BCM4_ADD1_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT4_BCM4_ADD1                FLASH_BOOT4_BCM4_ADD1_Msk               /*!< Arm Cortex-M4 boot address 1 */
+
+/*******************  Bits definition for FLASH_CRCCR register  ********************/
+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */
+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)
+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
+#define FLASH_CRCCR_START_CRC_Pos            (16U)
+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)
+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
+
+/*******************  Bits definition for FLASH_CRCSADD register  ****************/
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
+
+/*******************  Bits definition for FLASH_CRCEADD register  ****************/
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
+
+/*******************  Bits definition for FLASH_CRCDATA register  ***************/
+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
+
+/*******************  Bits definition for FLASH_ECC_FA register  *******************/
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)
+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+#define FMC_BCR1_BMAP_Pos          (24U)
+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
+
+#define FMC_BCR1_FMCEN_Pos         (31U)
+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos             (0U)
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos       (0U)
+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos      (8U)
+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos      (16U)
+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos       (24U)
+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET_Pos       (0U)
+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos      (8U)
+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos      (16U)
+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos       (24U)
+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos         (0U)
+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
+
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
+
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
+
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
+
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
+
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDCRx_RBURST_Pos       (12U)
+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
+
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
+
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
+
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
+
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
+
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
+
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
+
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos         (3U)
+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos         (4U)
+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos        (1U)
+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************************************************************************/
+/*                                                                            */
+/*                        HSEM HW Semaphore                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for HSEM_R register  ********************/
+#define HSEM_R_PROCID_Pos         (0U)
+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos         (8U)
+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
+#define HSEM_R_LOCK_Pos           (31U)
+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_RLR register  ******************/
+#define HSEM_RLR_PROCID_Pos       (0U)
+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos       (8U)
+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
+#define HSEM_RLR_LOCK_Pos         (31U)
+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_C1IER register  *****************/
+#define HSEM_C1IER_ISE0_Pos       (0U)
+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE1_Pos       (1U)
+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE2_Pos       (2U)
+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE3_Pos       (3U)
+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE4_Pos       (4U)
+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE5_Pos       (5U)
+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE6_Pos       (6U)
+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE7_Pos       (7U)
+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE8_Pos       (8U)
+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE9_Pos       (9U)
+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE10_Pos      (10U)
+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE11_Pos      (11U)
+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE12_Pos      (12U)
+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE13_Pos      (13U)
+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE14_Pos      (14U)
+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE15_Pos      (15U)
+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos      (16U)
+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos      (17U)
+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos      (18U)
+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos      (19U)
+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos      (20U)
+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos      (21U)
+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos      (22U)
+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos      (23U)
+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos      (24U)
+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos      (25U)
+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos      (26U)
+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos      (27U)
+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos      (28U)
+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos      (29U)
+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos      (30U)
+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos      (31U)
+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
+
+/********************  Bit definition for HSEM_C1ICR register  *****************/
+#define HSEM_C1ICR_ISC0_Pos       (0U)
+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC1_Pos       (1U)
+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC2_Pos       (2U)
+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC3_Pos       (3U)
+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC4_Pos       (4U)
+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC5_Pos       (5U)
+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC6_Pos       (6U)
+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC7_Pos       (7U)
+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC8_Pos       (8U)
+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC9_Pos       (9U)
+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC10_Pos      (10U)
+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos      (11U)
+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos      (12U)
+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos      (13U)
+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos      (14U)
+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos      (15U)
+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos      (16U)
+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos      (17U)
+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos      (18U)
+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos      (19U)
+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos      (20U)
+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos      (21U)
+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos      (22U)
+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos      (23U)
+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos      (24U)
+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos      (25U)
+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos      (26U)
+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos      (27U)
+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos      (28U)
+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos      (29U)
+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos      (30U)
+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos      (31U)
+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
+
+/********************  Bit definition for HSEM_C1ISR register  *****************/
+#define HSEM_C1ISR_ISF0_Pos       (0U)
+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF1_Pos       (1U)
+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF2_Pos       (2U)
+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF3_Pos       (3U)
+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF4_Pos       (4U)
+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF5_Pos       (5U)
+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF6_Pos       (6U)
+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF7_Pos       (7U)
+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF8_Pos       (8U)
+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF9_Pos       (9U)
+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF10_Pos      (10U)
+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos      (11U)
+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos      (12U)
+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos      (13U)
+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos      (14U)
+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos      (15U)
+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos      (16U)
+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos      (17U)
+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos      (18U)
+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos      (19U)
+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos      (20U)
+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos      (21U)
+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos      (22U)
+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos      (23U)
+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos      (24U)
+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos      (25U)
+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos      (26U)
+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos      (27U)
+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos      (28U)
+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos      (29U)
+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos      (30U)
+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos      (31U)
+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
+
+/********************  Bit definition for HSEM_C1MISR register  *****************/
+#define HSEM_C1MISR_MISF0_Pos     (0U)
+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF1_Pos     (1U)
+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF2_Pos     (2U)
+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF3_Pos     (3U)
+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF4_Pos     (4U)
+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF5_Pos     (5U)
+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF6_Pos     (6U)
+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF7_Pos     (7U)
+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF8_Pos     (8U)
+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF9_Pos     (9U)
+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF10_Pos    (10U)
+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos    (11U)
+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos    (12U)
+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos    (13U)
+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos    (14U)
+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos    (15U)
+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos    (16U)
+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos    (17U)
+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos    (18U)
+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos    (19U)
+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos    (20U)
+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos    (21U)
+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos    (22U)
+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos    (23U)
+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos    (24U)
+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos    (25U)
+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos    (26U)
+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos    (27U)
+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos    (28U)
+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos    (29U)
+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos    (30U)
+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos    (31U)
+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/********************  Bit definition for HSEM_C2IER register  *****************/
+#define HSEM_C2IER_ISE0_Pos       (0U)
+#define HSEM_C2IER_ISE0_Msk       (0x1UL << HSEM_C2IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C2IER_ISE0           HSEM_C2IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE1_Pos       (1U)
+#define HSEM_C2IER_ISE1_Msk       (0x1UL << HSEM_C2IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C2IER_ISE1           HSEM_C2IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE2_Pos       (2U)
+#define HSEM_C2IER_ISE2_Msk       (0x1UL << HSEM_C2IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C2IER_ISE2           HSEM_C2IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE3_Pos       (3U)
+#define HSEM_C2IER_ISE3_Msk       (0x1UL << HSEM_C2IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C2IER_ISE3           HSEM_C2IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE4_Pos       (4U)
+#define HSEM_C2IER_ISE4_Msk       (0x1UL << HSEM_C2IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C2IER_ISE4           HSEM_C2IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE5_Pos       (5U)
+#define HSEM_C2IER_ISE5_Msk       (0x1UL << HSEM_C2IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C2IER_ISE5           HSEM_C2IER_ISE5_Msk                          /*!<semaphore 5 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE6_Pos       (6U)
+#define HSEM_C2IER_ISE6_Msk       (0x1UL << HSEM_C2IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C2IER_ISE6           HSEM_C2IER_ISE6_Msk                          /*!<semaphore 6 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE7_Pos       (7U)
+#define HSEM_C2IER_ISE7_Msk       (0x1UL << HSEM_C2IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C2IER_ISE7           HSEM_C2IER_ISE7_Msk                          /*!<semaphore 7 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE8_Pos       (8U)
+#define HSEM_C2IER_ISE8_Msk       (0x1UL << HSEM_C2IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C2IER_ISE8           HSEM_C2IER_ISE8_Msk                          /*!<semaphore 8 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE9_Pos       (9U)
+#define HSEM_C2IER_ISE9_Msk       (0x1UL << HSEM_C2IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C2IER_ISE9           HSEM_C2IER_ISE9_Msk                          /*!<semaphore 9 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE10_Pos      (10U)
+#define HSEM_C2IER_ISE10_Msk      (0x1UL << HSEM_C2IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C2IER_ISE10          HSEM_C2IER_ISE10_Msk                         /*!<semaphore 10 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE11_Pos      (11U)
+#define HSEM_C2IER_ISE11_Msk      (0x1UL << HSEM_C2IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C2IER_ISE11          HSEM_C2IER_ISE11_Msk                         /*!<semaphore 11 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE12_Pos      (12U)
+#define HSEM_C2IER_ISE12_Msk      (0x1UL << HSEM_C2IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C2IER_ISE12          HSEM_C2IER_ISE12_Msk                         /*!<semaphore 12 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE13_Pos      (13U)
+#define HSEM_C2IER_ISE13_Msk      (0x1UL << HSEM_C2IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C2IER_ISE13          HSEM_C2IER_ISE13_Msk                         /*!<semaphore 13 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE14_Pos      (14U)
+#define HSEM_C2IER_ISE14_Msk      (0x1UL << HSEM_C2IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C2IER_ISE14          HSEM_C2IER_ISE14_Msk                         /*!<semaphore 14 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE15_Pos      (15U)
+#define HSEM_C2IER_ISE15_Msk      (0x1UL << HSEM_C2IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C2IER_ISE15          HSEM_C2IER_ISE15_Msk                         /*!<semaphore 15 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE16_Pos      (16U)
+#define HSEM_C2IER_ISE16_Msk      (0x1UL << HSEM_C2IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C2IER_ISE16          HSEM_C2IER_ISE16_Msk                         /*!<semaphore 16 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE17_Pos      (17U)
+#define HSEM_C2IER_ISE17_Msk      (0x1UL << HSEM_C2IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C2IER_ISE17          HSEM_C2IER_ISE17_Msk                         /*!<semaphore 17 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE18_Pos      (18U)
+#define HSEM_C2IER_ISE18_Msk      (0x1UL << HSEM_C2IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C2IER_ISE18          HSEM_C2IER_ISE18_Msk                         /*!<semaphore 18 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE19_Pos      (19U)
+#define HSEM_C2IER_ISE19_Msk      (0x1UL << HSEM_C2IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C2IER_ISE19          HSEM_C2IER_ISE19_Msk                         /*!<semaphore 19 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE20_Pos      (20U)
+#define HSEM_C2IER_ISE20_Msk      (0x1UL << HSEM_C2IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C2IER_ISE20          HSEM_C2IER_ISE20_Msk                         /*!<semaphore 20 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE21_Pos      (21U)
+#define HSEM_C2IER_ISE21_Msk      (0x1UL << HSEM_C2IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C2IER_ISE21          HSEM_C2IER_ISE21_Msk                         /*!<semaphore 21 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE22_Pos      (22U)
+#define HSEM_C2IER_ISE22_Msk      (0x1UL << HSEM_C2IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C2IER_ISE22          HSEM_C2IER_ISE22_Msk                         /*!<semaphore 22 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE23_Pos      (23U)
+#define HSEM_C2IER_ISE23_Msk      (0x1UL << HSEM_C2IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C2IER_ISE23          HSEM_C2IER_ISE23_Msk                         /*!<semaphore 23 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE24_Pos      (24U)
+#define HSEM_C2IER_ISE24_Msk      (0x1UL << HSEM_C2IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C2IER_ISE24          HSEM_C2IER_ISE24_Msk                         /*!<semaphore 24 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE25_Pos      (25U)
+#define HSEM_C2IER_ISE25_Msk      (0x1UL << HSEM_C2IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C2IER_ISE25          HSEM_C2IER_ISE25_Msk                         /*!<semaphore 25 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE26_Pos      (26U)
+#define HSEM_C2IER_ISE26_Msk      (0x1UL << HSEM_C2IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C2IER_ISE26          HSEM_C2IER_ISE26_Msk                         /*!<semaphore 26 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE27_Pos      (27U)
+#define HSEM_C2IER_ISE27_Msk      (0x1UL << HSEM_C2IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C2IER_ISE27          HSEM_C2IER_ISE27_Msk                         /*!<semaphore 27 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE28_Pos      (28U)
+#define HSEM_C2IER_ISE28_Msk      (0x1UL << HSEM_C2IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C2IER_ISE28          HSEM_C2IER_ISE28_Msk                         /*!<semaphore 28 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE29_Pos      (29U)
+#define HSEM_C2IER_ISE29_Msk      (0x1UL << HSEM_C2IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C2IER_ISE29          HSEM_C2IER_ISE29_Msk                         /*!<semaphore 29 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE30_Pos      (30U)
+#define HSEM_C2IER_ISE30_Msk      (0x1UL << HSEM_C2IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C2IER_ISE30          HSEM_C2IER_ISE30_Msk                         /*!<semaphore 30 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE31_Pos      (31U)
+#define HSEM_C2IER_ISE31_Msk      (0x1UL << HSEM_C2IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C2IER_ISE31          HSEM_C2IER_ISE31_Msk                         /*!<semaphore 31 interrupt 1 enable bit. */
+
+/********************  Bit definition for HSEM_C2ICR register  *****************/
+#define HSEM_C2ICR_ISC0_Pos       (0U)
+#define HSEM_C2ICR_ISC0_Msk       (0x1UL << HSEM_C2ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C2ICR_ISC0           HSEM_C2ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC1_Pos       (1U)
+#define HSEM_C2ICR_ISC1_Msk       (0x1UL << HSEM_C2ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C2ICR_ISC1           HSEM_C2ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC2_Pos       (2U)
+#define HSEM_C2ICR_ISC2_Msk       (0x1UL << HSEM_C2ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C2ICR_ISC2           HSEM_C2ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC3_Pos       (3U)
+#define HSEM_C2ICR_ISC3_Msk       (0x1UL << HSEM_C2ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C2ICR_ISC3           HSEM_C2ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC4_Pos       (4U)
+#define HSEM_C2ICR_ISC4_Msk       (0x1UL << HSEM_C2ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C2ICR_ISC4           HSEM_C2ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC5_Pos       (5U)
+#define HSEM_C2ICR_ISC5_Msk       (0x1UL << HSEM_C2ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C2ICR_ISC5           HSEM_C2ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC6_Pos       (6U)
+#define HSEM_C2ICR_ISC6_Msk       (0x1UL << HSEM_C2ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C2ICR_ISC6           HSEM_C2ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC7_Pos       (7U)
+#define HSEM_C2ICR_ISC7_Msk       (0x1UL << HSEM_C2ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C2ICR_ISC7           HSEM_C2ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC8_Pos       (8U)
+#define HSEM_C2ICR_ISC8_Msk       (0x1UL << HSEM_C2ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C2ICR_ISC8           HSEM_C2ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC9_Pos       (9U)
+#define HSEM_C2ICR_ISC9_Msk       (0x1UL << HSEM_C2ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C2ICR_ISC9           HSEM_C2ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC10_Pos      (10U)
+#define HSEM_C2ICR_ISC10_Msk      (0x1UL << HSEM_C2ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C2ICR_ISC10          HSEM_C2ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC11_Pos      (11U)
+#define HSEM_C2ICR_ISC11_Msk      (0x1UL << HSEM_C2ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C2ICR_ISC11          HSEM_C2ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC12_Pos      (12U)
+#define HSEM_C2ICR_ISC12_Msk      (0x1UL << HSEM_C2ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C2ICR_ISC12          HSEM_C2ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC13_Pos      (13U)
+#define HSEM_C2ICR_ISC13_Msk      (0x1UL << HSEM_C2ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C2ICR_ISC13          HSEM_C2ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC14_Pos      (14U)
+#define HSEM_C2ICR_ISC14_Msk      (0x1UL << HSEM_C2ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C2ICR_ISC14          HSEM_C2ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC15_Pos      (15U)
+#define HSEM_C2ICR_ISC15_Msk      (0x1UL << HSEM_C2ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C2ICR_ISC15          HSEM_C2ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC16_Pos      (16U)
+#define HSEM_C2ICR_ISC16_Msk      (0x1UL << HSEM_C2ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C2ICR_ISC16          HSEM_C2ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC17_Pos      (17U)
+#define HSEM_C2ICR_ISC17_Msk      (0x1UL << HSEM_C2ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C2ICR_ISC17          HSEM_C2ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC18_Pos      (18U)
+#define HSEM_C2ICR_ISC18_Msk      (0x1UL << HSEM_C2ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C2ICR_ISC18          HSEM_C2ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC19_Pos      (19U)
+#define HSEM_C2ICR_ISC19_Msk      (0x1UL << HSEM_C2ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C2ICR_ISC19          HSEM_C2ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC20_Pos      (20U)
+#define HSEM_C2ICR_ISC20_Msk      (0x1UL << HSEM_C2ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C2ICR_ISC20          HSEM_C2ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC21_Pos      (21U)
+#define HSEM_C2ICR_ISC21_Msk      (0x1UL << HSEM_C2ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C2ICR_ISC21          HSEM_C2ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC22_Pos      (22U)
+#define HSEM_C2ICR_ISC22_Msk      (0x1UL << HSEM_C2ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C2ICR_ISC22          HSEM_C2ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC23_Pos      (23U)
+#define HSEM_C2ICR_ISC23_Msk      (0x1UL << HSEM_C2ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C2ICR_ISC23          HSEM_C2ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC24_Pos      (24U)
+#define HSEM_C2ICR_ISC24_Msk      (0x1UL << HSEM_C2ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C2ICR_ISC24          HSEM_C2ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC25_Pos      (25U)
+#define HSEM_C2ICR_ISC25_Msk      (0x1UL << HSEM_C2ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C2ICR_ISC25          HSEM_C2ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC26_Pos      (26U)
+#define HSEM_C2ICR_ISC26_Msk      (0x1UL << HSEM_C2ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C2ICR_ISC26          HSEM_C2ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC27_Pos      (27U)
+#define HSEM_C2ICR_ISC27_Msk      (0x1UL << HSEM_C2ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C2ICR_ISC27          HSEM_C2ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC28_Pos      (28U)
+#define HSEM_C2ICR_ISC28_Msk      (0x1UL << HSEM_C2ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C2ICR_ISC28          HSEM_C2ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC29_Pos      (29U)
+#define HSEM_C2ICR_ISC29_Msk      (0x1UL << HSEM_C2ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C2ICR_ISC29          HSEM_C2ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC30_Pos      (30U)
+#define HSEM_C2ICR_ISC30_Msk      (0x1UL << HSEM_C2ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C2ICR_ISC30          HSEM_C2ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC31_Pos      (31U)
+#define HSEM_C2ICR_ISC31_Msk      (0x1UL << HSEM_C2ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C2ICR_ISC31          HSEM_C2ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 1 clear bit. */
+
+/********************  Bit definition for HSEM_C2ISR register  *****************/
+#define HSEM_C2ISR_ISF0_Pos       (0U)
+#define HSEM_C2ISR_ISF0_Msk       (0x1UL << HSEM_C2ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C2ISR_ISF0           HSEM_C2ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF1_Pos       (1U)
+#define HSEM_C2ISR_ISF1_Msk       (0x1UL << HSEM_C2ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C2ISR_ISF1           HSEM_C2ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF2_Pos       (2U)
+#define HSEM_C2ISR_ISF2_Msk       (0x1UL << HSEM_C2ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C2ISR_ISF2           HSEM_C2ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF3_Pos       (3U)
+#define HSEM_C2ISR_ISF3_Msk       (0x1UL << HSEM_C2ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C2ISR_ISF3           HSEM_C2ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF4_Pos       (4U)
+#define HSEM_C2ISR_ISF4_Msk       (0x1UL << HSEM_C2ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C2ISR_ISF4           HSEM_C2ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF5_Pos       (5U)
+#define HSEM_C2ISR_ISF5_Msk       (0x1UL << HSEM_C2ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C2ISR_ISF5           HSEM_C2ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF6_Pos       (6U)
+#define HSEM_C2ISR_ISF6_Msk       (0x1UL << HSEM_C2ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C2ISR_ISF6           HSEM_C2ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF7_Pos       (7U)
+#define HSEM_C2ISR_ISF7_Msk       (0x1UL << HSEM_C2ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C2ISR_ISF7           HSEM_C2ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF8_Pos       (8U)
+#define HSEM_C2ISR_ISF8_Msk       (0x1UL << HSEM_C2ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C2ISR_ISF8           HSEM_C2ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF9_Pos       (9U)
+#define HSEM_C2ISR_ISF9_Msk       (0x1UL << HSEM_C2ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C2ISR_ISF9           HSEM_C2ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF10_Pos      (10U)
+#define HSEM_C2ISR_ISF10_Msk      (0x1UL << HSEM_C2ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C2ISR_ISF10          HSEM_C2ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF11_Pos      (11U)
+#define HSEM_C2ISR_ISF11_Msk      (0x1UL << HSEM_C2ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C2ISR_ISF11          HSEM_C2ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF12_Pos      (12U)
+#define HSEM_C2ISR_ISF12_Msk      (0x1UL << HSEM_C2ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C2ISR_ISF12          HSEM_C2ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF13_Pos      (13U)
+#define HSEM_C2ISR_ISF13_Msk      (0x1UL << HSEM_C2ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C2ISR_ISF13          HSEM_C2ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF14_Pos      (14U)
+#define HSEM_C2ISR_ISF14_Msk      (0x1UL << HSEM_C2ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C2ISR_ISF14          HSEM_C2ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF15_Pos      (15U)
+#define HSEM_C2ISR_ISF15_Msk      (0x1UL << HSEM_C2ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C2ISR_ISF15          HSEM_C2ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF16_Pos      (16U)
+#define HSEM_C2ISR_ISF16_Msk      (0x1UL << HSEM_C2ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C2ISR_ISF16          HSEM_C2ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF17_Pos      (17U)
+#define HSEM_C2ISR_ISF17_Msk      (0x1UL << HSEM_C2ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C2ISR_ISF17          HSEM_C2ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF18_Pos      (18U)
+#define HSEM_C2ISR_ISF18_Msk      (0x1UL << HSEM_C2ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C2ISR_ISF18          HSEM_C2ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF19_Pos      (19U)
+#define HSEM_C2ISR_ISF19_Msk      (0x1UL << HSEM_C2ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C2ISR_ISF19          HSEM_C2ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF20_Pos      (20U)
+#define HSEM_C2ISR_ISF20_Msk      (0x1UL << HSEM_C2ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C2ISR_ISF20          HSEM_C2ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF21_Pos      (21U)
+#define HSEM_C2ISR_ISF21_Msk      (0x1UL << HSEM_C2ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C2ISR_ISF21          HSEM_C2ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF22_Pos      (22U)
+#define HSEM_C2ISR_ISF22_Msk      (0x1UL << HSEM_C2ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C2ISR_ISF22          HSEM_C2ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF23_Pos      (23U)
+#define HSEM_C2ISR_ISF23_Msk      (0x1UL << HSEM_C2ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C2ISR_ISF23          HSEM_C2ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF24_Pos      (24U)
+#define HSEM_C2ISR_ISF24_Msk      (0x1UL << HSEM_C2ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C2ISR_ISF24          HSEM_C2ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF25_Pos      (25U)
+#define HSEM_C2ISR_ISF25_Msk      (0x1UL << HSEM_C2ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C2ISR_ISF25          HSEM_C2ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF26_Pos      (26U)
+#define HSEM_C2ISR_ISF26_Msk      (0x1UL << HSEM_C2ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C2ISR_ISF26          HSEM_C2ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF27_Pos      (27U)
+#define HSEM_C2ISR_ISF27_Msk      (0x1UL << HSEM_C2ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C2ISR_ISF27          HSEM_C2ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF28_Pos      (28U)
+#define HSEM_C2ISR_ISF28_Msk      (0x1UL << HSEM_C2ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C2ISR_ISF28          HSEM_C2ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF29_Pos      (29U)
+#define HSEM_C2ISR_ISF29_Msk      (0x1UL << HSEM_C2ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C2ISR_ISF29          HSEM_C2ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF30_Pos      (30U)
+#define HSEM_C2ISR_ISF30_Msk      (0x1UL << HSEM_C2ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C2ISR_ISF30          HSEM_C2ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF31_Pos      (31U)
+#define HSEM_C2ISR_ISF31_Msk      (0x1UL << HSEM_C2ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C2ISR_ISF31          HSEM_C2ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 1 status bit. */
+
+/********************  Bit definition for HSEM_C2MISR register  *****************/
+#define HSEM_C2MISR_MISF0_Pos     (0U)
+#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF1_Pos     (1U)
+#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF2_Pos     (2U)
+#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF3_Pos     (3U)
+#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF4_Pos     (4U)
+#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF5_Pos     (5U)
+#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF6_Pos     (6U)
+#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF7_Pos     (7U)
+#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF8_Pos     (8U)
+#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF9_Pos     (9U)
+#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF10_Pos    (10U)
+#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF11_Pos    (11U)
+#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF12_Pos    (12U)
+#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF13_Pos    (13U)
+#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF14_Pos    (14U)
+#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF15_Pos    (15U)
+#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF16_Pos    (16U)
+#define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF17_Pos    (17U)
+#define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF18_Pos    (18U)
+#define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF19_Pos    (19U)
+#define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF20_Pos    (20U)
+#define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF21_Pos    (21U)
+#define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF22_Pos    (22U)
+#define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF23_Pos    (23U)
+#define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF24_Pos    (24U)
+#define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF25_Pos    (25U)
+#define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF26_Pos    (26U)
+#define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF27_Pos    (27U)
+#define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF28_Pos    (28U)
+#define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF29_Pos    (29U)
+#define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF30_Pos    (30U)
+#define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF31_Pos    (31U)
+#define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 1 masked status bit. */
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CR_COREID_Pos        (8U)
+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos           (16U)
+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
+
+/********************  Bit definition for HSEM_KEYR register  *****************/
+#define HSEM_KEYR_KEY_Pos         (16U)
+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (4U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (5U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW_Pos            (16U)
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP_Pos           (16U)
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */
+#define LTDC_AWCR_AAW_Pos            (16U)
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total height */
+#define LTDC_TWCR_TOTALW_Pos         (16U)
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW_Pos             (4U)
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW_Pos             (8U)
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW_Pos             (12U)
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN_Pos             (16U)
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL_Pos           (28U)
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL_Pos           (29U)
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL_Pos           (30U)
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL_Pos           (31U)
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR_Pos            (1U)
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE_Pos            (1U)
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE_Pos          (2U)
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE_Pos            (3U)
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES_Pos           (1U)
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN_Pos         (1U)
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     MDMA                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDMA_GISR0 register  ****************/
+#define MDMA_GISR0_GIF0_Pos       (0U)
+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos       (1U)
+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos       (2U)
+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos       (3U)
+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos       (4U)
+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos       (5U)
+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos       (6U)
+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos       (7U)
+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos       (8U)
+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos       (9U)
+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos      (10U)
+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos      (11U)
+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos      (12U)
+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos      (13U)
+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos      (14U)
+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos      (15U)
+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
+
+/********************  Bit definition for MDMA_CxISR register  ****************/
+#define MDMA_CISR_TEIF_Pos        (0U)
+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos       (1U)
+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos       (2U)
+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos        (3U)
+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos        (4U)
+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos        (16U)
+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x request Active flag */
+
+/********************  Bit definition for MDMA_CxIFCR register  ****************/
+#define MDMA_CIFCR_CTEIF_Pos      (0U)
+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos     (1U)
+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos     (2U)
+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos      (3U)
+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos     (4U)
+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/********************  Bit definition for MDMA_CxESR register  ****************/
+#define MDMA_CESR_TEA_Pos         (0U)
+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos         (7U)
+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos        (8U)
+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos        (9U)
+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos         (10U)
+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
+#define MDMA_CESR_BSE_Pos         (11U)
+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
+
+/********************  Bit definition for MDMA_CxCR register  ****************/
+#define MDMA_CCR_EN_Pos           (0U)
+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos         (1U)
+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos        (2U)
+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos        (3U)
+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos         (4U)
+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos         (5U)
+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos           (6U)
+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
+#define MDMA_CCR_BEX_Pos          (12U)
+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianness eXchange */
+#define MDMA_CCR_HEX_Pos          (13U)
+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianness eXchange */
+#define MDMA_CCR_WEX_Pos          (14U)
+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianness eXchange */
+#define MDMA_CCR_SWRQ_Pos         (16U)
+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
+
+/********************  Bit definition for MDMA_CxTCR register  ****************/
+#define MDMA_CTCR_SINC_Pos        (0U)
+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos        (2U)
+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos       (4U)
+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos       (6U)
+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos      (8U)
+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos      (10U)
+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos      (12U)
+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
+#define MDMA_CTCR_DBURST_Pos      (15U)
+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos        (18U)
+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos         (25U)
+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos         (26U)
+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignment Mode */
+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos        (28U)
+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos        (30U)
+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos         (31U)
+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
+
+/********************  Bit definition for MDMA_CxBNDTR register  ****************/
+#define MDMA_CBNDTR_BNDT_Pos      (0U)
+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos     (18U)
+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos     (19U)
+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos       (20U)
+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
+
+/********************  Bit definition for MDMA_CxSAR register  ****************/
+#define MDMA_CSAR_SAR_Pos         (0U)
+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
+
+/********************  Bit definition for MDMA_CxDAR register  ****************/
+#define MDMA_CDAR_DAR_Pos         (0U)
+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
+
+/********************  Bit definition for MDMA_CxBRUR  ************************/
+#define MDMA_CBRUR_SUV_Pos        (0U)
+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos        (16U)
+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
+
+/********************  Bit definition for MDMA_CxLAR  *************************/
+#define MDMA_CLAR_LAR_Pos         (0U)
+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
+
+/********************  Bit definition for MDMA_CxTBR)  ************************/
+#define MDMA_CTBR_TSEL_Pos        (0U)
+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos        (16U)
+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos        (17U)
+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
+
+/********************  Bit definition for MDMA_CxMAR)  ************************/
+#define MDMA_CMAR_MAR_Pos         (0U)
+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
+
+/********************  Bit definition for MDMA_CxMDR)  ************************/
+#define MDMA_CMDR_MDR_Pos         (0U)
+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos            (1U)
+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos              (2U)
+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos              (5U)
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos             (8U)
+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos              (11U)
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos             (12U)
+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (14U)
+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos           (18U)
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos             (29U)
+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos             (30U)
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos            (1U)
+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos              (2U)
+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (5U)
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos             (8U)
+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos              (11U)
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos             (12U)
+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos             (14U)
+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos           (18U)
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos             (29U)
+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos             (30U)
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos            (1U)
+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos              (2U)
+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (5U)
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos             (8U)
+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos              (11U)
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos             (12U)
+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos             (14U)
+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos           (18U)
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos             (29U)
+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos             (30U)
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_HSOTR register  ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*************************  NUMBER OF POWER DOMAINS  **************************/
+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */
+
+/********************  Bit definition for PWR_CR1 register  *******************/
+#define PWR_CR1_ALS_Pos                (17U)
+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
+#define PWR_CR1_AVDEN_Pos              (16U)
+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
+#define PWR_CR1_SVOS_Pos               (14U)
+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
+#define PWR_CR1_FLPS_Pos               (9U)
+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
+#define PWR_CR1_DBP_Pos                (8U)
+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos                (5U)
+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
+#define PWR_CR1_PVDEN_Pos              (4U)
+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR1_LPDS_Pos               (0U)
+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos           (5U)
+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos           (6U)
+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos           (5U)
+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos           (7U)
+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos           (5U)
+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos           (6U)
+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos           (5U)
+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos           (17U)
+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos           (18U)
+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos           (17U)
+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
+
+/********************  Bit definition for PWR_CSR1 register  ******************/
+#define PWR_CSR1_AVDO_Pos              (16U)
+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
+#define PWR_CSR1_ACTVOS_Pos            (14U)
+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)
+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
+#define PWR_CSR1_PVDO_Pos              (4U)
+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
+
+/********************  Bit definition for PWR_CR2 register  *******************/
+#define PWR_CR2_TEMPH_Pos              (23U)
+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
+#define PWR_CR2_TEMPL_Pos              (22U)
+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
+#define PWR_CR2_VBATH_Pos              (21U)
+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
+#define PWR_CR2_VBATL_Pos              (20U)
+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
+#define PWR_CR2_BRRDY_Pos              (16U)
+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
+#define PWR_CR2_MONEN_Pos              (4U)
+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BREN_Pos               (0U)
+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
+
+/********************  Bit definition for PWR_CR3 register  *******************/
+#define PWR_CR3_USB33RDY_Pos           (26U)
+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
+#define PWR_CR3_USBREGEN_Pos           (25U)
+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
+#define PWR_CR3_USB33DEN_Pos           (24U)
+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)
+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */
+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */
+#define PWR_CR3_VBRS_Pos               (9U)
+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
+#define PWR_CR3_VBE_Pos                (8U)
+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
+#define PWR_CR3_SMPSLEVEL_Pos          (4U)
+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */
+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */
+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */
+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */
+#define PWR_CR3_SMPSEXTHP_Pos          (3U)
+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */
+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */
+#define PWR_CR3_SMPSEN_Pos             (2U)
+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */
+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */
+#define PWR_CR3_LDOEN_Pos              (1U)
+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
+#define PWR_CR3_BYPASS_Pos             (0U)
+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
+
+/********************  Bit definition for PWR_CPUCR register  *****************/
+#define PWR_CPUCR_RUN_D3_Pos           (11U)
+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */
+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPUCR_HOLD2_Pos            (10U)
+#define PWR_CPUCR_HOLD2_Msk            (0x1UL << PWR_CPUCR_HOLD2_Pos)          /*!< 0x00000400 */
+#define PWR_CPUCR_HOLD2                PWR_CPUCR_HOLD2_Msk                     /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */
+#define PWR_CPUCR_CSSF_Pos             (9U)
+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
+#define PWR_CPUCR_SBF_D2_Pos           (8U)
+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */
+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_D1_Pos           (7U)
+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */
+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_Pos              (6U)
+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
+#define PWR_CPUCR_STOPF_Pos            (5U)
+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
+#define PWR_CPUCR_HOLD2F_Pos           (4U)
+#define PWR_CPUCR_HOLD2F_Msk           (0x1UL << PWR_CPUCR_HOLD2F_Pos)         /*!< 0x00000010 */
+#define PWR_CPUCR_HOLD2F               PWR_CPUCR_HOLD2F_Msk                    /*!< CPU2 in hold wakeup flag */
+#define PWR_CPUCR_PDDS_D3_Pos          (2U)
+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */
+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D2_Pos          (1U)
+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */
+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D1_Pos          (0U)
+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */
+
+/********************  Bit definition for PWR_CPU2CR register  ****************/
+#define PWR_CPU2CR_RUN_D3_Pos          (11U)
+#define PWR_CPU2CR_RUN_D3_Msk          (0x1UL << PWR_CPU2CR_RUN_D3_Pos)        /*!< 0x00000800 */
+#define PWR_CPU2CR_RUN_D3              PWR_CPU2CR_RUN_D3_Msk                   /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPU2CR_HOLD1_Pos           (10U)
+#define PWR_CPU2CR_HOLD1_Msk           (0x1UL << PWR_CPU2CR_HOLD1_Pos)         /*!< 0x00000400 */
+#define PWR_CPU2CR_HOLD1               PWR_CPU2CR_HOLD1_Msk                    /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */
+#define PWR_CPU2CR_CSSF_Pos            (9U)
+#define PWR_CPU2CR_CSSF_Msk            (0x1UL << PWR_CPU2CR_CSSF_Pos)          /*!< 0x00000200 */
+#define PWR_CPU2CR_CSSF                PWR_CPU2CR_CSSF_Msk                     /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */
+#define PWR_CPU2CR_SBF_D2_Pos          (8U)
+#define PWR_CPU2CR_SBF_D2_Msk          (0x1UL << PWR_CPU2CR_SBF_D2_Pos)        /*!< 0x00000100 */
+#define PWR_CPU2CR_SBF_D2              PWR_CPU2CR_SBF_D2_Msk                   /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPU2CR_SBF_D1_Pos          (7U)
+#define PWR_CPU2CR_SBF_D1_Msk          (0x1UL << PWR_CPU2CR_SBF_D1_Pos)        /*!< 0x00000080 */
+#define PWR_CPU2CR_SBF_D1              PWR_CPU2CR_SBF_D1_Msk                   /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPU2CR_SBF_Pos             (6U)
+#define PWR_CPU2CR_SBF_Msk             (0x1UL << PWR_CPU2CR_SBF_Pos)           /*!< 0x00000040 */
+#define PWR_CPU2CR_SBF                 PWR_CPU2CR_SBF_Msk                      /*!< System STANDBY Flag */
+#define PWR_CPU2CR_STOPF_Pos           (5U)
+#define PWR_CPU2CR_STOPF_Msk           (0x1UL << PWR_CPU2CR_STOPF_Pos)         /*!< 0x00000020 */
+#define PWR_CPU2CR_STOPF               PWR_CPU2CR_STOPF_Msk                    /*!< STOP Flag */
+#define PWR_CPU2CR_HOLD1F_Pos          (4U)
+#define PWR_CPU2CR_HOLD1F_Msk          (0x1UL << PWR_CPU2CR_HOLD1F_Pos)        /*!< 0x00000010 */
+#define PWR_CPU2CR_HOLD1F              PWR_CPU2CR_HOLD1F_Msk                   /*!< CPU1 in hold wakeup flag */
+#define PWR_CPU2CR_PDDS_D3_Pos         (2U)
+#define PWR_CPU2CR_PDDS_D3_Msk         (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)       /*!< 0x00000004 */
+#define PWR_CPU2CR_PDDS_D3             PWR_CPU2CR_PDDS_D3_Msk                  /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPU2CR_PDDS_D2_Pos         (1U)
+#define PWR_CPU2CR_PDDS_D2_Msk         (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)       /*!< 0x00000002 */
+#define PWR_CPU2CR_PDDS_D2             PWR_CPU2CR_PDDS_D2_Msk                  /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPU2CR_PDDS_D1_Pos         (0U)
+#define PWR_CPU2CR_PDDS_D1_Msk         (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)       /*!< 0x00000001 */
+#define PWR_CPU2CR_PDDS_D1             PWR_CPU2CR_PDDS_D1_Msk                  /*!< D1 domain Power Down Deepsleep selection */
+
+
+/********************  Bit definition for PWR_D3CR register  ******************/
+#define PWR_D3CR_VOS_Pos               (14U)
+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */
+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */
+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */
+#define PWR_D3CR_VOSRDY_Pos            (13U)
+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */
+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
+
+/******************  Bit definition for PWR_WKUPCR register  ******************/
+#define PWR_WKUPCR_WKUPC6_Pos          (5U)
+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos          (4U)
+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
+
+/********************  Bit definition for PWR_WKUPFR register  ****************/
+#define PWR_WKUPFR_WKUPF6_Pos          (5U)
+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos          (4U)
+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos          (3U)
+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos          (2U)
+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos          (1U)
+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos          (0U)
+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
+
+/******************  Bit definition for PWR_WKUPEPR register  *****************/
+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)
+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)
+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  RCC VERSION  ********************************/
+#define RCC_VER_X
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                       (0U)
+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos                    (1U)
+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                      (2U)
+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIV_Pos                      (3U)
+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
+
+#define RCC_CR_HSIDIVF_Pos                     (5U)
+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
+#define RCC_CR_CSION_Pos                       (7U)
+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
+#define RCC_CR_CSIRDY_Pos                      (8U)
+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
+#define RCC_CR_CSIKERON_Pos                    (9U)
+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
+#define RCC_CR_HSI48ON_Pos                     (12U)
+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
+#define RCC_CR_HSI48RDY_Pos                    (13U)
+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
+
+#define RCC_CR_D1CKRDY_Pos                     (14U)
+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */
+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */
+#define RCC_CR_D2CKRDY_Pos                     (15U)
+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */
+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */
+
+#define RCC_CR_HSEON_Pos                       (16U)
+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                      (17U)
+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
+#define RCC_CR_HSEBYP_Pos                      (18U)
+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos                    (19U)
+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
+
+
+#define RCC_CR_PLL1ON_Pos                      (24U)
+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
+#define RCC_CR_PLL1RDY_Pos                     (25U)
+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
+#define RCC_CR_PLL2ON_Pos                      (26U)
+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
+#define RCC_CR_PLL2RDY_Pos                     (27U)
+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
+#define RCC_CR_PLL3ON_Pos                      (28U)
+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
+#define RCC_CR_PLL3RDY_Pos                     (29U)
+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
+
+/*Legacy */
+#define RCC_CR_PLLON_Pos                       (24U)
+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                      (25U)
+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_HSICFGR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_HSICFGR_HSICAL_Pos                 (0U)
+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
+
+/*!< HSITRIM configuration */
+#define RCC_HSICFGR_HSITRIM_Pos                (24U)
+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
+
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)
+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+
+
+/********************  Bit definition for RCC_CSICFGR register  *****************/
+/*!< CSICAL configuration */
+#define RCC_CSICFGR_CSICAL_Pos                 (0U)
+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
+
+/*!< CSITRIM configuration */
+#define RCC_CSICFGR_CSITRIM_Pos                (24U)
+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                        (0U)
+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
+
+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                       (3U)
+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
+
+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
+
+#define RCC_CFGR_STOPWUCK_Pos                  (6U)
+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
+
+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)
+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                    (8U)
+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
+
+/*!< HRTIMSEL configuration */
+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)
+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */
+
+/*!< TIMPRE configuration */
+#define RCC_CFGR_TIMPRE_Pos                    (15U)
+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                      (22U)
+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
+
+#define RCC_CFGR_MCO1PRE_Pos                   (18U)
+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
+
+#define RCC_CFGR_MCO2PRE_Pos                   (25U)
+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
+
+#define RCC_CFGR_MCO2_Pos                      (29U)
+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_D1CFGR register  ******************/
+/*!< D1HPRE configuration */
+#define RCC_D1CFGR_HPRE_Pos                    (0U)
+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */
+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */
+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */
+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
+
+
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)
+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */
+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)
+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */
+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)
+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */
+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)
+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */
+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */
+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)
+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */
+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */
+
+/*!< D1PPRE configuration */
+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)
+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */
+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */
+
+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)
+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
+
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */
+
+/********************  Bit definition for RCC_D2CFGR register  ******************/
+/*!< D2PPRE1 configuration */
+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)
+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
+
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
+
+/*!< D2PPRE2 configuration */
+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)
+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
+
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
+
+/********************  Bit definition for RCC_D3CFGR register  ******************/
+/*!< D3PPRE configuration */
+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)
+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
+
+/********************  Bit definition for RCC_PLLCKSELR register  *************/
+
+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
+
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
+
+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)
+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
+
+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)
+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)
+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+
+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+
+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+
+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+
+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
+
+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
+
+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
+
+
+/********************  Bit definition for RCC_PLL1DIVR register  ***************/
+#define RCC_PLL1DIVR_N1_Pos                    (0U)
+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
+#define RCC_PLL1DIVR_P1_Pos                    (9U)
+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
+#define RCC_PLL1DIVR_Q1_Pos                    (16U)
+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
+#define RCC_PLL1DIVR_R1_Pos                    (24U)
+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
+
+/********************  Bit definition for RCC_PLL1FRACR register  ***************/
+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)
+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
+
+/********************  Bit definition for RCC_PLL2DIVR register  ***************/
+#define RCC_PLL2DIVR_N2_Pos                    (0U)
+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
+#define RCC_PLL2DIVR_P2_Pos                    (9U)
+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
+#define RCC_PLL2DIVR_Q2_Pos                    (16U)
+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
+#define RCC_PLL2DIVR_R2_Pos                    (24U)
+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
+
+/********************  Bit definition for RCC_PLL2FRACR register  ***************/
+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)
+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
+
+/********************  Bit definition for RCC_PLL3DIVR register  ***************/
+#define RCC_PLL3DIVR_N3_Pos                    (0U)
+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
+#define RCC_PLL3DIVR_P3_Pos                    (9U)
+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
+#define RCC_PLL3DIVR_Q3_Pos                    (16U)
+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
+#define RCC_PLL3DIVR_R3_Pos                    (24U)
+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
+
+/********************  Bit definition for RCC_PLL3FRACR register  ***************/
+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)
+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ***************/
+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)
+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk
+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)
+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk
+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)
+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)
+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_D2CCIP1R register  ***************/
+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)
+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk
+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)
+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk
+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
+
+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)
+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk
+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
+
+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)
+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk
+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
+
+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)
+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk
+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk
+
+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)
+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk
+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)
+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk
+
+/********************  Bit definition for RCC_D2CCIP2R register  ***************/
+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)
+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk
+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)
+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk
+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)
+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk
+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)
+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk
+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)
+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk
+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)
+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk
+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk
+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_D3CCIPR register  ***************/
+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)
+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk
+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)
+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk
+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)
+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk
+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
+
+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)
+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk
+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)
+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk
+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)
+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk
+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)
+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk
+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)
+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk
+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                  (0U)
+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                  (1U)
+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                  (2U)
+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                  (3U)
+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_CSIRDYIE_Pos                  (4U)
+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos                (5U)
+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)
+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)
+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)
+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                  (9U)
+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                   (0U)
+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                   (1U)
+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                   (2U)
+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                   (3U)
+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_CSIRDYF_Pos                   (4U)
+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)
+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                   (6U)
+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)
+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)
+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
+#define RCC_CIFR_LSECSSF_Pos                   (9U)
+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSECSSF_Pos                   (10U)
+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                   (0U)
+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                   (1U)
+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                   (2U)
+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                   (3U)
+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_CSIRDYC_Pos                   (4U)
+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
+#define RCC_CICR_HSI48RDYC_Pos                 (5U)
+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                   (6U)
+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLL2RDYC_Pos                  (7U)
+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
+#define RCC_CICR_PLL3RDYC_Pos                  (8U)
+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
+#define RCC_CICR_LSECSSC_Pos                   (9U)
+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSECSSC_Pos                   (10U)
+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                     (0U)
+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                    (1U)
+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                    (2U)
+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                    (3U)
+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                  (5U)
+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                   (6U)
+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                    (8U)
+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                     (15U)
+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                     (16U)
+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                      (0U)
+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                     (1U)
+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
+
+
+/********************  Bit definition for RCC_AHB3ENR register  **************/
+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)
+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)
+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */
+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk
+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
+#define RCC_AHB3ENR_FLASHEN_Pos                (8U)
+#define RCC_AHB3ENR_FLASHEN_Msk                (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)      /*!< 0x00000100 */
+#define RCC_AHB3ENR_FLASHEN                    RCC_AHB3ENR_FLASHEN_Msk
+#define RCC_AHB3ENR_DTCM1EN_Pos                (28U)
+#define RCC_AHB3ENR_DTCM1EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)      /*!< 0x10000000 */
+#define RCC_AHB3ENR_DTCM1EN                    RCC_AHB3ENR_DTCM1EN_Msk
+#define RCC_AHB3ENR_DTCM2EN_Pos                (29U)
+#define RCC_AHB3ENR_DTCM2EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)      /*!< 0x20000000 */
+#define RCC_AHB3ENR_DTCM2EN                    RCC_AHB3ENR_DTCM2EN_Msk
+#define RCC_AHB3ENR_ITCMEN_Pos                 (30U)
+#define RCC_AHB3ENR_ITCMEN_Msk                 (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB3ENR_ITCMEN                     RCC_AHB3ENR_ITCMEN_Msk
+#define RCC_AHB3ENR_AXISRAMEN_Pos              (31U)
+#define RCC_AHB3ENR_AXISRAMEN_Msk              (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)    /*!< 0x80000000 */
+#define RCC_AHB3ENR_AXISRAMEN                  RCC_AHB3ENR_AXISRAMEN_Msk
+
+/* Legacy define */
+#define RCC_AHB3ENR_D1SRAM1EN_Pos              RCC_AHB3ENR_AXISRAMEN_Pos
+#define RCC_AHB3ENR_D1SRAM1EN_Msk              RCC_AHB3ENR_AXISRAMEN_Msk
+#define RCC_AHB3ENR_D1SRAM1EN                  RCC_AHB3ENR_AXISRAMEN
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
+#define RCC_AHB1ENR_ARTEN_Pos                  (14U)
+#define RCC_AHB1ENR_ARTEN_Msk                  (0x1UL << RCC_AHB1ENR_ARTEN_Pos)           /*!< 0x00004000 */
+#define RCC_AHB1ENR_ARTEN                      RCC_AHB1ENR_ARTEN_Msk
+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)
+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */
+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk
+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)
+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk
+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)
+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */
+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */
+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN
+
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)
+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)
+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */
+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)
+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)
+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */
+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk
+
+/* Legacy define */
+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos
+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN
+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos
+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN
+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos
+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk
+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN
+
+/********************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk
+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)
+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */
+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk
+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)
+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */
+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk
+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)
+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */
+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk
+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
+
+/********************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)
+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)
+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk
+
+/********************  Bit definition for RCC_APB1LENR register  ******************/
+
+#define RCC_APB1LENR_TIM2EN_Pos                (0U)
+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
+#define RCC_APB1LENR_TIM3EN_Pos                (1U)
+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
+#define RCC_APB1LENR_TIM4EN_Pos                (2U)
+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
+#define RCC_APB1LENR_TIM5EN_Pos                (3U)
+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
+#define RCC_APB1LENR_TIM6EN_Pos                (4U)
+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
+#define RCC_APB1LENR_TIM7EN_Pos                (5U)
+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
+#define RCC_APB1LENR_TIM12EN_Pos               (6U)
+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
+#define RCC_APB1LENR_TIM13EN_Pos               (7U)
+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
+#define RCC_APB1LENR_TIM14EN_Pos               (8U)
+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
+
+#define RCC_APB1LENR_WWDG2EN_Pos               (11U)
+#define RCC_APB1LENR_WWDG2EN_Msk               (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LENR_WWDG2EN                   RCC_APB1LENR_WWDG2EN_Msk
+
+#define RCC_APB1LENR_SPI2EN_Pos                (14U)
+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
+#define RCC_APB1LENR_SPI3EN_Pos                (15U)
+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
+#define RCC_APB1LENR_USART2EN_Pos              (17U)
+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
+#define RCC_APB1LENR_USART3EN_Pos              (18U)
+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
+#define RCC_APB1LENR_UART4EN_Pos               (19U)
+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
+#define RCC_APB1LENR_UART5EN_Pos               (20U)
+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
+#define RCC_APB1LENR_I2C1EN_Pos                (21U)
+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
+#define RCC_APB1LENR_I2C2EN_Pos                (22U)
+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
+#define RCC_APB1LENR_I2C3EN_Pos                (23U)
+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
+#define RCC_APB1LENR_CECEN_Pos                 (27U)
+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_DAC12EN_Pos               (29U)
+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
+#define RCC_APB1LENR_UART7EN_Pos               (30U)
+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
+#define RCC_APB1LENR_UART8EN_Pos               (31U)
+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
+
+/* Legacy define */
+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
+/********************  Bit definition for RCC_APB1HENR register  ******************/
+#define RCC_APB1HENR_CRSEN_Pos                 (1U)
+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)
+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)
+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)
+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
+#define RCC_APB1HENR_FDCANEN_Pos               (8U)
+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos               (4U)
+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos               (5U)
+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos                (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos                (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos                (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)
+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)
+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)
+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)
+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)
+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk
+
+/********************  Bit definition for RCC_APB4ENR register  ******************/
+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk
+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk
+#define RCC_APB4ENR_COMP12EN_Pos               (14U)
+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
+#define RCC_APB4ENR_VREFEN_Pos                 (15U)
+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)
+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk
+
+
+/********************  Bit definition for RCC_AHB3RSTR register  ***************/
+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)
+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)
+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)
+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */
+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk
+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
+
+
+/********************  Bit definition for RCC_AHB1RSTR register  ***************/
+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
+#define RCC_AHB1RSTR_ARTRST_Pos                (14U)
+#define RCC_AHB1RSTR_ARTRST_Msk                (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)       /*!< 0x00004000 */
+#define RCC_AHB1RSTR_ARTRST                    RCC_AHB1RSTR_ARTRST_Msk
+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)
+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */
+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk
+
+/* Legacy define */
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST
+
+/********************  Bit definition for RCC_AHB2RSTR register  ***************/
+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
+
+/********************  Bit definition for RCC_AHB4RSTR register  ******************/
+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk
+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)
+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */
+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk
+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)
+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */
+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk
+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)
+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */
+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk
+
+
+/********************  Bit definition for RCC_APB3RSTR register  ******************/
+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)
+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
+
+/********************  Bit definition for RCC_APB1LRSTR register  ******************/
+
+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)
+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)
+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)
+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)
+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
+#define RCC_APB1LRSTR_CECRST_Pos               (27U)
+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)
+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)
+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
+
+/* Legacy define */
+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
+/********************  Bit definition for RCC_APB1HRSTR register  ******************/
+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)
+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  ******************/
+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos             (4U)
+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos             (5U)
+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)
+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)
+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk
+
+/********************  Bit definition for RCC_APB4RSTR register  ******************/
+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk
+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk
+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)
+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
+#define RCC_APB4RSTR_VREFRST_Pos               (15U)
+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)
+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk
+
+
+/********************  Bit definition for RCC_GCR register  ********************/
+#define RCC_GCR_WW1RSC_Pos                     (0U)
+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */
+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk
+#define RCC_GCR_WW2RSC_Pos                     (1U)
+#define RCC_GCR_WW2RSC_Msk                     (0x1UL << RCC_GCR_WW2RSC_Pos)   /*!< 0x00000002 */
+#define RCC_GCR_WW2RSC                         RCC_GCR_WW2RSC_Msk
+#define RCC_GCR_BOOT_C1_Pos                    (2U)
+#define RCC_GCR_BOOT_C1_Msk                    (0x1UL << RCC_GCR_BOOT_C1_Pos)  /*!< 0x00000004 */
+#define RCC_GCR_BOOT_C1                        RCC_GCR_BOOT_C1_Msk
+#define RCC_GCR_BOOT_C2_Pos                    (3U)
+#define RCC_GCR_BOOT_C2_Msk                    (0x1UL << RCC_GCR_BOOT_C2_Pos)  /*!< 0x00000008 */
+#define RCC_GCR_BOOT_C2                        RCC_GCR_BOOT_C2_Msk
+
+/********************  Bit definition for RCC_D3AMR register  ********************/
+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)
+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk
+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)
+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk
+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)
+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk
+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)
+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk
+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)
+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk
+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)
+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk
+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)
+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk
+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)
+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk
+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)
+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk
+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)
+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk
+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)
+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk
+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)
+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk
+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)
+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk
+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)
+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk
+
+
+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)
+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk
+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)
+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk
+/********************  Bit definition for RCC_AHB3LPENR register  **************/
+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */
+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk
+
+
+/********************  Bit definition for RCC_AHB1LPENR register  ***************/
+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
+#define RCC_AHB1LPENR_ARTLPEN_Pos              (14U)
+#define RCC_AHB1LPENR_ARTLPEN_Msk              (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB1LPENR_ARTLPEN                  RCC_AHB1LPENR_ARTLPEN_Msk
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN
+
+/********************  Bit definition for RCC_AHB2LPENR register  ***************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)
+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)
+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)
+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN
+
+/********************  Bit definition for RCC_AHB4LPENR register  ******************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk
+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)
+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk
+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)
+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)
+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk
+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN
+/********************  Bit definition for RCC_APB3LPENR register  ******************/
+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)
+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk
+
+/********************  Bit definition for RCC_APB1LLPENR register  ******************/
+
+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
+
+#define RCC_APB1LLPENR_WWDG2LPEN_Pos           (11U)
+#define RCC_APB1LLPENR_WWDG2LPEN_Msk           (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LLPENR_WWDG2LPEN               RCC_APB1LLPENR_WWDG2LPEN_Msk
+
+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
+
+/* Legacy define */
+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
+/********************  Bit definition for RCC_APB1HLPENR register  ******************/
+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
+
+/********************  Bit definition for RCC_APB2LPENR register  ******************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)
+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)
+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk
+
+/********************  Bit definition for RCC_APB4LPENR register  ******************/
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk
+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)
+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk
+
+
+/********************  Bit definition for RCC_RSR register  *******************/
+#define RCC_RSR_RMVF_Pos                       (16U)
+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
+#define RCC_RSR_C1RSTF_Pos                     (17U)
+#define RCC_RSR_C1RSTF_Msk                     (0x1UL << RCC_RSR_C1RSTF_Pos)   /*!< 0x00020000 */
+#define RCC_RSR_C1RSTF                         RCC_RSR_C1RSTF_Msk
+#define RCC_RSR_D1RSTF_Pos                     (19U)
+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */
+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk
+#define RCC_RSR_D2RSTF_Pos                     (20U)
+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */
+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk
+#define RCC_RSR_BORRSTF_Pos                    (21U)
+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
+#define RCC_RSR_PINRSTF_Pos                    (22U)
+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
+#define RCC_RSR_PORRSTF_Pos                    (23U)
+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
+#define RCC_RSR_SFT1RSTF_Pos                   (24U)
+#define RCC_RSR_SFT1RSTF_Msk                   (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */
+#define RCC_RSR_SFT1RSTF                       RCC_RSR_SFT1RSTF_Msk
+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)
+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk
+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)
+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk
+
+#define RCC_RSR_WWDG2RSTF_Pos                  (29U)
+#define RCC_RSR_WWDG2RSTF_Msk                  (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */
+#define RCC_RSR_WWDG2RSTF                      RCC_RSR_WWDG2RSTF_Msk
+#define RCC_RSR_IWDG2RSTF_Pos                  (27U)
+#define RCC_RSR_IWDG2RSTF_Msk                  (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */
+#define RCC_RSR_IWDG2RSTF                      RCC_RSR_IWDG2RSTF_Msk
+#define RCC_RSR_SFT2RSTF_Pos                   (25U)
+#define RCC_RSR_SFT2RSTF_Msk                   (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */
+#define RCC_RSR_SFT2RSTF                       RCC_RSR_SFT2RSTF_Msk
+#define RCC_RSR_C2RSTF_Pos                     (18U)
+#define RCC_RSR_C2RSTF_Msk                     (0x1UL << RCC_RSR_C2RSTF_Pos)   /*!< 0x00040000 */
+#define RCC_RSR_C2RSTF                         RCC_RSR_C2RSTF_Msk
+#define RCC_RSR_LPWR1RSTF_Pos                  (30U)
+#define RCC_RSR_LPWR1RSTF_Msk                  (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */
+#define RCC_RSR_LPWR1RSTF                      RCC_RSR_LPWR1RSTF_Msk
+#define RCC_RSR_LPWR2RSTF_Pos                  (31U)
+#define RCC_RSR_LPWR2RSTF_Msk                  (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */
+#define RCC_RSR_LPWR2RSTF                      RCC_RSR_LPWR2RSTF_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_CED_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                  (20U)
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                  (8U)
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos                 (23U)
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                (21U)
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos               (19U)
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                 (18U)
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos               (17U)
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos               (16U)
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                (15U)
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos               (14U)
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos              (13U)
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos              (12U)
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                 (11U)
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                (10U)
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos               (9U)
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos               (8U)
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos                 (6U)
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos             (5U)
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos             (4U)
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos              (3U)
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos             (0U)
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos            (16U)
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos             (15U)
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos             (14U)
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos             (13U)
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos              (12U)
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                (11U)
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos               (10U)
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos              (9U)
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos              (8U)
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos               (7U)
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos              (6U)
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                (5U)
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos              (4U)
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos               (3U)
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos              (2U)
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos             (1U)
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos             (0U)
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos          (0U)
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos           (30U)
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos              (28U)
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos              (22U)
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos              (20U)
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos             (12U)
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos              (4U)
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos           (30U)
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos              (28U)
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos              (22U)
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos              (20U)
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos             (12U)
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos              (4U)
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos           (31U)
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                (20U)
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                (8U)
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos             (14U)
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos            (13U)
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos              (0U)
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_OR register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER_Pos             (5U)
+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */
+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos       (3U)
+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos        (4U)
+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos         (6U)
+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos         (7U)
+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos        (8U)
+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos        (9U)
+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos        (11U)
+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos         (12U)
+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos          (14U)
+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos        (16U)
+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos        (20U)
+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos      (2U)
+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos       (3U)
+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos       (6U)
+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos         (0U)
+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos        (1U)
+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos         (2U)
+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos          (3U)
+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos          (4U)
+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos        (5U)
+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos         (6U)
+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos         (7U)
+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos         (8U)
+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos       (16U)
+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos          (0U)
+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos          (24U)
+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos           (25U)
+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos           (26U)
+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos           (27U)
+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos          (28U)
+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos          (8U)
+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos          (4U)
+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos           (3U)
+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos           (2U)
+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos           (1U)
+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos          (0U)
+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos       (16U)
+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos       (0U)
+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos         (0U)
+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos          (16U)
+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos         (24U)
+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos         (0U)
+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos         (16U)
+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
+
+/*******************  Bit definition for SPDIFRX_VERR register    *******************/
+#define SPDIFRX_VERR_MINREV_Pos     (0U)
+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
+#define SPDIFRX_VERR_MAJREV_Pos     (4U)
+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
+
+/*******************  Bit definition for SPDIFRX_IDR register    *******************/
+#define SPDIFRX_IDR_ID_Pos          (0U)
+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
+
+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/
+#define SPDIFRX_SIDR_SID_Pos        (0U)
+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  SAI VERSION  ********************************/
+#define SAI_VER_V2_X
+
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
+
+/* Legacy define */
+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/* Legacy define */
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/*******************  Bit definition for SAI_PDMCR register  ******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos          (0U)
+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos          (2U)
+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos           (4U)
+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
+
+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos              (18U)
+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos             (0U)
+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos           (0U)
+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos           (6U)
+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos            (7U)
+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
+
+#define SDMMC_CMD_WAITRESP_Pos           (8U)
+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos            (10U)
+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos           (11U)
+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos             (12U)
+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos             (13U)
+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos           (14U)
+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos             (15U)
+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos        (0U)
+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos             (0U)
+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos            (1U)
+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos           (2U)
+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos          (8U)
+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos            (10U)
+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos          (13U)
+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos           (0U)
+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos           (1U)
+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos           (2U)
+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos           (3U)
+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos           (4U)
+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos            (5U)
+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos            (6U)
+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos            (7U)
+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos            (8U)
+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos              (9U)
+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos            (10U)
+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos             (11U)
+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos            (12U)
+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos            (13U)
+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos           (14U)
+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos           (15U)
+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos            (16U)
+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos            (17U)
+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos            (18U)
+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos            (19U)
+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos             (20U)
+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos          (21U)
+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos             (22U)
+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos            (23U)
+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos             (25U)
+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos             (26U)
+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos             (27U)
+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos            (28U)
+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos           (5U)
+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos           (6U)
+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos           (7U)
+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos           (8U)
+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos             (9U)
+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos           (10U)
+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos            (11U)
+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos            (22U)
+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos           (23U)
+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos            (25U)
+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos            (26U)
+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos            (27U)
+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos           (28U)
+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos         (8U)
+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos           (9U)
+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos          (11U)
+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos           (22U)
+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos          (25U)
+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos          (0U)
+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos            (0U)
+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos          (2U)
+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
+
+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos         (0U)
+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos         (1U)
+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
+
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos       (0U)
+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos      (8U)
+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos       (16U)
+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos      (31U)
+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI/I2S)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos             (0U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
+#define SPI_CR1_MASRX_Pos           (8U)
+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
+#define SPI_CR1_CSTART_Pos          (9U)
+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
+#define SPI_CR1_CSUSP_Pos           (10U)
+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
+#define SPI_CR1_HDDIR_Pos           (11U)
+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
+#define SPI_CR1_SSI_Pos             (12U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
+#define SPI_CR1_CRC33_17_Pos        (13U)
+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
+#define SPI_CR1_RCRCINI_Pos         (14U)
+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
+#define SPI_CR1_TCRCINI_Pos         (15U)
+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
+#define SPI_CR1_IOLOCK_Pos          (16U)
+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSER_Pos            (16U)
+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
+#define SPI_CR2_TSIZE_Pos           (0U)
+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
+
+/*******************  Bit definition for SPI_CFG1 register  ********************/
+#define SPI_CFG1_DSIZE_Pos          (0U)
+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos          (5U)
+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos         (9U)
+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos         (11U)
+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos        (14U)
+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
+#define SPI_CFG1_TXDMAEN_Pos        (15U)
+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
+
+#define SPI_CFG1_CRCSIZE_Pos        (16U)
+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos          (22U)
+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos            (28U)
+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
+
+/*******************  Bit definition for SPI_CFG2 register  ********************/
+#define SPI_CFG2_MSSI_Pos           (0U)
+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos           (4U)
+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos          (15U)
+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos           (17U)
+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos             (19U)
+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos         (22U)
+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
+#define SPI_CFG2_LSBFRST_Pos        (23U)
+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
+#define SPI_CFG2_CPHA_Pos           (24U)
+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
+#define SPI_CFG2_CPOL_Pos           (25U)
+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
+#define SPI_CFG2_SSM_Pos            (26U)
+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos          (28U)
+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos           (29U)
+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos           (30U)
+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos         (31U)
+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos           (0U)
+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
+#define SPI_IER_TXPIE_Pos           (1U)
+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
+#define SPI_IER_DXPIE_Pos           (2U)
+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
+#define SPI_IER_EOTIE_Pos           (3U)
+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
+#define SPI_IER_TXTFIE_Pos          (4U)
+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
+#define SPI_IER_UDRIE_Pos           (5U)
+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
+#define SPI_IER_OVRIE_Pos           (6U)
+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
+#define SPI_IER_CRCEIE_Pos          (7U)
+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
+#define SPI_IER_TIFREIE_Pos         (8U)
+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos          (9U)
+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
+#define SPI_IER_TSERFIE_Pos         (10U)
+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
+
+/*******************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXP_Pos              (0U)
+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_TXP_Pos              (1U)
+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
+#define SPI_SR_DXP_Pos              (2U)
+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_EOT_Pos              (3U)
+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_TXTF_Pos             (4U)
+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
+#define SPI_SR_UDR_Pos              (5U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_CRCE_Pos             (7U)
+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
+#define SPI_SR_TIFRE_Pos            (8U)
+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
+#define SPI_SR_MODF_Pos             (9U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
+#define SPI_SR_TSERF_Pos            (10U)
+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
+#define SPI_SR_SUSP_Pos             (11U)
+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
+#define SPI_SR_TXC_Pos              (12U)
+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos           (13U)
+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos            (15U)
+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
+#define SPI_SR_CTSIZE_Pos           (16U)
+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
+
+/*******************  Bit definition for SPI_IFCR register  ********************/
+#define SPI_IFCR_EOTC_Pos           (3U)
+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
+#define SPI_IFCR_TXTFC_Pos          (4U)
+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos           (5U)
+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
+#define SPI_IFCR_OVRC_Pos           (6U)
+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
+#define SPI_IFCR_CRCEC_Pos          (7U)
+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
+#define SPI_IFCR_TIFREC_Pos         (8U)
+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
+#define SPI_IFCR_MODFC_Pos          (9U)
+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
+#define SPI_IFCR_TSERFC_Pos         (10U)
+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
+#define SPI_IFCR_SUSPC_Pos          (11U)
+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
+
+/*******************  Bit definition for SPI_TXDR register  ********************/
+#define SPI_TXDR_TXDR_Pos           (0U)
+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  ********************/
+#define SPI_RXDR_RXDR_Pos           (0U)
+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
+
+/*******************  Bit definition for SPI_TXCRC register  ********************/
+#define SPI_TXCRC_TXCRC_Pos         (0U)
+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ********************/
+#define SPI_RXCRC_RXCRC_Pos         (0U)
+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ********************/
+#define SPI_UDRDR_UDRDR_Pos         (0U)
+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
+#define SPI_I2SCFGR_DATLEN_Pos      (8U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos       (10U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos       (11U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
+#define SPI_I2SCFGR_FIXCH_Pos       (12U)
+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
+#define SPI_I2SCFGR_WSINV_Pos       (13U)
+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
+#define SPI_I2SCFGR_DATFMT_Pos      (14U)
+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos         (24U)
+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos       (25U)
+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos             (1U)
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos             (2U)
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< Reserved: needed for softawre compatibility (DMA Enable) */
+#define QUADSPI_CR_TCEN_Pos              (3U)
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos               (6U)
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos              (7U)
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos            (8U)
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos              (16U)
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos              (17U)
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos              (19U)
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos              (20U)
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos              (22U)
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos               (23U)
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos               (1U)
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos               (3U)
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos               (4U)
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos              (5U)
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos             (1U)
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos             (4U)
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos             (31U)
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SYSCFG_PMCR register  ******************/
+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)
+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */
+
+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)
+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */
+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */
+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */
+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */
+#define SYSCFG_PMCR_PA0SO_Pos           (24U)
+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
+#define SYSCFG_PMCR_PA1SO_Pos           (25U)
+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
+#define SYSCFG_PMCR_PC2SO_Pos           (26U)
+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
+#define SYSCFG_PMCR_PC3SO_Pos           (27U)
+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
+
+/******************  Bit definition for SYSCFG_CFGR register  ******************/
+#define SYSCFG_CFGR_CM4L_Pos            (0U)
+#define SYSCFG_CFGR_CM4L_Msk            (0x1UL << SYSCFG_CFGR_CM4L_Pos)        /*!< 0x00000001 */
+#define SYSCFG_CFGR_CM4L                SYSCFG_CFGR_CM4L_Msk                   /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_PVDL_Pos            (2U)
+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
+#define SYSCFG_CFGR_FLASHL_Pos          (3U)
+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
+#define SYSCFG_CFGR_CM7L_Pos            (6U)
+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_BKRAML_Pos          (7U)
+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */
+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)
+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */
+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)
+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */
+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)
+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */
+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)
+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */
+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */
+#define SYSCFG_CFGR_DTCML_Pos           (13U)
+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
+#define SYSCFG_CFGR_ITCML_Pos           (14U)
+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)
+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */
+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */
+
+/******************  Bit definition for SYSCFG_CCCSR register  ******************/
+#define SYSCFG_CCCSR_EN_Pos             (0U)
+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
+#define SYSCFG_CCCSR_CS_Pos             (1U)
+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
+#define SYSCFG_CCCSR_READY_Pos          (8U)
+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
+#define SYSCFG_CCCSR_HSLV_Pos           (16U)
+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */
+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */
+
+/******************  Bit definition for SYSCFG_CCVR register  *******************/
+#define SYSCFG_CCVR_NCV_Pos             (0U)
+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
+#define SYSCFG_CCVR_PCV_Pos             (4U)
+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
+
+/******************  Bit definition for SYSCFG_CCCR register  *******************/
+#define SYSCFG_CCCR_NCC_Pos             (0U)
+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
+#define SYSCFG_CCCR_PCC_Pos             (4U)
+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
+/******************  Bit definition for SYSCFG_PWRCR register  *******************/
+#define SYSCFG_PWRCR_ODEN_Pos           (0U)
+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */
+
+/******************  Bit definition for SYSCFG_PKGR register  *******************/
+#define SYSCFG_PKGR_PKG_Pos             (0U)
+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */
+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */
+
+/******************  Bit definition for SYSCFG_UR0 register  *******************/
+#define SYSCFG_UR0_BKS_Pos              (0U)
+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */
+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */
+#define SYSCFG_UR0_RDP_Pos              (16U)
+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */
+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */
+
+/******************  Bit definition for SYSCFG_UR1 register  *******************/
+#define SYSCFG_UR1_BCM4_Pos             (0U)
+#define SYSCFG_UR1_BCM4_Msk             (0x1UL << SYSCFG_UR1_BCM4_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR1_BCM4                 SYSCFG_UR1_BCM4_Msk                    /*!< Boot Cortex-M4 */
+#define SYSCFG_UR1_BCM7_Pos             (16U)
+#define SYSCFG_UR1_BCM7_Msk             (0x1UL << SYSCFG_UR1_BCM7_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR1_BCM7                 SYSCFG_UR1_BCM7_Msk                    /*!< Boot Cortex-M7 */
+/******************  Bit definition for SYSCFG_UR2 register  *******************/
+#define SYSCFG_UR2_BORH_Pos             (0U)
+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */
+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */
+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */
+#define SYSCFG_UR2_BCM7_ADD0_Pos        (16U)
+#define SYSCFG_UR2_BCM7_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR2_BCM7_ADD0            SYSCFG_UR2_BCM7_ADD0_Msk               /*!< Boot Cortex-M7 Address 0 */
+/******************  Bit definition for SYSCFG_UR3 register  *******************/
+#define SYSCFG_UR3_BCM7_ADD1_Pos        (0U)
+#define SYSCFG_UR3_BCM7_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR3_BCM7_ADD1            SYSCFG_UR3_BCM7_ADD1_Msk               /*!< Boot Cortex-M7 Address 1 */
+
+#define SYSCFG_UR3_BCM4_ADD0_Pos        (16U)
+#define SYSCFG_UR3_BCM4_ADD0_Msk        (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR3_BCM4_ADD0            SYSCFG_UR3_BCM4_ADD0_Msk               /*!< Boot Cortex-M4 Address 0 */
+
+/******************  Bit definition for SYSCFG_UR4 register  *******************/
+
+#define SYSCFG_UR4_BCM4_ADD1_Pos        (0U)
+#define SYSCFG_UR4_BCM4_ADD1_Msk        (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR4_BCM4_ADD1            SYSCFG_UR4_BCM4_ADD1_Msk               /*!< Boot Cortex-M4 Address 1 */
+
+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)
+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR5 register  *******************/
+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)
+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */
+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)
+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */
+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */
+
+/******************  Bit definition for SYSCFG_UR6 register  *******************/
+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */
+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR7 register  *******************/
+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */
+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR8 register  *******************/
+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)
+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */
+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)
+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR9 register  *******************/
+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)
+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */
+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */
+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)
+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR10 register  *******************/
+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */
+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)
+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR11 register  *******************/
+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */
+#define SYSCFG_UR11_IWDG1M_Pos          (16U)
+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */
+
+/******************  Bit definition for SYSCFG_UR12 register  *******************/
+#define SYSCFG_UR12_IWDG2M_Pos          (0U)
+#define SYSCFG_UR12_IWDG2M_Msk          (0x1UL << SYSCFG_UR12_IWDG2M_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR12_IWDG2M              SYSCFG_UR12_IWDG2M_Msk                 /*!< Independent Watchdog 2 mode (SW or HW) */
+
+#define SYSCFG_UR12_SECURE_Pos          (16U)
+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */
+
+/******************  Bit definition for SYSCFG_UR13 register  *******************/
+#define SYSCFG_UR13_SDRS_Pos            (0U)
+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */
+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */
+#define SYSCFG_UR13_D1SBRST_Pos         (16U)
+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */
+
+/******************  Bit definition for SYSCFG_UR14 register  *******************/
+#define SYSCFG_UR14_D1STPRST_Pos        (0U)
+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */
+#define SYSCFG_UR14_D2SBRST_Pos         (16U)
+#define SYSCFG_UR14_D2SBRST_Msk         (0x1UL << SYSCFG_UR14_D2SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR14_D2SBRST             SYSCFG_UR14_D2SBRST_Msk                /*!< D2 Standby Reset */
+
+/******************  Bit definition for SYSCFG_UR15 register  *******************/
+#define SYSCFG_UR15_D2STPRST_Pos        (0U)
+#define SYSCFG_UR15_D2STPRST_Msk        (0x1UL << SYSCFG_UR15_D2STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR15_D2STPRST            SYSCFG_UR15_D2STPRST_Msk               /*!< D2 Stop Reset */
+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)
+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */
+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */
+
+/******************  Bit definition for SYSCFG_UR16 register  *******************/
+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)
+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */
+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */
+#define SYSCFG_UR16_PKP_Pos             (16U)
+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */
+
+/******************  Bit definition for SYSCFG_UR17 register  *******************/
+#define SYSCFG_UR17_IOHSLV_Pos          (0U)
+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
+/*******************  Bit definition for TIM1_AF1 register  *********************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos       (0U)
+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2CMP1E_Pos     (1U)
+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM1_AF2_BK2CMP2E_Pos     (2U)
+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)
+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos       (9U)
+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos     (10U)
+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos     (11U)
+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM8_AF1 register  *********************/
+#define TIM8_AF1_BKINE_Pos        (0U)
+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKCMP1E_Pos      (1U)
+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM8_AF1_BKCMP2E_Pos      (2U)
+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM8_AF1_BKDFBK2E_Pos     (8U)
+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos        (9U)
+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM8_AF1_BKCMP1P_Pos      (10U)
+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM8_AF1_BKCMP2P_Pos      (11U)
+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos       (14U)
+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+/*******************  Bit definition for TIM8_AF2 register  *********************/
+#define TIM8_AF2_BK2INE_Pos       (0U)
+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2CMP1E_Pos     (1U)
+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM8_AF2_BK2CMP2E_Pos     (2U)
+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos       (9U)
+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM8_AF2_BK2CMP1P_Pos     (10U)
+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM8_AF2_BK2CMP2P_Pos     (11U)
+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_AF1 register  *********************/
+#define TIM2_AF1_ETRSEL_Pos      (14U)
+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM3_AF1 register  *********************/
+#define TIM3_AF1_ETRSEL_Pos      (14U)
+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM5_AF1 register  *********************/
+#define TIM5_AF1_ETRSEL_Pos      (14U)
+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM15_AF1 register  *********************/
+#define TIM15_AF1_BKINE_Pos        (0U)
+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos      (1U)
+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos      (2U)
+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos        (9U)
+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos      (10U)
+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos      (11U)
+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_ register  *********************/
+#define TIM16_AF1_BKINE_Pos        (0U)
+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKCMP1E_Pos      (1U)
+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM16_AF1_BKCMP2E_Pos      (2U)
+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos        (9U)
+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM16_AF1_BKCMP1P_Pos      (10U)
+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P_Pos      (11U)
+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_AF1 register  *********************/
+#define TIM17_AF1_BKINE_Pos        (0U)
+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKCMP1E_Pos      (1U)
+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM17_AF1_BKCMP2E_Pos      (2U)
+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos        (9U)
+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM17_AF1_BKCMP1P_Pos      (10U)
+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P_Pos      (11U)
+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for COMP_SR register  ********************/
+#define COMP_SR_C1VAL_Pos            (0U)
+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos            (1U)
+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos             (16U)
+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos             (17U)
+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
+/*******************  Bit definition for COMP_ICFR register  ********************/
+#define COMP_ICFR_C1IF_Pos           (16U)
+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos           (17U)
+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
+/*******************  Bit definition for COMP_OR register  ********************/
+#define COMP_OR_AFOPA6_Pos           (0U)
+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos           (1U)
+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos          (2U)
+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos           (3U)
+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos          (4U)
+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos           (5U)
+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos           (6U)
+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos           (7U)
+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos           (8U)
+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos           (9U)
+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos           (10U)
+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
+
+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/
+#define COMP_CFGRx_EN_Pos            (0U)
+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
+#define COMP_CFGRx_BRGEN_Pos         (1U)
+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
+#define COMP_CFGRx_SCALEN_Pos        (2U)
+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
+#define COMP_CFGRx_POLARITY_Pos      (3U)
+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
+#define COMP_CFGRx_WINMODE_Pos       (4U)
+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
+#define COMP_CFGRx_ITEN_Pos          (6U)
+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
+#define COMP_CFGRx_HYST_Pos          (8U)
+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos       (12U)
+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos        (16U)
+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos        (20U)
+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
+#define COMP_CFGRx_BLANKING_Pos      (24U)
+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos          (31U)
+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                (0U)
+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
+#define USART_CR1_UESM_Pos              (1U)
+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                (2U)
+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                (3U)
+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos            (4U)
+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos              (6U)
+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos              (8U)
+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                (9U)
+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
+#define USART_CR1_PCE_Pos               (10U)
+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos              (11U)
+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                 (12U)
+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                (12U)
+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos               (13U)
+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos              (14U)
+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos             (15U)
+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos              (16U)
+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos              (21U)
+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos             (26U)
+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos             (27U)
+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                (28U)
+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos            (29U)
+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos            (30U)
+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos            (31U)
+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
+
+/* Legacy define */
+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos             (0U)
+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
+#define USART_CR2_DIS_NSS_Pos           (3U)
+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos             (4U)
+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos              (5U)
+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos             (6U)
+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos              (8U)
+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos              (9U)
+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos              (10U)
+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos             (11U)
+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
+#define USART_CR2_STOP_Pos              (12U)
+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos             (14U)
+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos              (15U)
+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos             (16U)
+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos             (17U)
+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos           (18U)
+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos          (19U)
+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos             (20U)
+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos           (21U)
+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos             (23U)
+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos               (24U)
+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos               (0U)
+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos              (1U)
+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos              (2U)
+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos             (3U)
+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos              (4U)
+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos              (5U)
+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos              (6U)
+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos              (7U)
+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos              (8U)
+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos              (9U)
+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos             (10U)
+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos            (11U)
+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos            (12U)
+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos              (13U)
+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos               (14U)
+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos               (15U)
+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos           (17U)
+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos               (20U)
+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos             (22U)
+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos            (23U)
+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos           (24U)
+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
+#define USART_CR3_RXFTCFG_Pos           (25U)
+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos            (28U)
+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos           (29U)
+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos      (0U)
+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos      (4U)
+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos              (0U)
+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos               (8U)
+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos              (0U)
+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos             (24U)
+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos             (0U)
+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos             (1U)
+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos              (2U)
+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos             (3U)
+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos             (4U)
+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                (0U)
+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
+#define USART_ISR_FE_Pos                (1U)
+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
+#define USART_ISR_NE_Pos                (2U)
+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos               (3U)
+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos              (4U)
+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos        (5U)
+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                (6U)
+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos         (7U)
+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos              (8U)
+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos             (9U)
+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos               (10U)
+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
+#define USART_ISR_RTOF_Pos              (11U)
+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos              (12U)
+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos               (13U)
+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos              (14U)
+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos              (15U)
+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos              (16U)
+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
+#define USART_ISR_CMF_Pos               (17U)
+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos              (18U)
+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos               (19U)
+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos               (20U)
+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos             (21U)
+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos             (22U)
+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos              (23U)
+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos              (24U)
+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos             (25U)
+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
+#define USART_ISR_RXFT_Pos              (26U)
+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
+#define USART_ISR_TXFT_Pos              (27U)
+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos              (0U)
+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos              (1U)
+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos              (2U)
+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos             (3U)
+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos            (4U)
+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos            (5U)
+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
+#define USART_ICR_TCCF_Pos              (6U)
+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos           (7U)
+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
+#define USART_ICR_LBDCF_Pos             (8U)
+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos             (9U)
+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos             (11U)
+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos             (12U)
+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos             (13U)
+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
+#define USART_ICR_CMCF_Pos              (17U)
+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos              (20U)
+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos               (0U)
+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos               (0U)
+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ******************/
+#define USART_PRESC_PRESCALER_Pos       (0U)
+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+#define SWPMI_CR_SWPEN_Pos       (11U)
+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)
+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+#define SWPMI_ISR_RDYF_Pos       (11U)
+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+#define SWPMI_ICR_CRDYF_Pos      (11U)
+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_RXBFIE_Pos     (0U)
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+#define SWPMI_IER_TXBEIE_Pos     (1U)
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RIE_Pos        (5U)
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TIE_Pos        (6U)
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_TCIE_Pos       (7U)
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_SRIE_Pos       (8U)
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_RDYIE_Pos      (11U)
+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */
+
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/*********************************  DEVICE ID  ********************************/
+#define STM32H7_DEV_ID           0x450UL
+
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)
+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk
+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)
+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk
+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)
+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk
+#define DBGMCU_CR_DBG_SLEEPD2_Pos         (3U)
+#define DBGMCU_CR_DBG_SLEEPD2_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */
+#define DBGMCU_CR_DBG_SLEEPD2             DBGMCU_CR_DBG_SLEEPD2_Msk
+#define DBGMCU_CR_DBG_STOPD2_Pos          (4U)
+#define DBGMCU_CR_DBG_STOPD2_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)  /*!< 0x00000010 */
+#define DBGMCU_CR_DBG_STOPD2              DBGMCU_CR_DBG_STOPD2_Msk
+#define DBGMCU_CR_DBG_STANDBYD2_Pos       (5U)
+#define DBGMCU_CR_DBG_STANDBYD2_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_DBG_STANDBYD2           DBGMCU_CR_DBG_STANDBYD2_Msk
+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)
+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk
+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)
+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
+
+/********************  Bit definition for APB3FZ1 register  ************/
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
+/********************  Bit definition for APB3FZ2 register  ************/
+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ2_DBG_WWDG1          DBGMCU_APB3FZ2_DBG_WWDG1_Msk
+/********************  Bit definition for APB1LFZ1 register  ************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos     (11U)
+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ1_DBG_WWDG2         DBGMCU_APB1LFZ1_DBG_WWDG2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
+
+/********************  Bit definition for APB1LFZ2 register  ************/
+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ2_DBG_TIM2          DBGMCU_APB1LFZ2_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ2_DBG_TIM3          DBGMCU_APB1LFZ2_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ2_DBG_TIM4          DBGMCU_APB1LFZ2_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ2_DBG_TIM5          DBGMCU_APB1LFZ2_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ2_DBG_TIM6          DBGMCU_APB1LFZ2_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ2_DBG_TIM7          DBGMCU_APB1LFZ2_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ2_DBG_TIM12         DBGMCU_APB1LFZ2_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ2_DBG_TIM13         DBGMCU_APB1LFZ2_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ2_DBG_TIM14         DBGMCU_APB1LFZ2_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1        DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos     (11U)
+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ2_DBG_WWDG2         DBGMCU_APB1LFZ2_DBG_WWDG2_Msk
+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ2_DBG_I2C1          DBGMCU_APB1LFZ2_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ2_DBG_I2C2          DBGMCU_APB1LFZ2_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ2_DBG_I2C3          DBGMCU_APB1LFZ2_DBG_I2C3_Msk
+/********************  Bit definition for APB1HFZ1 register  ************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
+/********************  Bit definition for APB1HFZ2 register  ************/
+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ2_DBG_FDCAN         DBGMCU_APB1HFZ2_DBG_FDCAN_Msk
+
+/********************  Bit definition for APB2FZ1 register  ************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk
+
+/********************  Bit definition for APB2FZ2 register  ************/
+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ2_DBG_TIM1           DBGMCU_APB2FZ2_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ2_DBG_TIM8           DBGMCU_APB2FZ2_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ2_DBG_TIM15          DBGMCU_APB2FZ2_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ2_DBG_TIM16          DBGMCU_APB2FZ2_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ2_DBG_TIM17          DBGMCU_APB2FZ2_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ2_DBG_HRTIM          DBGMCU_APB2FZ2_DBG_HRTIM_Msk
+/********************  Bit definition for APB4FZ1 register  ************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos      (19U)
+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG2          DBGMCU_APB4FZ1_DBG_IWDG2_Msk
+/********************  Bit definition for APB4FZ2 register  ************/
+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ2_DBG_I2C4           DBGMCU_APB4FZ2_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM2         DBGMCU_APB4FZ2_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM3         DBGMCU_APB4FZ2_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM4         DBGMCU_APB4FZ2_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM5         DBGMCU_APB4FZ2_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ2_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ2_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ2_DBG_RTC            DBGMCU_APB4FZ2_DBG_RTC_Msk
+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ2_DBG_IWDG1          DBGMCU_APB4FZ2_DBG_IWDG1_Msk
+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos      (19U)
+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */
+#define DBGMCU_APB4FZ2_DBG_IWDG2          DBGMCU_APB4FZ2_DBG_IWDG2_Msk
+/******************************************************************************/
+/*                                                                            */
+/*                        High Resolution Timer (HRTIM)                       */
+/*                                                                            */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC_Pos          (0U)
+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
+
+#define HRTIM_MCR_CONT_Pos            (3U)
+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG_Pos          (4U)
+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF_Pos            (5U)
+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN_Pos         (8U)
+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)
+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)
+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)
+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
+
+#define HRTIM_MCR_MCEN_Pos            (16U)
+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
+#define HRTIM_MCR_TACEN_Pos           (17U)
+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN_Pos           (18U)
+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN_Pos           (19U)
+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN_Pos           (20U)
+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN_Pos           (21U)
+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC_Pos         (25U)
+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
+
+#define HRTIM_MCR_PREEN_Pos           (27U)
+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
+#define HRTIM_MCR_MREPU_Pos           (29U)
+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA_Pos         (30U)
+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1_Pos          (0U)
+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2_Pos          (1U)
+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3_Pos          (2U)
+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4_Pos          (3U)
+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP_Pos           (4U)
+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC_Pos           (5U)
+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD_Pos           (6U)
+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1_Pos          (0U)
+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2_Pos          (1U)
+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3_Pos          (2U)
+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4_Pos          (3U)
+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP_Pos           (4U)
+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC_Pos           (5U)
+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD_Pos           (6U)
+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)
+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)
+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)
+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)
+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE_Pos        (4U)
+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE_Pos        (5U)
+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE_Pos        (6U)
+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)
+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)
+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)
+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)
+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE_Pos        (20U)
+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE_Pos        (21U)
+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE_Pos        (22U)
+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
+
+/*******************  Bit definition for HRTIM_MCNTR register  ****************/
+#define HRTIM_MCNTR_MCNTR_Pos         (0U)
+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for HRTIM_MPER register  *****************/
+#define HRTIM_MPER_MPER_Pos           (0U)
+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_MREP register  *****************/
+#define HRTIM_MREP_MREP_Pos           (0U)
+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */
+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
+
+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/
+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/
+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/
+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/
+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)
+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
+
+#define HRTIM_TIMCR_CONT_Pos          (3U)
+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG_Pos        (4U)
+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF_Pos          (5U)
+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)
+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)
+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)
+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)
+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
+
+#define HRTIM_TIMCR_TREPU_Pos         (17U)
+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU_Pos         (18U)
+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU_Pos           (19U)
+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU_Pos           (20U)
+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU_Pos           (21U)
+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU_Pos           (22U)
+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU_Pos           (23U)
+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU_Pos          (24U)
+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */
+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)
+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
+#define HRTIM_TIMCR_PREEN_Pos         (27U)
+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)
+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1_Pos         (0U)
+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2_Pos         (1U)
+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3_Pos         (2U)
+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4_Pos         (3U)
+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP_Pos          (4U)
+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD_Pos          (6U)
+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1_Pos         (7U)
+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2_Pos         (8U)
+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1_Pos         (9U)
+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1_Pos         (10U)
+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2_Pos         (11U)
+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2_Pos         (12U)
+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST_Pos          (13U)
+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)
+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT_Pos       (18U)
+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT_Pos       (19U)
+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY_Pos        (20U)
+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY_Pos        (21U)
+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C_Pos        (0U)
+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C_Pos        (1U)
+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C_Pos        (2U)
+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C_Pos        (3U)
+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC_Pos         (4U)
+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC_Pos         (6U)
+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C_Pos        (7U)
+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C_Pos        (8U)
+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C_Pos        (9U)
+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C_Pos        (10U)
+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C_Pos        (11U)
+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C_Pos        (12U)
+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC_Pos         (13U)
+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE_Pos       (4U)
+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)
+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)
+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)
+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)
+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)
+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)
+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE_Pos       (20U)
+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)
+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)
+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)
+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)
+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)
+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)
+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
+
+/******************  Bit definition for HRTIM_CNTR register  ****************/
+#define HRTIM_CNTR_CNTR_Pos           (0U)
+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
+
+/*******************  Bit definition for HRTIM_PER register  *****************/
+#define HRTIM_PER_PER_Pos             (0U)
+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */
+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_REP register  *****************/
+#define HRTIM_REP_REP_Pos             (0U)
+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */
+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
+
+/*******************  Bit definition for HRTIM_CMP1R register  *****************/
+#define HRTIM_CMP1R_CMP1R_Pos         (0U)
+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/
+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP2R register  *****************/
+#define HRTIM_CMP2R_CMP2R_Pos         (0U)
+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP3R register  *****************/
+#define HRTIM_CMP3R_CMP3R_Pos         (0U)
+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP4R register  *****************/
+#define HRTIM_CMP4R_CMP4R_Pos         (0U)
+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CPT1R register  ****************/
+#define HRTIM_CPT1R_CPT1R_Pos         (0U)
+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
+
+/*******************  Bit definition for HRTIM_CPT2R register  ****************/
+#define HRTIM_CPT2R_CPT2R_Pos         (0U)
+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR_Pos             (0U)
+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
+#define HRTIM_DTR_SDTR_Pos            (9U)
+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC_Pos          (10U)
+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
+#define HRTIM_DTR_DTRSLK_Pos          (14U)
+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK_Pos           (15U)
+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF_Pos             (16U)
+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
+#define HRTIM_DTR_SDTF_Pos            (25U)
+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK_Pos          (30U)
+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK_Pos           (31U)
+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST_Pos           (0U)
+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC_Pos        (1U)
+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER_Pos           (2U)
+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET1R_CMP1_Pos          (3U)
+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2_Pos          (4U)
+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3_Pos          (5U)
+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4_Pos          (6U)
+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER_Pos        (7U)
+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE_Pos        (31U)
+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT_Pos           (0U)
+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC_Pos        (1U)
+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER_Pos           (2U)
+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST1R_CMP1_Pos          (3U)
+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2_Pos          (4U)
+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3_Pos          (5U)
+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4_Pos          (6U)
+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER_Pos        (7U)
+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE_Pos        (31U)
+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST_Pos           (0U)
+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC_Pos        (1U)
+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER_Pos           (2U)
+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET2R_CMP1_Pos          (3U)
+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2_Pos          (4U)
+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3_Pos          (5U)
+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4_Pos          (6U)
+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER_Pos        (7U)
+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE_Pos        (31U)
+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT_Pos           (0U)
+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC_Pos        (1U)
+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER_Pos           (2U)
+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST2R_CMP1_Pos          (3U)
+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2_Pos          (4U)
+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3_Pos          (5U)
+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4_Pos          (6U)
+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER_Pos        (7U)
+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE_Pos        (31U)
+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering  register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
+
+/**** Bit definition for Slave external event filtering  register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE_Pos         (1U)
+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
+#define HRTIM_RSTR_CMP2_Pos           (2U)
+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4_Pos           (3U)
+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER_Pos         (4U)
+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)
+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)
+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)
+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)
+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
+
+/* Slave Timer A reset enable bits upon other slave timers events */
+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
+
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ_Pos         (0U)
+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
+
+#define HRTIM_CHPR_CARDTY_Pos         (4U)
+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
+
+#define HRTIM_CHPR_STRPW_Pos          (7U)
+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1_Pos           (1U)
+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1_Pos          (2U)
+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1_Pos         (3U)
+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1_Pos         (4U)
+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
+#define HRTIM_OUTR_CHP1_Pos           (6U)
+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1_Pos          (7U)
+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN_Pos           (8U)
+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT_Pos         (10U)
+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
+
+#define HRTIM_OUTR_POL2_Pos           (17U)
+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2_Pos          (18U)
+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2_Pos         (19U)
+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2_Pos         (20U)
+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
+#define HRTIM_OUTR_CHP2_Pos           (22U)
+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2_Pos          (23U)
+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN_Pos         (0U)
+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN_Pos         (1U)
+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN_Pos         (2U)
+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN_Pos         (3U)
+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN_Pos         (4U)
+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTLCK_Pos         (31U)
+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS_Pos           (0U)
+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */
+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS_Pos          (1U)
+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */
+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS_Pos          (2U)
+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */
+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS_Pos          (3U)
+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */
+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS_Pos          (4U)
+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */
+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS_Pos          (5U)
+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */
+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC_Pos        (16U)
+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */
+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_CR1_ADC2USRC_Pos        (19U)
+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */
+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
+#define HRTIM_CR1_ADC3USRC_Pos        (22U)
+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */
+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_CR1_ADC4USRC_Pos        (25U)
+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */
+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU_Pos            (0U)
+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */
+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
+#define HRTIM_CR2_TASWU_Pos           (1U)
+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */
+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU_Pos           (2U)
+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */
+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU_Pos           (3U)
+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */
+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU_Pos           (4U)
+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */
+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
+#define HRTIM_CR2_TESWU_Pos           (5U)
+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */
+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
+#define HRTIM_CR2_MRST_Pos            (8U)
+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */
+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
+#define HRTIM_CR2_TARST_Pos           (9U)
+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */
+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST_Pos           (10U)
+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */
+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST_Pos           (11U)
+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */
+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST_Pos           (12U)
+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */
+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST_Pos           (13U)
+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */
+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1_Pos            (0U)
+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2_Pos            (1U)
+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3_Pos            (2U)
+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4_Pos            (3U)
+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5_Pos            (4U)
+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT_Pos          (5U)
+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
+#define HRTIM_ISR_BMPER_Pos           (17U)
+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C_Pos           (0U)
+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C_Pos           (1U)
+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C_Pos           (2U)
+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C_Pos           (3U)
+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C_Pos           (4U)
+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC_Pos         (5U)
+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_BMPERC_Pos          (17U)
+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1_Pos            (0U)
+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2_Pos            (1U)
+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3_Pos            (2U)
+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4_Pos            (3U)
+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5_Pos            (4U)
+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT_Pos          (5U)
+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
+#define HRTIM_IER_BMPER_Pos           (17U)
+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN_Pos         (0U)
+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN_Pos         (1U)
+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN_Pos         (2U)
+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN_Pos         (3U)
+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN_Pos         (4U)
+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN_Pos         (5U)
+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN_Pos         (6U)
+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN_Pos         (7U)
+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN_Pos         (8U)
+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN_Pos         (9U)
+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)
+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)
+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)
+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)
+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)
+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)
+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)
+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)
+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)
+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)
+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS_Pos         (0U)
+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS_Pos         (1U)
+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS_Pos         (2U)
+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS_Pos         (3U)
+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS_Pos         (4U)
+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS_Pos         (5U)
+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS_Pos         (6U)
+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS_Pos         (7U)
+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS_Pos         (8U)
+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS_Pos         (9U)
+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME_Pos            (0U)
+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enable */
+#define HRTIM_BMCR_BMOM_Pos           (1U)
+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK_Pos          (2U)
+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
+#define HRTIM_BMCR_BMPRSC_Pos         (6U)
+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
+#define HRTIM_BMCR_BMPREN_Pos         (10U)
+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM_Pos           (16U)
+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM_Pos           (17U)
+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM_Pos           (18U)
+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM_Pos           (19U)
+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM_Pos           (20U)
+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM_Pos           (21U)
+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT_Pos         (31U)
+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW_Pos           (0U)
+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)
+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)
+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST_Pos        (7U)
+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
+#define HRTIM_BMTRGR_TAREP_Pos        (8U)
+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)
+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)
+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
+#define HRTIM_BMTRGR_TBRST_Pos        (11U)
+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
+#define HRTIM_BMTRGR_TBREP_Pos        (12U)
+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST_Pos        (15U)
+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
+#define HRTIM_BMTRGR_TCREP_Pos        (16U)
+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */
+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST_Pos        (19U)
+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
+#define HRTIM_BMTRGR_TDREP_Pos        (20U)
+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */
+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST_Pos        (23U)
+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */
+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
+#define HRTIM_BMTRGR_TEREP_Pos        (24U)
+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)
+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)
+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
+#define HRTIM_BMTRGR_EEV7_Pos         (29U)
+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8_Pos         (30U)
+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
+
+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/
+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
+
+/*******************  Bit definition for HRTIM_BMPER register  ****************/
+#define HRTIM_BMPER_BMPER_Pos         (0U)
+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
+
+/*******************  Bit definition for HRTIM_EECR1 register  ****************/
+#define HRTIM_EECR1_EE1SRC_Pos        (0U)
+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR1_EE1POL_Pos        (2U)
+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS_Pos        (3U)
+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
+#define HRTIM_EECR1_EE1FAST_Pos       (5U)
+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC_Pos        (6U)
+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR1_EE2POL_Pos        (8U)
+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS_Pos        (9U)
+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
+#define HRTIM_EECR1_EE2FAST_Pos       (11U)
+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC_Pos        (12U)
+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR1_EE3POL_Pos        (14U)
+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS_Pos        (15U)
+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
+#define HRTIM_EECR1_EE3FAST_Pos       (17U)
+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC_Pos        (18U)
+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR1_EE4POL_Pos        (20U)
+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS_Pos        (21U)
+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
+#define HRTIM_EECR1_EE4FAST_Pos       (23U)
+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC_Pos        (24U)
+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_EECR1_EE5POL_Pos        (26U)
+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS_Pos        (27U)
+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
+#define HRTIM_EECR1_EE5FAST_Pos       (29U)
+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
+
+/*******************  Bit definition for HRTIM_EECR2 register  ****************/
+#define HRTIM_EECR2_EE6SRC_Pos        (0U)
+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR2_EE6POL_Pos        (2U)
+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS_Pos        (3U)
+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
+
+#define HRTIM_EECR2_EE7SRC_Pos        (6U)
+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR2_EE7POL_Pos        (8U)
+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS_Pos        (9U)
+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
+
+#define HRTIM_EECR2_EE8SRC_Pos        (12U)
+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR2_EE8POL_Pos        (14U)
+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS_Pos        (15U)
+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
+
+#define HRTIM_EECR2_EE9SRC_Pos        (18U)
+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR2_EE9POL_Pos        (20U)
+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS_Pos        (21U)
+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
+
+#define HRTIM_EECR2_EE10SRC_Pos       (24U)
+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
+#define HRTIM_EECR2_EE10POL_Pos       (26U)
+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS_Pos       (27U)
+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
+
+/*******************  Bit definition for HRTIM_EECR3 register  ****************/
+#define HRTIM_EECR3_EE6F_Pos          (0U)
+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
+#define HRTIM_EECR3_EE7F_Pos          (6U)
+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
+#define HRTIM_EECR3_EE8F_Pos          (12U)
+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
+#define HRTIM_EECR3_EE9F_Pos          (18U)
+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
+#define HRTIM_EECR3_EE10F_Pos         (24U)
+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
+#define HRTIM_EECR3_EEVSD_Pos         (30U)
+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for HRTIM_ADC1R register  ****************/
+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)
+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)
+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)
+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)
+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)
+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)
+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC2R register  ****************/
+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)
+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)
+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)
+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)
+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)
+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)
+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_ADC3R register  ****************/
+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)
+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)
+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)
+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)
+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)
+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)
+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC4R register  ****************/
+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)
+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)
+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)
+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)
+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)
+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)
+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)
+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)
+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)
+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)
+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)
+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */
+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)
+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)
+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)
+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */
+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)
+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)
+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)
+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */
+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)
+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
+
+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)
+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)
+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)
+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)
+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
+
+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/
+#define HRTIM_BDMUPR_MCR_Pos          (0U)
+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR_Pos         (1U)
+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER_Pos        (2U)
+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT_Pos         (3U)
+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER_Pos         (4U)
+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP_Pos         (5U)
+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)
+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)
+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)
+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)
+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
+
+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/
+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)
+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)
+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)
+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)
+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
+
+/*******************  Bit definition for HRTIM_BDMADR register  ***************/
+#define HRTIM_BDMADR_BDMADR_Pos       (0U)
+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             RAM ECC monitoring                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for RAMECC_IER register  ******************/
+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)
+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_IER_GECCDEIE_Pos           (2U)
+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
+#define RAMECC_IER_GECCSEIE_Pos           (1U)
+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
+#define RAMECC_IER_GIE_Pos                (0U)
+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
+
+/*******************  Bit definition for RAMECC_CR register  ******************/
+#define RAMECC_CR_ECCELEN_Pos             (5U)
+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)
+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_CR_ECCDEIE_Pos             (3U)
+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
+#define RAMECC_CR_ECCSEIE_Pos             (2U)
+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
+
+/*******************  Bit definition for RAMECC_SR register  ******************/
+#define RAMECC_SR_DEBWDF_Pos             (2U)
+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
+#define RAMECC_SR_DEDF_Pos               (1U)
+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
+#define RAMECC_SR_SEDCF_Pos              (0U)
+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
+
+/******************  Bit definition for RAMECC_FAR register  ******************/
+#define RAMECC_FAR_FADD_Pos              (0U)
+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRL register  *****************/
+#define RAMECC_FAR_FDATAL_Pos            (0U)
+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRH register  *****************/
+#define RAMECC_FAR_FDATAH_Pos            (0U)
+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
+
+/*****************  Bit definition for RAMECC_FECR register  ******************/
+#define RAMECC_FECR_FEC_Pos              (0U)
+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
+                                          ((INSTANCE) == ADC3_COMMON))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
+                                         ((INSTANCE) == DLYB_SDMMC2) || \
+                                         ((INSTANCE) == DLYB_QUADSPI))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                               ((INSTANCE) == DFSDM1_Filter1) || \
+                                               ((INSTANCE) == DFSDM1_Filter2) || \
+                                               ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+/****************************** RAMECC Instances ******************************/
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor2))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                       ((INSTANCE) == DMA1_Stream1)   || \
+                                       ((INSTANCE) == DMA1_Stream2)   || \
+                                       ((INSTANCE) == DMA1_Stream3)   || \
+                                       ((INSTANCE) == DMA1_Stream4)   || \
+                                       ((INSTANCE) == DMA1_Stream5)   || \
+                                       ((INSTANCE) == DMA1_Stream6)   || \
+                                       ((INSTANCE) == DMA1_Stream7)   || \
+                                       ((INSTANCE) == DMA2_Stream0)   || \
+                                       ((INSTANCE) == DMA2_Stream1)   || \
+                                       ((INSTANCE) == DMA2_Stream2)   || \
+                                       ((INSTANCE) == DMA2_Stream3)   || \
+                                       ((INSTANCE) == DMA2_Stream4)   || \
+                                       ((INSTANCE) == DMA2_Stream5)   || \
+                                       ((INSTANCE) == DMA2_Stream6)   || \
+                                       ((INSTANCE) == DMA2_Stream7)   || \
+                                       ((INSTANCE) == BDMA_Channel0) || \
+                                       ((INSTANCE) == BDMA_Channel1) || \
+                                       ((INSTANCE) == BDMA_Channel2) || \
+                                       ((INSTANCE) == BDMA_Channel3) || \
+                                       ((INSTANCE) == BDMA_Channel4) || \
+                                       ((INSTANCE) == BDMA_Channel5) || \
+                                       ((INSTANCE) == BDMA_Channel6) || \
+                                       ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA CHANNEL Instances ***************************/
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
+                                            ((INSTANCE) == BDMA_Channel1) || \
+                                            ((INSTANCE) == BDMA_Channel2) || \
+                                            ((INSTANCE) == BDMA_Channel3) || \
+                                            ((INSTANCE) == BDMA_Channel4) || \
+                                            ((INSTANCE) == BDMA_Channel5) || \
+                                            ((INSTANCE) == BDMA_Channel6) || \
+                                            ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA DMAMUX ALL Instances ***************************/
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
+                                               ((INSTANCE) == DMA1_Stream1)    || \
+                                               ((INSTANCE) == DMA1_Stream2)    || \
+                                               ((INSTANCE) == DMA1_Stream3)    || \
+                                               ((INSTANCE) == DMA1_Stream4)    || \
+                                               ((INSTANCE) == DMA1_Stream5)    || \
+                                               ((INSTANCE) == DMA1_Stream6)    || \
+                                               ((INSTANCE) == DMA1_Stream7)    || \
+                                               ((INSTANCE) == DMA2_Stream0)    || \
+                                               ((INSTANCE) == DMA2_Stream1)    || \
+                                               ((INSTANCE) == DMA2_Stream2)    || \
+                                               ((INSTANCE) == DMA2_Stream3)    || \
+                                               ((INSTANCE) == DMA2_Stream4)    || \
+                                               ((INSTANCE) == DMA2_Stream5)    || \
+                                               ((INSTANCE) == DMA2_Stream6)    || \
+                                               ((INSTANCE) == DMA2_Stream7)    || \
+                                               ((INSTANCE) == BDMA_Channel0)   || \
+                                               ((INSTANCE) == BDMA_Channel1)   || \
+                                               ((INSTANCE) == BDMA_Channel2)   || \
+                                               ((INSTANCE) == BDMA_Channel3)   || \
+                                               ((INSTANCE) == BDMA_Channel4)   || \
+                                               ((INSTANCE) == BDMA_Channel5)   || \
+                                               ((INSTANCE) == BDMA_Channel6)   || \
+                                               ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA DMAMUX Instances ***************************/
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \
+                                                    ((INSTANCE) == BDMA_Channel1) || \
+                                                    ((INSTANCE) == BDMA_Channel2) || \
+                                                    ((INSTANCE) == BDMA_Channel3) || \
+                                                    ((INSTANCE) == BDMA_Channel4) || \
+                                                    ((INSTANCE) == BDMA_Channel5) || \
+                                                    ((INSTANCE) == BDMA_Channel6) || \
+                                                    ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA STREAM Instances ***************************/
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                          ((INSTANCE) == DMA1_Stream1)   || \
+                                          ((INSTANCE) == DMA1_Stream2)   || \
+                                          ((INSTANCE) == DMA1_Stream3)   || \
+                                          ((INSTANCE) == DMA1_Stream4)   || \
+                                          ((INSTANCE) == DMA1_Stream5)   || \
+                                          ((INSTANCE) == DMA1_Stream6)   || \
+                                          ((INSTANCE) == DMA1_Stream7)   || \
+                                          ((INSTANCE) == DMA2_Stream0)   || \
+                                          ((INSTANCE) == DMA2_Stream1)   || \
+                                          ((INSTANCE) == DMA2_Stream2)   || \
+                                          ((INSTANCE) == DMA2_Stream3)   || \
+                                          ((INSTANCE) == DMA2_Stream4)   || \
+                                          ((INSTANCE) == DMA2_Stream5)   || \
+                                          ((INSTANCE) == DMA2_Stream6)   || \
+                                          ((INSTANCE) == DMA2_Stream7))
+
+/****************************** DMA DMAMUX Instances ***************************/
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
+                                                  ((INSTANCE) == DMA1_Stream1)   || \
+                                                  ((INSTANCE) == DMA1_Stream2)   || \
+                                                  ((INSTANCE) == DMA1_Stream3)   || \
+                                                  ((INSTANCE) == DMA1_Stream4)   || \
+                                                  ((INSTANCE) == DMA1_Stream5)   || \
+                                                  ((INSTANCE) == DMA1_Stream6)   || \
+                                                  ((INSTANCE) == DMA1_Stream7)   || \
+                                                  ((INSTANCE) == DMA2_Stream0)   || \
+                                                  ((INSTANCE) == DMA2_Stream1)   || \
+                                                  ((INSTANCE) == DMA2_Stream2)   || \
+                                                  ((INSTANCE) == DMA2_Stream3)   || \
+                                                  ((INSTANCE) == DMA2_Stream4)   || \
+                                                  ((INSTANCE) == DMA2_Stream5)   || \
+                                                  ((INSTANCE) == DMA2_Stream6)   || \
+                                                  ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
+                                               ((INSTANCE) == MDMA_Channel1)  || \
+                                               ((INSTANCE) == MDMA_Channel2)  || \
+                                               ((INSTANCE) == MDMA_Channel3)  || \
+                                               ((INSTANCE) == MDMA_Channel4)  || \
+                                               ((INSTANCE) == MDMA_Channel5)  || \
+                                               ((INSTANCE) == MDMA_Channel6)  || \
+                                               ((INSTANCE) == MDMA_Channel7)  || \
+                                               ((INSTANCE) == MDMA_Channel8)  || \
+                                               ((INSTANCE) == MDMA_Channel9)  || \
+                                               ((INSTANCE) == MDMA_Channel10) || \
+                                               ((INSTANCE) == MDMA_Channel11) || \
+                                               ((INSTANCE) == MDMA_Channel12) || \
+                                               ((INSTANCE) == MDMA_Channel13) || \
+                                               ((INSTANCE) == MDMA_Channel14) || \
+                                               ((INSTANCE) == MDMA_Channel15))
+
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
+                                             ((__INSTANCE__) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On H7, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CPU1_COREID    (0x00000003U) /* Semaphore Core CM7 ID */
+#define HSEM_CPU2_COREID    (0x00000001U) /* Semaphore Core CM4 ID */
+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#define HSEM_CR_COREID_CPU2      (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
+#if defined(CORE_CM4)
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
+#else  /* CORE_CM7 */
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#endif /* CORE_CM4 */
+
+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
+                                         ((INSTANCE) == SPI2) || \
+                                         ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SDMMC Instances *********************************/
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
+                                           ((_INSTANCE_) == SDMMC2))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                           ((INSTANCE) == SPI2) || \
+                                           ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2) || \
+                                         ((INSTANCE) == LPTIM3) || \
+                                         ((INSTANCE) == LPTIM4) || \
+                                         ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                                           ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                                ((__INSTANCE__) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM6)   || \
+                                           ((INSTANCE) == TIM7)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM15)  || \
+                                           ((INSTANCE) == TIM16)  || \
+                                           ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM8)  || \
+                                          ((INSTANCE) == TIM16) || \
+                                          ((INSTANCE) == TIM17))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                              ((INSTANCE) == TIM2)   || \
+                                              ((INSTANCE) == TIM3)   || \
+                                              ((INSTANCE) == TIM5)   || \
+                                              ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM12)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
+                                          ((INSTANCE) == TIM2)   || \
+                                          ((INSTANCE) == TIM3)   || \
+                                          ((INSTANCE) == TIM4)   || \
+                                          ((INSTANCE) == TIM5)   || \
+                                          ((INSTANCE) == TIM8)   || \
+                                          ((INSTANCE) == TIM15)  || \
+                                          ((INSTANCE) == TIM16)  || \
+                                          ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+                                                     ((INSTANCE) == TIM8)    || \
+                                                     ((INSTANCE) == TIM15)   || \
+                                                     ((INSTANCE) == TIM16)   || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
+                                                      ((__INSTANCE__) == TIM2)      || \
+                                                      ((__INSTANCE__) == TIM3)      || \
+                                                      ((__INSTANCE__) == TIM4)      || \
+                                                      ((__INSTANCE__) == TIM5)      || \
+                                                      ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                                       ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM3) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1)||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM4) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM5) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM8) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+  ||                                           \
+     (((INSTANCE) == TIM12) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+  ||                                           \
+     (((INSTANCE) == TIM13) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+     ((CHANNEL) == TIM_CHANNEL_2)))            \
+  ||                                           \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM17) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+      ((INSTANCE) == TIM8)     || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+ ||                                             \
+      (((INSTANCE) == TIM8) &&                  \
+      (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM8)    || \
+     ((__INSTANCE__) == TIM12)   || \
+     ((__INSTANCE__) == TIM15))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1)     || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
+                                                             ((__INSTANCE__) == TIM2)  || \
+                                                             ((__INSTANCE__) == TIM3)  || \
+                                                             ((__INSTANCE__) == TIM4)  || \
+                                                             ((__INSTANCE__) == TIM5)  || \
+                                                             ((__INSTANCE__) == TIM15) || \
+                                                             ((__INSTANCE__) == TIM8))
+
+/****************************** HRTIM Instances *******************************/
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3) || \
+                                              ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4)  || \
+                                         ((INSTANCE) == UART5)  || \
+                                         ((INSTANCE) == USART6) || \
+                                         ((INSTANCE) == UART7)  || \
+                                         ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5)  || \
+                                                            ((INSTANCE) == USART6) || \
+                                                            ((INSTANCE) == UART7)  || \
+                                                            ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3) || \
+                                                  ((INSTANCE) == UART4)  || \
+                                                  ((INSTANCE) == UART5)  || \
+                                                  ((INSTANCE) == USART6) || \
+                                                  ((INSTANCE) == UART7)  || \
+                                                  ((INSTANCE) == UART8)  || \
+                                                  ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8)  || \
+                                               ((INSTANCE) == LPUART1))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == USART6) || \
+                                           ((INSTANCE) == UART7)  || \
+                                           ((INSTANCE) == UART8)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                        ((INSTANCE) == USART2) || \
+                                        ((INSTANCE) == USART3) || \
+                                        ((INSTANCE) == UART4)  || \
+                                        ((INSTANCE) == UART5)  || \
+                                        ((INSTANCE) == USART6) || \
+                                        ((INSTANCE) == UART7)  || \
+                                        ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                    ((INSTANCE) == USART2) || \
+                                                    ((INSTANCE) == USART3) || \
+                                                    ((INSTANCE) == UART4)  || \
+                                                    ((INSTANCE) == UART5)  || \
+                                                    ((INSTANCE) == USART6) || \
+                                                    ((INSTANCE) == UART7)  || \
+                                                    ((INSTANCE) == UART8)  || \
+                                                    ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/****************************** LPUART Instance *******************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG1) || \
+                                         ((INSTANCE) == WWDG2))
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                    ((INSTANCE) == SAI1_Block_B) || \
+                     ((INSTANCE) == SAI2_Block_A) || \
+                     ((INSTANCE) == SAI2_Block_B) || \
+                     ((INSTANCE) == SAI3_Block_A) || \
+                     ((INSTANCE) == SAI3_Block_B) || \
+                     ((INSTANCE) == SAI4_Block_A) || \
+                     ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/*********************** USB OTG PCD Instances ********************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** USB OTG HCD Instances ********************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32H7xx device product       */
+/*  lines, or with STM32F7xx devices the aliases defined below are put        */
+/*   in place to overcome the differences in the interrupt handlers and IRQn  */
+/*   definitions. No need to update developed interrupt code when moving      */
+/*  across product lines within the same STM32H7 Family                       */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define  HASH_RNG_IRQn                  RNG_IRQn
+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
+#define  PVD_IRQn                       PVD_AVD_IRQn
+
+
+
+/* Aliases for __IRQHandler */
+#define  HASH_RNG_IRQHandler           RNG_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define PVD_IRQHandler                 PVD_AVD_IRQHandler
+
+/* Aliases for COMP __IRQHandler */
+#define COMP_IRQHandler                COMP1_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H745xG_H */
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xx.h
index 56afb783a0..0c4fc0395d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h745xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -222,22 +221,22 @@ typedef enum
   * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
    */
 #ifdef CORE_CM4
-#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< CM4 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM4 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
 
 #include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */
 #else  /* CORE_CM7 */
 #ifdef CORE_CM7
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */
 #else  /* UNKNOWN_CORE */
 #error Please #define CORE_CM4 or CORE_CM7
@@ -251,7 +250,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -933,8 +931,8 @@ __IO uint32_t C2PR3;               /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1800,7 +1798,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2807,6 +2805,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2856,6 +2863,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4119,7 +4129,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6076,10 +6086,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6834,7 +6844,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6853,14 +6863,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -6971,7 +6981,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7007,21 +7017,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7040,7 +7050,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7065,7 +7075,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7121,7 +7131,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7157,7 +7167,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7190,7 +7200,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7392,7 +7402,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7416,7 +7426,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7573,7 +7583,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7728,12 +7738,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8231,14 +8241,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8273,10 +8283,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8323,10 +8333,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8349,7 +8359,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8362,7 +8372,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8394,14 +8404,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8441,7 +8451,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8463,7 +8473,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8487,11 +8497,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8500,12 +8510,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8523,12 +8533,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10757,11 +10767,15 @@ typedef struct
 /*
 * @brief FLASH Global Defines
 */
+#if defined(CORE_CM4)
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#else
 #define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
-#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
                                              ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
                                              (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
+#endif /* CORE_CM4 */
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
 #define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
 #define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -10770,7 +10784,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10780,6 +10794,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10788,12 +10810,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11580,7 +11596,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -13718,7 +13734,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -15128,7 +15144,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -15162,7 +15178,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -15184,7 +15200,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -15219,7 +15235,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -15241,7 +15257,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -15264,7 +15280,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -15284,7 +15300,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18692,10 +18708,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -19141,12 +19157,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -19421,61 +19438,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19493,60 +19510,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19565,62 +19582,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19638,59 +19655,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_CM4L_Pos            (0U)
@@ -20004,8 +20021,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -20282,8 +20299,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -20307,12 +20324,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20552,8 +20569,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20571,12 +20588,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -21685,7 +21702,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -22063,7 +22080,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -22272,7 +22289,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -23159,6 +23176,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -23199,6 +23217,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -24882,6 +25064,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -24907,7 +25092,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -24918,13 +25103,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -24994,6 +25187,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -25111,7 +25310,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -26719,7 +26918,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -26916,6 +27116,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -26926,6 +27127,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -27157,4 +27359,3 @@ typedef struct
 
 #endif /* STM32H745xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xg.h
new file mode 100644
index 0000000000..dab35c4260
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xg.h
@@ -0,0 +1,30534 @@
+/**
+  ******************************************************************************
+  * @file    stm32h747xg.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32H747xG Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral's registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32h747xg
+  * @{
+  */
+
+#ifndef STM32H747xG_H
+#define STM32H747xG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum
+{
+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */
+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */
+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */
+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */
+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */
+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */
+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */
+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */
+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */
+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */
+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */
+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */
+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */
+  CM7_SEV_IRQn                = 64,     /*!< CM7 Send event interrupt for CM4                                  */
+  CM4_SEV_IRQn                = 65,     /*!< CM4 Send event interrupt for CM7                                  */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */
+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */
+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */
+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */
+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */
+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */
+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */
+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */
+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */
+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */
+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */
+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */
+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */
+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */
+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */
+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */
+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */
+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */
+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */
+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */
+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */
+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */
+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */
+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */
+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */
+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */
+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */
+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */
+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */
+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */
+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */
+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */
+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */
+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */
+  DSI_IRQn                    = 123,    /*!< DSI global Interrupt                                              */
+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */
+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */
+  HSEM2_IRQn                  = 126,    /*!< HSEM2 global Interrupt                                            */
+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */
+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */
+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */
+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */
+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */
+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */
+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */
+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */
+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */
+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */
+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */
+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */
+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */
+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */
+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */
+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */
+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */
+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */
+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */
+  HOLD_CORE_IRQn              = 148,    /*!< Hold core interrupt                                               */
+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+#define DUAL_CORE  /*!< Dual core line feature */
+
+#define SMPS       /*!< Switched mode power supply feature */
+
+
+
+/**
+  * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
+   */
+#ifdef CORE_CM4
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< CM4 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM4 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+
+#include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */
+#else  /* CORE_CM7 */
+#ifdef CORE_CM7
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */
+#else  /* UNKNOWN_CORE */
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM7 */
+#endif /* CORE_CM4 */
+
+/**
+  * @}
+  */
+
+
+
+
+#include "system_stm32h7xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */
+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */
+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */
+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */
+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */
+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */
+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */
+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */
+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */
+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */
+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */
+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */
+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */
+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */
+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */
+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */
+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */
+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */
+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */
+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */
+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */
+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */
+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */
+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */
+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */
+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */
+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */
+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */
+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */
+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */
+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */
+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */
+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */
+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */
+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */
+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */
+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */
+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */
+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */
+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */
+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */
+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */
+} ADC_TypeDef;
+
+
+typedef struct
+{
+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
+
+} ADC_Common_TypeDef;
+
+/**
+  * @brief ART
+  */
+
+typedef struct
+{
+  __IO uint32_t  CTR;        /*!< ART accelerator - control register */
+}ART_TypeDef;
+
+/**
+  * @brief VREFBUF
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */
+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */
+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */
+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */
+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */
+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */
+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */
+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */
+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */
+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */
+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */
+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */
+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */
+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */
+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */
+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */
+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */
+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */
+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */
+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */
+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */
+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */
+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */
+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */
+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */
+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */
+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */
+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */
+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */
+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */
+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */
+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */
+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */
+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */
+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */
+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */
+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */
+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */
+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */
+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */
+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */
+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */
+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */
+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */
+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */
+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */
+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */
+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */
+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */
+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */
+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */
+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */
+} FDCAN_GlobalTypeDef;
+
+/**
+  * @brief TTFD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */
+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */
+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */
+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */
+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */
+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */
+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */
+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */
+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */
+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */
+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */
+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */
+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */
+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */
+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */
+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */
+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */
+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */
+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */
+} TTCAN_TypeDef;
+
+/**
+  * @brief FD Controller Area Network
+  */
+
+typedef struct
+{
+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */
+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */
+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */
+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */
+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */
+} FDCAN_ClockCalibrationUnit_TypeDef;
+
+
+/**
+  * @brief Consumer Electronics Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
+} CRC_TypeDef;
+
+
+/**
+  * @brief Clock Recovery System
+  */
+typedef struct
+{
+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */
+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */
+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */
+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
+} CRS_TypeDef;
+
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */
+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */
+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */
+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
+} DAC_TypeDef;
+
+/**
+  * @brief DFSDM module registers
+  */
+typedef struct
+{
+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */
+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */
+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */
+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */
+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */
+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */
+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */
+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */
+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */
+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */
+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */
+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */
+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */
+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */
+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+  * @brief DFSDM channel configuration registers
+  */
+typedef struct
+{
+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */
+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */
+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and
+                                   short circuit detector register,                  Address offset: 0x08 */
+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */
+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+typedef struct
+{
+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */
+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */
+  __IO uint32_t  RESERVED4[11]; /*!< Reserved,                               Address offset: 0x08 */
+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */
+  __IO uint32_t APB3FZ2;     /*!< Debug MCU APB3FZ2 freeze register,    Address offset: 0x38 */
+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */
+  __IO uint32_t APB1LFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x40 */
+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */
+  __IO uint32_t APB1HFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x48 */
+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */
+  __IO uint32_t APB2FZ2;     /*!< Debug MCU APB2FZ2 freeze register,    Address offset: 0x50 */
+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */
+  __IO uint32_t APB4FZ2;     /*!< Debug MCU APB4FZ2 freeze register,    Address offset: 0x58 */
+
+}DBGMCU_TypeDef;
+/**
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */
+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */
+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */
+} BDMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} BDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */
+}DMAMUX_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */
+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */
+}DMAMUX_ChannelStatus_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */
+}DMAMUX_RequestGen_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */
+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */
+}DMAMUX_RequestGenStatus_TypeDef;
+
+/**
+  * @brief MDMA Controller
+  */
+typedef struct
+{
+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */
+}MDMA_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */
+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */
+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */
+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */
+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */
+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */
+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */
+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */
+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */
+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */
+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */
+  uint32_t       RESERVED0; /*!< Reserved, 0x6C                                                             */
+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */
+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */
+}MDMA_Channel_TypeDef;
+
+/**
+  * @brief DMA2D Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */
+} DMA2D_TypeDef;
+
+/**
+  * @brief DSI Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */
+  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */
+  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */
+  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */
+  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */
+  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */
+  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */
+  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */
+  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */
+  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */
+  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */
+  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */
+  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */
+  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */
+  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */
+  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */
+  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */
+  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */
+  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */
+  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */
+  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */
+  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */
+  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */
+  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */
+  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */
+  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */
+  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */
+  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */
+  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */
+  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */
+  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */
+  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */
+  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */
+  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */
+  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */
+  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */
+  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */
+  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */
+  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */
+  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */
+  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */
+  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */
+  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */
+  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */
+  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */
+  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */
+  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */
+  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */
+  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */
+  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */
+  __IO uint32_t VCCCR;         /*!< DSI Host Video Chunks Current Configuration Register,     Address offset: 0x140     */
+  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */
+  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */
+  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */
+  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */
+  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */
+  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */
+  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */
+  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */
+  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */
+  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */
+  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                                */
+  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                        Address offset: 0x400       */
+  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                              Address offset: 0x404       */
+  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                     Address offset: 0x408       */
+  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                 Address offset: 0x40C       */
+  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                 Address offset: 0x410       */
+  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                        */
+  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                    Address offset: 0x418-0x42B */
+  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                        */
+  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                  */
+} DSI_TypeDef;
+
+/**
+  * @brief Ethernet MAC
+  */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACECR;
+  __IO uint32_t MACPFR;
+  __IO uint32_t MACWTR;
+  __IO uint32_t MACHT0R;
+  __IO uint32_t MACHT1R;
+  uint32_t      RESERVED1[14];
+  __IO uint32_t MACVTR;
+  uint32_t      RESERVED2;
+  __IO uint32_t MACVHTR;
+  uint32_t      RESERVED3;
+  __IO uint32_t MACVIR;
+  __IO uint32_t MACIVIR;
+  uint32_t      RESERVED4[2];
+  __IO uint32_t MACTFCR;
+  uint32_t      RESERVED5[7];
+  __IO uint32_t MACRFCR;
+  uint32_t      RESERVED6[7];
+  __IO uint32_t MACISR;
+  __IO uint32_t MACIER;
+  __IO uint32_t MACRXTXSR;
+  uint32_t      RESERVED7;
+  __IO uint32_t MACPCSR;
+  __IO uint32_t MACRWKPFR;
+  uint32_t      RESERVED8[2];
+  __IO uint32_t MACLCSR;
+  __IO uint32_t MACLTCR;
+  __IO uint32_t MACLETR;
+  __IO uint32_t MAC1USTCR;
+  uint32_t      RESERVED9[12];
+  __IO uint32_t MACVR;
+  __IO uint32_t MACDR;
+  uint32_t      RESERVED10;
+  __IO uint32_t MACHWF0R;
+  __IO uint32_t MACHWF1R;
+  __IO uint32_t MACHWF2R;
+  uint32_t      RESERVED11[54];
+  __IO uint32_t MACMDIOAR;
+  __IO uint32_t MACMDIODR;
+  uint32_t      RESERVED12[2];
+  __IO uint32_t MACARPAR;
+  uint32_t      RESERVED13[59];
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+  uint32_t      RESERVED14[248];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+  uint32_t      RESERVED15[14];
+  __IO uint32_t MMCTSCGPR;
+  __IO uint32_t MMCTMCGPR;
+  uint32_t      RESERVED16[5];
+  __IO uint32_t MMCTPCGR;
+  uint32_t      RESERVED17[10];
+  __IO uint32_t MMCRCRCEPR;
+  __IO uint32_t MMCRAEPR;
+  uint32_t      RESERVED18[10];
+  __IO uint32_t MMCRUPGR;
+  uint32_t      RESERVED19[9];
+  __IO uint32_t MMCTLPIMSTR;
+  __IO uint32_t MMCTLPITCR;
+  __IO uint32_t MMCRLPIMSTR;
+  __IO uint32_t MMCRLPITCR;
+  uint32_t      RESERVED20[65];
+  __IO uint32_t MACL3L4C0R;
+  __IO uint32_t MACL4A0R;
+  uint32_t      RESERVED21[2];
+  __IO uint32_t MACL3A0R0R;
+  __IO uint32_t MACL3A1R0R;
+  __IO uint32_t MACL3A2R0R;
+  __IO uint32_t MACL3A3R0R;
+  uint32_t      RESERVED22[4];
+  __IO uint32_t MACL3L4C1R;
+  __IO uint32_t MACL4A1R;
+  uint32_t      RESERVED23[2];
+  __IO uint32_t MACL3A0R1R;
+  __IO uint32_t MACL3A1R1R;
+  __IO uint32_t MACL3A2R1R;
+  __IO uint32_t MACL3A3R1R;
+  uint32_t      RESERVED24[108];
+  __IO uint32_t MACTSCR;
+  __IO uint32_t MACSSIR;
+  __IO uint32_t MACSTSR;
+  __IO uint32_t MACSTNR;
+  __IO uint32_t MACSTSUR;
+  __IO uint32_t MACSTNUR;
+  __IO uint32_t MACTSAR;
+  uint32_t      RESERVED25;
+  __IO uint32_t MACTSSR;
+  uint32_t      RESERVED26[3];
+  __IO uint32_t MACTTSSNR;
+  __IO uint32_t MACTTSSSR;
+  uint32_t      RESERVED27[2];
+  __IO uint32_t MACACR;
+  uint32_t      RESERVED28;
+  __IO uint32_t MACATSNR;
+  __IO uint32_t MACATSSR;
+  __IO uint32_t MACTSIACR;
+  __IO uint32_t MACTSEACR;
+  __IO uint32_t MACTSICNR;
+  __IO uint32_t MACTSECNR;
+  uint32_t      RESERVED29[4];
+  __IO uint32_t MACPPSCR;
+  uint32_t      RESERVED30[3];
+  __IO uint32_t MACPPSTTSR;
+  __IO uint32_t MACPPSTTNR;
+  __IO uint32_t MACPPSIR;
+  __IO uint32_t MACPPSWR;
+  uint32_t      RESERVED31[12];
+  __IO uint32_t MACPOCR;
+  __IO uint32_t MACSPI0R;
+  __IO uint32_t MACSPI1R;
+  __IO uint32_t MACSPI2R;
+  __IO uint32_t MACLMIR;
+  uint32_t      RESERVED32[11];
+  __IO uint32_t MTLOMR;
+  uint32_t      RESERVED33[7];
+  __IO uint32_t MTLISR;
+  uint32_t      RESERVED34[55];
+  __IO uint32_t MTLTQOMR;
+  __IO uint32_t MTLTQUR;
+  __IO uint32_t MTLTQDR;
+  uint32_t      RESERVED35[8];
+  __IO uint32_t MTLQICSR;
+  __IO uint32_t MTLRQOMR;
+  __IO uint32_t MTLRQMPOCR;
+  __IO uint32_t MTLRQDR;
+  uint32_t      RESERVED36[177];
+  __IO uint32_t DMAMR;
+  __IO uint32_t DMASBMR;
+  __IO uint32_t DMAISR;
+  __IO uint32_t DMADSR;
+  uint32_t      RESERVED37[60];
+  __IO uint32_t DMACCR;
+  __IO uint32_t DMACTCR;
+  __IO uint32_t DMACRCR;
+  uint32_t      RESERVED38[2];
+  __IO uint32_t DMACTDLAR;
+  uint32_t      RESERVED39;
+  __IO uint32_t DMACRDLAR;
+  __IO uint32_t DMACTDTPR;
+  uint32_t      RESERVED40;
+  __IO uint32_t DMACRDTPR;
+  __IO uint32_t DMACTDRLR;
+  __IO uint32_t DMACRDRLR;
+  __IO uint32_t DMACIER;
+  __IO uint32_t DMACRIWTR;
+__IO uint32_t DMACSFCSR;
+  uint32_t      RESERVED41;
+  __IO uint32_t DMACCATDR;
+  uint32_t      RESERVED42;
+  __IO uint32_t DMACCARDR;
+  uint32_t      RESERVED43;
+  __IO uint32_t DMACCATBR;
+  uint32_t      RESERVED44;
+  __IO uint32_t DMACCARBR;
+  __IO uint32_t DMACSR;
+uint32_t      RESERVED45[2];
+__IO uint32_t DMACMFCR;
+}ETH_TypeDef;
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */
+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */
+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */
+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */
+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */
+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */
+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */
+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */
+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */
+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */
+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */
+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */
+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */
+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */
+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */
+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */
+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */
+uint32_t      RESERVED6[5];        /*!< Reserved,                                        0xAC to 0xBC         */
+__IO uint32_t C2IMR1;              /*!< EXTI Interrupt mask register,                    Address offset: 0xC0 */
+__IO uint32_t C2EMR1;              /*!< EXTI Event mask register,                        Address offset: 0xC4 */
+__IO uint32_t C2PR1;               /*!< EXTI Pending register,                           Address offset: 0xC8 */
+uint32_t      RESERVED7;           /*!< Reserved,                                        0xCC                 */
+__IO uint32_t C2IMR2;              /*!< EXTI Interrupt mask register,                    Address offset: 0xD0 */
+__IO uint32_t C2EMR2;              /*!< EXTI Event mask register,                        Address offset: 0xD4 */
+__IO uint32_t C2PR2;               /*!< EXTI Pending register,                           Address offset: 0xD8 */
+uint32_t      RESERVED8;           /*!< Reserved,                                        0xDC                 */
+__IO uint32_t C2IMR3;              /*!< EXTI Interrupt mask register,                    Address offset: 0xE0 */
+__IO uint32_t C2EMR3;              /*!< EXTI Event mask register,                        Address offset: 0xE4 */
+__IO uint32_t C2PR3;               /*!< EXTI Pending register,                           Address offset: 0xE8 */
+
+}EXTI_TypeDef;
+
+/**
+  * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
+  *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
+  *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
+  *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
+  */
+
+typedef struct
+{
+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */
+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */
+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */
+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */
+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */
+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */
+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */
+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */
+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */
+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */
+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */
+}EXTI_Core_TypeDef;
+
+
+/**
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */
+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */
+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */
+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */
+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */
+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */
+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */
+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */
+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */
+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */
+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */
+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */
+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */
+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */
+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */
+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */
+  __IO uint32_t BOOT7_CUR;       /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */
+  __IO uint32_t BOOT7_PRG;       /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */
+  __IO uint32_t BOOT4_CUR;       /*!< Flash Current Boot Address for M4 Core Register,          Address offset: 0x48  */
+  __IO uint32_t BOOT4_PRG;       /*!< Flash Boot Address to Program for M4 Core Register,       Address offset: 0x4C  */
+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */
+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */
+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */
+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */
+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */
+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */
+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */
+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */
+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */
+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */
+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */
+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */
+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */
+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */
+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */
+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */
+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */
+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */
+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */
+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */
+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */
+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */
+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */
+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FMC_Bank1_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FMC_Bank1E_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank2
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FMC_Bank2_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank3
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FMC_Bank3_TypeDef;
+
+/**
+  * @brief Flexible Memory Controller Bank5 and 6
+  */
+
+
+typedef struct
+{
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */
+} FMC_Bank5_6_TypeDef;
+
+/**
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief Operational Amplifier (OPAMP)
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */
+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */
+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */
+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */
+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */
+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */
+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */
+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */
+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */
+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */
+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */
+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */
+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */
+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */
+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */
+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */
+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */
+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */
+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */
+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */
+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */
+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */
+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */
+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */
+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */
+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */
+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */
+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */
+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */
+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */
+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */
+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */
+
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+
+/**
+  * @brief JPEG Codec
+  */
+typedef struct
+{
+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */
+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */
+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */
+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */
+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */
+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */
+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */
+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */
+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */
+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */
+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */
+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */
+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */
+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */
+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */
+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */
+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */
+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */
+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */
+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */
+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */
+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */
+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */
+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */
+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */
+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */
+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */
+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */
+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */
+
+} JPEG_TypeDef;
+
+/**
+  * @brief LCD-TFT Display Controller
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */
+} LTDC_TypeDef;
+
+/**
+  * @brief LCD-TFT Display layer x Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */
+  uint32_t      RESERVED0[2];  /*!< Reserved */
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */
+  uint32_t      RESERVED1[3];  /*!< Reserved */
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */
+
+} LTDC_Layer_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */
+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */
+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */
+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */
+  __IO uint32_t CPU2CR;    /*!< PWR CPU2 control register,               Address offset: 0x14 */
+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */
+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */
+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */
+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */
+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */
+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */
+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */
+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */
+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */
+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */
+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */
+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */
+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */
+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */
+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */
+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */
+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */
+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */
+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */
+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */
+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */
+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */
+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */
+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */
+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */
+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */
+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */
+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */
+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */
+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */
+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */
+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */
+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */
+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */
+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */
+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */
+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */
+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */
+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */
+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */
+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */
+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */
+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */
+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */
+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */
+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */
+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */
+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */
+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */
+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */
+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */
+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */
+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */
+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */
+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */
+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */
+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */
+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */
+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */
+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */
+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */
+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */
+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */
+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */
+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */
+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */
+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */
+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */
+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */
+
+} RCC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t RSR;          /*!< RCC Reset status register,                                               Address offset: 0x00 */
+  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clock  register,                            Address offset: 0x04 */
+  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clock  register,                            Address offset: 0x08 */
+  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clock  register,                            Address offset: 0x0C */
+  __IO uint32_t AHB4ENR;      /*!< RCC AHB4 peripheral clock  register,                            Address offset: 0x10 */
+  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clock  register,                            Address offset: 0x14 */
+  __IO uint32_t APB1LENR;     /*!< RCC APB1 peripheral clock  Low Word register,                   Address offset: 0x18 */
+  __IO uint32_t APB1HENR;     /*!< RCC APB1 peripheral clock  High Word register,                  Address offset: 0x1C */
+  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clock  register,                            Address offset: 0x20 */
+  __IO uint32_t APB4ENR;      /*!< RCC APB4 peripheral clock  register,                            Address offset: 0x24 */
+  uint32_t      RESERVED9;    /*!< Reserved,                                                       Address offset: 0x28 */
+  __IO uint32_t AHB3LPENR;    /*!< RCC AHB3 peripheral sleep clock  register,                      Address offset: 0x3C */
+  __IO uint32_t AHB1LPENR;    /*!< RCC AHB1 peripheral sleep clock  register,                      Address offset: 0x40 */
+  __IO uint32_t AHB2LPENR;    /*!< RCC AHB2 peripheral sleep clock  register,                      Address offset: 0x44 */
+  __IO uint32_t AHB4LPENR;    /*!< RCC AHB4 peripheral sleep clock  register,                      Address offset: 0x48 */
+  __IO uint32_t APB3LPENR;    /*!< RCC APB3 peripheral sleep clock  register,                      Address offset: 0x4C */
+  __IO uint32_t APB1LLPENR;   /*!< RCC APB1 peripheral sleep clock  Low Word register,             Address offset: 0x50 */
+  __IO uint32_t APB1HLPENR;   /*!< RCC APB1 peripheral sleep clock  High Word register,            Address offset: 0x54 */
+  __IO uint32_t APB2LPENR;    /*!< RCC APB2 peripheral sleep clock  register,                      Address offset: 0x58 */
+  __IO uint32_t APB4LPENR;    /*!< RCC APB4 peripheral sleep clock  register,                      Address offset: 0x5C */
+  uint32_t     RESERVED10[4]; /*!< Reserved, 0x60-0x6C                                             Address offset: 0x60 */
+
+} RCC_Core_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Audio Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */
+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */
+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */
+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */
+} SAI_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+/**
+  * @brief SPDIF-RX Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */
+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */
+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */
+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */
+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */
+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */
+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */
+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */
+} SPDIFRX_TypeDef;
+
+
+/**
+  * @brief Secure digital input/output Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */
+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */
+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */
+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */
+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */
+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */
+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */
+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */
+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */
+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */
+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */
+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */
+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */
+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */
+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */
+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */
+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */
+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */
+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */
+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */
+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */
+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */
+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */
+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */
+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */
+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */
+} SDMMC_TypeDef;
+
+
+/**
+  * @brief Delay Block DLYB
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */
+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */
+} DLYB_TypeDef;
+
+/**
+  * @brief HW Semaphore HSEM
+  */
+
+typedef struct
+{
+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */
+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */
+  __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */
+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */
+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */
+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */
+  __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */
+  __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */
+  __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */
+  __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */
+   uint32_t  Reserved[8];   /* Reserved                                         Address offset: 120h-13Ch*/
+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */
+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */
+
+} HSEM_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
+} HSEM_Common_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */
+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */
+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */
+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */
+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */
+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */
+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */
+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */
+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */
+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */
+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */
+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */
+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */
+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */
+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */
+
+} SPI_TypeDef;
+/**
+  * @brief QUAD Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */
+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */
+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */
+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */
+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */
+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */
+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */
+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */
+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */
+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */
+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */
+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */
+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */
+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */
+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */
+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
+} TIM_TypeDef;
+
+/**
+  * @brief LPTIMIMER
+  */
+typedef struct
+{
+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */
+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */
+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */
+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */
+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */
+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */
+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */
+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */
+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */
+} LPTIM_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+typedef struct
+{
+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */
+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */
+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */
+} COMPOPT_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */
+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */
+} USART_TypeDef;
+
+/**
+  * @brief Single Wire Protocol Master Interface SPWMI
+  */
+typedef struct
+{
+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */
+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */
+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */
+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */
+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */
+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */
+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */
+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */
+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */
+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @brief RAM_ECC_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */
+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */
+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */
+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */
+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */
+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */
+} RAMECC_MonitorTypeDef;
+
+typedef struct
+{
+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */
+} RAMECC_TypeDef;
+/**
+  * @}
+  */
+
+
+
+/**
+  * @brief High resolution Timer (HRTIM)
+  */
+/* HRTIM master registers definition */
+typedef struct
+{
+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */
+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */
+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interrupt clear register,             Address offset: 0x08 */
+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */
+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */
+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */
+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */
+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */
+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */
+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */
+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */
+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */
+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */
+}HRTIM_Master_TypeDef;
+
+/* HRTIM Timer A to E registers definition */
+typedef struct
+{
+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */
+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */
+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */
+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */
+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */
+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */
+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */
+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */
+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */
+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */
+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */
+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */
+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */
+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */
+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */
+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */
+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */
+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */
+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */
+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */
+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */
+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */
+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */
+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */
+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */
+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */
+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */
+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */
+}HRTIM_Timerx_TypeDef;
+
+/* HRTIM common register definition */
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */
+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */
+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */
+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */
+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */
+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */
+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */
+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */
+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */
+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */
+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */
+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */
+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */
+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */
+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */
+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */
+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */
+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */
+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */
+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */
+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */
+}HRTIM_Common_TypeDef;
+
+/* HRTIM  register definition */
+typedef struct {
+  HRTIM_Master_TypeDef sMasterRegs;
+  HRTIM_Timerx_TypeDef sTimerxRegs[5];
+  uint32_t             RESERVED0[32];
+  HRTIM_Common_TypeDef sCommonRegs;
+}HRTIM_TypeDef;
+/**
+  * @brief RNG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @brief MDIOS
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t WRFR;
+  __IO uint32_t CWRFR;
+  __IO uint32_t RDFR;
+  __IO uint32_t CRDFR;
+  __IO uint32_t SR;
+  __IO uint32_t CLRFR;
+  uint32_t RESERVED[57];
+  __IO uint32_t DINR0;
+  __IO uint32_t DINR1;
+  __IO uint32_t DINR2;
+  __IO uint32_t DINR3;
+  __IO uint32_t DINR4;
+  __IO uint32_t DINR5;
+  __IO uint32_t DINR6;
+  __IO uint32_t DINR7;
+  __IO uint32_t DINR8;
+  __IO uint32_t DINR9;
+  __IO uint32_t DINR10;
+  __IO uint32_t DINR11;
+  __IO uint32_t DINR12;
+  __IO uint32_t DINR13;
+  __IO uint32_t DINR14;
+  __IO uint32_t DINR15;
+  __IO uint32_t DINR16;
+  __IO uint32_t DINR17;
+  __IO uint32_t DINR18;
+  __IO uint32_t DINR19;
+  __IO uint32_t DINR20;
+  __IO uint32_t DINR21;
+  __IO uint32_t DINR22;
+  __IO uint32_t DINR23;
+  __IO uint32_t DINR24;
+  __IO uint32_t DINR25;
+  __IO uint32_t DINR26;
+  __IO uint32_t DINR27;
+  __IO uint32_t DINR28;
+  __IO uint32_t DINR29;
+  __IO uint32_t DINR30;
+  __IO uint32_t DINR31;
+  __IO uint32_t DOUTR0;
+  __IO uint32_t DOUTR1;
+  __IO uint32_t DOUTR2;
+  __IO uint32_t DOUTR3;
+  __IO uint32_t DOUTR4;
+  __IO uint32_t DOUTR5;
+  __IO uint32_t DOUTR6;
+  __IO uint32_t DOUTR7;
+  __IO uint32_t DOUTR8;
+  __IO uint32_t DOUTR9;
+  __IO uint32_t DOUTR10;
+  __IO uint32_t DOUTR11;
+  __IO uint32_t DOUTR12;
+  __IO uint32_t DOUTR13;
+  __IO uint32_t DOUTR14;
+  __IO uint32_t DOUTR15;
+  __IO uint32_t DOUTR16;
+  __IO uint32_t DOUTR17;
+  __IO uint32_t DOUTR18;
+  __IO uint32_t DOUTR19;
+  __IO uint32_t DOUTR20;
+  __IO uint32_t DOUTR21;
+  __IO uint32_t DOUTR22;
+  __IO uint32_t DOUTR23;
+  __IO uint32_t DOUTR24;
+  __IO uint32_t DOUTR25;
+  __IO uint32_t DOUTR26;
+  __IO uint32_t DOUTR27;
+  __IO uint32_t DOUTR28;
+  __IO uint32_t DOUTR29;
+  __IO uint32_t DOUTR30;
+  __IO uint32_t DOUTR31;
+} MDIOS_TypeDef;
+
+
+/**
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/
+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/
+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/
+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */
+  uint32_t  Reserved6;                /*!< Reserved                                     050h */
+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */
+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */
+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */
+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */
+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
+} USB_OTG_GlobalTypeDef;
+
+
+/**
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+
+/**
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+
+/**
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/**
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+/**
+  * @}
+  */
+
+
+/**
+  * @brief Global Programmer View
+  */
+
+typedef struct
+{
+  uint32_t      RESERVED0[2036];     /*!< Reserved,                                                                           Address offset: 0x00-0x1FCC     */
+  __IO uint32_t AXI_PERIPH_ID_4;     /*!< AXI interconnect - peripheral ID4 register,                                         Address offset: 0x1FD0          */
+  uint32_t      AXI_PERIPH_ID_5;     /*!< Reserved,                                                                           Address offset: 0x1FD4          */
+  uint32_t      AXI_PERIPH_ID_6;     /*!< Reserved,                                                                           Address offset: 0x1FD8          */
+  uint32_t      AXI_PERIPH_ID_7;     /*!< Reserved,                                                                           Address offset: 0x1FDC          */
+  __IO uint32_t AXI_PERIPH_ID_0;     /*!< AXI interconnect - peripheral ID0 register,                                         Address offset: 0x1FE0          */
+  __IO uint32_t AXI_PERIPH_ID_1;     /*!< AXI interconnect - peripheral ID1 register,                                         Address offset: 0x1FE4          */
+  __IO uint32_t AXI_PERIPH_ID_2;     /*!< AXI interconnect - peripheral ID2 register,                                         Address offset: 0x1FE8          */
+  __IO uint32_t AXI_PERIPH_ID_3;     /*!< AXI interconnect - peripheral ID3 register,                                         Address offset: 0x1FEC          */
+  __IO uint32_t AXI_COMP_ID_0;       /*!< AXI interconnect - component ID0 register,                                          Address offset: 0x1FF0          */
+  __IO uint32_t AXI_COMP_ID_1;       /*!< AXI interconnect - component ID1 register,                                          Address offset: 0x1FF4          */
+  __IO uint32_t AXI_COMP_ID_2;       /*!< AXI interconnect - component ID2 register,                                          Address offset: 0x1FF8          */
+  __IO uint32_t AXI_COMP_ID_3;       /*!< AXI interconnect - component ID3 register,                                          Address offset: 0x1FFC          */
+  uint32_t      RESERVED1[2];        /*!< Reserved,                                                                           Address offset: 0x2000-0x2004   */
+  __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register,           Address offset: 0x2008          */
+  uint32_t      RESERVED2[6];        /*!< Reserved,                                                                           Address offset: 0x200C-0x2020   */
+  __IO uint32_t AXI_TARG1_FN_MOD2;   /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register,                      Address offset: 0x2024          */
+  uint32_t      RESERVED3;           /*!< Reserved,                                                                           Address offset: 0x2028          */
+  __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register,           Address offset: 0x202C          */
+  uint32_t      RESERVED4[54];       /*!< Reserved,                                                                           Address offset: 0x2030-0x2104   */
+  __IO uint32_t AXI_TARG1_FN_MOD;    /*!< AXI interconnect - TARG 1 issuing functionality modification register,              Address offset: 0x2108          */
+  uint32_t      RESERVED5[959];      /*!< Reserved,                                                                           Address offset: 0x210C-0x3004   */
+  __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register,           Address offset: 0x3008          */
+  uint32_t      RESERVED6[6];        /*!< Reserved,                                                                           Address offset: 0x300C-0x3020   */
+  __IO uint32_t AXI_TARG2_FN_MOD2;   /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register,                      Address offset: 0x3024          */
+  uint32_t      RESERVED7;           /*!< Reserved,                                                                           Address offset: 0x3028          */
+  __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register,           Address offset: 0x302C          */
+  uint32_t      RESERVED8[54];       /*!< Reserved,                                                                           Address offset: 0x3030-0x3104   */
+  __IO uint32_t AXI_TARG2_FN_MOD;    /*!< AXI interconnect - TARG 2 issuing functionality modification register,              Address offset: 0x3108          */
+  uint32_t      RESERVED9[959];      /*!< Reserved,                                                                           Address offset: 0x310C-0x4004   */
+  __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;   /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register,          Address offset: 0x4008          */
+  uint32_t      RESERVED10[1023];    /*!< Reserved,                                                                           Address offset: 0x400C-0x5004   */
+  __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register,           Address offset: 0x5008          */
+  uint32_t      RESERVED11[1023];    /*!< Reserved,                                                                           Address offset: 0x500C-0x6004   */
+  __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register,           Address offset: 0x6008          */
+  uint32_t      RESERVED12[1023];    /*!< Reserved,                                                                           Address offset: 0x600C-0x7004   */
+  __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register,           Address offset: 0x7008          */
+  uint32_t      RESERVED13[1023];    /*!< Reserved,                                                                           Address offset: 0x700C-0x8004   */
+  __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;  /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register,           Address offset: 0x8008          */
+  uint32_t      RESERVED14[6];       /*!< Reserved,                                                                           Address offset: 0x800C-0x8020   */
+  __IO uint32_t AXI_TARG7_FN_MOD2;   /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register,                      Address offset: 0x8024          */
+  uint32_t      RESERVED15;          /*!< Reserved,                                                                           Address offset: 0x8028          */
+  __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register,           Address offset: 0x802C          */
+  uint32_t      RESERVED16[54];      /*!< Reserved,                                                                           Address offset: 0x8030-0x8104   */
+  __IO uint32_t AXI_TARG7_FN_MOD;    /*!< AXI interconnect - TARG 7 issuing functionality modification register,              Address offset: 0x8108          */
+  uint32_t      RESERVED17[59334];    /*!< Reserved,                                                                          Address offset: 0x810C-0x42020  */
+  __IO uint32_t AXI_INI1_FN_MOD2;    /*!< AXI interconnect - INI 1 functionality modification 2 register,                     Address offset: 0x42024         */
+  __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register,                   Address offset: 0x42028         */
+  uint32_t      RESERVED18[53];      /*!< Reserved,                                                                           Address offset: 0x4202C-0x420FC */
+  __IO uint32_t AXI_INI1_READ_QOS;   /*!< AXI interconnect - INI 1 read QoS register,                                         Address offset: 0x42100         */
+  __IO uint32_t AXI_INI1_WRITE_QOS;  /*!< AXI interconnect - INI 1 write QoS register,                                        Address offset: 0x42104         */
+  __IO uint32_t AXI_INI1_FN_MOD;     /*!< AXI interconnect - INI 1 issuing functionality modification register,               Address offset: 0x42108         */
+  uint32_t      RESERVED19[1021];    /*!< Reserved,                                                                           Address offset: 0x4210C-0x430FC */
+  __IO uint32_t AXI_INI2_READ_QOS;   /*!< AXI interconnect - INI 2 read QoS register,                                         Address offset: 0x43100         */
+  __IO uint32_t AXI_INI2_WRITE_QOS;  /*!< AXI interconnect - INI 2 write QoS register,                                        Address offset: 0x43104         */
+  __IO uint32_t AXI_INI2_FN_MOD;     /*!< AXI interconnect - INI 2 issuing functionality modification register,               Address offset: 0x43108         */
+  uint32_t      RESERVED20[966];     /*!< Reserved,                                                                           Address offset: 0x4310C-0x44020 */
+  __IO uint32_t AXI_INI3_FN_MOD2;    /*!< AXI interconnect - INI 3 functionality modification 2 register,                     Address offset: 0x44024         */
+  __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register,                   Address offset: 0x44028         */
+  uint32_t      RESERVED21[53];      /*!< Reserved,                                                                           Address offset: 0x4402C-0x440FC */
+  __IO uint32_t AXI_INI3_READ_QOS;   /*!< AXI interconnect - INI 3 read QoS register,                                         Address offset: 0x44100         */
+  __IO uint32_t AXI_INI3_WRITE_QOS;  /*!< AXI interconnect - INI 3 write QoS register,                                        Address offset: 0x44104         */
+  __IO uint32_t AXI_INI3_FN_MOD;     /*!< AXI interconnect - INI 3 issuing functionality modification register,               Address offset: 0x44108         */
+  uint32_t      RESERVED22[1021];    /*!< Reserved,                                                                           Address offset: 0x4410C-0x450FC */
+  __IO uint32_t AXI_INI4_READ_QOS;   /*!< AXI interconnect - INI 4 read QoS register,                                         Address offset: 0x45100         */
+  __IO uint32_t AXI_INI4_WRITE_QOS;  /*!< AXI interconnect - INI 4 write QoS register,                                        Address offset: 0x45104         */
+  __IO uint32_t AXI_INI4_FN_MOD;     /*!< AXI interconnect - INI 4 issuing functionality modification register,               Address offset: 0x45108         */
+  uint32_t      RESERVED23[1021];    /*!< Reserved,                                                                           Address offset: 0x4510C-0x460FC */
+  __IO uint32_t AXI_INI5_READ_QOS;   /*!< AXI interconnect - INI 5 read QoS register,                                         Address offset: 0x46100         */
+  __IO uint32_t AXI_INI5_WRITE_QOS;  /*!< AXI interconnect - INI 5 write QoS register,                                        Address offset: 0x46104         */
+  __IO uint32_t AXI_INI5_FN_MOD;     /*!< AXI interconnect - INI 5 issuing functionality modification register,               Address offset: 0x46108         */
+  uint32_t      RESERVED24[1021];    /*!< Reserved,                                                                           Address offset: 0x4610C-0x470FC */
+  __IO uint32_t AXI_INI6_READ_QOS;   /*!< AXI interconnect - INI 6 read QoS register,                                         Address offset: 0x47100         */
+  __IO uint32_t AXI_INI6_WRITE_QOS;  /*!< AXI interconnect - INI 6 write QoS register,                                        Address offset: 0x47104         */
+  __IO uint32_t AXI_INI6_FN_MOD;     /*!< AXI interconnect - INI 6 issuing functionality modification register,               Address offset: 0x47108         */
+  uint32_t      RESERVED25[1021];    /*!< Reserved,                                                                           Address offset: 0x4710C-0x480FC */
+  __IO uint32_t AXI_INI7_READ_QOS;   /*!< AXI interconnect - INI 7 read QoS register,                                         Address offset: 0x48100         */
+  __IO uint32_t AXI_INI7_WRITE_QOS;  /*!< AXI interconnect - INI 7 write QoS register,                                        Address offset: 0x48104         */
+  __IO uint32_t AXI_INI7_FN_MOD;     /*!< AXI interconnect - INI 7 issuing functionality modification register,               Address offset: 0x48108         */
+
+} GPV_TypeDef;
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */
+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */
+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */
+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */
+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */
+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */
+
+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */
+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */
+
+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */
+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */
+
+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */
+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */
+
+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */
+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */
+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */
+
+/* Legacy define */
+#define FLASH_BASE                FLASH_BANK1_BASE
+
+/*!< Device electronic signature memory map */
+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */
+
+
+/*!< Peripheral memory map */
+#define D2_APB1PERIPH_BASE        PERIPH_BASE
+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)
+
+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)
+
+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)
+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)
+
+/*!< Legacy Peripheral memory map */
+#define APB1PERIPH_BASE        PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< D1_AHB1PERIPH peripherals */
+
+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)
+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)
+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)
+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)
+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)
+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)
+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)
+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)
+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)
+
+/*!< D2_AHB1PERIPH peripherals */
+
+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)
+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)
+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)
+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)
+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)
+#define ART_BASE                (D2_AHB1PERIPH_BASE + 0x4400UL)
+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE            (ETH_BASE)
+
+/*!< USB registers base address */
+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)
+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)
+#define USB_OTG_GLOBAL_BASE                  (0x000UL)
+#define USB_OTG_DEVICE_BASE                  (0x800UL)
+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)
+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)
+#define USB_OTG_EP_REG_SIZE                  (0x20UL)
+#define USB_OTG_HOST_BASE                    (0x400UL)
+#define USB_OTG_HOST_PORT_BASE               (0x440UL)
+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)
+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)
+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)
+#define USB_OTG_FIFO_BASE                    (0x1000UL)
+#define USB_OTG_FIFO_SIZE                    (0x1000UL)
+
+/*!< D2_AHB2PERIPH peripherals */
+
+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)
+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)
+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)
+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)
+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)
+
+/*!< D3_AHB1PERIPH peripherals */
+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)
+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)
+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)
+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)
+#define RCC_C1_BASE           (RCC_BASE + 0x130UL)
+#define RCC_C2_BASE           (RCC_BASE + 0x190UL)
+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)
+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)
+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)
+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)
+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)
+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)
+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)
+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)
+
+/*!< D1_APB1PERIPH peripherals */
+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)
+#define DSI_BASE              (D1_APB1PERIPH_BASE)
+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)
+
+/*!< D2_APB1PERIPH peripherals */
+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)
+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)
+
+#define WWDG2_BASE            (D2_APB1PERIPH_BASE + 0x2C00UL)
+
+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)
+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)
+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)
+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)
+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)
+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)
+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)
+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)
+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)
+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)
+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)
+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)
+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)
+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)
+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)
+
+/*!< D2_APB2PERIPH peripherals */
+
+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)
+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)
+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)
+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)
+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)
+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)
+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)
+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)
+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)
+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)
+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)
+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)
+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)
+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)
+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)
+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)
+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)
+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)
+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)
+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)
+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)
+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)
+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)
+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)
+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)
+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)
+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)
+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)
+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)
+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)
+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)
+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)
+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)
+
+
+/*!< D3_APB1PERIPH peripherals */
+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)
+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)
+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)
+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)
+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)
+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)
+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)
+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)
+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)
+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)
+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)
+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)
+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)
+#define COMP2_BASE            (COMP12_BASE + 0x10UL)
+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)
+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)
+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)
+
+#define IWDG2_BASE            (D3_APB1PERIPH_BASE + 0x4C00UL)
+
+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)
+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)
+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)
+
+
+
+
+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)
+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)
+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)
+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)
+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)
+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)
+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)
+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)
+
+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)
+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)
+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)
+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)
+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)
+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)
+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)
+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)
+
+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)
+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)
+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)
+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)
+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)
+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)
+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)
+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)
+
+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)
+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)
+
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+
+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)
+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)
+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)
+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)
+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)
+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)
+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)
+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)
+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)
+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)
+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)
+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)
+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)
+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)
+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)
+
+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)
+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)
+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)
+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)
+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)
+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)
+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)
+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)
+
+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)
+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)
+
+/*!< FMC Banks registers base  address */
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           (0x5C001000UL)
+
+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)
+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)
+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)
+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)
+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)
+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)
+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)
+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)
+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)
+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)
+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)
+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)
+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)
+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
+
+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
+
+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
+
+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
+
+
+
+#define GPV_BASE       (PERIPH_BASE + 0x11000000UL)   /*!<  GPV_BASE       (PERIPH_BASE + 0x11000000UL)                    */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)
+
+#define WWDG2               ((WWDG_TypeDef *) WWDG2_BASE)
+#define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)
+
+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define CRS                 ((CRS_TypeDef *) CRS_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)
+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)
+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)
+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)
+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)
+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)
+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)
+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)
+
+
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)
+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)
+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)
+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
+
+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define RCC_C1              ((RCC_Core_TypeDef *) RCC_C1_BASE)
+#define RCC_C2              ((RCC_Core_TypeDef *) RCC_C2_BASE)
+
+#define ART                 ((ART_TypeDef *)  ART_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
+
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)
+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
+
+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)
+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
+
+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)
+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
+
+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)
+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
+
+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)
+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
+
+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
+
+
+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
+
+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
+
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+
+
+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
+
+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
+
+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)
+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
+
+
+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
+
+
+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)
+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)
+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)
+#if defined(CORE_CM4)
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
+#else  /* CORE_CM7 */
+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
+#endif /* CORE_CM4 */
+
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#define DSI                 ((DSI_TypeDef *)DSI_BASE)
+
+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)
+
+#define ETH                 ((ETH_TypeDef *)ETH_BASE)
+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)
+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
+
+
+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
+
+/* Legacy defines */
+#define USB_OTG_HS                   USB1_OTG_HS
+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE
+#define USB_OTG_FS                   USB2_OTG_FS
+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE
+
+#define GPV                ((GPV_TypeDef *) GPV_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  ADC VERSION  ********************************/
+#define ADC_VER_V5_X
+/********************  Bit definition for ADC_ISR register  ********************/
+#define ADC_ISR_ADRDY_Pos                 (0U)
+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */
+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */
+#define ADC_ISR_EOSMP_Pos                 (1U)
+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */
+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */
+#define ADC_ISR_EOC_Pos                   (2U)
+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */
+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */
+#define ADC_ISR_EOS_Pos                   (3U)
+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */
+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_ISR_OVR_Pos                   (4U)
+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */
+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */
+#define ADC_ISR_JEOC_Pos                  (5U)
+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */
+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */
+#define ADC_ISR_JEOS_Pos                  (6U)
+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */
+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_ISR_AWD1_Pos                  (7U)
+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */
+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos                  (8U)
+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */
+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos                  (9U)
+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */
+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos                 (10U)
+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
+
+/********************  Bit definition for ADC_IER register  ********************/
+#define ADC_IER_ADRDYIE_Pos               (0U)
+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */
+#define ADC_IER_EOSMPIE_Pos               (1U)
+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */
+#define ADC_IER_EOCIE_Pos                 (2U)
+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */
+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */
+#define ADC_IER_EOSIE_Pos                 (3U)
+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */
+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */
+#define ADC_IER_OVRIE_Pos                 (4U)
+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */
+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */
+#define ADC_IER_JEOCIE_Pos                (5U)
+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */
+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */
+#define ADC_IER_JEOSIE_Pos                (6U)
+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */
+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */
+#define ADC_IER_AWD1IE_Pos                (7U)
+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */
+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */
+#define ADC_IER_AWD2IE_Pos                (8U)
+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */
+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */
+#define ADC_IER_AWD3IE_Pos                (9U)
+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */
+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */
+#define ADC_IER_JQOVFIE_Pos               (10U)
+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/********************  Bit definition for ADC_CR register  ********************/
+#define ADC_CR_ADEN_Pos                   (0U)
+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */
+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */
+#define ADC_CR_ADDIS_Pos                  (1U)
+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */
+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */
+#define ADC_CR_ADSTART_Pos                (2U)
+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */
+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */
+#define ADC_CR_JADSTART_Pos               (3U)
+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */
+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */
+#define ADC_CR_ADSTP_Pos                  (4U)
+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */
+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */
+#define ADC_CR_JADSTP_Pos                 (5U)
+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */
+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */
+#define ADC_CR_BOOST_Pos                  (8U)
+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */
+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */
+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */
+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */
+#define ADC_CR_ADCALLIN_Pos               (16U)
+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */
+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */
+#define ADC_CR_LINCALRDYW1_Pos            (22U)
+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */
+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */
+#define ADC_CR_LINCALRDYW2_Pos            (23U)
+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */
+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */
+#define ADC_CR_LINCALRDYW3_Pos            (24U)
+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */
+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */
+#define ADC_CR_LINCALRDYW4_Pos            (25U)
+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */
+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */
+#define ADC_CR_LINCALRDYW5_Pos            (26U)
+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */
+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */
+#define ADC_CR_LINCALRDYW6_Pos            (27U)
+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */
+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */
+#define ADC_CR_ADVREGEN_Pos               (28U)
+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */
+#define ADC_CR_DEEPPWD_Pos                (29U)
+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */
+#define ADC_CR_ADCALDIF_Pos               (30U)
+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */
+#define ADC_CR_ADCAL_Pos                  (31U)
+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */
+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */
+
+/********************  Bit definition for ADC_CFGR register  ********************/
+#define ADC_CFGR_DMNGT_Pos                (0U)
+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */
+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */
+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */
+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */
+
+#define ADC_CFGR_RES_Pos                  (2U)
+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */
+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */
+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */
+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */
+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */
+
+#define ADC_CFGR_EXTSEL_Pos               (5U)
+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */
+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */
+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */
+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos                (10U)
+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */
+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos               (12U)
+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */
+#define ADC_CFGR_CONT_Pos                 (13U)
+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */
+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */
+#define ADC_CFGR_AUTDLY_Pos               (14U)
+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */
+
+#define ADC_CFGR_DISCEN_Pos               (16U)
+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */
+
+#define ADC_CFGR_DISCNUM_Pos              (17U)
+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */
+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos              (20U)
+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */
+#define ADC_CFGR_JQM_Pos                  (21U)
+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */
+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */
+#define ADC_CFGR_AWD1SGL_Pos              (22U)
+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR_AWD1EN_Pos               (23U)
+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */
+#define ADC_CFGR_JAWD1EN_Pos              (24U)
+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */
+#define ADC_CFGR_JAUTO_Pos                (25U)
+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */
+
+#define ADC_CFGR_AWD1CH_Pos               (26U)
+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */
+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos                (31U)
+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */
+
+/********************  Bit definition for ADC_CFGR2 register  ********************/
+#define ADC_CFGR2_ROVSE_Pos               (0U)
+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */
+#define ADC_CFGR2_JOVSE_Pos               (1U)
+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */
+
+#define ADC_CFGR2_OVSS_Pos                (5U)
+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */
+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos               (9U)
+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */
+#define ADC_CFGR2_ROVSM_Pos               (10U)
+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */
+
+#define ADC_CFGR2_RSHIFT1_Pos             (11U)
+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */
+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */
+#define ADC_CFGR2_RSHIFT2_Pos             (12U)
+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */
+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */
+#define ADC_CFGR2_RSHIFT3_Pos             (13U)
+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */
+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */
+#define ADC_CFGR2_RSHIFT4_Pos             (14U)
+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */
+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */
+
+#define ADC_CFGR2_OVSR_Pos                (16U)
+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */
+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */
+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */
+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */
+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */
+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */
+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */
+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */
+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */
+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */
+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */
+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */
+
+#define ADC_CFGR2_LSHIFT_Pos              (28U)
+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */
+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */
+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */
+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */
+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */
+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_SMPR1 register  ********************/
+#define ADC_SMPR1_SMP0_Pos                (0U)
+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */
+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos                (3U)
+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */
+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos                (6U)
+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */
+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos                (9U)
+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */
+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos                (12U)
+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */
+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos                (15U)
+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */
+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos                (18U)
+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */
+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos                (21U)
+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */
+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos                (24U)
+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */
+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos                (27U)
+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */
+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_SMPR2 register  ********************/
+#define ADC_SMPR2_SMP10_Pos               (0U)
+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */
+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos               (3U)
+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */
+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos               (6U)
+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */
+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos               (9U)
+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */
+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos               (12U)
+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */
+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos               (15U)
+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */
+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos               (18U)
+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */
+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos               (21U)
+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */
+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos               (24U)
+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */
+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos               (27U)
+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */
+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */
+
+/********************  Bit definition for ADC_PCSEL register  ********************/
+#define ADC_PCSEL_PCSEL_Pos               (0U)
+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */
+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */
+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */
+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */
+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */
+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */
+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */
+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */
+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */
+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */
+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */
+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */
+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */
+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */
+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */
+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */
+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */
+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */
+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */
+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */
+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */
+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */
+
+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/
+#define ADC_LTR_LT_Pos                    (0U)
+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
+
+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/
+#define ADC_HTR_HT_Pos                    (0U)
+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */
+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
+
+
+/********************  Bit definition for ADC_SQR1 register  ********************/
+#define ADC_SQR1_L_Pos                    (0U)
+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */
+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence length */
+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */
+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */
+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */
+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos                  (6U)
+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */
+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos                  (12U)
+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */
+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos                  (18U)
+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */
+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos                  (24U)
+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */
+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR2 register  ********************/
+#define ADC_SQR2_SQ5_Pos                  (0U)
+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */
+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */
+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos                  (6U)
+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */
+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos                  (12U)
+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */
+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos                  (18U)
+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */
+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos                  (24U)
+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */
+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR3 register  ********************/
+#define ADC_SQR3_SQ10_Pos                 (0U)
+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */
+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */
+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos                 (6U)
+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */
+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos                 (12U)
+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */
+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos                 (18U)
+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */
+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos                 (24U)
+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */
+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */
+
+/********************  Bit definition for ADC_SQR4 register  ********************/
+#define ADC_SQR4_SQ15_Pos                 (0U)
+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */
+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */
+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos                 (6U)
+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */
+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_RDATA_Pos                  (0U)
+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */
+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */
+
+/********************  Bit definition for ADC_JSQR register  ********************/
+#define ADC_JSQR_JL_Pos                   (0U)
+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */
+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */
+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */
+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos              (2U)
+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */
+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */
+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */
+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */
+
+#define ADC_JSQR_JEXTEN_Pos               (7U)
+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */
+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */
+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */
+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */
+
+#define ADC_JSQR_JSQ1_Pos                 (9U)
+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */
+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */
+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */
+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */
+
+#define ADC_JSQR_JSQ2_Pos                 (15U)
+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */
+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */
+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */
+
+#define ADC_JSQR_JSQ3_Pos                 (21U)
+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */
+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */
+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */
+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */
+
+#define ADC_JSQR_JSQ4_Pos                 (27U)
+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */
+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */
+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */
+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_OFR1 register  ********************/
+#define ADC_OFR1_OFFSET1_Pos              (0U)
+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */
+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR1_SSATE_Pos                (31U)
+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR2 register  ********************/
+#define ADC_OFR2_OFFSET2_Pos              (0U)
+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */
+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR2_SSATE_Pos                (31U)
+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR3 register  ********************/
+#define ADC_OFR3_OFFSET3_Pos              (0U)
+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */
+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR3_SSATE_Pos                (31U)
+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_OFR4 register  ********************/
+#define ADC_OFR4_OFFSET4_Pos              (0U)
+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */
+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */
+
+#define ADC_OFR4_SSATE_Pos                (31U)
+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */
+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */
+
+
+/********************  Bit definition for ADC_JDR1 register  ********************/
+#define ADC_JDR1_JDATA_Pos                (0U)
+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR2 register  ********************/
+#define ADC_JDR2_JDATA_Pos                (0U)
+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR3 register  ********************/
+#define ADC_JDR3_JDATA_Pos                (0U)
+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_JDR4 register  ********************/
+#define ADC_JDR4_JDATA_Pos                (0U)
+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */
+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */
+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */
+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */
+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */
+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */
+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */
+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */
+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */
+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */
+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */
+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */
+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */
+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */
+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */
+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */
+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */
+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */
+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */
+
+/********************  Bit definition for ADC_AWD2CR register  ********************/
+#define ADC_AWD2CR_AWD2CH_Pos             (0U)
+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_AWD3CR register  ********************/
+#define ADC_AWD3CR_AWD3CH_Pos             (0U)
+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */
+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */
+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */
+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_DIFSEL register  ********************/
+#define ADC_DIFSEL_DIFSEL_Pos             (0U)
+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */
+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */
+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */
+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */
+
+/********************  Bit definition for ADC_CALFACT register  ********************/
+#define ADC_CALFACT_CALFACT_S_Pos         (0U)
+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT_CALFACT_D_Pos         (16U)
+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */
+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
+
+/********************  Bit definition for ADC_CALFACT2 register  ********************/
+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)
+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */
+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
+
+/*************************  ADC Common registers  *****************************/
+/********************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_ADRDY_MST_Pos             (0U)
+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */
+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */
+#define ADC_CSR_EOSMP_MST_Pos             (1U)
+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */
+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */
+#define ADC_CSR_EOC_MST_Pos               (2U)
+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */
+#define ADC_CSR_EOS_MST_Pos               (3U)
+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */
+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */
+#define ADC_CSR_OVR_MST_Pos               (4U)
+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */
+#define ADC_CSR_JEOC_MST_Pos              (5U)
+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */
+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */
+#define ADC_CSR_JEOS_MST_Pos              (6U)
+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */
+#define ADC_CSR_AWD1_MST_Pos              (7U)
+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */
+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */
+#define ADC_CSR_AWD2_MST_Pos              (8U)
+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */
+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */
+#define ADC_CSR_AWD3_MST_Pos              (9U)
+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */
+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */
+#define ADC_CSR_JQOVF_MST_Pos             (10U)
+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */
+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */
+#define ADC_CSR_ADRDY_SLV_Pos             (16U)
+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */
+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */
+#define ADC_CSR_EOSMP_SLV_Pos             (17U)
+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */
+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */
+#define ADC_CSR_EOC_SLV_Pos               (18U)
+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */
+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */
+#define ADC_CSR_EOS_SLV_Pos               (19U)
+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */
+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */
+#define ADC_CSR_OVR_SLV_Pos               (20U)
+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */
+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */
+#define ADC_CSR_JEOC_SLV_Pos              (21U)
+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */
+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */
+#define ADC_CSR_JEOS_SLV_Pos              (22U)
+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */
+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */
+#define ADC_CSR_AWD1_SLV_Pos              (23U)
+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */
+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */
+#define ADC_CSR_AWD2_SLV_Pos              (24U)
+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */
+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */
+#define ADC_CSR_AWD3_SLV_Pos              (25U)
+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */
+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */
+#define ADC_CSR_JQOVF_SLV_Pos             (26U)
+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */
+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */
+
+/********************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_DUAL_Pos                  (0U)
+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */
+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */
+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */
+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */
+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */
+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */
+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */
+
+#define ADC_CCR_DELAY_Pos                 (8U)
+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */
+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */
+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */
+
+
+#define ADC_CCR_DAMDF_Pos                 (14U)
+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */
+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */
+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */
+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */
+
+#define ADC_CCR_CKMODE_Pos                (16U)
+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */
+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */
+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos                 (18U)
+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */
+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */
+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos                (22U)
+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */
+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */
+#define ADC_CCR_TSEN_Pos                  (23U)
+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */
+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos                (24U)
+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */
+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */
+
+/********************  Bit definition for ADC_CDR register  *******************/
+#define ADC_CDR_RDATA_MST_Pos             (0U)
+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */
+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */
+
+#define ADC_CDR_RDATA_SLV_Pos             (16U)
+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */
+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */
+
+/********************  Bit definition for ADC_CDR2 register  ******************/
+#define ADC_CDR2_RDATA_ALT_Pos            (0U)
+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        ART accelerator                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for ART_CTR register  ********************/
+#define ART_CTR_EN_Pos              (0U)
+#define ART_CTR_EN_Msk              (0x1UL << ART_CTR_EN_Pos)                /*!< 0x00000001 */
+#define ART_CTR_EN                  ART_CTR_EN_Msk                           /*!< Cache enable*/
+
+#define ART_CTR_PCACHEADDR_Pos      (8U)
+#define ART_CTR_PCACHEADDR_Msk      (0xFFFUL << ART_CTR_PCACHEADDR_Pos)      /*!< 0x000FFF00 */
+#define ART_CTR_PCACHEADDR          ART_CTR_PCACHEADDR_Msk                   /*!< Cacheable page index */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                   VREFBUF                                  */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for VREFBUF_CSR register  ****************/
+#define VREFBUF_CSR_ENVR_Pos        (0U)
+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */
+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */
+#define VREFBUF_CSR_HIZ_Pos         (1U)
+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */
+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */
+#define VREFBUF_CSR_VRR_Pos         (3U)
+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */
+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */
+#define VREFBUF_CSR_VRS_Pos         (4U)
+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
+
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)
+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */
+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */
+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)
+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */
+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */
+
+/*******************  Bit definition for VREFBUF_CCR register  ****************/
+#define VREFBUF_CCR_TRIM_Pos        (0U)
+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */
+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Flexible Datarate Controller Area Network                  */
+/*                                                                            */
+/******************************************************************************/
+/*!<FDCAN control and status registers */
+/*****************  Bit definition for FDCAN_CREL register  *******************/
+#define FDCAN_CREL_DAY_Pos        (0U)
+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */
+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */
+#define FDCAN_CREL_MON_Pos        (8U)
+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */
+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */
+#define FDCAN_CREL_YEAR_Pos       (16U)
+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */
+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */
+#define FDCAN_CREL_SUBSTEP_Pos    (20U)
+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */
+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */
+#define FDCAN_CREL_STEP_Pos       (24U)
+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */
+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */
+#define FDCAN_CREL_REL_Pos        (28U)
+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */
+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */
+
+/*****************  Bit definition for FDCAN_ENDN register  *******************/
+#define FDCAN_ENDN_ETV_Pos        (0U)
+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endianness Test Value                   */
+
+/*****************  Bit definition for FDCAN_DBTP register  *******************/
+#define FDCAN_DBTP_DSJW_Pos       (0U)
+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */
+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */
+#define FDCAN_DBTP_DTSEG2_Pos     (4U)
+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */
+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */
+#define FDCAN_DBTP_DTSEG1_Pos     (8U)
+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */
+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */
+#define FDCAN_DBTP_DBRP_Pos       (16U)
+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */
+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */
+#define FDCAN_DBTP_TDC_Pos        (23U)
+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */
+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */
+
+/*****************  Bit definition for FDCAN_TEST register  *******************/
+#define FDCAN_TEST_LBCK_Pos       (4U)
+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */
+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */
+#define FDCAN_TEST_TX_Pos         (5U)
+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */
+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */
+#define FDCAN_TEST_RX_Pos         (7U)
+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */
+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */
+
+/*****************  Bit definition for FDCAN_RWD register  ********************/
+#define FDCAN_RWD_WDC_Pos         (0U)
+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */
+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */
+#define FDCAN_RWD_WDV_Pos         (8U)
+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */
+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */
+
+/*****************  Bit definition for FDCAN_CCCR register  ********************/
+#define FDCAN_CCCR_INIT_Pos       (0U)
+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */
+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */
+#define FDCAN_CCCR_CCE_Pos        (1U)
+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */
+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */
+#define FDCAN_CCCR_ASM_Pos        (2U)
+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */
+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */
+#define FDCAN_CCCR_CSA_Pos        (3U)
+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */
+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */
+#define FDCAN_CCCR_CSR_Pos        (4U)
+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */
+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */
+#define FDCAN_CCCR_MON_Pos        (5U)
+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */
+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */
+#define FDCAN_CCCR_DAR_Pos        (6U)
+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */
+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */
+#define FDCAN_CCCR_TEST_Pos       (7U)
+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */
+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */
+#define FDCAN_CCCR_FDOE_Pos       (8U)
+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */
+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */
+#define FDCAN_CCCR_BRSE_Pos       (9U)
+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */
+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */
+#define FDCAN_CCCR_PXHD_Pos       (12U)
+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */
+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */
+#define FDCAN_CCCR_EFBI_Pos       (13U)
+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */
+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */
+#define FDCAN_CCCR_TXP_Pos        (14U)
+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */
+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */
+#define FDCAN_CCCR_NISO_Pos       (15U)
+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */
+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */
+
+/*****************  Bit definition for FDCAN_NBTP register  ********************/
+#define FDCAN_NBTP_NTSEG2_Pos     (0U)
+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */
+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */
+#define FDCAN_NBTP_NTSEG1_Pos     (8U)
+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */
+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */
+#define FDCAN_NBTP_NBRP_Pos       (16U)
+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */
+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */
+#define FDCAN_NBTP_NSJW_Pos       (25U)
+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */
+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */
+
+/*****************  Bit definition for FDCAN_TSCC register  ********************/
+#define FDCAN_TSCC_TSS_Pos        (0U)
+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */
+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */
+#define FDCAN_TSCC_TCP_Pos        (16U)
+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */
+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */
+
+/*****************  Bit definition for FDCAN_TSCV register  ********************/
+#define FDCAN_TSCV_TSC_Pos        (0U)
+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */
+
+/*****************  Bit definition for FDCAN_TOCC register  ********************/
+#define FDCAN_TOCC_ETOC_Pos       (0U)
+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */
+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */
+#define FDCAN_TOCC_TOS_Pos        (1U)
+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */
+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */
+#define FDCAN_TOCC_TOP_Pos        (16U)
+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */
+
+/*****************  Bit definition for FDCAN_TOCV register  ********************/
+#define FDCAN_TOCV_TOC_Pos        (0U)
+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */
+
+/*****************  Bit definition for FDCAN_ECR register  *********************/
+#define FDCAN_ECR_TEC_Pos         (0U)
+#define FDCAN_ECR_TEC_Msk         (0xFFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x000000FF */
+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */
+#define FDCAN_ECR_REC_Pos         (8U)
+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */
+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */
+#define FDCAN_ECR_RP_Pos          (15U)
+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */
+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */
+#define FDCAN_ECR_CEL_Pos         (16U)
+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */
+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */
+
+/*****************  Bit definition for FDCAN_PSR register  *********************/
+#define FDCAN_PSR_LEC_Pos         (0U)
+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */
+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */
+#define FDCAN_PSR_ACT_Pos         (3U)
+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */
+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */
+#define FDCAN_PSR_EP_Pos          (5U)
+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */
+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */
+#define FDCAN_PSR_EW_Pos          (6U)
+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */
+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */
+#define FDCAN_PSR_BO_Pos          (7U)
+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */
+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */
+#define FDCAN_PSR_DLEC_Pos        (8U)
+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */
+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */
+#define FDCAN_PSR_RESI_Pos        (11U)
+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */
+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */
+#define FDCAN_PSR_RBRS_Pos        (12U)
+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */
+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */
+#define FDCAN_PSR_REDL_Pos        (13U)
+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */
+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */
+#define FDCAN_PSR_PXE_Pos         (14U)
+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */
+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */
+#define FDCAN_PSR_TDCV_Pos        (16U)
+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */
+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */
+
+/*****************  Bit definition for FDCAN_TDCR register  ********************/
+#define FDCAN_TDCR_TDCF_Pos       (0U)
+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */
+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */
+#define FDCAN_TDCR_TDCO_Pos       (8U)
+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */
+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */
+
+/*****************  Bit definition for FDCAN_IR register  **********************/
+#define FDCAN_IR_RF0N_Pos         (0U)
+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */
+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */
+#define FDCAN_IR_RF0W_Pos         (1U)
+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */
+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */
+#define FDCAN_IR_RF0F_Pos         (2U)
+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */
+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */
+#define FDCAN_IR_RF0L_Pos         (3U)
+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */
+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */
+#define FDCAN_IR_RF1N_Pos         (4U)
+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */
+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */
+#define FDCAN_IR_RF1W_Pos         (5U)
+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */
+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */
+#define FDCAN_IR_RF1F_Pos         (6U)
+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */
+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */
+#define FDCAN_IR_RF1L_Pos         (7U)
+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */
+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */
+#define FDCAN_IR_HPM_Pos          (8U)
+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */
+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */
+#define FDCAN_IR_TC_Pos           (9U)
+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */
+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */
+#define FDCAN_IR_TCF_Pos          (10U)
+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */
+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */
+#define FDCAN_IR_TFE_Pos          (11U)
+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */
+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */
+#define FDCAN_IR_TEFN_Pos         (12U)
+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */
+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */
+#define FDCAN_IR_TEFW_Pos         (13U)
+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */
+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */
+#define FDCAN_IR_TEFF_Pos         (14U)
+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */
+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */
+#define FDCAN_IR_TEFL_Pos         (15U)
+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */
+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */
+#define FDCAN_IR_TSW_Pos          (16U)
+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */
+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */
+#define FDCAN_IR_MRAF_Pos         (17U)
+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */
+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */
+#define FDCAN_IR_TOO_Pos          (18U)
+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */
+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */
+#define FDCAN_IR_DRX_Pos          (19U)
+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */
+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */
+#define FDCAN_IR_ELO_Pos          (22U)
+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */
+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */
+#define FDCAN_IR_EP_Pos           (23U)
+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */
+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */
+#define FDCAN_IR_EW_Pos           (24U)
+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */
+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */
+#define FDCAN_IR_BO_Pos           (25U)
+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */
+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */
+#define FDCAN_IR_WDI_Pos          (26U)
+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */
+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */
+#define FDCAN_IR_PEA_Pos          (27U)
+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */
+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */
+#define FDCAN_IR_PED_Pos          (28U)
+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */
+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */
+#define FDCAN_IR_ARA_Pos          (29U)
+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */
+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */
+
+/*****************  Bit definition for FDCAN_IE register  **********************/
+#define FDCAN_IE_RF0NE_Pos        (0U)
+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */
+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */
+#define FDCAN_IE_RF0WE_Pos        (1U)
+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */
+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */
+#define FDCAN_IE_RF0FE_Pos        (2U)
+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */
+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */
+#define FDCAN_IE_RF0LE_Pos        (3U)
+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */
+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */
+#define FDCAN_IE_RF1NE_Pos        (4U)
+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */
+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */
+#define FDCAN_IE_RF1WE_Pos        (5U)
+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */
+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */
+#define FDCAN_IE_RF1FE_Pos        (6U)
+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */
+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */
+#define FDCAN_IE_RF1LE_Pos        (7U)
+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */
+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */
+#define FDCAN_IE_HPME_Pos         (8U)
+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */
+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */
+#define FDCAN_IE_TCE_Pos          (9U)
+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */
+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */
+#define FDCAN_IE_TCFE_Pos         (10U)
+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */
+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */
+#define FDCAN_IE_TFEE_Pos         (11U)
+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */
+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */
+#define FDCAN_IE_TEFNE_Pos        (12U)
+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */
+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */
+#define FDCAN_IE_TEFWE_Pos        (13U)
+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */
+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */
+#define FDCAN_IE_TEFFE_Pos        (14U)
+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */
+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */
+#define FDCAN_IE_TEFLE_Pos        (15U)
+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */
+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */
+#define FDCAN_IE_TSWE_Pos         (16U)
+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */
+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */
+#define FDCAN_IE_MRAFE_Pos        (17U)
+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */
+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */
+#define FDCAN_IE_TOOE_Pos         (18U)
+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */
+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */
+#define FDCAN_IE_DRXE_Pos         (19U)
+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */
+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */
+#define FDCAN_IE_BECE_Pos         (20U)
+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */
+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */
+#define FDCAN_IE_BEUE_Pos         (21U)
+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */
+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */
+#define FDCAN_IE_ELOE_Pos         (22U)
+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */
+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */
+#define FDCAN_IE_EPE_Pos          (23U)
+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */
+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */
+#define FDCAN_IE_EWE_Pos          (24U)
+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */
+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */
+#define FDCAN_IE_BOE_Pos          (25U)
+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */
+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */
+#define FDCAN_IE_WDIE_Pos         (26U)
+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */
+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */
+#define FDCAN_IE_PEAE_Pos         (27U)
+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */
+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */
+#define FDCAN_IE_PEDE_Pos         (28U)
+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */
+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */
+#define FDCAN_IE_ARAE_Pos         (29U)
+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */
+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */
+
+/*****************  Bit definition for FDCAN_ILS register  **********************/
+#define FDCAN_ILS_RF0NL_Pos       (0U)
+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */
+#define FDCAN_ILS_RF0WL_Pos       (1U)
+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */
+#define FDCAN_ILS_RF0FL_Pos       (2U)
+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */
+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */
+#define FDCAN_ILS_RF0LL_Pos       (3U)
+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */
+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */
+#define FDCAN_ILS_RF1NL_Pos       (4U)
+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */
+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */
+#define FDCAN_ILS_RF1WL_Pos       (5U)
+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */
+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */
+#define FDCAN_ILS_RF1FL_Pos       (6U)
+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */
+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */
+#define FDCAN_ILS_RF1LL_Pos       (7U)
+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */
+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */
+#define FDCAN_ILS_HPML_Pos        (8U)
+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */
+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */
+#define FDCAN_ILS_TCL_Pos         (9U)
+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */
+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */
+#define FDCAN_ILS_TCFL_Pos        (10U)
+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */
+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */
+#define FDCAN_ILS_TFEL_Pos        (11U)
+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */
+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */
+#define FDCAN_ILS_TEFNL_Pos       (12U)
+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */
+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */
+#define FDCAN_ILS_TEFWL_Pos       (13U)
+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */
+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */
+#define FDCAN_ILS_TEFFL_Pos       (14U)
+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */
+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */
+#define FDCAN_ILS_TEFLL_Pos       (15U)
+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */
+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */
+#define FDCAN_ILS_TSWL_Pos        (16U)
+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */
+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */
+#define FDCAN_ILS_MRAFE_Pos       (17U)
+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */
+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */
+#define FDCAN_ILS_TOOE_Pos        (18U)
+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */
+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */
+#define FDCAN_ILS_DRXE_Pos        (19U)
+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */
+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */
+#define FDCAN_ILS_BECE_Pos        (20U)
+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */
+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */
+#define FDCAN_ILS_BEUE_Pos        (21U)
+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */
+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */
+#define FDCAN_ILS_ELOE_Pos        (22U)
+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */
+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */
+#define FDCAN_ILS_EPE_Pos         (23U)
+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */
+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */
+#define FDCAN_ILS_EWE_Pos         (24U)
+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */
+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */
+#define FDCAN_ILS_BOE_Pos         (25U)
+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */
+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */
+#define FDCAN_ILS_WDIE_Pos        (26U)
+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */
+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */
+#define FDCAN_ILS_PEAE_Pos        (27U)
+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */
+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */
+#define FDCAN_ILS_PEDE_Pos        (28U)
+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */
+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */
+#define FDCAN_ILS_ARAE_Pos        (29U)
+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */
+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */
+
+/*****************  Bit definition for FDCAN_ILE register  **********************/
+#define FDCAN_ILE_EINT0_Pos       (0U)
+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */
+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */
+#define FDCAN_ILE_EINT1_Pos       (1U)
+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */
+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */
+
+/*****************  Bit definition for FDCAN_GFC register  **********************/
+#define FDCAN_GFC_RRFE_Pos        (0U)
+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */
+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */
+#define FDCAN_GFC_RRFS_Pos        (1U)
+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */
+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */
+#define FDCAN_GFC_ANFE_Pos        (2U)
+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */
+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */
+#define FDCAN_GFC_ANFS_Pos        (4U)
+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */
+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */
+
+/*****************  Bit definition for FDCAN_SIDFC register  ********************/
+#define FDCAN_SIDFC_FLSSA_Pos     (2U)
+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_SIDFC_LSS_Pos       (16U)
+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */
+
+/*****************  Bit definition for FDCAN_XIDFC register  ********************/
+#define FDCAN_XIDFC_FLESA_Pos     (2U)
+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */
+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */
+#define FDCAN_XIDFC_LSE_Pos       (16U)
+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */
+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */
+
+/*****************  Bit definition for FDCAN_XIDAM register  ********************/
+#define FDCAN_XIDAM_EIDM_Pos      (0U)
+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */
+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */
+
+/*****************  Bit definition for FDCAN_HPMS register  *********************/
+#define FDCAN_HPMS_BIDX_Pos       (0U)
+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */
+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */
+#define FDCAN_HPMS_MSI_Pos        (6U)
+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */
+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */
+#define FDCAN_HPMS_FIDX_Pos       (8U)
+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */
+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */
+#define FDCAN_HPMS_FLST_Pos       (15U)
+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */
+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */
+
+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/
+#define FDCAN_NDAT1_ND0_Pos       (0U)
+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */
+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */
+#define FDCAN_NDAT1_ND1_Pos       (1U)
+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */
+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */
+#define FDCAN_NDAT1_ND2_Pos       (2U)
+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */
+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */
+#define FDCAN_NDAT1_ND3_Pos       (3U)
+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */
+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */
+#define FDCAN_NDAT1_ND4_Pos       (4U)
+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */
+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */
+#define FDCAN_NDAT1_ND5_Pos       (5U)
+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */
+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */
+#define FDCAN_NDAT1_ND6_Pos       (6U)
+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */
+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */
+#define FDCAN_NDAT1_ND7_Pos       (7U)
+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */
+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */
+#define FDCAN_NDAT1_ND8_Pos       (8U)
+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */
+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */
+#define FDCAN_NDAT1_ND9_Pos       (9U)
+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */
+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */
+#define FDCAN_NDAT1_ND10_Pos      (10U)
+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */
+#define FDCAN_NDAT1_ND11_Pos      (11U)
+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */
+#define FDCAN_NDAT1_ND12_Pos      (12U)
+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */
+#define FDCAN_NDAT1_ND13_Pos      (13U)
+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */
+#define FDCAN_NDAT1_ND14_Pos      (14U)
+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */
+#define FDCAN_NDAT1_ND15_Pos      (15U)
+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */
+#define FDCAN_NDAT1_ND16_Pos      (16U)
+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */
+#define FDCAN_NDAT1_ND17_Pos      (17U)
+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */
+#define FDCAN_NDAT1_ND18_Pos      (18U)
+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */
+#define FDCAN_NDAT1_ND19_Pos      (19U)
+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */
+#define FDCAN_NDAT1_ND20_Pos      (20U)
+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */
+#define FDCAN_NDAT1_ND21_Pos      (21U)
+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */
+#define FDCAN_NDAT1_ND22_Pos      (22U)
+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */
+#define FDCAN_NDAT1_ND23_Pos      (23U)
+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */
+#define FDCAN_NDAT1_ND24_Pos      (24U)
+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */
+#define FDCAN_NDAT1_ND25_Pos      (25U)
+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */
+#define FDCAN_NDAT1_ND26_Pos      (26U)
+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */
+#define FDCAN_NDAT1_ND27_Pos      (27U)
+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */
+#define FDCAN_NDAT1_ND28_Pos      (28U)
+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */
+#define FDCAN_NDAT1_ND29_Pos      (29U)
+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */
+#define FDCAN_NDAT1_ND30_Pos      (30U)
+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */
+#define FDCAN_NDAT1_ND31_Pos      (31U)
+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */
+
+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/
+#define FDCAN_NDAT2_ND32_Pos      (0U)
+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */
+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */
+#define FDCAN_NDAT2_ND33_Pos      (1U)
+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */
+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */
+#define FDCAN_NDAT2_ND34_Pos      (2U)
+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */
+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */
+#define FDCAN_NDAT2_ND35_Pos      (3U)
+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */
+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */
+#define FDCAN_NDAT2_ND36_Pos      (4U)
+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */
+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */
+#define FDCAN_NDAT2_ND37_Pos      (5U)
+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */
+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */
+#define FDCAN_NDAT2_ND38_Pos      (6U)
+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */
+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */
+#define FDCAN_NDAT2_ND39_Pos      (7U)
+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */
+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */
+#define FDCAN_NDAT2_ND40_Pos      (8U)
+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */
+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */
+#define FDCAN_NDAT2_ND41_Pos      (9U)
+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */
+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */
+#define FDCAN_NDAT2_ND42_Pos      (10U)
+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */
+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */
+#define FDCAN_NDAT2_ND43_Pos      (11U)
+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */
+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */
+#define FDCAN_NDAT2_ND44_Pos      (12U)
+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */
+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */
+#define FDCAN_NDAT2_ND45_Pos      (13U)
+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */
+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */
+#define FDCAN_NDAT2_ND46_Pos      (14U)
+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */
+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */
+#define FDCAN_NDAT2_ND47_Pos      (15U)
+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */
+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */
+#define FDCAN_NDAT2_ND48_Pos      (16U)
+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */
+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */
+#define FDCAN_NDAT2_ND49_Pos      (17U)
+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */
+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */
+#define FDCAN_NDAT2_ND50_Pos      (18U)
+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */
+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */
+#define FDCAN_NDAT2_ND51_Pos      (19U)
+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */
+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */
+#define FDCAN_NDAT2_ND52_Pos      (20U)
+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */
+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */
+#define FDCAN_NDAT2_ND53_Pos      (21U)
+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */
+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */
+#define FDCAN_NDAT2_ND54_Pos      (22U)
+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */
+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */
+#define FDCAN_NDAT2_ND55_Pos      (23U)
+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */
+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */
+#define FDCAN_NDAT2_ND56_Pos      (24U)
+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */
+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */
+#define FDCAN_NDAT2_ND57_Pos      (25U)
+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */
+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */
+#define FDCAN_NDAT2_ND58_Pos      (26U)
+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */
+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */
+#define FDCAN_NDAT2_ND59_Pos      (27U)
+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */
+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */
+#define FDCAN_NDAT2_ND60_Pos      (28U)
+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */
+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */
+#define FDCAN_NDAT2_ND61_Pos      (29U)
+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */
+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */
+#define FDCAN_NDAT2_ND62_Pos      (30U)
+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */
+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */
+#define FDCAN_NDAT2_ND63_Pos      (31U)
+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */
+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */
+
+/*****************  Bit definition for FDCAN_RXF0C register  ********************/
+#define FDCAN_RXF0C_F0SA_Pos      (2U)
+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */
+#define FDCAN_RXF0C_F0S_Pos       (16U)
+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */
+#define FDCAN_RXF0C_F0WM_Pos      (24U)
+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */
+#define FDCAN_RXF0C_F0OM_Pos      (31U)
+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF0S register  ********************/
+#define FDCAN_RXF0S_F0FL_Pos      (0U)
+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */
+#define FDCAN_RXF0S_F0GI_Pos      (8U)
+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */
+#define FDCAN_RXF0S_F0PI_Pos      (16U)
+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */
+#define FDCAN_RXF0S_F0F_Pos       (24U)
+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */
+#define FDCAN_RXF0S_RF0L_Pos      (25U)
+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF0A register  ********************/
+#define FDCAN_RXF0A_F0AI_Pos      (0U)
+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXBC register  ********************/
+#define FDCAN_RXBC_RBSA_Pos       (2U)
+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */
+
+/*****************  Bit definition for FDCAN_RXF1C register  ********************/
+#define FDCAN_RXF1C_F1SA_Pos      (2U)
+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */
+#define FDCAN_RXF1C_F1S_Pos       (16U)
+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */
+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */
+#define FDCAN_RXF1C_F1WM_Pos      (24U)
+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */
+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */
+#define FDCAN_RXF1C_F1OM_Pos      (31U)
+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */
+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */
+
+/*****************  Bit definition for FDCAN_RXF1S register  ********************/
+#define FDCAN_RXF1S_F1FL_Pos      (0U)
+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */
+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */
+#define FDCAN_RXF1S_F1GI_Pos      (8U)
+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */
+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */
+#define FDCAN_RXF1S_F1PI_Pos      (16U)
+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */
+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */
+#define FDCAN_RXF1S_F1F_Pos       (24U)
+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */
+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */
+#define FDCAN_RXF1S_RF1L_Pos      (25U)
+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */
+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */
+
+/*****************  Bit definition for FDCAN_RXF1A register  ********************/
+#define FDCAN_RXF1A_F1AI_Pos      (0U)
+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */
+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */
+
+/*****************  Bit definition for FDCAN_RXESC register  ********************/
+#define FDCAN_RXESC_F0DS_Pos      (0U)
+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */
+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */
+#define FDCAN_RXESC_F1DS_Pos      (4U)
+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */
+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */
+#define FDCAN_RXESC_RBDS_Pos      (8U)
+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */
+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBC register  *********************/
+#define FDCAN_TXBC_TBSA_Pos       (2U)
+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */
+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */
+#define FDCAN_TXBC_NDTB_Pos       (16U)
+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */
+#define FDCAN_TXBC_TFQS_Pos       (24U)
+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */
+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */
+#define FDCAN_TXBC_TFQM_Pos       (30U)
+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */
+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */
+
+/*****************  Bit definition for FDCAN_TXFQS register  *********************/
+#define FDCAN_TXFQS_TFFL_Pos      (0U)
+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */
+#define FDCAN_TXFQS_TFGI_Pos      (8U)
+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */
+#define FDCAN_TXFQS_TFQPI_Pos     (16U)
+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */
+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */
+#define FDCAN_TXFQS_TFQF_Pos      (21U)
+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */
+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */
+
+/*****************  Bit definition for FDCAN_TXESC register  *********************/
+#define FDCAN_TXESC_TBDS_Pos      (0U)
+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */
+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */
+
+/*****************  Bit definition for FDCAN_TXBRP register  *********************/
+#define FDCAN_TXBRP_TRP_Pos       (0U)
+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */
+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */
+
+/*****************  Bit definition for FDCAN_TXBAR register  *********************/
+#define FDCAN_TXBAR_AR_Pos        (0U)
+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */
+
+/*****************  Bit definition for FDCAN_TXBCR register  *********************/
+#define FDCAN_TXBCR_CR_Pos        (0U)
+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */
+
+/*****************  Bit definition for FDCAN_TXBTO register  *********************/
+#define FDCAN_TXBTO_TO_Pos        (0U)
+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */
+
+/*****************  Bit definition for FDCAN_TXBCF register  *********************/
+#define FDCAN_TXBCF_CF_Pos        (0U)
+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */
+
+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/
+#define FDCAN_TXBTIE_TIE_Pos      (0U)
+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */
+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */
+
+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/
+#define FDCAN_TXBCIE_CFIE_Pos     (0U)
+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */
+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */
+
+/*****************  Bit definition for FDCAN_TXEFC register  *********************/
+#define FDCAN_TXEFC_EFSA_Pos      (2U)
+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */
+#define FDCAN_TXEFC_EFS_Pos       (16U)
+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */
+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */
+#define FDCAN_TXEFC_EFWM_Pos      (24U)
+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */
+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */
+
+/*****************  Bit definition for FDCAN_TXEFS register  *********************/
+#define FDCAN_TXEFS_EFFL_Pos      (0U)
+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */
+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */
+#define FDCAN_TXEFS_EFGI_Pos      (8U)
+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */
+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */
+#define FDCAN_TXEFS_EFPI_Pos      (16U)
+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */
+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */
+#define FDCAN_TXEFS_EFF_Pos       (24U)
+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */
+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */
+#define FDCAN_TXEFS_TEFL_Pos      (25U)
+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */
+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */
+
+/*****************  Bit definition for FDCAN_TXEFA register  *********************/
+#define FDCAN_TXEFA_EFAI_Pos      (0U)
+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */
+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */
+
+/*****************  Bit definition for FDCAN_TTTMC register  *********************/
+#define FDCAN_TTTMC_TMSA_Pos      (2U)
+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */
+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */
+#define FDCAN_TTTMC_TME_Pos       (16U)
+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */
+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */
+
+/*****************  Bit definition for FDCAN_TTRMC register  *********************/
+#define FDCAN_TTRMC_RID_Pos       (0U)
+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */
+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */
+#define FDCAN_TTRMC_XTD_Pos       (30U)
+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */
+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */
+#define FDCAN_TTRMC_RMPS_Pos      (31U)
+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */
+
+/*****************  Bit definition for FDCAN_TTOCF register  *********************/
+#define FDCAN_TTOCF_OM_Pos        (0U)
+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */
+#define FDCAN_TTOCF_GEN_Pos       (3U)
+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */
+#define FDCAN_TTOCF_TM_Pos        (4U)
+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */
+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */
+#define FDCAN_TTOCF_LDSDL_Pos     (5U)
+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */
+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */
+#define FDCAN_TTOCF_IRTO_Pos      (8U)
+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */
+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */
+#define FDCAN_TTOCF_EECS_Pos      (15U)
+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */
+#define FDCAN_TTOCF_AWL_Pos       (16U)
+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */
+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */
+#define FDCAN_TTOCF_EGTF_Pos      (24U)
+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */
+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */
+#define FDCAN_TTOCF_ECC_Pos       (25U)
+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */
+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */
+#define FDCAN_TTOCF_EVTP_Pos      (26U)
+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */
+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */
+
+/*****************  Bit definition for FDCAN_TTMLM register  *********************/
+#define FDCAN_TTMLM_CCM_Pos       (0U)
+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */
+#define FDCAN_TTMLM_CSS_Pos       (6U)
+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */
+#define FDCAN_TTMLM_TXEW_Pos      (8U)
+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */
+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */
+#define FDCAN_TTMLM_ENTT_Pos      (16U)
+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */
+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */
+
+/*****************  Bit definition for FDCAN_TURCF register  *********************/
+#define FDCAN_TURCF_NCL_Pos       (0U)
+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */
+#define FDCAN_TURCF_DC_Pos        (16U)
+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */
+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */
+#define FDCAN_TURCF_ELT_Pos       (31U)
+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */
+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */
+
+/*****************  Bit definition for FDCAN_TTOCN register  ********************/
+#define FDCAN_TTOCN_SGT_Pos       (0U)
+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */
+#define FDCAN_TTOCN_ECS_Pos       (1U)
+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */
+#define FDCAN_TTOCN_SWP_Pos       (2U)
+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */
+#define FDCAN_TTOCN_SWS_Pos       (3U)
+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */
+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */
+#define FDCAN_TTOCN_RTIE_Pos      (5U)
+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */
+#define FDCAN_TTOCN_TMC_Pos       (6U)
+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */
+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */
+#define FDCAN_TTOCN_TTIE_Pos      (8U)
+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */
+#define FDCAN_TTOCN_GCS_Pos       (9U)
+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */
+#define FDCAN_TTOCN_FGP_Pos       (10U)
+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */
+#define FDCAN_TTOCN_TMG_Pos       (11U)
+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */
+#define FDCAN_TTOCN_NIG_Pos       (12U)
+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */
+#define FDCAN_TTOCN_ESCN_Pos      (13U)
+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */
+#define FDCAN_TTOCN_LCKC_Pos      (15U)
+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */
+
+/*****************  Bit definition for FDCAN_TTGTP register  ********************/
+#define FDCAN_TTGTP_TP_Pos        (0U)
+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */
+#define FDCAN_TTGTP_CTP_Pos       (16U)
+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */
+
+/*****************  Bit definition for FDCAN_TTTMK register  ********************/
+#define FDCAN_TTTMK_TM_Pos        (0U)
+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */
+#define FDCAN_TTTMK_TICC_Pos      (16U)
+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */
+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */
+#define FDCAN_TTTMK_LCKM_Pos      (31U)
+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */
+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */
+
+/*****************  Bit definition for FDCAN_TTIR register  ********************/
+#define FDCAN_TTIR_SBC_Pos        (0U)
+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */
+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */
+#define FDCAN_TTIR_SMC_Pos        (1U)
+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */
+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */
+#define FDCAN_TTIR_CSM_Pos        (2U)
+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */
+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */
+#define FDCAN_TTIR_SOG_Pos        (3U)
+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */
+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */
+#define FDCAN_TTIR_RTMI_Pos       (4U)
+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */
+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */
+#define FDCAN_TTIR_TTMI_Pos       (5U)
+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */
+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */
+#define FDCAN_TTIR_SWE_Pos        (6U)
+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */
+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */
+#define FDCAN_TTIR_GTW_Pos        (7U)
+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */
+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */
+#define FDCAN_TTIR_GTD_Pos        (8U)
+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */
+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */
+#define FDCAN_TTIR_GTE_Pos        (9U)
+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */
+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */
+#define FDCAN_TTIR_TXU_Pos        (10U)
+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */
+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */
+#define FDCAN_TTIR_TXO_Pos        (11U)
+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */
+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */
+#define FDCAN_TTIR_SE1_Pos        (12U)
+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */
+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */
+#define FDCAN_TTIR_SE2_Pos        (13U)
+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */
+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */
+#define FDCAN_TTIR_ELC_Pos        (14U)
+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */
+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */
+#define FDCAN_TTIR_IWT_Pos        (15U)
+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */
+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */
+#define FDCAN_TTIR_WT_Pos         (16U)
+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */
+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */
+#define FDCAN_TTIR_AW_Pos         (17U)
+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */
+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */
+#define FDCAN_TTIR_CER_Pos        (18U)
+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */
+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */
+
+/*****************  Bit definition for FDCAN_TTIE register  ********************/
+#define FDCAN_TTIE_SBCE_Pos       (0U)
+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */
+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */
+#define FDCAN_TTIE_SMCE_Pos       (1U)
+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */
+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */
+#define FDCAN_TTIE_CSME_Pos       (2U)
+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */
+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */
+#define FDCAN_TTIE_SOGE_Pos       (3U)
+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */
+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */
+#define FDCAN_TTIE_RTMIE_Pos      (4U)
+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */
+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */
+#define FDCAN_TTIE_TTMIE_Pos      (5U)
+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */
+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */
+#define FDCAN_TTIE_SWEE_Pos       (6U)
+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */
+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */
+#define FDCAN_TTIE_GTWE_Pos       (7U)
+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */
+#define FDCAN_TTIE_GTDE_Pos       (8U)
+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */
+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */
+#define FDCAN_TTIE_GTEE_Pos       (9U)
+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */
+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */
+#define FDCAN_TTIE_TXUE_Pos       (10U)
+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */
+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */
+#define FDCAN_TTIE_TXOE_Pos       (11U)
+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */
+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */
+#define FDCAN_TTIE_SE1E_Pos       (12U)
+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */
+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */
+#define FDCAN_TTIE_SE2E_Pos       (13U)
+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */
+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */
+#define FDCAN_TTIE_ELCE_Pos       (14U)
+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */
+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */
+#define FDCAN_TTIE_IWTE_Pos       (15U)
+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */
+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */
+#define FDCAN_TTIE_WTE_Pos        (16U)
+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */
+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */
+#define FDCAN_TTIE_AWE_Pos        (17U)
+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */
+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */
+#define FDCAN_TTIE_CERE_Pos       (18U)
+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */
+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */
+
+/*****************  Bit definition for FDCAN_TTILS register  ********************/
+#define FDCAN_TTILS_SBCS_Pos      (0U)
+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */
+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */
+#define FDCAN_TTILS_SMCS_Pos      (1U)
+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */
+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */
+#define FDCAN_TTILS_CSMS_Pos      (2U)
+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */
+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */
+#define FDCAN_TTILS_SOGS_Pos      (3U)
+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */
+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */
+#define FDCAN_TTILS_RTMIS_Pos     (4U)
+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */
+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */
+#define FDCAN_TTILS_TTMIS_Pos     (5U)
+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */
+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */
+#define FDCAN_TTILS_SWES_Pos      (6U)
+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */
+#define FDCAN_TTILS_GTWS_Pos      (7U)
+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */
+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */
+#define FDCAN_TTILS_GTDS_Pos      (8U)
+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */
+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */
+#define FDCAN_TTILS_GTES_Pos      (9U)
+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */
+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */
+#define FDCAN_TTILS_TXUS_Pos      (10U)
+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */
+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */
+#define FDCAN_TTILS_TXOS_Pos      (11U)
+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */
+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */
+#define FDCAN_TTILS_SE1S_Pos      (12U)
+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */
+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */
+#define FDCAN_TTILS_SE2S_Pos      (13U)
+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */
+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */
+#define FDCAN_TTILS_ELCS_Pos      (14U)
+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */
+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */
+#define FDCAN_TTILS_IWTS_Pos      (15U)
+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */
+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */
+#define FDCAN_TTILS_WTS_Pos       (16U)
+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */
+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */
+#define FDCAN_TTILS_AWS_Pos       (17U)
+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */
+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */
+#define FDCAN_TTILS_CERS_Pos      (18U)
+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */
+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */
+
+/*****************  Bit definition for FDCAN_TTOST register  ********************/
+#define FDCAN_TTOST_EL_Pos        (0U)
+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */
+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */
+#define FDCAN_TTOST_MS_Pos        (2U)
+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */
+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */
+#define FDCAN_TTOST_SYS_Pos       (4U)
+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */
+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */
+#define FDCAN_TTOST_QGTP_Pos      (6U)
+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */
+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */
+#define FDCAN_TTOST_QCS_Pos       (7U)
+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */
+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */
+#define FDCAN_TTOST_RTO_Pos       (8U)
+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */
+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */
+#define FDCAN_TTOST_WGTD_Pos      (22U)
+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */
+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */
+#define FDCAN_TTOST_GFI_Pos       (23U)
+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */
+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */
+#define FDCAN_TTOST_TMP_Pos       (24U)
+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */
+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */
+#define FDCAN_TTOST_GSI_Pos       (27U)
+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */
+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */
+#define FDCAN_TTOST_WFE_Pos       (28U)
+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */
+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */
+#define FDCAN_TTOST_AWE_Pos       (29U)
+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */
+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */
+#define FDCAN_TTOST_WECS_Pos      (30U)
+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */
+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */
+#define FDCAN_TTOST_SPL_Pos       (31U)
+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */
+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */
+
+/*****************  Bit definition for FDCAN_TURNA register  ********************/
+#define FDCAN_TURNA_NAV_Pos       (0U)
+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */
+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */
+
+/*****************  Bit definition for FDCAN_TTLGT register  ********************/
+#define FDCAN_TTLGT_LT_Pos        (0U)
+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */
+#define FDCAN_TTLGT_GT_Pos        (16U)
+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */
+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */
+
+/*****************  Bit definition for FDCAN_TTCTC register  ********************/
+#define FDCAN_TTCTC_CT_Pos        (0U)
+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */
+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */
+#define FDCAN_TTCTC_CC_Pos        (16U)
+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */
+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */
+
+/*****************  Bit definition for FDCAN_TTCPT register  ********************/
+#define FDCAN_TTCPT_CCV_Pos       (0U)
+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */
+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */
+#define FDCAN_TTCPT_SWV_Pos       (16U)
+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */
+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */
+
+/*****************  Bit definition for FDCAN_TTCSM register  ********************/
+#define FDCAN_TTCSM_CSM_Pos       (0U)
+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */
+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */
+
+/*****************  Bit definition for FDCAN_TTTS register  *********************/
+#define FDCAN_TTTS_SWTSEL_Pos     (0U)
+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */
+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */
+#define FDCAN_TTTS_EVTSEL_Pos     (4U)
+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */
+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */
+
+/********************************************************************************/
+/*                                                                              */
+/*                      FDCANCCU (Clock Calibration unit)                       */
+/*                                                                              */
+/********************************************************************************/
+
+/*****************  Bit definition for FDCANCCU_CREL register  ******************/
+#define FDCANCCU_CREL_DAY_Pos        (0U)
+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */
+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */
+#define FDCANCCU_CREL_MON_Pos        (8U)
+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */
+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */
+#define FDCANCCU_CREL_YEAR_Pos       (16U)
+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */
+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)
+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */
+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */
+#define FDCANCCU_CREL_STEP_Pos       (24U)
+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */
+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */
+#define FDCANCCU_CREL_REL_Pos        (28U)
+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */
+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */
+
+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/
+#define FDCANCCU_CCFG_TQBT_Pos       (0U)
+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */
+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */
+#define FDCANCCU_CCFG_BCC_Pos        (6U)
+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */
+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */
+#define FDCANCCU_CCFG_CFL_Pos        (7U)
+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */
+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */
+#define FDCANCCU_CCFG_OCPM_Pos       (8U)
+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */
+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */
+#define FDCANCCU_CCFG_CDIV_Pos       (16U)
+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */
+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */
+#define FDCANCCU_CCFG_SWR_Pos        (31U)
+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */
+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */
+
+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/
+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)
+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */
+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */
+#define FDCANCCU_CSTAT_TQC_Pos       (18U)
+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */
+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */
+#define FDCANCCU_CSTAT_CALS_Pos      (30U)
+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */
+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */
+
+/******************  Bit definition for FDCANCCU_CWD register  ******************/
+#define FDCANCCU_CWD_WDC_Pos         (0U)
+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */
+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */
+#define FDCANCCU_CWD_WDV_Pos         (16U)
+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */
+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */
+
+/******************  Bit definition for FDCANCCU_IR register  *******************/
+#define FDCANCCU_IR_CWE_Pos          (0U)
+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */
+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */
+#define FDCANCCU_IR_CSC_Pos          (1U)
+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */
+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */
+
+/******************  Bit definition for FDCANCCU_IE register  *******************/
+#define FDCANCCU_IE_CWEE_Pos         (0U)
+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */
+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */
+#define FDCANCCU_IE_CSCE_Pos         (1U)
+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */
+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          HDMI-CEC (CEC)                                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define CEC_CR_CECEN_Pos         (0U)
+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */
+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */
+#define CEC_CR_TXSOM_Pos         (1U)
+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */
+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */
+#define CEC_CR_TXEOM_Pos         (2U)
+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */
+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define CEC_CFGR_SFT_Pos         (0U)
+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */
+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */
+#define CEC_CFGR_RXTOL_Pos       (3U)
+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */
+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */
+#define CEC_CFGR_BRESTP_Pos      (4U)
+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */
+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */
+#define CEC_CFGR_BREGEN_Pos      (5U)
+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */
+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */
+#define CEC_CFGR_LBPEGEN_Pos     (6U)
+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */
+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */
+#define CEC_CFGR_SFTOPT_Pos      (8U)
+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */
+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */
+#define CEC_CFGR_BRDNOGEN_Pos    (7U)
+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */
+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */
+#define CEC_CFGR_OAR_Pos         (16U)
+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */
+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */
+#define CEC_CFGR_LSTN_Pos        (31U)
+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */
+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define CEC_TXDR_TXD_Pos         (0U)
+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */
+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define CEC_RXDR_RXD_Pos         (0U)
+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */
+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define CEC_ISR_RXBR_Pos         (0U)
+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */
+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */
+#define CEC_ISR_RXEND_Pos        (1U)
+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */
+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */
+#define CEC_ISR_RXOVR_Pos        (2U)
+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */
+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */
+#define CEC_ISR_BRE_Pos          (3U)
+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */
+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */
+#define CEC_ISR_SBPE_Pos         (4U)
+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */
+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */
+#define CEC_ISR_LBPE_Pos         (5U)
+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */
+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */
+#define CEC_ISR_RXACKE_Pos       (6U)
+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */
+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */
+#define CEC_ISR_ARBLST_Pos       (7U)
+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */
+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */
+#define CEC_ISR_TXBR_Pos         (8U)
+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */
+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */
+#define CEC_ISR_TXEND_Pos        (9U)
+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */
+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */
+#define CEC_ISR_TXUDR_Pos        (10U)
+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */
+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */
+#define CEC_ISR_TXERR_Pos        (11U)
+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */
+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */
+#define CEC_ISR_TXACKE_Pos       (12U)
+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */
+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define CEC_IER_RXBRIE_Pos       (0U)
+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */
+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */
+#define CEC_IER_RXENDIE_Pos      (1U)
+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */
+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */
+#define CEC_IER_RXOVRIE_Pos      (2U)
+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */
+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */
+#define CEC_IER_BREIE_Pos        (3U)
+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */
+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */
+#define CEC_IER_SBPEIE_Pos       (4U)
+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */
+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */
+#define CEC_IER_LBPEIE_Pos       (5U)
+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */
+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */
+#define CEC_IER_RXACKEIE_Pos     (6U)
+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */
+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */
+#define CEC_IER_ARBLSTIE_Pos     (7U)
+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */
+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */
+#define CEC_IER_TXBRIE_Pos       (8U)
+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */
+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */
+#define CEC_IER_TXENDIE_Pos      (9U)
+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */
+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */
+#define CEC_IER_TXUDRIE_Pos      (10U)
+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */
+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */
+#define CEC_IER_TXERRIE_Pos      (11U)
+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */
+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */
+#define CEC_IER_TXACKEIE_Pos     (12U)
+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */
+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos            (0U)
+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos          (0U)
+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos         (0U)
+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
+#define CRC_CR_POLYSIZE_Pos      (3U)
+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */
+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */
+#define CRC_CR_REV_IN_Pos        (5U)
+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */
+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */
+#define CRC_CR_REV_OUT_Pos       (7U)
+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define CRC_INIT_INIT_Pos        (0U)
+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
+
+/*******************  Bit definition for CRC_POL register  ********************/
+#define CRC_POL_POL_Pos          (0U)
+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRS Clock Recovery System                         */
+/******************************************************************************/
+
+/*******************  Bit definition for CRS_CR register  *********************/
+#define CRS_CR_SYNCOKIE_Pos       (0U)
+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */
+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE_Pos     (1U)
+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */
+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */
+#define CRS_CR_ERRIE_Pos          (2U)
+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */
+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */
+#define CRS_CR_ESYNCIE_Pos        (3U)
+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */
+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */
+#define CRS_CR_CEN_Pos            (5U)
+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */
+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN_Pos     (6U)
+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */
+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */
+#define CRS_CR_SWSYNC_Pos         (7U)
+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */
+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */
+#define CRS_CR_TRIM_Pos           (8U)
+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */
+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */
+
+/*******************  Bit definition for CRS_CFGR register  *********************/
+#define CRS_CFGR_RELOAD_Pos       (0U)
+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */
+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */
+#define CRS_CFGR_FELIM_Pos        (16U)
+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */
+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */
+
+#define CRS_CFGR_SYNCDIV_Pos      (24U)
+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */
+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */
+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */
+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */
+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */
+
+#define CRS_CFGR_SYNCSRC_Pos      (28U)
+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */
+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */
+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */
+
+#define CRS_CFGR_SYNCPOL_Pos      (31U)
+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */
+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */
+
+/*******************  Bit definition for CRS_ISR register  *********************/
+#define CRS_ISR_SYNCOKF_Pos       (0U)
+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */
+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF_Pos     (1U)
+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */
+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */
+#define CRS_ISR_ERRF_Pos          (2U)
+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */
+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */
+#define CRS_ISR_ESYNCF_Pos        (3U)
+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */
+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */
+#define CRS_ISR_SYNCERR_Pos       (8U)
+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */
+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */
+#define CRS_ISR_SYNCMISS_Pos      (9U)
+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */
+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */
+#define CRS_ISR_TRIMOVF_Pos       (10U)
+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */
+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */
+#define CRS_ISR_FEDIR_Pos         (15U)
+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */
+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */
+#define CRS_ISR_FECAP_Pos         (16U)
+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */
+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */
+
+/*******************  Bit definition for CRS_ICR register  *********************/
+#define CRS_ICR_SYNCOKC_Pos       (0U)
+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */
+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC_Pos     (1U)
+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */
+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */
+#define CRS_ICR_ERRC_Pos          (2U)
+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */
+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */
+#define CRS_ICR_ESYNCC_Pos        (3U)
+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */
+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_TEN1_Pos             (1U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (2U)
+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_TEN2_Pos             (17U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (18U)
+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+#define DAC_SR_BWST1_Pos            (15U)
+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */
+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+#define DAC_SR_BWST2_Pos            (31U)
+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */
+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */
+
+/*******************  Bit definition for DAC_CCR register  ********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk
+#define DCMI_CR_CM_Pos             (1U)
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk
+#define DCMI_CR_CROP_Pos           (2U)
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk
+#define DCMI_CR_JPEG_Pos           (3U)
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk
+#define DCMI_CR_ESS_Pos            (4U)
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk
+#define DCMI_CR_PCKPOL_Pos         (5U)
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk
+#define DCMI_CR_HSPOL_Pos          (6U)
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk
+#define DCMI_CR_VSPOL_Pos          (7U)
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
+#define DCMI_CR_CRE_Pos            (12U)
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk
+#define DCMI_CR_ENABLE_Pos         (14U)
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk
+#define DCMI_CR_BSM_Pos            (16U)
+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */
+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk
+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */
+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */
+#define DCMI_CR_OEBS_Pos           (18U)
+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */
+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk
+#define DCMI_CR_LSM_Pos            (19U)
+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */
+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk
+#define DCMI_CR_OELS_Pos           (20U)
+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */
+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk
+#define DCMI_SR_VSYNC_Pos          (1U)
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk
+#define DCMI_SR_FNE_Pos            (2U)
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk
+
+/********************  Bits definition for DCMI_RIS register   ****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk
+#define DCMI_RIS_OVR_RIS_Pos       (1U)
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk
+#define DCMI_RIS_ERR_RIS_Pos       (2U)
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk
+#define DCMI_RIS_LINE_RIS_Pos      (4U)
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk
+#define DCMI_IER_OVR_IE_Pos        (1U)
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk
+#define DCMI_IER_ERR_IE_Pos        (2U)
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk
+#define DCMI_IER_VSYNC_IE_Pos      (3U)
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk
+#define DCMI_IER_LINE_IE_Pos       (4U)
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk
+
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk
+#define DCMI_MIS_OVR_MIS_Pos       (1U)
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk
+#define DCMI_MIS_ERR_MIS_Pos       (2U)
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk
+#define DCMI_MIS_LINE_MIS_Pos      (4U)
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk
+
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk
+#define DCMI_ICR_OVR_ISC_Pos       (1U)
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk
+#define DCMI_ICR_ERR_ISC_Pos       (2U)
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk
+#define DCMI_ICR_LINE_ISC_Pos      (4U)
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk
+
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk
+#define DCMI_ESCR_LSC_Pos          (8U)
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk
+#define DCMI_ESCR_LEC_Pos          (16U)
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk
+#define DCMI_ESCR_FEC_Pos          (24U)
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk
+#define DCMI_ESUR_LSU_Pos          (8U)
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk
+#define DCMI_ESUR_LEU_Pos          (16U)
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk
+#define DCMI_ESUR_FEU_Pos          (24U)
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk
+#define DCMI_CWSTRT_VST_Pos        (16U)
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk
+#define DCMI_CWSIZE_VLINE_Pos      (16U)
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk
+
+/********************  Bits definition for DCMI_DR register  ******************/
+#define DCMI_DR_BYTE0_Pos          (0U)
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk
+#define DCMI_DR_BYTE1_Pos          (8U)
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk
+#define DCMI_DR_BYTE2_Pos          (16U)
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk
+#define DCMI_DR_BYTE3_Pos          (24U)
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                 Digital Filter for Sigma Delta Modulators                  */
+/*                                                                            */
+/******************************************************************************/
+
+/****************   DFSDM channel configuration registers  ********************/
+
+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/
+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)
+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */
+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */
+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)
+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */
+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */
+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)
+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */
+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)
+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */
+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */
+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */
+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */
+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)
+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */
+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */
+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */
+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */
+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)
+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */
+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */
+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)
+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */
+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */
+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)
+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */
+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */
+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)
+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)
+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */
+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */
+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */
+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */
+#define DFSDM_CHCFGR1_SITP_Pos          (0U)
+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */
+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */
+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */
+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */
+
+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/
+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)
+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)
+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */
+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */
+
+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/
+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)
+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */
+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */
+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */
+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)
+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */
+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)
+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */
+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)
+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */
+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */
+
+/****************  Bit definition for DFSDM_CHWDATR register *******************/
+#define DFSDM_CHWDATR_WDATA_Pos         (0U)
+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */
+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */
+
+/****************  Bit definition for DFSDM_CHDATINR register *****************/
+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)
+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)
+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */
+
+/************************   DFSDM module registers  ****************************/
+
+/********************  Bit definition for DFSDM_FLTCR1 register *******************/
+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)
+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */
+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */
+#define DFSDM_FLTCR1_FAST_Pos           (29U)
+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */
+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */
+#define DFSDM_FLTCR1_RCH_Pos            (24U)
+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */
+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */
+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)
+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */
+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */
+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)
+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */
+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */
+#define DFSDM_FLTCR1_RCONT_Pos          (18U)
+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */
+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */
+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)
+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */
+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */
+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)
+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */
+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */
+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */
+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)
+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */
+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */
+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */
+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */
+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */
+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */
+
+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)
+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */
+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */
+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)
+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */
+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)
+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */
+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)
+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */
+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */
+#define DFSDM_FLTCR1_DFEN_Pos           (0U)
+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */
+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */
+
+/********************  Bit definition for DFSDM_FLTCR2 register *******************/
+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)
+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */
+#define DFSDM_FLTCR2_EXCH_Pos           (8U)
+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */
+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */
+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)
+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */
+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */
+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)
+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */
+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */
+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)
+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */
+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */
+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)
+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */
+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */
+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)
+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */
+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */
+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)
+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */
+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */
+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)
+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */
+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */
+
+/********************  Bit definition for DFSDM_FLTISR register *******************/
+#define DFSDM_FLTISR_SCDF_Pos           (24U)
+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */
+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */
+#define DFSDM_FLTISR_CKABF_Pos          (16U)
+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */
+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */
+#define DFSDM_FLTISR_RCIP_Pos           (14U)
+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */
+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */
+#define DFSDM_FLTISR_JCIP_Pos           (13U)
+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */
+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */
+#define DFSDM_FLTISR_AWDF_Pos           (4U)
+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */
+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */
+#define DFSDM_FLTISR_ROVRF_Pos          (3U)
+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */
+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */
+#define DFSDM_FLTISR_JOVRF_Pos          (2U)
+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */
+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */
+#define DFSDM_FLTISR_REOCF_Pos          (1U)
+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */
+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */
+#define DFSDM_FLTISR_JEOCF_Pos          (0U)
+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */
+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */
+
+/********************  Bit definition for DFSDM_FLTICR register *******************/
+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)
+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */
+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)
+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */
+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */
+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)
+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */
+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */
+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)
+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */
+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */
+
+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/
+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)
+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */
+
+/********************  Bit definition for DFSDM_FLTFCR register *******************/
+#define DFSDM_FLTFCR_FORD_Pos           (29U)
+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */
+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */
+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */
+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */
+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */
+#define DFSDM_FLTFCR_FOSR_Pos           (16U)
+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */
+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
+#define DFSDM_FLTFCR_IOSR_Pos           (0U)
+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */
+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
+
+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/
+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)
+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */
+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)
+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/
+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)
+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */
+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)
+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */
+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */
+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)
+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */
+
+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/
+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)
+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */
+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)
+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/
+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)
+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */
+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)
+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */
+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
+
+/******************  Bit definition for DFSDM_FLTAWSR register ******************/
+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)
+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */
+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)
+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */
+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
+
+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/
+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)
+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)
+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
+
+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/
+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)
+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */
+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)
+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
+
+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/
+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)
+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */
+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)
+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */
+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */
+
+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/
+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)
+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           BDMA Controller                                  */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for BDMA_ISR register  ********************/
+#define BDMA_ISR_GIF0_Pos       (0U)
+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */
+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */
+#define BDMA_ISR_TCIF0_Pos      (1U)
+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */
+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */
+#define BDMA_ISR_HTIF0_Pos      (2U)
+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */
+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */
+#define BDMA_ISR_TEIF0_Pos      (3U)
+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */
+#define BDMA_ISR_GIF1_Pos       (4U)
+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */
+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */
+#define BDMA_ISR_TCIF1_Pos      (5U)
+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */
+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */
+#define BDMA_ISR_HTIF1_Pos      (6U)
+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */
+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */
+#define BDMA_ISR_TEIF1_Pos      (7U)
+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */
+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */
+#define BDMA_ISR_GIF2_Pos       (8U)
+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */
+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */
+#define BDMA_ISR_TCIF2_Pos      (9U)
+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */
+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */
+#define BDMA_ISR_HTIF2_Pos      (10U)
+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */
+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */
+#define BDMA_ISR_TEIF2_Pos      (11U)
+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */
+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */
+#define BDMA_ISR_GIF3_Pos       (12U)
+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */
+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */
+#define BDMA_ISR_TCIF3_Pos      (13U)
+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */
+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */
+#define BDMA_ISR_HTIF3_Pos      (14U)
+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */
+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */
+#define BDMA_ISR_TEIF3_Pos      (15U)
+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */
+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */
+#define BDMA_ISR_GIF4_Pos       (16U)
+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */
+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */
+#define BDMA_ISR_TCIF4_Pos      (17U)
+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */
+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */
+#define BDMA_ISR_HTIF4_Pos      (18U)
+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */
+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */
+#define BDMA_ISR_TEIF4_Pos      (19U)
+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */
+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */
+#define BDMA_ISR_GIF5_Pos       (20U)
+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */
+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */
+#define BDMA_ISR_TCIF5_Pos      (21U)
+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */
+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */
+#define BDMA_ISR_HTIF5_Pos      (22U)
+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */
+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */
+#define BDMA_ISR_TEIF5_Pos      (23U)
+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */
+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */
+#define BDMA_ISR_GIF6_Pos       (24U)
+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */
+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */
+#define BDMA_ISR_TCIF6_Pos      (25U)
+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */
+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */
+#define BDMA_ISR_HTIF6_Pos      (26U)
+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */
+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */
+#define BDMA_ISR_TEIF6_Pos      (27U)
+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */
+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */
+#define BDMA_ISR_GIF7_Pos       (28U)
+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */
+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */
+#define BDMA_ISR_TCIF7_Pos      (29U)
+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */
+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */
+#define BDMA_ISR_HTIF7_Pos      (30U)
+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */
+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */
+#define BDMA_ISR_TEIF7_Pos      (31U)
+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */
+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for BDMA_IFCR register  *******************/
+#define BDMA_IFCR_CGIF0_Pos     (0U)
+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */
+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */
+#define BDMA_IFCR_CTCIF0_Pos    (1U)
+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */
+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF0_Pos    (2U)
+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */
+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */
+#define BDMA_IFCR_CTEIF0_Pos    (3U)
+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */
+#define BDMA_IFCR_CGIF1_Pos     (4U)
+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */
+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */
+#define BDMA_IFCR_CTCIF1_Pos    (5U)
+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */
+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF1_Pos    (6U)
+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */
+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */
+#define BDMA_IFCR_CTEIF1_Pos    (7U)
+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */
+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */
+#define BDMA_IFCR_CGIF2_Pos     (8U)
+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */
+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */
+#define BDMA_IFCR_CTCIF2_Pos    (9U)
+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */
+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF2_Pos    (10U)
+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */
+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */
+#define BDMA_IFCR_CTEIF2_Pos    (11U)
+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */
+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */
+#define BDMA_IFCR_CGIF3_Pos     (12U)
+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */
+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */
+#define BDMA_IFCR_CTCIF3_Pos    (13U)
+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */
+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF3_Pos    (14U)
+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */
+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */
+#define BDMA_IFCR_CTEIF3_Pos    (15U)
+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */
+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */
+#define BDMA_IFCR_CGIF4_Pos     (16U)
+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */
+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */
+#define BDMA_IFCR_CTCIF4_Pos    (17U)
+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */
+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF4_Pos    (18U)
+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */
+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */
+#define BDMA_IFCR_CTEIF4_Pos    (19U)
+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */
+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */
+#define BDMA_IFCR_CGIF5_Pos     (20U)
+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */
+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */
+#define BDMA_IFCR_CTCIF5_Pos    (21U)
+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */
+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF5_Pos    (22U)
+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */
+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */
+#define BDMA_IFCR_CTEIF5_Pos    (23U)
+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */
+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */
+#define BDMA_IFCR_CGIF6_Pos     (24U)
+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */
+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */
+#define BDMA_IFCR_CTCIF6_Pos    (25U)
+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */
+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF6_Pos    (26U)
+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */
+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */
+#define BDMA_IFCR_CTEIF6_Pos    (27U)
+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */
+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */
+#define BDMA_IFCR_CGIF7_Pos     (28U)
+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */
+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */
+#define BDMA_IFCR_CTCIF7_Pos    (29U)
+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */
+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */
+#define BDMA_IFCR_CHTIF7_Pos    (30U)
+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */
+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */
+#define BDMA_IFCR_CTEIF7_Pos    (31U)
+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */
+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for BDMA_CCR register  ********************/
+#define BDMA_CCR_EN_Pos         (0U)
+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */
+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */
+#define BDMA_CCR_TCIE_Pos       (1U)
+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */
+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */
+#define BDMA_CCR_HTIE_Pos       (2U)
+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */
+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */
+#define BDMA_CCR_TEIE_Pos       (3U)
+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */
+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */
+#define BDMA_CCR_DIR_Pos        (4U)
+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */
+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */
+#define BDMA_CCR_CIRC_Pos       (5U)
+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */
+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */
+#define BDMA_CCR_PINC_Pos       (6U)
+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */
+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */
+#define BDMA_CCR_MINC_Pos       (7U)
+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */
+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */
+
+#define BDMA_CCR_PSIZE_Pos      (8U)
+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */
+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */
+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */
+
+#define BDMA_CCR_MSIZE_Pos      (10U)
+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */
+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */
+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */
+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */
+
+#define BDMA_CCR_PL_Pos         (12U)
+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */
+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/
+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */
+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */
+
+#define BDMA_CCR_MEM2MEM_Pos    (14U)
+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */
+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */
+#define BDMA_CCR_DBM_Pos        (15U)
+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */
+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */
+#define BDMA_CCR_CT_Pos         (16U)
+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */
+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */
+
+/******************  Bit definition for BDMA_CNDTR register  *******************/
+#define BDMA_CNDTR_NDT_Pos      (0U)
+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */
+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */
+
+/******************  Bit definition for BDMA_CPAR register  ********************/
+#define BDMA_CPAR_PA_Pos        (0U)
+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */
+
+/******************  Bit definition for BDMA_CM0AR register  ********************/
+#define BDMA_CM0AR_MA_Pos        (0U)
+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************  Bit definition for BDMA_CM1AR register  ********************/
+#define BDMA_CM1AR_MA_Pos        (0U)
+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */
+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Configuration Register register */
+#define ETH_MACCR_ARP_Pos                             (31U)
+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */
+#define ETH_MACCR_SARC_Pos                            (28U)
+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)
+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)
+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
+#define ETH_MACCR_IPC_Pos                             (27U)
+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */
+#define ETH_MACCR_IPG_Pos                             (24U)
+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_GPSLCE_Pos                          (23U)
+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
+#define ETH_MACCR_S2KP_Pos                            (22U)
+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */
+#define ETH_MACCR_CST_Pos                             (21U)
+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */
+#define ETH_MACCR_ACS_Pos                             (20U)
+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */
+#define ETH_MACCR_WD_Pos                              (19U)
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (17U)
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_JE_Pos                              (16U)
+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */
+#define ETH_MACCR_FES_Pos                             (14U)
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_DM_Pos                              (13U)
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_LM_Pos                              (12U)
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_ECRSFD_Pos                          (11U)
+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
+#define ETH_MACCR_DO_Pos                              (10U)
+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */
+#define ETH_MACCR_DCRS_Pos                            (9U)
+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */
+#define ETH_MACCR_DR_Pos                              (8U)
+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */
+#define ETH_MACCR_BL_Pos                              (5U)
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */
+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_DC_Pos                              (4U)
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_PRELEN_Pos                          (2U)
+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */
+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE_Pos                              (1U)
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (0U)
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Extended Configuration Register register */
+#define ETH_MACECR_EIPG_Pos                           (25U)
+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */
+#define ETH_MACECR_EIPGEN_Pos                         (24U)
+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */
+#define ETH_MACECR_USP_Pos                            (18U)
+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */
+#define ETH_MACECR_SPEN_Pos                           (17U)
+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */
+#define ETH_MACECR_DCRCC_Pos                          (16U)
+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */
+#define ETH_MACECR_GPSL_Pos                           (0U)
+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */
+
+/* Bit definition for Ethernet MAC Packet Filter Register */
+#define ETH_MACPFR_RA_Pos                             (31U)
+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */
+#define ETH_MACPFR_DNTU_Pos                           (21U)
+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */
+#define ETH_MACPFR_IPFE_Pos                           (20U)
+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */
+#define ETH_MACPFR_VTFE_Pos                           (16U)
+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */
+#define ETH_MACPFR_HPF_Pos                            (10U)
+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACPFR_SAF_Pos                            (9U)
+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACPFR_SAIF_Pos                           (8U)
+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */
+#define ETH_MACPFR_PCF_Pos                            (6U)
+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)
+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
+#define ETH_MACPFR_DBF_Pos                            (5U)
+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */
+#define ETH_MACPFR_PM_Pos                             (4U)
+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */
+#define ETH_MACPFR_DAIF_Pos                           (3U)
+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACPFR_HMC_Pos                            (2U)
+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */
+#define ETH_MACPFR_HUC_Pos                            (1U)
+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */
+#define ETH_MACPFR_PR_Pos                             (0U)
+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Watchdog Timeout Register */
+#define ETH_MACWTR_PWE_Pos                            (8U)
+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */
+#define ETH_MACWTR_WTO_Pos                            (0U)
+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)
+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */
+#define ETH_MACVTR_EIVLS_Pos                          (28U)
+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_ERIVLT_Pos                         (27U)
+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */
+#define ETH_MACVTR_EDVLP_Pos                          (26U)
+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */
+#define ETH_MACVTR_VTHM_Pos                           (25U)
+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */
+#define ETH_MACVTR_EVLRXS_Pos                         (24U)
+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */
+#define ETH_MACVTR_EVLS_Pos                           (21U)
+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)
+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
+#define ETH_MACVTR_DOVLTC_Pos                         (20U)
+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */
+#define ETH_MACVTR_ERSVLM_Pos                         (19U)
+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */
+#define ETH_MACVTR_ESVL_Pos                           (18U)
+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */
+#define ETH_MACVTR_VTIM_Pos                           (17U)
+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */
+#define ETH_MACVTR_ETV_Pos                            (16U)
+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */
+#define ETH_MACVTR_VL_Pos                             (0U)
+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */
+#define ETH_MACVTR_VL_UP_Pos                          (13U)
+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */
+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)
+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVTR_VL_VID_Pos                         (0U)
+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC VLAN Hash Table Register */
+#define ETH_MACVHTR_VLHT_Pos                          (0U)
+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */
+
+/* Bit definition for Ethernet MAC VLAN Incl Register */
+#define ETH_MACVIR_VLTI_Pos                           (20U)
+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */
+#define ETH_MACVIR_CSVL_Pos                           (19U)
+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */
+#define ETH_MACVIR_VLP_Pos                            (18U)
+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */
+#define ETH_MACVIR_VLC_Pos                            (16U)
+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)
+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)
+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACVIR_VLT_Pos                            (0U)
+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */
+#define ETH_MACVIR_VLT_UP_Pos                         (13U)
+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */
+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)
+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACVIR_VLT_VID_Pos                        (0U)
+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
+#define ETH_MACIVIR_VLTI_Pos                          (20U)
+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */
+#define ETH_MACIVIR_CSVL_Pos                          (19U)
+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */
+#define ETH_MACIVIR_VLP_Pos                           (18U)
+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */
+#define ETH_MACIVIR_VLC_Pos                           (16U)
+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)
+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
+#define ETH_MACIVIR_VLT_Pos                           (0U)
+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */
+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)
+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */
+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)
+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)
+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */
+
+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
+#define ETH_MACTFCR_PT_Pos                            (16U)
+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */
+#define ETH_MACTFCR_DZPQ_Pos                          (7U)
+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */
+#define ETH_MACTFCR_PLT_Pos                           (4U)
+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)
+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)
+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)
+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
+#define ETH_MACTFCR_TFE_Pos                           (1U)
+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */
+#define ETH_MACTFCR_FCB_Pos                           (0U)
+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */
+
+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
+#define ETH_MACRFCR_UP_Pos                            (1U)
+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */
+#define ETH_MACRFCR_RFE_Pos                           (0U)
+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */
+
+/* Bit definition for Ethernet MAC Interrupt Status Register */
+#define ETH_MACISR_RXSTSIS_Pos                        (14U)
+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */
+#define ETH_MACISR_TXSTSIS_Pos                        (13U)
+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */
+#define ETH_MACISR_TSIS_Pos                           (12U)
+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */
+#define ETH_MACISR_MMCTXIS_Pos                        (10U)
+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */
+#define ETH_MACISR_MMCRXIS_Pos                        (9U)
+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */
+#define ETH_MACISR_MMCIS_Pos                          (8U)
+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */
+#define ETH_MACISR_LPIIS_Pos                          (5U)
+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */
+#define ETH_MACISR_PMTIS_Pos                          (4U)
+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */
+#define ETH_MACISR_PHYIS_Pos                          (3U)
+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */
+
+/* Bit definition for Ethernet MAC Interrupt Enable Register */
+#define ETH_MACIER_RXSTSIE_Pos                        (14U)
+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */
+#define ETH_MACIER_TXSTSIE_Pos                        (13U)
+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */
+#define ETH_MACIER_TSIE_Pos                           (12U)
+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */
+#define ETH_MACIER_LPIIE_Pos                          (5U)
+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */
+#define ETH_MACIER_PMTIE_Pos                          (4U)
+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */
+#define ETH_MACIER_PHYIE_Pos                          (3U)
+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */
+
+/* Bit definition for Ethernet MAC Rx Tx Status Register */
+#define ETH_MACRXTXSR_RWT_Pos                         (8U)
+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */
+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)
+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */
+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)
+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */
+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)
+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */
+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)
+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */
+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)
+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */
+#define ETH_MACRXTXSR_TJT_Pos                         (0U)
+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */
+
+/* Bit definition for Ethernet MAC PMT Control Status Register */
+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)
+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)
+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */
+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)
+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */
+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)
+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)
+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)
+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)
+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)
+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)
+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */
+
+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
+#define ETH_MACRWUPFR_D_Pos                           (0U)
+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */
+
+/* Bit definition for Ethernet MAC LPI Control Status Register */
+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)
+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */
+#define ETH_MACLCSR_LPITE_Pos                         (20U)
+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */
+#define ETH_MACLCSR_LPITXA_Pos                        (19U)
+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */
+#define ETH_MACLCSR_PLS_Pos                           (17U)
+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */
+#define ETH_MACLCSR_LPIEN_Pos                         (16U)
+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */
+#define ETH_MACLCSR_RLPIST_Pos                        (9U)
+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */
+#define ETH_MACLCSR_TLPIST_Pos                        (8U)
+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */
+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)
+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */
+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)
+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */
+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)
+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */
+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)
+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */
+
+/* Bit definition for Ethernet MAC LPI Timers Control Register */
+#define ETH_MACLTCR_LST_Pos                           (16U)
+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */
+#define ETH_MACLTCR_TWT_Pos                           (0U)
+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */
+
+/* Bit definition for Ethernet MAC LPI Entry Timer Register */
+#define ETH_MACLETR_LPIET_Pos                         (0U)
+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */
+
+/* Bit definition for Ethernet MAC 1US Tic Counter Register */
+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)
+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
+
+/* Bit definition for Ethernet MAC Version Register */
+#define ETH_MACVR_USERVER_Pos                         (8U)
+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */
+#define ETH_MACVR_SNPSVER_Pos                         (0U)
+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */
+
+/* Bit definition for Ethernet MAC Debug Register */
+#define ETH_MACDR_TFCSTS_Pos                          (17U)
+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)
+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)
+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
+#define ETH_MACDR_TPESTS_Pos                          (16U)
+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */
+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)
+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */
+#define ETH_MACDR_RPESTS_Pos                          (0U)
+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */
+
+/* Bit definition for Ethernet MAC HW Feature0 Register */
+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)
+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)
+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)
+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)
+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)
+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)
+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)
+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)
+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)
+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */
+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)
+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */
+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)
+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)
+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */
+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)
+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */
+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)
+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */
+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)
+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */
+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)
+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */
+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)
+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)
+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */
+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)
+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)
+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */
+
+/* Bit definition for Ethernet MAC HW Feature1 Register */
+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)
+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)
+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)
+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */
+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)
+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)
+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */
+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)
+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */
+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)
+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */
+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)
+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */
+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)
+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)
+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */
+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)
+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */
+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)
+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)
+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
+
+/* Bit definition for Ethernet MAC HW Feature2 Register */
+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)
+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)
+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */
+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)
+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)
+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)
+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */
+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)
+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */
+
+/* Bit definition for Ethernet MAC MDIO Address Register */
+#define ETH_MACMDIOAR_PSE_Pos                         (27U)
+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */
+#define ETH_MACMDIOAR_BTB_Pos                         (26U)
+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */
+#define ETH_MACMDIOAR_PA_Pos                          (21U)
+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */
+#define ETH_MACMDIOAR_RDA_Pos                         (16U)
+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */
+#define ETH_MACMDIOAR_NTC_Pos                         (12U)
+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */
+#define ETH_MACMDIOAR_CR_Pos                          (8U)
+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)
+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)
+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)
+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)
+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)
+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)
+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)
+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)
+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)
+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)
+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */
+#define ETH_MACMDIOAR_MOC_Pos                         (2U)
+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */
+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */
+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)
+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)
+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */
+#define ETH_MACMDIOAR_C45E_Pos                        (1U)
+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */
+#define ETH_MACMDIOAR_MB_Pos                          (0U)
+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */
+
+/* Bit definition for Ethernet MAC MDIO Data Register */
+#define ETH_MACMDIODR_RA_Pos                          (16U)
+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */
+#define ETH_MACMDIODR_MD_Pos                          (0U)
+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */
+
+/* Bit definition for Ethernet ARP Address Register */
+#define ETH_MACARPAR_ARPPA_Pos                         (0U)
+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */
+
+/* Bit definition for Ethernet MAC Address 0 High Register */
+#define ETH_MACA0HR_AE_Pos                            (31U)
+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/
+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 0 Low Register */
+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/
+
+/* Bit definition for Ethernet MAC Address 1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/
+#define ETH_MACA1HR_SA_Pos                            (30U)
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 1 Low Register */
+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/
+#define ETH_MACA2HR_SA_Pos                            (30U)
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 2 Low Register */
+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/
+
+/* Bit definition for Ethernet MAC Address 3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/
+#define ETH_MACA3HR_SA_Pos                            (30U)
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)
+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/
+
+/* Bit definition for Ethernet MAC Address 3 Low Register */
+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)
+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/
+
+/* Bit definition for Ethernet MAC Address High Register */
+#define ETH_MACAHR_AE_Pos                             (31U)
+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */
+#define ETH_MACAHR_SA_Pos                             (30U)
+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */
+#define ETH_MACAHR_MBC_Pos                            (24U)
+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MACAH_Pos                          (0U)
+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
+
+/* Bit definition for Ethernet MAC Address Low Register */
+#define ETH_MACALR_MACAL_Pos                          (0U)
+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_UCDBC_Pos                           (8U)
+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */
+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)
+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */
+#define ETH_MMCCR_CNTPRST_Pos                         (4U)
+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */
+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)
+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */
+#define ETH_MMCCR_RSTONRD_Pos                         (2U)
+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */
+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)
+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */
+#define ETH_MMCCR_CNTRST_Pos                          (0U)
+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */
+
+/* Bit definition for Ethernet MMC Rx Interrupt Register */
+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)
+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */
+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */
+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)
+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)
+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)
+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Register */
+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)
+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */
+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)
+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */
+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)
+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)
+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)
+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+
+/* Bit definition for Ethernet MMC Rx interrupt Mask register */
+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)
+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */
+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */
+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)
+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)
+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)
+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)
+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/
+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)
+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/
+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)
+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/
+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)
+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)
+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+
+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)
+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)
+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
+
+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)
+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
+
+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)
+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
+
+/* Bit definition for Ethernet MMC Rx alignment error packets register */
+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)
+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
+
+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)
+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
+
+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)
+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)
+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)
+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
+
+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)
+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
+
+/* Bit definition for Ethernet MAC L3 L4 Control Register */
+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)
+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)
+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */
+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)
+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)
+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */
+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)
+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */
+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)
+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)
+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)
+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)
+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */
+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)
+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)
+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/
+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)
+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */
+
+/* Bit definition for Ethernet MAC L4 Address Register */
+#define ETH_MACL4AR_L4DP_Pos                          (16U)
+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */
+#define ETH_MACL4AR_L4SP_Pos                          (0U)
+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */
+
+/* Bit definition for Ethernet MAC L3 Address0 Register */
+#define ETH_MACL3A0R_L3A0_Pos                         (0U)
+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */
+
+/* Bit definition for Ethernet MAC L4 Address1 Register */
+#define ETH_MACL3A1R_L3A1_Pos                         (0U)
+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */
+
+/* Bit definition for Ethernet MAC L4 Address2 Register */
+#define ETH_MACL3A2R_L3A2_Pos                         (0U)
+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */
+
+/* Bit definition for Ethernet MAC L4 Address3 Register */
+#define ETH_MACL3A3R_L3A3_Pos                         (0U)
+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */
+
+/* Bit definition for Ethernet MAC Timestamp Control Register */
+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)
+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */
+#define ETH_MACTSCR_CSC_Pos                           (19U)
+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)
+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */
+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)
+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */
+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)
+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */
+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)
+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */
+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)
+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */
+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)
+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */
+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)
+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */
+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)
+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */
+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)
+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */
+#define ETH_MACTSCR_TSENALL_Pos                       (8U)
+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */
+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)
+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */
+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)
+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */
+#define ETH_MACTSCR_TSINIT_Pos                        (2U)
+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */
+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)
+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/
+#define ETH_MACTSCR_TSENA_Pos                         (0U)
+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */
+
+/* Bit definition for Ethernet MAC Sub-second Increment Register */
+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)
+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */
+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)
+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */
+
+/* Bit definition for Ethernet MAC System Time Seconds Register */
+#define ETH_MACSTSR_TSS_Pos                           (0U)
+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
+#define ETH_MACSTNR_TSSS_Pos                          (0U)
+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC System Time Seconds Update Register */
+#define ETH_MACSTSUR_TSS_Pos                          (0U)
+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */
+
+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)
+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */
+#define ETH_MACSTNUR_TSSS_Pos                         (0U)
+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */
+
+/* Bit definition for Ethernet MAC Timestamp Addend Register */
+#define ETH_MACTSAR_TSAR_Pos                          (0U)
+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */
+
+/* Bit definition for Ethernet MAC Timestamp Status Register */
+#define ETH_MACTSSR_ATSNS_Pos                         (25U)
+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */
+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)
+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */
+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)
+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */
+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)
+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */
+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)
+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */
+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)
+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/
+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)
+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */
+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)
+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)
+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */
+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)
+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */
+
+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)
+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */
+
+/* Bit definition for Ethernet MAC Auxiliary Control Register*/
+#define ETH_MACACR_ATSEN3_Pos                         (7U)
+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */
+#define ETH_MACACR_ATSEN2_Pos                         (6U)
+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */
+#define ETH_MACACR_ATSEN1_Pos                         (5U)
+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */
+#define ETH_MACACR_ATSEN0_Pos                         (4U)
+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */
+#define ETH_MACACR_ATSFC_Pos                          (0U)
+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)
+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)
+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)
+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)
+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
+#define ETH_MACTSICNR_TSIC_Pos                        (0U)
+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */
+
+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
+#define ETH_MACTSECNR_TSEC_Pos                        (0U)
+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */
+
+/* Bit definition for Ethernet MAC PPS Control Register */
+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)
+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */
+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)
+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */
+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)
+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */
+
+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)
+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */
+
+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)
+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */
+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)
+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */
+
+/* Bit definition for Ethernet MAC PPS Interval Register */
+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)
+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */
+
+/* Bit definition for Ethernet MAC PPS Width Register */
+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)
+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */
+
+/* Bit definition for Ethernet MAC PTP Offload Control Register */
+#define ETH_MACPOCR_DN_Pos                            (8U)
+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */
+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)
+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */
+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)
+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */
+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)
+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */
+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)
+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */
+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)
+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */
+#define ETH_MACPOCR_PTOEN_Pos                         (0U)
+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
+#define ETH_MACSPI0R_SPI0_Pos                         (0U)
+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
+#define ETH_MACSPI1R_SPI1_Pos                         (0U)
+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */
+
+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
+#define ETH_MACSPI2R_SPI2_Pos                         (0U)
+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */
+
+/* Bit definition for Ethernet MAC Log Message Interval Register */
+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)
+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */
+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)
+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */
+#define ETH_MACLMIR_LSI_Pos                           (0U)
+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */
+
+/* Bit definition for Ethernet MTL Operation Mode Register */
+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)
+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */
+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)
+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */
+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)
+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */
+
+/* Bit definition for Ethernet MTL Interrupt Status Register */
+#define ETH_MTLISR_MACIS_Pos                          (16U)
+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_MTLISR_QIS_Pos                            (0U)
+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */
+
+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
+#define ETH_MTLTQOMR_TTC_Pos                          (4U)
+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TSF_Pos                          (1U)
+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)
+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */
+
+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)
+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)
+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Tx Queue Debug Register */
+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)
+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */
+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)
+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */
+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)
+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)
+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */
+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)
+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */
+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
+
+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)
+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */
+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)
+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)
+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */
+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)
+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
+#define ETH_MTLRQOMR_RQS_Pos                          (20U)
+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
+#define ETH_MTLRQOMR_RFD_Pos                          (14U)
+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
+#define ETH_MTLRQOMR_RFA_Pos                          (8U)
+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)
+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)
+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
+#define ETH_MTLRQOMR_RSF_Pos                          (5U)
+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */
+#define ETH_MTLRQOMR_FEP_Pos                          (4U)
+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */
+#define ETH_MTLRQOMR_FUP_Pos                          (3U)
+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */
+#define ETH_MTLRQOMR_RTC_Pos                          (0U)
+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
+
+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)
+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)
+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)
+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
+
+/* Bit definition for Ethernet MTL Rx Queue Debug Register */
+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)
+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */
+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)
+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)
+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)
+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */
+
+/* Bit definition for Ethernet MTL Rx Queue Control Register */
+#define ETH_MTLRQCR_RQPA_Pos                          (3U)
+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */
+#define ETH_MTLRQCR_RQW_Pos                           (0U)
+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */
+
+/* Bit definition for Ethernet DMA Mode Register */
+#define ETH_DMAMR_INTM_Pos                            (16U)
+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */
+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
+#define ETH_DMAMR_PR_Pos                              (12U)
+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_TXPR_Pos                            (11U)
+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
+#define ETH_DMAMR_DA_Pos                              (1U)
+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */
+#define ETH_DMAMR_SWR_Pos                             (0U)
+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */
+
+/* Bit definition for Ethernet DMA SysBus Mode Register */
+#define ETH_DMASBMR_RB_Pos                            (15U)
+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */
+#define ETH_DMASBMR_MB_Pos                            (14U)
+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMASBMR_AAL_Pos                           (12U)
+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */
+#define ETH_DMASBMR_FB_Pos                            (0U)
+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */
+
+/* Bit definition for Ethernet DMA Interrupt Status Register */
+#define ETH_DMAISR_MACIS_Pos                          (17U)
+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_MTLIS_Pos                          (16U)
+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */
+#define ETH_DMAISR_DMACIS_Pos                         (0U)
+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */
+
+/* Bit definition for Ethernet DMA Debug Status Register */
+#define ETH_DMADSR_TPS_Pos                            (12U)
+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)
+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_TPS_READING_Pos                    (12U)
+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)
+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)
+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
+#define ETH_DMADSR_RPS_Pos                            (8U)
+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)
+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)
+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)
+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)
+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)
+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
+
+/* Bit definition for Ethernet DMA Channel Control Register */
+#define ETH_DMACCR_DSL_Pos                            (18U)
+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
+#define ETH_DMACCR_MSS_Pos                            (0U)
+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
+
+/* Bit definition for Ethernet DMA Channel Tx Control Register */
+#define ETH_DMACTCR_TPBL_Pos                          (16U)
+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TSE_Pos                           (12U)
+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
+#define ETH_DMACTCR_OSP_Pos                           (4U)
+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */
+#define ETH_DMACTCR_ST_Pos                            (0U)
+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */
+
+/* Bit definition for Ethernet DMA Channel Rx Control Register */
+#define ETH_DMACRCR_RPF_Pos                           (31U)
+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */
+#define ETH_DMACRCR_RPBL_Pos                          (16U)
+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RBSZ_Pos                          (1U)
+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
+#define ETH_DMACRCR_SR_Pos                            (0U)
+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */
+
+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)
+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
+
+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)
+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
+#define ETH_DMACTDTPR_TDT_Pos                         (2U)
+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
+#define ETH_DMACRDTPR_RDT_Pos                         (2U)
+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */
+
+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)
+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)
+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */
+
+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
+#define ETH_DMACIER_NIE_Pos                           (15U)
+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */
+#define ETH_DMACIER_AIE_Pos                           (14U)
+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */
+#define ETH_DMACIER_CDEE_Pos                          (13U)
+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */
+#define ETH_DMACIER_FBEE_Pos                          (12U)
+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */
+#define ETH_DMACIER_ERIE_Pos                          (11U)
+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */
+#define ETH_DMACIER_ETIE_Pos                          (10U)
+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */
+#define ETH_DMACIER_RWTE_Pos                          (9U)
+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */
+#define ETH_DMACIER_RSE_Pos                           (8U)
+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */
+#define ETH_DMACIER_RBUE_Pos                          (7U)
+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */
+#define ETH_DMACIER_RIE_Pos                           (6U)
+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */
+#define ETH_DMACIER_TBUE_Pos                          (2U)
+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */
+#define ETH_DMACIER_TXSE_Pos                          (1U)
+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */
+#define ETH_DMACIER_TIE_Pos                           (0U)
+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */
+
+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
+#define ETH_DMACRIWTR_RWT_Pos                         (0U)
+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)
+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)
+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)
+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)
+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
+
+/* Bit definition for Ethernet DMA Channel Status Register */
+#define ETH_DMACSR_REB_Pos                            (19U)
+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */
+#define ETH_DMACSR_TEB_Pos                            (16U)
+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */
+#define ETH_DMACSR_NIS_Pos                            (15U)
+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */
+#define ETH_DMACSR_AIS_Pos                            (14U)
+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */
+#define ETH_DMACSR_CDE_Pos                            (13U)
+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */
+#define ETH_DMACSR_FBE_Pos                            (12U)
+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */
+#define ETH_DMACSR_ERI_Pos                            (11U)
+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */
+#define ETH_DMACSR_ETI_Pos                            (10U)
+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */
+#define ETH_DMACSR_RWT_Pos                            (9U)
+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */
+#define ETH_DMACSR_RPS_Pos                            (8U)
+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */
+#define ETH_DMACSR_RBU_Pos                            (7U)
+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */
+#define ETH_DMACSR_RI_Pos                             (6U)
+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */
+#define ETH_DMACSR_TBU_Pos                            (2U)
+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */
+#define ETH_DMACSR_TPS_Pos                            (1U)
+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */
+#define ETH_DMACSR_TI_Pos                             (0U)
+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */
+
+/* Bit definition for Ethernet DMA Channel missed frame count register */
+#define ETH_DMACMFCR_MFCO_Pos                         (15U)
+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */
+#define ETH_DMACMFCR_MFC_Pos                          (0U)
+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_MBURST_Pos      (23U)
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_TRBUFF_Pos      (20U)
+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */
+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */
+#define DMA_SxCR_CT_Pos          (19U)
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */
+#define DMA_SxCR_DBM_Pos         (18U)
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */
+#define DMA_SxCR_PL_Pos          (16U)
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */
+#define DMA_SxCR_MSIZE_Pos       (13U)
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */
+#define DMA_SxCR_PINC_Pos        (9U)
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */
+#define DMA_SxCR_CIRC_Pos        (8U)
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */
+#define DMA_SxCR_DIR_Pos         (6U)
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */
+#define DMA_SxCR_TCIE_Pos        (4U)
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */
+#define DMA_SxCR_HTIE_Pos        (3U)
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */
+#define DMA_SxCR_TEIE_Pos        (2U)
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */
+#define DMA_SxCR_DMEIE_Pos       (1U)
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */
+#define DMA_SxCR_EN_Pos          (0U)
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/
+#define DMA_SxFCR_FEIE_Pos       (7U)
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */
+#define DMA_SxFCR_FS_Pos         (3U)
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */
+#define DMA_SxFCR_FTH_Pos        (0U)
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/
+#define DMA_LISR_TCIF3_Pos       (27U)
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */
+#define DMA_LISR_HTIF3_Pos       (26U)
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */
+#define DMA_LISR_TEIF3_Pos       (25U)
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */
+#define DMA_LISR_DMEIF3_Pos      (24U)
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */
+#define DMA_LISR_FEIF3_Pos       (22U)
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */
+#define DMA_LISR_TCIF2_Pos       (21U)
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */
+#define DMA_LISR_HTIF2_Pos       (20U)
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */
+#define DMA_LISR_TEIF2_Pos       (19U)
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */
+#define DMA_LISR_DMEIF2_Pos      (18U)
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */
+#define DMA_LISR_FEIF2_Pos       (16U)
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */
+#define DMA_LISR_TCIF1_Pos       (11U)
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */
+#define DMA_LISR_HTIF1_Pos       (10U)
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */
+#define DMA_LISR_TEIF1_Pos       (9U)
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */
+#define DMA_LISR_DMEIF1_Pos      (8U)
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */
+#define DMA_LISR_FEIF1_Pos       (6U)
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */
+#define DMA_LISR_TCIF0_Pos       (5U)
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */
+#define DMA_LISR_HTIF0_Pos       (4U)
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */
+#define DMA_LISR_TEIF0_Pos       (3U)
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */
+#define DMA_LISR_DMEIF0_Pos      (2U)
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */
+#define DMA_LISR_FEIF0_Pos       (0U)
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HISR register  *****************/
+#define DMA_HISR_TCIF7_Pos       (27U)
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */
+#define DMA_HISR_HTIF7_Pos       (26U)
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */
+#define DMA_HISR_TEIF7_Pos       (25U)
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */
+#define DMA_HISR_DMEIF7_Pos      (24U)
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */
+#define DMA_HISR_FEIF7_Pos       (22U)
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */
+#define DMA_HISR_TCIF6_Pos       (21U)
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */
+#define DMA_HISR_HTIF6_Pos       (20U)
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */
+#define DMA_HISR_TEIF6_Pos       (19U)
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */
+#define DMA_HISR_DMEIF6_Pos      (18U)
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */
+#define DMA_HISR_FEIF6_Pos       (16U)
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */
+#define DMA_HISR_TCIF5_Pos       (11U)
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */
+#define DMA_HISR_HTIF5_Pos       (10U)
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */
+#define DMA_HISR_TEIF5_Pos       (9U)
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */
+#define DMA_HISR_DMEIF5_Pos      (8U)
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */
+#define DMA_HISR_FEIF5_Pos       (6U)
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */
+#define DMA_HISR_TCIF4_Pos       (5U)
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */
+#define DMA_HISR_HTIF4_Pos       (4U)
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */
+#define DMA_HISR_TEIF4_Pos       (3U)
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */
+#define DMA_HISR_DMEIF4_Pos      (2U)
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */
+#define DMA_HISR_FEIF4_Pos       (0U)
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_LIFCR register  ****************/
+#define DMA_LIFCR_CTCIF3_Pos     (27U)
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF3_Pos     (26U)
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF3_Pos     (25U)
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF3_Pos     (22U)
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF2_Pos     (21U)
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF2_Pos     (20U)
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF2_Pos     (19U)
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF2_Pos     (16U)
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF1_Pos     (11U)
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF1_Pos     (10U)
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF1_Pos     (9U)
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF1_Pos     (6U)
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */
+#define DMA_LIFCR_CTCIF0_Pos     (5U)
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */
+#define DMA_LIFCR_CHTIF0_Pos     (4U)
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */
+#define DMA_LIFCR_CTEIF0_Pos     (3U)
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */
+#define DMA_LIFCR_CFEIF0_Pos     (0U)
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/
+#define DMA_HIFCR_CTCIF7_Pos     (27U)
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF7_Pos     (26U)
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF7_Pos     (25U)
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF7_Pos     (22U)
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF6_Pos     (21U)
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF6_Pos     (20U)
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF6_Pos     (19U)
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF6_Pos     (16U)
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF5_Pos     (11U)
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF5_Pos     (10U)
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF5_Pos     (9U)
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF5_Pos     (6U)
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */
+#define DMA_HIFCR_CTCIF4_Pos     (5U)
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */
+#define DMA_HIFCR_CHTIF4_Pos     (4U)
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */
+#define DMA_HIFCR_CTEIF4_Pos     (3U)
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */
+#define DMA_HIFCR_CFEIF4_Pos     (0U)
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMAMUX Controller                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMAMUX_CxCR register  **************/
+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)
+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */
+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */
+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */
+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */
+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */
+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */
+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */
+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */
+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */
+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */
+#define DMAMUX_CxCR_SOIE_Pos           (8U)
+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */
+#define DMAMUX_CxCR_EGE_Pos            (9U)
+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */
+#define DMAMUX_CxCR_SE_Pos             (16U)
+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */
+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */
+#define DMAMUX_CxCR_SPOL_Pos           (17U)
+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */
+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */
+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */
+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */
+#define DMAMUX_CxCR_NBREQ_Pos          (19U)
+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */
+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */
+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */
+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */
+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */
+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */
+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */
+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)
+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */
+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */
+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */
+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */
+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */
+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */
+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */
+
+/********************  Bits definition for DMAMUX_CSR register  **************/
+#define DMAMUX_CSR_SOF0_Pos            (0U)
+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF1_Pos            (1U)
+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF2_Pos            (2U)
+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF3_Pos            (3U)
+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF4_Pos            (4U)
+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF5_Pos            (5U)
+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF6_Pos            (6U)
+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF7_Pos            (7U)
+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF8_Pos            (8U)
+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */
+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF9_Pos            (9U)
+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */
+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF10_Pos           (10U)
+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */
+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF11_Pos           (11U)
+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */
+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF12_Pos           (12U)
+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */
+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF13_Pos           (13U)
+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */
+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF14_Pos           (14U)
+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */
+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */
+#define DMAMUX_CSR_SOF15_Pos           (15U)
+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */
+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_CFR register  **************/
+#define DMAMUX_CFR_CSOF0_Pos           (0U)
+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */
+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF1_Pos           (1U)
+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */
+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF2_Pos           (2U)
+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */
+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF3_Pos           (3U)
+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */
+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF4_Pos           (4U)
+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */
+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF5_Pos           (5U)
+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */
+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF6_Pos           (6U)
+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */
+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF7_Pos           (7U)
+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */
+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF8_Pos           (8U)
+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */
+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF9_Pos           (9U)
+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */
+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF10_Pos          (10U)
+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */
+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF11_Pos          (11U)
+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */
+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF12_Pos          (12U)
+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */
+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF13_Pos          (13U)
+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */
+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF14_Pos          (14U)
+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */
+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */
+#define DMAMUX_CFR_CSOF15_Pos          (15U)
+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */
+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGxCR register  ************/
+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)
+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */
+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */
+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */
+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */
+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */
+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */
+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */
+#define DMAMUX_RGxCR_OIE_Pos           (8U)
+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */
+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */
+#define DMAMUX_RGxCR_GE_Pos            (16U)
+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */
+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */
+#define DMAMUX_RGxCR_GPOL_Pos          (17U)
+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */
+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */
+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */
+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */
+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)
+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */
+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */
+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */
+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */
+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */
+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */
+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */
+
+/********************  Bits definition for DMAMUX_RGSR register  **************/
+#define DMAMUX_RGSR_OF0_Pos            (0U)
+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */
+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF1_Pos            (1U)
+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */
+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF2_Pos            (2U)
+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */
+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF3_Pos            (3U)
+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */
+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF4_Pos            (4U)
+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */
+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF5_Pos            (5U)
+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */
+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF6_Pos            (6U)
+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */
+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */
+#define DMAMUX_RGSR_OF7_Pos            (7U)
+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */
+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */
+
+/********************  Bits definition for DMAMUX_RGCFR register  **************/
+#define DMAMUX_RGCFR_COF0_Pos          (0U)
+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */
+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF1_Pos          (1U)
+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */
+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF2_Pos          (2U)
+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */
+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF3_Pos          (3U)
+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */
+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF4_Pos          (4U)
+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */
+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF5_Pos          (5U)
+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */
+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF6_Pos          (6U)
+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */
+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */
+#define DMAMUX_RGCFR_COF7_Pos          (7U)
+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */
+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         AHB Master DMA2D Controller (DMA2D)                */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DMA2D_CR register  ******************/
+
+#define DMA2D_CR_START_Pos         (0U)
+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */
+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */
+#define DMA2D_CR_SUSP_Pos          (1U)
+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */
+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */
+#define DMA2D_CR_ABORT_Pos         (2U)
+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */
+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */
+#define DMA2D_CR_LOM_Pos           (6U)
+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */
+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */
+#define DMA2D_CR_TEIE_Pos          (8U)
+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */
+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */
+#define DMA2D_CR_TCIE_Pos          (9U)
+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */
+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */
+#define DMA2D_CR_TWIE_Pos          (10U)
+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */
+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */
+#define DMA2D_CR_CAEIE_Pos         (11U)
+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */
+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */
+#define DMA2D_CR_CTCIE_Pos         (12U)
+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */
+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */
+#define DMA2D_CR_CEIE_Pos          (13U)
+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */
+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */
+#define DMA2D_CR_MODE_Pos          (16U)
+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */
+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */
+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */
+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */
+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */
+
+/********************  Bit definition for DMA2D_ISR register  *****************/
+
+#define DMA2D_ISR_TEIF_Pos         (0U)
+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */
+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */
+#define DMA2D_ISR_TCIF_Pos         (1U)
+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */
+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */
+#define DMA2D_ISR_TWIF_Pos         (2U)
+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */
+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */
+#define DMA2D_ISR_CAEIF_Pos        (3U)
+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */
+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */
+#define DMA2D_ISR_CTCIF_Pos        (4U)
+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */
+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_ISR_CEIF_Pos         (5U)
+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */
+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_IFCR register  ****************/
+
+#define DMA2D_IFCR_CTEIF_Pos       (0U)
+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */
+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */
+#define DMA2D_IFCR_CTCIF_Pos       (1U)
+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */
+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */
+#define DMA2D_IFCR_CTWIF_Pos       (2U)
+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */
+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */
+#define DMA2D_IFCR_CAECIF_Pos      (3U)
+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */
+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */
+#define DMA2D_IFCR_CCTCIF_Pos      (4U)
+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */
+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */
+#define DMA2D_IFCR_CCEIF_Pos       (5U)
+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */
+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */
+
+/********************  Bit definition for DMA2D_FGMAR register  ***************/
+
+#define DMA2D_FGMAR_MA_Pos         (0U)
+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */
+
+/********************  Bit definition for DMA2D_FGOR register  ****************/
+
+#define DMA2D_FGOR_LO_Pos          (0U)
+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_BGMAR register  ***************/
+
+#define DMA2D_BGMAR_MA_Pos         (0U)
+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */
+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */
+
+/********************  Bit definition for DMA2D_BGOR register  ****************/
+
+#define DMA2D_BGOR_LO_Pos          (0U)
+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */
+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */
+
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/
+
+#define DMA2D_FGPFCCR_CM_Pos       (0U)
+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_FGPFCCR_CCM_Pos      (4U)
+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_FGPFCCR_START_Pos    (5U)
+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_FGPFCCR_CS_Pos       (8U)
+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_FGPFCCR_AM_Pos       (16U)
+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_FGPFCCR_CSS_Pos      (18U)
+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */
+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */
+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */
+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */
+#define DMA2D_FGPFCCR_AI_Pos       (20U)
+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */
+#define DMA2D_FGPFCCR_RBS_Pos      (21U)
+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */
+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */
+
+/********************  Bit definition for DMA2D_FGCOLR register  **************/
+
+#define DMA2D_FGCOLR_BLUE_Pos      (0U)
+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */
+#define DMA2D_FGCOLR_GREEN_Pos     (8U)
+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */
+#define DMA2D_FGCOLR_RED_Pos       (16U)
+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */
+
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/
+
+#define DMA2D_BGPFCCR_CM_Pos       (0U)
+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */
+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */
+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */
+#define DMA2D_BGPFCCR_CCM_Pos      (4U)
+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */
+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */
+#define DMA2D_BGPFCCR_START_Pos    (5U)
+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */
+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */
+#define DMA2D_BGPFCCR_CS_Pos       (8U)
+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */
+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */
+#define DMA2D_BGPFCCR_AM_Pos       (16U)
+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */
+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */
+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */
+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */
+#define DMA2D_BGPFCCR_AI_Pos       (20U)
+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */
+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */
+#define DMA2D_BGPFCCR_RBS_Pos      (21U)
+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */
+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */
+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)
+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */
+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */
+
+/********************  Bit definition for DMA2D_BGCOLR register  **************/
+
+#define DMA2D_BGCOLR_BLUE_Pos      (0U)
+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */
+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */
+#define DMA2D_BGCOLR_GREEN_Pos     (8U)
+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */
+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */
+#define DMA2D_BGCOLR_RED_Pos       (16U)
+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */
+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */
+
+/********************  Bit definition for DMA2D_FGCMAR register  **************/
+
+#define DMA2D_FGCMAR_MA_Pos        (0U)
+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_BGCMAR register  **************/
+
+#define DMA2D_BGCMAR_MA_Pos        (0U)
+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */
+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */
+
+/********************  Bit definition for DMA2D_OPFCCR register  **************/
+
+#define DMA2D_OPFCCR_CM_Pos        (0U)
+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */
+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */
+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */
+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */
+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */
+#define DMA2D_OPFCCR_SB_Pos        (8U)
+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */
+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */
+#define DMA2D_OPFCCR_AI_Pos        (20U)
+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */
+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */
+#define DMA2D_OPFCCR_RBS_Pos       (21U)
+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */
+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */
+
+/********************  Bit definition for DMA2D_OCOLR register  ***************/
+
+/*!<Mode_ARGB8888/RGB888 */
+
+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/
+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)
+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/
+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_1_Pos      (16U)
+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */
+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)
+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/
+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_RGB565 */
+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */
+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_2_Pos      (11U)
+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/
+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */
+
+/*!<Mode_ARGB1555 */
+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/
+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)
+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/
+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_3_Pos      (10U)
+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/
+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)
+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/
+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */
+
+/*!<Mode_ARGB4444 */
+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)
+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/
+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */
+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)
+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/
+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */
+#define DMA2D_OCOLR_RED_4_Pos      (8U)
+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/
+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */
+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)
+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/
+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */
+
+/********************  Bit definition for DMA2D_OMAR register  ****************/
+
+#define DMA2D_OMAR_MA_Pos          (0U)
+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */
+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */
+
+/********************  Bit definition for DMA2D_OOR register  *****************/
+
+#define DMA2D_OOR_LO_Pos           (0U)
+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */
+
+/********************  Bit definition for DMA2D_NLR register  *****************/
+
+#define DMA2D_NLR_NL_Pos           (0U)
+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */
+#define DMA2D_NLR_PL_Pos           (16U)
+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */
+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */
+
+/********************  Bit definition for DMA2D_LWR register  *****************/
+
+#define DMA2D_LWR_LW_Pos           (0U)
+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */
+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */
+
+/********************  Bit definition for DMA2D_AMTCR register  ***************/
+
+#define DMA2D_AMTCR_EN_Pos         (0U)
+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */
+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */
+#define DMA2D_AMTCR_DT_Pos         (8U)
+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */
+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */
+
+
+/********************  Bit definition for DMA2D_FGCLUT register  **************/
+
+/********************  Bit definition for DMA2D_BGCLUT register  **************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Display Serial Interface (DSI)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DSI_VR register  *****************/
+#define DSI_VR_Pos                    (1U)
+#define DSI_VR_Msk                    (0x18999815UL << DSI_VR_Pos)             /*!< 0x3133302A */
+#define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version */
+
+/*******************  Bit definition for DSI_CR register  *****************/
+#define DSI_CR_EN_Pos                 (0U)
+#define DSI_CR_EN_Msk                 (0x1UL << DSI_CR_EN_Pos)                 /*!< 0x00000001 */
+#define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */
+
+/*******************  Bit definition for DSI_CCR register  ****************/
+#define DSI_CCR_TXECKDIV_Pos          (0U)
+#define DSI_CCR_TXECKDIV_Msk          (0xFFUL << DSI_CCR_TXECKDIV_Pos)         /*!< 0x000000FF */
+#define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */
+#define DSI_CCR_TXECKDIV0_Pos         (0U)
+#define DSI_CCR_TXECKDIV0_Msk         (0x1UL << DSI_CCR_TXECKDIV0_Pos)         /*!< 0x00000001 */
+#define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk
+#define DSI_CCR_TXECKDIV1_Pos         (1U)
+#define DSI_CCR_TXECKDIV1_Msk         (0x1UL << DSI_CCR_TXECKDIV1_Pos)         /*!< 0x00000002 */
+#define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk
+#define DSI_CCR_TXECKDIV2_Pos         (2U)
+#define DSI_CCR_TXECKDIV2_Msk         (0x1UL << DSI_CCR_TXECKDIV2_Pos)         /*!< 0x00000004 */
+#define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk
+#define DSI_CCR_TXECKDIV3_Pos         (3U)
+#define DSI_CCR_TXECKDIV3_Msk         (0x1UL << DSI_CCR_TXECKDIV3_Pos)         /*!< 0x00000008 */
+#define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk
+#define DSI_CCR_TXECKDIV4_Pos         (4U)
+#define DSI_CCR_TXECKDIV4_Msk         (0x1UL << DSI_CCR_TXECKDIV4_Pos)         /*!< 0x00000010 */
+#define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk
+#define DSI_CCR_TXECKDIV5_Pos         (5U)
+#define DSI_CCR_TXECKDIV5_Msk         (0x1UL << DSI_CCR_TXECKDIV5_Pos)         /*!< 0x00000020 */
+#define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk
+#define DSI_CCR_TXECKDIV6_Pos         (6U)
+#define DSI_CCR_TXECKDIV6_Msk         (0x1UL << DSI_CCR_TXECKDIV6_Pos)         /*!< 0x00000040 */
+#define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk
+#define DSI_CCR_TXECKDIV7_Pos         (7U)
+#define DSI_CCR_TXECKDIV7_Msk         (0x1UL << DSI_CCR_TXECKDIV7_Pos)         /*!< 0x00000080 */
+#define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk
+
+#define DSI_CCR_TOCKDIV_Pos           (8U)
+#define DSI_CCR_TOCKDIV_Msk           (0xFFUL << DSI_CCR_TOCKDIV_Pos)          /*!< 0x0000FF00 */
+#define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */
+#define DSI_CCR_TOCKDIV0_Pos          (8U)
+#define DSI_CCR_TOCKDIV0_Msk          (0x1UL << DSI_CCR_TOCKDIV0_Pos)          /*!< 0x00000100 */
+#define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk
+#define DSI_CCR_TOCKDIV1_Pos          (9U)
+#define DSI_CCR_TOCKDIV1_Msk          (0x1UL << DSI_CCR_TOCKDIV1_Pos)          /*!< 0x00000200 */
+#define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk
+#define DSI_CCR_TOCKDIV2_Pos          (10U)
+#define DSI_CCR_TOCKDIV2_Msk          (0x1UL << DSI_CCR_TOCKDIV2_Pos)          /*!< 0x00000400 */
+#define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk
+#define DSI_CCR_TOCKDIV3_Pos          (11U)
+#define DSI_CCR_TOCKDIV3_Msk          (0x1UL << DSI_CCR_TOCKDIV3_Pos)          /*!< 0x00000800 */
+#define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk
+#define DSI_CCR_TOCKDIV4_Pos          (12U)
+#define DSI_CCR_TOCKDIV4_Msk          (0x1UL << DSI_CCR_TOCKDIV4_Pos)          /*!< 0x00001000 */
+#define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk
+#define DSI_CCR_TOCKDIV5_Pos          (13U)
+#define DSI_CCR_TOCKDIV5_Msk          (0x1UL << DSI_CCR_TOCKDIV5_Pos)          /*!< 0x00002000 */
+#define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk
+#define DSI_CCR_TOCKDIV6_Pos          (14U)
+#define DSI_CCR_TOCKDIV6_Msk          (0x1UL << DSI_CCR_TOCKDIV6_Pos)          /*!< 0x00004000 */
+#define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk
+#define DSI_CCR_TOCKDIV7_Pos          (15U)
+#define DSI_CCR_TOCKDIV7_Msk          (0x1UL << DSI_CCR_TOCKDIV7_Pos)          /*!< 0x00008000 */
+#define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk
+
+/*******************  Bit definition for DSI_LVCIDR register  *************/
+#define DSI_LVCIDR_VCID_Pos           (0U)
+#define DSI_LVCIDR_VCID_Msk           (0x3UL << DSI_LVCIDR_VCID_Pos)           /*!< 0x00000003 */
+#define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
+#define DSI_LVCIDR_VCID0_Pos          (0U)
+#define DSI_LVCIDR_VCID0_Msk          (0x1UL << DSI_LVCIDR_VCID0_Pos)          /*!< 0x00000001 */
+#define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk
+#define DSI_LVCIDR_VCID1_Pos          (1U)
+#define DSI_LVCIDR_VCID1_Msk          (0x1UL << DSI_LVCIDR_VCID1_Pos)          /*!< 0x00000002 */
+#define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk
+
+/*******************  Bit definition for DSI_LCOLCR register  *************/
+#define DSI_LCOLCR_COLC_Pos           (0U)
+#define DSI_LCOLCR_COLC_Msk           (0xFUL << DSI_LCOLCR_COLC_Pos)           /*!< 0x0000000F */
+#define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */
+#define DSI_LCOLCR_COLC0_Pos          (0U)
+#define DSI_LCOLCR_COLC0_Msk          (0x1UL << DSI_LCOLCR_COLC0_Pos)          /*!< 0x00000001 */
+#define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk
+#define DSI_LCOLCR_COLC1_Pos          (5U)
+#define DSI_LCOLCR_COLC1_Msk          (0x1UL << DSI_LCOLCR_COLC1_Pos)          /*!< 0x00000020 */
+#define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk
+#define DSI_LCOLCR_COLC2_Pos          (6U)
+#define DSI_LCOLCR_COLC2_Msk          (0x1UL << DSI_LCOLCR_COLC2_Pos)          /*!< 0x00000040 */
+#define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk
+#define DSI_LCOLCR_COLC3_Pos          (7U)
+#define DSI_LCOLCR_COLC3_Msk          (0x1UL << DSI_LCOLCR_COLC3_Pos)          /*!< 0x00000080 */
+#define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk
+
+#define DSI_LCOLCR_LPE_Pos            (8U)
+#define DSI_LCOLCR_LPE_Msk            (0x1UL << DSI_LCOLCR_LPE_Pos)            /*!< 0x00000100 */
+#define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosely Packet Enable */
+
+/*******************  Bit definition for DSI_LPCR register  ***************/
+#define DSI_LPCR_DEP_Pos              (0U)
+#define DSI_LPCR_DEP_Msk              (0x1UL << DSI_LPCR_DEP_Pos)              /*!< 0x00000001 */
+#define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */
+#define DSI_LPCR_VSP_Pos              (1U)
+#define DSI_LPCR_VSP_Msk              (0x1UL << DSI_LPCR_VSP_Pos)              /*!< 0x00000002 */
+#define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */
+#define DSI_LPCR_HSP_Pos              (2U)
+#define DSI_LPCR_HSP_Msk              (0x1UL << DSI_LPCR_HSP_Pos)              /*!< 0x00000004 */
+#define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */
+
+/*******************  Bit definition for DSI_LPMCR register  **************/
+#define DSI_LPMCR_VLPSIZE_Pos         (0U)
+#define DSI_LPMCR_VLPSIZE_Msk         (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)        /*!< 0x000000FF */
+#define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */
+#define DSI_LPMCR_VLPSIZE0_Pos        (0U)
+#define DSI_LPMCR_VLPSIZE0_Msk        (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)        /*!< 0x00000001 */
+#define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk
+#define DSI_LPMCR_VLPSIZE1_Pos        (1U)
+#define DSI_LPMCR_VLPSIZE1_Msk        (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)        /*!< 0x00000002 */
+#define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk
+#define DSI_LPMCR_VLPSIZE2_Pos        (2U)
+#define DSI_LPMCR_VLPSIZE2_Msk        (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)        /*!< 0x00000004 */
+#define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk
+#define DSI_LPMCR_VLPSIZE3_Pos        (3U)
+#define DSI_LPMCR_VLPSIZE3_Msk        (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)        /*!< 0x00000008 */
+#define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk
+#define DSI_LPMCR_VLPSIZE4_Pos        (4U)
+#define DSI_LPMCR_VLPSIZE4_Msk        (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)        /*!< 0x00000010 */
+#define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk
+#define DSI_LPMCR_VLPSIZE5_Pos        (5U)
+#define DSI_LPMCR_VLPSIZE5_Msk        (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)        /*!< 0x00000020 */
+#define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk
+#define DSI_LPMCR_VLPSIZE6_Pos        (6U)
+#define DSI_LPMCR_VLPSIZE6_Msk        (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)        /*!< 0x00000040 */
+#define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk
+#define DSI_LPMCR_VLPSIZE7_Pos        (7U)
+#define DSI_LPMCR_VLPSIZE7_Msk        (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)        /*!< 0x00000080 */
+#define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk
+
+#define DSI_LPMCR_LPSIZE_Pos          (16U)
+#define DSI_LPMCR_LPSIZE_Msk          (0xFFUL << DSI_LPMCR_LPSIZE_Pos)         /*!< 0x00FF0000 */
+#define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */
+#define DSI_LPMCR_LPSIZE0_Pos         (16U)
+#define DSI_LPMCR_LPSIZE0_Msk         (0x1UL << DSI_LPMCR_LPSIZE0_Pos)         /*!< 0x00010000 */
+#define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk
+#define DSI_LPMCR_LPSIZE1_Pos         (17U)
+#define DSI_LPMCR_LPSIZE1_Msk         (0x1UL << DSI_LPMCR_LPSIZE1_Pos)         /*!< 0x00020000 */
+#define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk
+#define DSI_LPMCR_LPSIZE2_Pos         (18U)
+#define DSI_LPMCR_LPSIZE2_Msk         (0x1UL << DSI_LPMCR_LPSIZE2_Pos)         /*!< 0x00040000 */
+#define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk
+#define DSI_LPMCR_LPSIZE3_Pos         (19U)
+#define DSI_LPMCR_LPSIZE3_Msk         (0x1UL << DSI_LPMCR_LPSIZE3_Pos)         /*!< 0x00080000 */
+#define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk
+#define DSI_LPMCR_LPSIZE4_Pos         (20U)
+#define DSI_LPMCR_LPSIZE4_Msk         (0x1UL << DSI_LPMCR_LPSIZE4_Pos)         /*!< 0x00100000 */
+#define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk
+#define DSI_LPMCR_LPSIZE5_Pos         (21U)
+#define DSI_LPMCR_LPSIZE5_Msk         (0x1UL << DSI_LPMCR_LPSIZE5_Pos)         /*!< 0x00200000 */
+#define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk
+#define DSI_LPMCR_LPSIZE6_Pos         (22U)
+#define DSI_LPMCR_LPSIZE6_Msk         (0x1UL << DSI_LPMCR_LPSIZE6_Pos)         /*!< 0x00400000 */
+#define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk
+#define DSI_LPMCR_LPSIZE7_Pos         (23U)
+#define DSI_LPMCR_LPSIZE7_Msk         (0x1UL << DSI_LPMCR_LPSIZE7_Pos)         /*!< 0x00800000 */
+#define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk
+
+/*******************  Bit definition for DSI_PCR register  ****************/
+#define DSI_PCR_ETTXE_Pos             (0U)
+#define DSI_PCR_ETTXE_Msk             (0x1UL << DSI_PCR_ETTXE_Pos)             /*!< 0x00000001 */
+#define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */
+#define DSI_PCR_ETRXE_Pos             (1U)
+#define DSI_PCR_ETRXE_Msk             (0x1UL << DSI_PCR_ETRXE_Pos)             /*!< 0x00000002 */
+#define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */
+#define DSI_PCR_BTAE_Pos              (2U)
+#define DSI_PCR_BTAE_Msk              (0x1UL << DSI_PCR_BTAE_Pos)              /*!< 0x00000004 */
+#define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */
+#define DSI_PCR_ECCRXE_Pos            (3U)
+#define DSI_PCR_ECCRXE_Msk            (0x1UL << DSI_PCR_ECCRXE_Pos)            /*!< 0x00000008 */
+#define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */
+#define DSI_PCR_CRCRXE_Pos            (4U)
+#define DSI_PCR_CRCRXE_Msk            (0x1UL << DSI_PCR_CRCRXE_Pos)            /*!< 0x00000010 */
+#define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */
+
+/*******************  Bit definition for DSI_GVCIDR register  *************/
+#define DSI_GVCIDR_VCID_Pos           (0U)
+#define DSI_GVCIDR_VCID_Msk           (0x3UL << DSI_GVCIDR_VCID_Pos)           /*!< 0x00000003 */
+#define DSI_GVCIDR_VCID               DSI_GVCIDR_VCID_Msk                      /*!< Virtual Channel ID */
+#define DSI_GVCIDR_VCID0_Pos          (0U)
+#define DSI_GVCIDR_VCID0_Msk          (0x1UL << DSI_GVCIDR_VCID0_Pos)          /*!< 0x00000001 */
+#define DSI_GVCIDR_VCID0              DSI_GVCIDR_VCID0_Msk
+#define DSI_GVCIDR_VCID1_Pos          (1U)
+#define DSI_GVCIDR_VCID1_Msk          (0x1UL << DSI_GVCIDR_VCID1_Pos)          /*!< 0x00000002 */
+#define DSI_GVCIDR_VCID1              DSI_GVCIDR_VCID1_Msk
+
+/*******************  Bit definition for DSI_MCR register  ****************/
+#define DSI_MCR_CMDM_Pos              (0U)
+#define DSI_MCR_CMDM_Msk              (0x1UL << DSI_MCR_CMDM_Pos)              /*!< 0x00000001 */
+#define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */
+
+/*******************  Bit definition for DSI_VMCR register  ***************/
+#define DSI_VMCR_VMT_Pos              (0U)
+#define DSI_VMCR_VMT_Msk              (0x3UL << DSI_VMCR_VMT_Pos)              /*!< 0x00000003 */
+#define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */
+#define DSI_VMCR_VMT0_Pos             (0U)
+#define DSI_VMCR_VMT0_Msk             (0x1UL << DSI_VMCR_VMT0_Pos)             /*!< 0x00000001 */
+#define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk
+#define DSI_VMCR_VMT1_Pos             (1U)
+#define DSI_VMCR_VMT1_Msk             (0x1UL << DSI_VMCR_VMT1_Pos)             /*!< 0x00000002 */
+#define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk
+
+#define DSI_VMCR_LPVSAE_Pos           (8U)
+#define DSI_VMCR_LPVSAE_Msk           (0x1UL << DSI_VMCR_LPVSAE_Pos)           /*!< 0x00000100 */
+#define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */
+#define DSI_VMCR_LPVBPE_Pos           (9U)
+#define DSI_VMCR_LPVBPE_Msk           (0x1UL << DSI_VMCR_LPVBPE_Pos)           /*!< 0x00000200 */
+#define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */
+#define DSI_VMCR_LPVFPE_Pos           (10U)
+#define DSI_VMCR_LPVFPE_Msk           (0x1UL << DSI_VMCR_LPVFPE_Pos)           /*!< 0x00000400 */
+#define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCR_LPVAE_Pos            (11U)
+#define DSI_VMCR_LPVAE_Msk            (0x1UL << DSI_VMCR_LPVAE_Pos)            /*!< 0x00000800 */
+#define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */
+#define DSI_VMCR_LPHBPE_Pos           (12U)
+#define DSI_VMCR_LPHBPE_Msk           (0x1UL << DSI_VMCR_LPHBPE_Pos)           /*!< 0x00001000 */
+#define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */
+#define DSI_VMCR_LPHFPE_Pos           (13U)
+#define DSI_VMCR_LPHFPE_Msk           (0x1UL << DSI_VMCR_LPHFPE_Pos)           /*!< 0x00002000 */
+#define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */
+#define DSI_VMCR_FBTAAE_Pos           (14U)
+#define DSI_VMCR_FBTAAE_Msk           (0x1UL << DSI_VMCR_FBTAAE_Pos)           /*!< 0x00004000 */
+#define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */
+#define DSI_VMCR_LPCE_Pos             (15U)
+#define DSI_VMCR_LPCE_Msk             (0x1UL << DSI_VMCR_LPCE_Pos)             /*!< 0x00008000 */
+#define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */
+#define DSI_VMCR_PGE_Pos              (16U)
+#define DSI_VMCR_PGE_Msk              (0x1UL << DSI_VMCR_PGE_Pos)              /*!< 0x00010000 */
+#define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */
+#define DSI_VMCR_PGM_Pos              (20U)
+#define DSI_VMCR_PGM_Msk              (0x1UL << DSI_VMCR_PGM_Pos)              /*!< 0x00100000 */
+#define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */
+#define DSI_VMCR_PGO_Pos              (24U)
+#define DSI_VMCR_PGO_Msk              (0x1UL << DSI_VMCR_PGO_Pos)              /*!< 0x01000000 */
+#define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */
+
+/*******************  Bit definition for DSI_VPCR register  ***************/
+#define DSI_VPCR_VPSIZE_Pos           (0U)
+#define DSI_VPCR_VPSIZE_Msk           (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)        /*!< 0x00003FFF */
+#define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */
+#define DSI_VPCR_VPSIZE0_Pos          (0U)
+#define DSI_VPCR_VPSIZE0_Msk          (0x1UL << DSI_VPCR_VPSIZE0_Pos)          /*!< 0x00000001 */
+#define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk
+#define DSI_VPCR_VPSIZE1_Pos          (1U)
+#define DSI_VPCR_VPSIZE1_Msk          (0x1UL << DSI_VPCR_VPSIZE1_Pos)          /*!< 0x00000002 */
+#define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk
+#define DSI_VPCR_VPSIZE2_Pos          (2U)
+#define DSI_VPCR_VPSIZE2_Msk          (0x1UL << DSI_VPCR_VPSIZE2_Pos)          /*!< 0x00000004 */
+#define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk
+#define DSI_VPCR_VPSIZE3_Pos          (3U)
+#define DSI_VPCR_VPSIZE3_Msk          (0x1UL << DSI_VPCR_VPSIZE3_Pos)          /*!< 0x00000008 */
+#define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk
+#define DSI_VPCR_VPSIZE4_Pos          (4U)
+#define DSI_VPCR_VPSIZE4_Msk          (0x1UL << DSI_VPCR_VPSIZE4_Pos)          /*!< 0x00000010 */
+#define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk
+#define DSI_VPCR_VPSIZE5_Pos          (5U)
+#define DSI_VPCR_VPSIZE5_Msk          (0x1UL << DSI_VPCR_VPSIZE5_Pos)          /*!< 0x00000020 */
+#define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk
+#define DSI_VPCR_VPSIZE6_Pos          (6U)
+#define DSI_VPCR_VPSIZE6_Msk          (0x1UL << DSI_VPCR_VPSIZE6_Pos)          /*!< 0x00000040 */
+#define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk
+#define DSI_VPCR_VPSIZE7_Pos          (7U)
+#define DSI_VPCR_VPSIZE7_Msk          (0x1UL << DSI_VPCR_VPSIZE7_Pos)          /*!< 0x00000080 */
+#define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk
+#define DSI_VPCR_VPSIZE8_Pos          (8U)
+#define DSI_VPCR_VPSIZE8_Msk          (0x1UL << DSI_VPCR_VPSIZE8_Pos)          /*!< 0x00000100 */
+#define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk
+#define DSI_VPCR_VPSIZE9_Pos          (9U)
+#define DSI_VPCR_VPSIZE9_Msk          (0x1UL << DSI_VPCR_VPSIZE9_Pos)          /*!< 0x00000200 */
+#define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk
+#define DSI_VPCR_VPSIZE10_Pos         (10U)
+#define DSI_VPCR_VPSIZE10_Msk         (0x1UL << DSI_VPCR_VPSIZE10_Pos)         /*!< 0x00000400 */
+#define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk
+#define DSI_VPCR_VPSIZE11_Pos         (11U)
+#define DSI_VPCR_VPSIZE11_Msk         (0x1UL << DSI_VPCR_VPSIZE11_Pos)         /*!< 0x00000800 */
+#define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk
+#define DSI_VPCR_VPSIZE12_Pos         (12U)
+#define DSI_VPCR_VPSIZE12_Msk         (0x1UL << DSI_VPCR_VPSIZE12_Pos)         /*!< 0x00001000 */
+#define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk
+#define DSI_VPCR_VPSIZE13_Pos         (13U)
+#define DSI_VPCR_VPSIZE13_Msk         (0x1UL << DSI_VPCR_VPSIZE13_Pos)         /*!< 0x00002000 */
+#define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk
+
+/*******************  Bit definition for DSI_VCCR register  ***************/
+#define DSI_VCCR_NUMC_Pos             (0U)
+#define DSI_VCCR_NUMC_Msk             (0x1FFFUL << DSI_VCCR_NUMC_Pos)          /*!< 0x00001FFF */
+#define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */
+#define DSI_VCCR_NUMC0_Pos            (0U)
+#define DSI_VCCR_NUMC0_Msk            (0x1UL << DSI_VCCR_NUMC0_Pos)            /*!< 0x00000001 */
+#define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk
+#define DSI_VCCR_NUMC1_Pos            (1U)
+#define DSI_VCCR_NUMC1_Msk            (0x1UL << DSI_VCCR_NUMC1_Pos)            /*!< 0x00000002 */
+#define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk
+#define DSI_VCCR_NUMC2_Pos            (2U)
+#define DSI_VCCR_NUMC2_Msk            (0x1UL << DSI_VCCR_NUMC2_Pos)            /*!< 0x00000004 */
+#define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk
+#define DSI_VCCR_NUMC3_Pos            (3U)
+#define DSI_VCCR_NUMC3_Msk            (0x1UL << DSI_VCCR_NUMC3_Pos)            /*!< 0x00000008 */
+#define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk
+#define DSI_VCCR_NUMC4_Pos            (4U)
+#define DSI_VCCR_NUMC4_Msk            (0x1UL << DSI_VCCR_NUMC4_Pos)            /*!< 0x00000010 */
+#define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk
+#define DSI_VCCR_NUMC5_Pos            (5U)
+#define DSI_VCCR_NUMC5_Msk            (0x1UL << DSI_VCCR_NUMC5_Pos)            /*!< 0x00000020 */
+#define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk
+#define DSI_VCCR_NUMC6_Pos            (6U)
+#define DSI_VCCR_NUMC6_Msk            (0x1UL << DSI_VCCR_NUMC6_Pos)            /*!< 0x00000040 */
+#define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk
+#define DSI_VCCR_NUMC7_Pos            (7U)
+#define DSI_VCCR_NUMC7_Msk            (0x1UL << DSI_VCCR_NUMC7_Pos)            /*!< 0x00000080 */
+#define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk
+#define DSI_VCCR_NUMC8_Pos            (8U)
+#define DSI_VCCR_NUMC8_Msk            (0x1UL << DSI_VCCR_NUMC8_Pos)            /*!< 0x00000100 */
+#define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk
+#define DSI_VCCR_NUMC9_Pos            (9U)
+#define DSI_VCCR_NUMC9_Msk            (0x1UL << DSI_VCCR_NUMC9_Pos)            /*!< 0x00000200 */
+#define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk
+#define DSI_VCCR_NUMC10_Pos           (10U)
+#define DSI_VCCR_NUMC10_Msk           (0x1UL << DSI_VCCR_NUMC10_Pos)           /*!< 0x00000400 */
+#define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk
+#define DSI_VCCR_NUMC11_Pos           (11U)
+#define DSI_VCCR_NUMC11_Msk           (0x1UL << DSI_VCCR_NUMC11_Pos)           /*!< 0x00000800 */
+#define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk
+#define DSI_VCCR_NUMC12_Pos           (12U)
+#define DSI_VCCR_NUMC12_Msk           (0x1UL << DSI_VCCR_NUMC12_Pos)           /*!< 0x00001000 */
+#define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk
+
+/*******************  Bit definition for DSI_VNPCR register  **************/
+#define DSI_VNPCR_NPSIZE_Pos          (0U)
+#define DSI_VNPCR_NPSIZE_Msk          (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)       /*!< 0x00001FFF */
+#define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */
+#define DSI_VNPCR_NPSIZE0_Pos         (0U)
+#define DSI_VNPCR_NPSIZE0_Msk         (0x1UL << DSI_VNPCR_NPSIZE0_Pos)         /*!< 0x00000001 */
+#define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk
+#define DSI_VNPCR_NPSIZE1_Pos         (1U)
+#define DSI_VNPCR_NPSIZE1_Msk         (0x1UL << DSI_VNPCR_NPSIZE1_Pos)         /*!< 0x00000002 */
+#define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk
+#define DSI_VNPCR_NPSIZE2_Pos         (2U)
+#define DSI_VNPCR_NPSIZE2_Msk         (0x1UL << DSI_VNPCR_NPSIZE2_Pos)         /*!< 0x00000004 */
+#define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk
+#define DSI_VNPCR_NPSIZE3_Pos         (3U)
+#define DSI_VNPCR_NPSIZE3_Msk         (0x1UL << DSI_VNPCR_NPSIZE3_Pos)         /*!< 0x00000008 */
+#define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk
+#define DSI_VNPCR_NPSIZE4_Pos         (4U)
+#define DSI_VNPCR_NPSIZE4_Msk         (0x1UL << DSI_VNPCR_NPSIZE4_Pos)         /*!< 0x00000010 */
+#define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk
+#define DSI_VNPCR_NPSIZE5_Pos         (5U)
+#define DSI_VNPCR_NPSIZE5_Msk         (0x1UL << DSI_VNPCR_NPSIZE5_Pos)         /*!< 0x00000020 */
+#define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk
+#define DSI_VNPCR_NPSIZE6_Pos         (6U)
+#define DSI_VNPCR_NPSIZE6_Msk         (0x1UL << DSI_VNPCR_NPSIZE6_Pos)         /*!< 0x00000040 */
+#define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk
+#define DSI_VNPCR_NPSIZE7_Pos         (7U)
+#define DSI_VNPCR_NPSIZE7_Msk         (0x1UL << DSI_VNPCR_NPSIZE7_Pos)         /*!< 0x00000080 */
+#define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk
+#define DSI_VNPCR_NPSIZE8_Pos         (8U)
+#define DSI_VNPCR_NPSIZE8_Msk         (0x1UL << DSI_VNPCR_NPSIZE8_Pos)         /*!< 0x00000100 */
+#define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk
+#define DSI_VNPCR_NPSIZE9_Pos         (9U)
+#define DSI_VNPCR_NPSIZE9_Msk         (0x1UL << DSI_VNPCR_NPSIZE9_Pos)         /*!< 0x00000200 */
+#define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk
+#define DSI_VNPCR_NPSIZE10_Pos        (10U)
+#define DSI_VNPCR_NPSIZE10_Msk        (0x1UL << DSI_VNPCR_NPSIZE10_Pos)        /*!< 0x00000400 */
+#define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk
+#define DSI_VNPCR_NPSIZE11_Pos        (11U)
+#define DSI_VNPCR_NPSIZE11_Msk        (0x1UL << DSI_VNPCR_NPSIZE11_Pos)        /*!< 0x00000800 */
+#define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk
+#define DSI_VNPCR_NPSIZE12_Pos        (12U)
+#define DSI_VNPCR_NPSIZE12_Msk        (0x1UL << DSI_VNPCR_NPSIZE12_Pos)        /*!< 0x00001000 */
+#define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk
+
+/*******************  Bit definition for DSI_VHSACR register  *************/
+#define DSI_VHSACR_HSA_Pos            (0U)
+#define DSI_VHSACR_HSA_Msk            (0xFFFUL << DSI_VHSACR_HSA_Pos)          /*!< 0x00000FFF */
+#define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACR_HSA0_Pos           (0U)
+#define DSI_VHSACR_HSA0_Msk           (0x1UL << DSI_VHSACR_HSA0_Pos)           /*!< 0x00000001 */
+#define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk
+#define DSI_VHSACR_HSA1_Pos           (1U)
+#define DSI_VHSACR_HSA1_Msk           (0x1UL << DSI_VHSACR_HSA1_Pos)           /*!< 0x00000002 */
+#define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk
+#define DSI_VHSACR_HSA2_Pos           (2U)
+#define DSI_VHSACR_HSA2_Msk           (0x1UL << DSI_VHSACR_HSA2_Pos)           /*!< 0x00000004 */
+#define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk
+#define DSI_VHSACR_HSA3_Pos           (3U)
+#define DSI_VHSACR_HSA3_Msk           (0x1UL << DSI_VHSACR_HSA3_Pos)           /*!< 0x00000008 */
+#define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk
+#define DSI_VHSACR_HSA4_Pos           (4U)
+#define DSI_VHSACR_HSA4_Msk           (0x1UL << DSI_VHSACR_HSA4_Pos)           /*!< 0x00000010 */
+#define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk
+#define DSI_VHSACR_HSA5_Pos           (5U)
+#define DSI_VHSACR_HSA5_Msk           (0x1UL << DSI_VHSACR_HSA5_Pos)           /*!< 0x00000020 */
+#define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk
+#define DSI_VHSACR_HSA6_Pos           (6U)
+#define DSI_VHSACR_HSA6_Msk           (0x1UL << DSI_VHSACR_HSA6_Pos)           /*!< 0x00000040 */
+#define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk
+#define DSI_VHSACR_HSA7_Pos           (7U)
+#define DSI_VHSACR_HSA7_Msk           (0x1UL << DSI_VHSACR_HSA7_Pos)           /*!< 0x00000080 */
+#define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk
+#define DSI_VHSACR_HSA8_Pos           (8U)
+#define DSI_VHSACR_HSA8_Msk           (0x1UL << DSI_VHSACR_HSA8_Pos)           /*!< 0x00000100 */
+#define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk
+#define DSI_VHSACR_HSA9_Pos           (9U)
+#define DSI_VHSACR_HSA9_Msk           (0x1UL << DSI_VHSACR_HSA9_Pos)           /*!< 0x00000200 */
+#define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk
+#define DSI_VHSACR_HSA10_Pos          (10U)
+#define DSI_VHSACR_HSA10_Msk          (0x1UL << DSI_VHSACR_HSA10_Pos)          /*!< 0x00000400 */
+#define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk
+#define DSI_VHSACR_HSA11_Pos          (11U)
+#define DSI_VHSACR_HSA11_Msk          (0x1UL << DSI_VHSACR_HSA11_Pos)          /*!< 0x00000800 */
+#define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk
+
+/*******************  Bit definition for DSI_VHBPCR register  *************/
+#define DSI_VHBPCR_HBP_Pos            (0U)
+#define DSI_VHBPCR_HBP_Msk            (0xFFFUL << DSI_VHBPCR_HBP_Pos)          /*!< 0x00000FFF */
+#define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCR_HBP0_Pos           (0U)
+#define DSI_VHBPCR_HBP0_Msk           (0x1UL << DSI_VHBPCR_HBP0_Pos)           /*!< 0x00000001 */
+#define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk
+#define DSI_VHBPCR_HBP1_Pos           (1U)
+#define DSI_VHBPCR_HBP1_Msk           (0x1UL << DSI_VHBPCR_HBP1_Pos)           /*!< 0x00000002 */
+#define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk
+#define DSI_VHBPCR_HBP2_Pos           (2U)
+#define DSI_VHBPCR_HBP2_Msk           (0x1UL << DSI_VHBPCR_HBP2_Pos)           /*!< 0x00000004 */
+#define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk
+#define DSI_VHBPCR_HBP3_Pos           (3U)
+#define DSI_VHBPCR_HBP3_Msk           (0x1UL << DSI_VHBPCR_HBP3_Pos)           /*!< 0x00000008 */
+#define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk
+#define DSI_VHBPCR_HBP4_Pos           (4U)
+#define DSI_VHBPCR_HBP4_Msk           (0x1UL << DSI_VHBPCR_HBP4_Pos)           /*!< 0x00000010 */
+#define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk
+#define DSI_VHBPCR_HBP5_Pos           (5U)
+#define DSI_VHBPCR_HBP5_Msk           (0x1UL << DSI_VHBPCR_HBP5_Pos)           /*!< 0x00000020 */
+#define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk
+#define DSI_VHBPCR_HBP6_Pos           (6U)
+#define DSI_VHBPCR_HBP6_Msk           (0x1UL << DSI_VHBPCR_HBP6_Pos)           /*!< 0x00000040 */
+#define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk
+#define DSI_VHBPCR_HBP7_Pos           (7U)
+#define DSI_VHBPCR_HBP7_Msk           (0x1UL << DSI_VHBPCR_HBP7_Pos)           /*!< 0x00000080 */
+#define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk
+#define DSI_VHBPCR_HBP8_Pos           (8U)
+#define DSI_VHBPCR_HBP8_Msk           (0x1UL << DSI_VHBPCR_HBP8_Pos)           /*!< 0x00000100 */
+#define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk
+#define DSI_VHBPCR_HBP9_Pos           (9U)
+#define DSI_VHBPCR_HBP9_Msk           (0x1UL << DSI_VHBPCR_HBP9_Pos)           /*!< 0x00000200 */
+#define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk
+#define DSI_VHBPCR_HBP10_Pos          (10U)
+#define DSI_VHBPCR_HBP10_Msk          (0x1UL << DSI_VHBPCR_HBP10_Pos)          /*!< 0x00000400 */
+#define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk
+#define DSI_VHBPCR_HBP11_Pos          (11U)
+#define DSI_VHBPCR_HBP11_Msk          (0x1UL << DSI_VHBPCR_HBP11_Pos)          /*!< 0x00000800 */
+#define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk
+
+/*******************  Bit definition for DSI_VLCR register  ***************/
+#define DSI_VLCR_HLINE_Pos            (0U)
+#define DSI_VLCR_HLINE_Msk            (0x7FFFUL << DSI_VLCR_HLINE_Pos)         /*!< 0x00007FFF */
+#define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */
+#define DSI_VLCR_HLINE0_Pos           (0U)
+#define DSI_VLCR_HLINE0_Msk           (0x1UL << DSI_VLCR_HLINE0_Pos)           /*!< 0x00000001 */
+#define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk
+#define DSI_VLCR_HLINE1_Pos           (1U)
+#define DSI_VLCR_HLINE1_Msk           (0x1UL << DSI_VLCR_HLINE1_Pos)           /*!< 0x00000002 */
+#define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk
+#define DSI_VLCR_HLINE2_Pos           (2U)
+#define DSI_VLCR_HLINE2_Msk           (0x1UL << DSI_VLCR_HLINE2_Pos)           /*!< 0x00000004 */
+#define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk
+#define DSI_VLCR_HLINE3_Pos           (3U)
+#define DSI_VLCR_HLINE3_Msk           (0x1UL << DSI_VLCR_HLINE3_Pos)           /*!< 0x00000008 */
+#define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk
+#define DSI_VLCR_HLINE4_Pos           (4U)
+#define DSI_VLCR_HLINE4_Msk           (0x1UL << DSI_VLCR_HLINE4_Pos)           /*!< 0x00000010 */
+#define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk
+#define DSI_VLCR_HLINE5_Pos           (5U)
+#define DSI_VLCR_HLINE5_Msk           (0x1UL << DSI_VLCR_HLINE5_Pos)           /*!< 0x00000020 */
+#define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk
+#define DSI_VLCR_HLINE6_Pos           (6U)
+#define DSI_VLCR_HLINE6_Msk           (0x1UL << DSI_VLCR_HLINE6_Pos)           /*!< 0x00000040 */
+#define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk
+#define DSI_VLCR_HLINE7_Pos           (7U)
+#define DSI_VLCR_HLINE7_Msk           (0x1UL << DSI_VLCR_HLINE7_Pos)           /*!< 0x00000080 */
+#define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk
+#define DSI_VLCR_HLINE8_Pos           (8U)
+#define DSI_VLCR_HLINE8_Msk           (0x1UL << DSI_VLCR_HLINE8_Pos)           /*!< 0x00000100 */
+#define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk
+#define DSI_VLCR_HLINE9_Pos           (9U)
+#define DSI_VLCR_HLINE9_Msk           (0x1UL << DSI_VLCR_HLINE9_Pos)           /*!< 0x00000200 */
+#define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk
+#define DSI_VLCR_HLINE10_Pos          (10U)
+#define DSI_VLCR_HLINE10_Msk          (0x1UL << DSI_VLCR_HLINE10_Pos)          /*!< 0x00000400 */
+#define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk
+#define DSI_VLCR_HLINE11_Pos          (11U)
+#define DSI_VLCR_HLINE11_Msk          (0x1UL << DSI_VLCR_HLINE11_Pos)          /*!< 0x00000800 */
+#define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk
+#define DSI_VLCR_HLINE12_Pos          (12U)
+#define DSI_VLCR_HLINE12_Msk          (0x1UL << DSI_VLCR_HLINE12_Pos)          /*!< 0x00001000 */
+#define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk
+#define DSI_VLCR_HLINE13_Pos          (13U)
+#define DSI_VLCR_HLINE13_Msk          (0x1UL << DSI_VLCR_HLINE13_Pos)          /*!< 0x00002000 */
+#define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk
+#define DSI_VLCR_HLINE14_Pos          (14U)
+#define DSI_VLCR_HLINE14_Msk          (0x1UL << DSI_VLCR_HLINE14_Pos)          /*!< 0x00004000 */
+#define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk
+
+/*******************  Bit definition for DSI_VVSACR register  *************/
+#define DSI_VVSACR_VSA_Pos            (0U)
+#define DSI_VVSACR_VSA_Msk            (0x3FFUL << DSI_VVSACR_VSA_Pos)          /*!< 0x000003FF */
+#define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACR_VSA0_Pos           (0U)
+#define DSI_VVSACR_VSA0_Msk           (0x1UL << DSI_VVSACR_VSA0_Pos)           /*!< 0x00000001 */
+#define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk
+#define DSI_VVSACR_VSA1_Pos           (1U)
+#define DSI_VVSACR_VSA1_Msk           (0x1UL << DSI_VVSACR_VSA1_Pos)           /*!< 0x00000002 */
+#define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk
+#define DSI_VVSACR_VSA2_Pos           (2U)
+#define DSI_VVSACR_VSA2_Msk           (0x1UL << DSI_VVSACR_VSA2_Pos)           /*!< 0x00000004 */
+#define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk
+#define DSI_VVSACR_VSA3_Pos           (3U)
+#define DSI_VVSACR_VSA3_Msk           (0x1UL << DSI_VVSACR_VSA3_Pos)           /*!< 0x00000008 */
+#define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk
+#define DSI_VVSACR_VSA4_Pos           (4U)
+#define DSI_VVSACR_VSA4_Msk           (0x1UL << DSI_VVSACR_VSA4_Pos)           /*!< 0x00000010 */
+#define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk
+#define DSI_VVSACR_VSA5_Pos           (5U)
+#define DSI_VVSACR_VSA5_Msk           (0x1UL << DSI_VVSACR_VSA5_Pos)           /*!< 0x00000020 */
+#define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk
+#define DSI_VVSACR_VSA6_Pos           (6U)
+#define DSI_VVSACR_VSA6_Msk           (0x1UL << DSI_VVSACR_VSA6_Pos)           /*!< 0x00000040 */
+#define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk
+#define DSI_VVSACR_VSA7_Pos           (7U)
+#define DSI_VVSACR_VSA7_Msk           (0x1UL << DSI_VVSACR_VSA7_Pos)           /*!< 0x00000080 */
+#define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk
+#define DSI_VVSACR_VSA8_Pos           (8U)
+#define DSI_VVSACR_VSA8_Msk           (0x1UL << DSI_VVSACR_VSA8_Pos)           /*!< 0x00000100 */
+#define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk
+#define DSI_VVSACR_VSA9_Pos           (9U)
+#define DSI_VVSACR_VSA9_Msk           (0x1UL << DSI_VVSACR_VSA9_Pos)           /*!< 0x00000200 */
+#define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk
+
+/*******************  Bit definition for DSI_VVBPCR register  *************/
+#define DSI_VVBPCR_VBP_Pos            (0U)
+#define DSI_VVBPCR_VBP_Msk            (0x3FFUL << DSI_VVBPCR_VBP_Pos)          /*!< 0x000003FF */
+#define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCR_VBP0_Pos           (0U)
+#define DSI_VVBPCR_VBP0_Msk           (0x1UL << DSI_VVBPCR_VBP0_Pos)           /*!< 0x00000001 */
+#define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk
+#define DSI_VVBPCR_VBP1_Pos           (1U)
+#define DSI_VVBPCR_VBP1_Msk           (0x1UL << DSI_VVBPCR_VBP1_Pos)           /*!< 0x00000002 */
+#define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk
+#define DSI_VVBPCR_VBP2_Pos           (2U)
+#define DSI_VVBPCR_VBP2_Msk           (0x1UL << DSI_VVBPCR_VBP2_Pos)           /*!< 0x00000004 */
+#define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk
+#define DSI_VVBPCR_VBP3_Pos           (3U)
+#define DSI_VVBPCR_VBP3_Msk           (0x1UL << DSI_VVBPCR_VBP3_Pos)           /*!< 0x00000008 */
+#define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk
+#define DSI_VVBPCR_VBP4_Pos           (4U)
+#define DSI_VVBPCR_VBP4_Msk           (0x1UL << DSI_VVBPCR_VBP4_Pos)           /*!< 0x00000010 */
+#define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk
+#define DSI_VVBPCR_VBP5_Pos           (5U)
+#define DSI_VVBPCR_VBP5_Msk           (0x1UL << DSI_VVBPCR_VBP5_Pos)           /*!< 0x00000020 */
+#define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk
+#define DSI_VVBPCR_VBP6_Pos           (6U)
+#define DSI_VVBPCR_VBP6_Msk           (0x1UL << DSI_VVBPCR_VBP6_Pos)           /*!< 0x00000040 */
+#define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk
+#define DSI_VVBPCR_VBP7_Pos           (7U)
+#define DSI_VVBPCR_VBP7_Msk           (0x1UL << DSI_VVBPCR_VBP7_Pos)           /*!< 0x00000080 */
+#define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk
+#define DSI_VVBPCR_VBP8_Pos           (8U)
+#define DSI_VVBPCR_VBP8_Msk           (0x1UL << DSI_VVBPCR_VBP8_Pos)           /*!< 0x00000100 */
+#define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk
+#define DSI_VVBPCR_VBP9_Pos           (9U)
+#define DSI_VVBPCR_VBP9_Msk           (0x1UL << DSI_VVBPCR_VBP9_Pos)           /*!< 0x00000200 */
+#define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk
+
+/*******************  Bit definition for DSI_VVFPCR register  *************/
+#define DSI_VVFPCR_VFP_Pos            (0U)
+#define DSI_VVFPCR_VFP_Msk            (0x3FFUL << DSI_VVFPCR_VFP_Pos)          /*!< 0x000003FF */
+#define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCR_VFP0_Pos           (0U)
+#define DSI_VVFPCR_VFP0_Msk           (0x1UL << DSI_VVFPCR_VFP0_Pos)           /*!< 0x00000001 */
+#define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk
+#define DSI_VVFPCR_VFP1_Pos           (1U)
+#define DSI_VVFPCR_VFP1_Msk           (0x1UL << DSI_VVFPCR_VFP1_Pos)           /*!< 0x00000002 */
+#define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk
+#define DSI_VVFPCR_VFP2_Pos           (2U)
+#define DSI_VVFPCR_VFP2_Msk           (0x1UL << DSI_VVFPCR_VFP2_Pos)           /*!< 0x00000004 */
+#define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk
+#define DSI_VVFPCR_VFP3_Pos           (3U)
+#define DSI_VVFPCR_VFP3_Msk           (0x1UL << DSI_VVFPCR_VFP3_Pos)           /*!< 0x00000008 */
+#define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk
+#define DSI_VVFPCR_VFP4_Pos           (4U)
+#define DSI_VVFPCR_VFP4_Msk           (0x1UL << DSI_VVFPCR_VFP4_Pos)           /*!< 0x00000010 */
+#define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk
+#define DSI_VVFPCR_VFP5_Pos           (5U)
+#define DSI_VVFPCR_VFP5_Msk           (0x1UL << DSI_VVFPCR_VFP5_Pos)           /*!< 0x00000020 */
+#define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk
+#define DSI_VVFPCR_VFP6_Pos           (6U)
+#define DSI_VVFPCR_VFP6_Msk           (0x1UL << DSI_VVFPCR_VFP6_Pos)           /*!< 0x00000040 */
+#define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk
+#define DSI_VVFPCR_VFP7_Pos           (7U)
+#define DSI_VVFPCR_VFP7_Msk           (0x1UL << DSI_VVFPCR_VFP7_Pos)           /*!< 0x00000080 */
+#define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk
+#define DSI_VVFPCR_VFP8_Pos           (8U)
+#define DSI_VVFPCR_VFP8_Msk           (0x1UL << DSI_VVFPCR_VFP8_Pos)           /*!< 0x00000100 */
+#define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk
+#define DSI_VVFPCR_VFP9_Pos           (9U)
+#define DSI_VVFPCR_VFP9_Msk           (0x1UL << DSI_VVFPCR_VFP9_Pos)           /*!< 0x00000200 */
+#define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk
+
+/*******************  Bit definition for DSI_VVACR register  **************/
+#define DSI_VVACR_VA_Pos              (0U)
+#define DSI_VVACR_VA_Msk              (0x3FFFUL << DSI_VVACR_VA_Pos)           /*!< 0x00003FFF */
+#define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */
+#define DSI_VVACR_VA0_Pos             (0U)
+#define DSI_VVACR_VA0_Msk             (0x1UL << DSI_VVACR_VA0_Pos)             /*!< 0x00000001 */
+#define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk
+#define DSI_VVACR_VA1_Pos             (1U)
+#define DSI_VVACR_VA1_Msk             (0x1UL << DSI_VVACR_VA1_Pos)             /*!< 0x00000002 */
+#define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk
+#define DSI_VVACR_VA2_Pos             (2U)
+#define DSI_VVACR_VA2_Msk             (0x1UL << DSI_VVACR_VA2_Pos)             /*!< 0x00000004 */
+#define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk
+#define DSI_VVACR_VA3_Pos             (3U)
+#define DSI_VVACR_VA3_Msk             (0x1UL << DSI_VVACR_VA3_Pos)             /*!< 0x00000008 */
+#define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk
+#define DSI_VVACR_VA4_Pos             (4U)
+#define DSI_VVACR_VA4_Msk             (0x1UL << DSI_VVACR_VA4_Pos)             /*!< 0x00000010 */
+#define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk
+#define DSI_VVACR_VA5_Pos             (5U)
+#define DSI_VVACR_VA5_Msk             (0x1UL << DSI_VVACR_VA5_Pos)             /*!< 0x00000020 */
+#define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk
+#define DSI_VVACR_VA6_Pos             (6U)
+#define DSI_VVACR_VA6_Msk             (0x1UL << DSI_VVACR_VA6_Pos)             /*!< 0x00000040 */
+#define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk
+#define DSI_VVACR_VA7_Pos             (7U)
+#define DSI_VVACR_VA7_Msk             (0x1UL << DSI_VVACR_VA7_Pos)             /*!< 0x00000080 */
+#define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk
+#define DSI_VVACR_VA8_Pos             (8U)
+#define DSI_VVACR_VA8_Msk             (0x1UL << DSI_VVACR_VA8_Pos)             /*!< 0x00000100 */
+#define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk
+#define DSI_VVACR_VA9_Pos             (9U)
+#define DSI_VVACR_VA9_Msk             (0x1UL << DSI_VVACR_VA9_Pos)             /*!< 0x00000200 */
+#define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk
+#define DSI_VVACR_VA10_Pos            (10U)
+#define DSI_VVACR_VA10_Msk            (0x1UL << DSI_VVACR_VA10_Pos)            /*!< 0x00000400 */
+#define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk
+#define DSI_VVACR_VA11_Pos            (11U)
+#define DSI_VVACR_VA11_Msk            (0x1UL << DSI_VVACR_VA11_Pos)            /*!< 0x00000800 */
+#define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk
+#define DSI_VVACR_VA12_Pos            (12U)
+#define DSI_VVACR_VA12_Msk            (0x1UL << DSI_VVACR_VA12_Pos)            /*!< 0x00001000 */
+#define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk
+#define DSI_VVACR_VA13_Pos            (13U)
+#define DSI_VVACR_VA13_Msk            (0x1UL << DSI_VVACR_VA13_Pos)            /*!< 0x00002000 */
+#define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk
+
+/*******************  Bit definition for DSI_LCCR register  ***************/
+#define DSI_LCCR_CMDSIZE_Pos          (0U)
+#define DSI_LCCR_CMDSIZE_Msk          (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)       /*!< 0x0000FFFF */
+#define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */
+#define DSI_LCCR_CMDSIZE0_Pos         (0U)
+#define DSI_LCCR_CMDSIZE0_Msk         (0x1UL << DSI_LCCR_CMDSIZE0_Pos)         /*!< 0x00000001 */
+#define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk
+#define DSI_LCCR_CMDSIZE1_Pos         (1U)
+#define DSI_LCCR_CMDSIZE1_Msk         (0x1UL << DSI_LCCR_CMDSIZE1_Pos)         /*!< 0x00000002 */
+#define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk
+#define DSI_LCCR_CMDSIZE2_Pos         (2U)
+#define DSI_LCCR_CMDSIZE2_Msk         (0x1UL << DSI_LCCR_CMDSIZE2_Pos)         /*!< 0x00000004 */
+#define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk
+#define DSI_LCCR_CMDSIZE3_Pos         (3U)
+#define DSI_LCCR_CMDSIZE3_Msk         (0x1UL << DSI_LCCR_CMDSIZE3_Pos)         /*!< 0x00000008 */
+#define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk
+#define DSI_LCCR_CMDSIZE4_Pos         (4U)
+#define DSI_LCCR_CMDSIZE4_Msk         (0x1UL << DSI_LCCR_CMDSIZE4_Pos)         /*!< 0x00000010 */
+#define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk
+#define DSI_LCCR_CMDSIZE5_Pos         (5U)
+#define DSI_LCCR_CMDSIZE5_Msk         (0x1UL << DSI_LCCR_CMDSIZE5_Pos)         /*!< 0x00000020 */
+#define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk
+#define DSI_LCCR_CMDSIZE6_Pos         (6U)
+#define DSI_LCCR_CMDSIZE6_Msk         (0x1UL << DSI_LCCR_CMDSIZE6_Pos)         /*!< 0x00000040 */
+#define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk
+#define DSI_LCCR_CMDSIZE7_Pos         (7U)
+#define DSI_LCCR_CMDSIZE7_Msk         (0x1UL << DSI_LCCR_CMDSIZE7_Pos)         /*!< 0x00000080 */
+#define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk
+#define DSI_LCCR_CMDSIZE8_Pos         (8U)
+#define DSI_LCCR_CMDSIZE8_Msk         (0x1UL << DSI_LCCR_CMDSIZE8_Pos)         /*!< 0x00000100 */
+#define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk
+#define DSI_LCCR_CMDSIZE9_Pos         (9U)
+#define DSI_LCCR_CMDSIZE9_Msk         (0x1UL << DSI_LCCR_CMDSIZE9_Pos)         /*!< 0x00000200 */
+#define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk
+#define DSI_LCCR_CMDSIZE10_Pos        (10U)
+#define DSI_LCCR_CMDSIZE10_Msk        (0x1UL << DSI_LCCR_CMDSIZE10_Pos)        /*!< 0x00000400 */
+#define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk
+#define DSI_LCCR_CMDSIZE11_Pos        (11U)
+#define DSI_LCCR_CMDSIZE11_Msk        (0x1UL << DSI_LCCR_CMDSIZE11_Pos)        /*!< 0x00000800 */
+#define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk
+#define DSI_LCCR_CMDSIZE12_Pos        (12U)
+#define DSI_LCCR_CMDSIZE12_Msk        (0x1UL << DSI_LCCR_CMDSIZE12_Pos)        /*!< 0x00001000 */
+#define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk
+#define DSI_LCCR_CMDSIZE13_Pos        (13U)
+#define DSI_LCCR_CMDSIZE13_Msk        (0x1UL << DSI_LCCR_CMDSIZE13_Pos)        /*!< 0x00002000 */
+#define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk
+#define DSI_LCCR_CMDSIZE14_Pos        (14U)
+#define DSI_LCCR_CMDSIZE14_Msk        (0x1UL << DSI_LCCR_CMDSIZE14_Pos)        /*!< 0x00004000 */
+#define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk
+#define DSI_LCCR_CMDSIZE15_Pos        (15U)
+#define DSI_LCCR_CMDSIZE15_Msk        (0x1UL << DSI_LCCR_CMDSIZE15_Pos)        /*!< 0x00008000 */
+#define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk
+
+/*******************  Bit definition for DSI_CMCR register  ***************/
+#define DSI_CMCR_TEARE_Pos            (0U)
+#define DSI_CMCR_TEARE_Msk            (0x1UL << DSI_CMCR_TEARE_Pos)            /*!< 0x00000001 */
+#define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */
+#define DSI_CMCR_ARE_Pos              (1U)
+#define DSI_CMCR_ARE_Msk              (0x1UL << DSI_CMCR_ARE_Pos)              /*!< 0x00000002 */
+#define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */
+#define DSI_CMCR_GSW0TX_Pos           (8U)
+#define DSI_CMCR_GSW0TX_Msk           (0x1UL << DSI_CMCR_GSW0TX_Pos)           /*!< 0x00000100 */
+#define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */
+#define DSI_CMCR_GSW1TX_Pos           (9U)
+#define DSI_CMCR_GSW1TX_Msk           (0x1UL << DSI_CMCR_GSW1TX_Pos)           /*!< 0x00000200 */
+#define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */
+#define DSI_CMCR_GSW2TX_Pos           (10U)
+#define DSI_CMCR_GSW2TX_Msk           (0x1UL << DSI_CMCR_GSW2TX_Pos)           /*!< 0x00000400 */
+#define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */
+#define DSI_CMCR_GSR0TX_Pos           (11U)
+#define DSI_CMCR_GSR0TX_Msk           (0x1UL << DSI_CMCR_GSR0TX_Pos)           /*!< 0x00000800 */
+#define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */
+#define DSI_CMCR_GSR1TX_Pos           (12U)
+#define DSI_CMCR_GSR1TX_Msk           (0x1UL << DSI_CMCR_GSR1TX_Pos)           /*!< 0x00001000 */
+#define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */
+#define DSI_CMCR_GSR2TX_Pos           (13U)
+#define DSI_CMCR_GSR2TX_Msk           (0x1UL << DSI_CMCR_GSR2TX_Pos)           /*!< 0x00002000 */
+#define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */
+#define DSI_CMCR_GLWTX_Pos            (14U)
+#define DSI_CMCR_GLWTX_Msk            (0x1UL << DSI_CMCR_GLWTX_Pos)            /*!< 0x00004000 */
+#define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */
+#define DSI_CMCR_DSW0TX_Pos           (16U)
+#define DSI_CMCR_DSW0TX_Msk           (0x1UL << DSI_CMCR_DSW0TX_Pos)           /*!< 0x00010000 */
+#define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */
+#define DSI_CMCR_DSW1TX_Pos           (17U)
+#define DSI_CMCR_DSW1TX_Msk           (0x1UL << DSI_CMCR_DSW1TX_Pos)           /*!< 0x00020000 */
+#define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */
+#define DSI_CMCR_DSR0TX_Pos           (18U)
+#define DSI_CMCR_DSR0TX_Msk           (0x1UL << DSI_CMCR_DSR0TX_Pos)           /*!< 0x00040000 */
+#define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */
+#define DSI_CMCR_DLWTX_Pos            (19U)
+#define DSI_CMCR_DLWTX_Msk            (0x1UL << DSI_CMCR_DLWTX_Pos)            /*!< 0x00080000 */
+#define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */
+#define DSI_CMCR_MRDPS_Pos            (24U)
+#define DSI_CMCR_MRDPS_Msk            (0x1UL << DSI_CMCR_MRDPS_Pos)            /*!< 0x01000000 */
+#define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */
+
+/*******************  Bit definition for DSI_GHCR register  ***************/
+#define DSI_GHCR_DT_Pos               (0U)
+#define DSI_GHCR_DT_Msk               (0x3FUL << DSI_GHCR_DT_Pos)              /*!< 0x0000003F */
+#define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */
+#define DSI_GHCR_DT0_Pos              (0U)
+#define DSI_GHCR_DT0_Msk              (0x1UL << DSI_GHCR_DT0_Pos)              /*!< 0x00000001 */
+#define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk
+#define DSI_GHCR_DT1_Pos              (1U)
+#define DSI_GHCR_DT1_Msk              (0x1UL << DSI_GHCR_DT1_Pos)              /*!< 0x00000002 */
+#define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk
+#define DSI_GHCR_DT2_Pos              (2U)
+#define DSI_GHCR_DT2_Msk              (0x1UL << DSI_GHCR_DT2_Pos)              /*!< 0x00000004 */
+#define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk
+#define DSI_GHCR_DT3_Pos              (3U)
+#define DSI_GHCR_DT3_Msk              (0x1UL << DSI_GHCR_DT3_Pos)              /*!< 0x00000008 */
+#define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk
+#define DSI_GHCR_DT4_Pos              (4U)
+#define DSI_GHCR_DT4_Msk              (0x1UL << DSI_GHCR_DT4_Pos)              /*!< 0x00000010 */
+#define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk
+#define DSI_GHCR_DT5_Pos              (5U)
+#define DSI_GHCR_DT5_Msk              (0x1UL << DSI_GHCR_DT5_Pos)              /*!< 0x00000020 */
+#define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk
+
+#define DSI_GHCR_VCID_Pos             (6U)
+#define DSI_GHCR_VCID_Msk             (0x3UL << DSI_GHCR_VCID_Pos)             /*!< 0x000000C0 */
+#define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */
+#define DSI_GHCR_VCID0_Pos            (6U)
+#define DSI_GHCR_VCID0_Msk            (0x1UL << DSI_GHCR_VCID0_Pos)            /*!< 0x00000040 */
+#define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk
+#define DSI_GHCR_VCID1_Pos            (7U)
+#define DSI_GHCR_VCID1_Msk            (0x1UL << DSI_GHCR_VCID1_Pos)            /*!< 0x00000080 */
+#define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk
+
+#define DSI_GHCR_WCLSB_Pos            (8U)
+#define DSI_GHCR_WCLSB_Msk            (0xFFUL << DSI_GHCR_WCLSB_Pos)           /*!< 0x0000FF00 */
+#define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */
+#define DSI_GHCR_WCLSB0_Pos           (8U)
+#define DSI_GHCR_WCLSB0_Msk           (0x1UL << DSI_GHCR_WCLSB0_Pos)           /*!< 0x00000100 */
+#define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk
+#define DSI_GHCR_WCLSB1_Pos           (9U)
+#define DSI_GHCR_WCLSB1_Msk           (0x1UL << DSI_GHCR_WCLSB1_Pos)           /*!< 0x00000200 */
+#define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk
+#define DSI_GHCR_WCLSB2_Pos           (10U)
+#define DSI_GHCR_WCLSB2_Msk           (0x1UL << DSI_GHCR_WCLSB2_Pos)           /*!< 0x00000400 */
+#define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk
+#define DSI_GHCR_WCLSB3_Pos           (11U)
+#define DSI_GHCR_WCLSB3_Msk           (0x1UL << DSI_GHCR_WCLSB3_Pos)           /*!< 0x00000800 */
+#define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk
+#define DSI_GHCR_WCLSB4_Pos           (12U)
+#define DSI_GHCR_WCLSB4_Msk           (0x1UL << DSI_GHCR_WCLSB4_Pos)           /*!< 0x00001000 */
+#define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk
+#define DSI_GHCR_WCLSB5_Pos           (13U)
+#define DSI_GHCR_WCLSB5_Msk           (0x1UL << DSI_GHCR_WCLSB5_Pos)           /*!< 0x00002000 */
+#define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk
+#define DSI_GHCR_WCLSB6_Pos           (14U)
+#define DSI_GHCR_WCLSB6_Msk           (0x1UL << DSI_GHCR_WCLSB6_Pos)           /*!< 0x00004000 */
+#define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk
+#define DSI_GHCR_WCLSB7_Pos           (15U)
+#define DSI_GHCR_WCLSB7_Msk           (0x1UL << DSI_GHCR_WCLSB7_Pos)           /*!< 0x00008000 */
+#define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk
+
+#define DSI_GHCR_WCMSB_Pos            (16U)
+#define DSI_GHCR_WCMSB_Msk            (0xFFUL << DSI_GHCR_WCMSB_Pos)           /*!< 0x00FF0000 */
+#define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */
+#define DSI_GHCR_WCMSB0_Pos           (16U)
+#define DSI_GHCR_WCMSB0_Msk           (0x1UL << DSI_GHCR_WCMSB0_Pos)           /*!< 0x00010000 */
+#define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk
+#define DSI_GHCR_WCMSB1_Pos           (17U)
+#define DSI_GHCR_WCMSB1_Msk           (0x1UL << DSI_GHCR_WCMSB1_Pos)           /*!< 0x00020000 */
+#define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk
+#define DSI_GHCR_WCMSB2_Pos           (18U)
+#define DSI_GHCR_WCMSB2_Msk           (0x1UL << DSI_GHCR_WCMSB2_Pos)           /*!< 0x00040000 */
+#define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk
+#define DSI_GHCR_WCMSB3_Pos           (19U)
+#define DSI_GHCR_WCMSB3_Msk           (0x1UL << DSI_GHCR_WCMSB3_Pos)           /*!< 0x00080000 */
+#define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk
+#define DSI_GHCR_WCMSB4_Pos           (20U)
+#define DSI_GHCR_WCMSB4_Msk           (0x1UL << DSI_GHCR_WCMSB4_Pos)           /*!< 0x00100000 */
+#define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk
+#define DSI_GHCR_WCMSB5_Pos           (21U)
+#define DSI_GHCR_WCMSB5_Msk           (0x1UL << DSI_GHCR_WCMSB5_Pos)           /*!< 0x00200000 */
+#define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk
+#define DSI_GHCR_WCMSB6_Pos           (22U)
+#define DSI_GHCR_WCMSB6_Msk           (0x1UL << DSI_GHCR_WCMSB6_Pos)           /*!< 0x00400000 */
+#define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk
+#define DSI_GHCR_WCMSB7_Pos           (23U)
+#define DSI_GHCR_WCMSB7_Msk           (0x1UL << DSI_GHCR_WCMSB7_Pos)           /*!< 0x00800000 */
+#define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk
+
+/*******************  Bit definition for DSI_GPDR register  ***************/
+#define DSI_GPDR_DATA1_Pos            (0U)
+#define DSI_GPDR_DATA1_Msk            (0xFFUL << DSI_GPDR_DATA1_Pos)           /*!< 0x000000FF */
+#define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */
+#define DSI_GPDR_DATA1_0              (0x01UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000001 */
+#define DSI_GPDR_DATA1_1              (0x02UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000002 */
+#define DSI_GPDR_DATA1_2              (0x04UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000004 */
+#define DSI_GPDR_DATA1_3              (0x08UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000008 */
+#define DSI_GPDR_DATA1_4              (0x10UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000010 */
+#define DSI_GPDR_DATA1_5              (0x20UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000020 */
+#define DSI_GPDR_DATA1_6              (0x40UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000040 */
+#define DSI_GPDR_DATA1_7              (0x80UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000080 */
+
+#define DSI_GPDR_DATA2_Pos            (8U)
+#define DSI_GPDR_DATA2_Msk            (0xFFUL << DSI_GPDR_DATA2_Pos)           /*!< 0x0000FF00 */
+#define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */
+#define DSI_GPDR_DATA2_0              (0x01UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000100 */
+#define DSI_GPDR_DATA2_1              (0x02UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000200 */
+#define DSI_GPDR_DATA2_2              (0x04UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000400 */
+#define DSI_GPDR_DATA2_3              (0x08UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000800 */
+#define DSI_GPDR_DATA2_4              (0x10UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00001000 */
+#define DSI_GPDR_DATA2_5              (0x20UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00002000 */
+#define DSI_GPDR_DATA2_6              (0x40UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00004000 */
+#define DSI_GPDR_DATA2_7              (0x80UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00008000 */
+
+#define DSI_GPDR_DATA3_Pos            (16U)
+#define DSI_GPDR_DATA3_Msk            (0xFFUL << DSI_GPDR_DATA3_Pos)           /*!< 0x00FF0000 */
+#define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */
+#define DSI_GPDR_DATA3_0              (0x01UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00010000 */
+#define DSI_GPDR_DATA3_1              (0x02UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00020000 */
+#define DSI_GPDR_DATA3_2              (0x04UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00040000 */
+#define DSI_GPDR_DATA3_3              (0x08UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00080000 */
+#define DSI_GPDR_DATA3_4              (0x10UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00100000 */
+#define DSI_GPDR_DATA3_5              (0x20UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00200000 */
+#define DSI_GPDR_DATA3_6              (0x40UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00400000 */
+#define DSI_GPDR_DATA3_7              (0x80UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00800000 */
+
+#define DSI_GPDR_DATA4_Pos            (24U)
+#define DSI_GPDR_DATA4_Msk            (0xFFUL << DSI_GPDR_DATA4_Pos)           /*!< 0xFF000000 */
+#define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */
+#define DSI_GPDR_DATA4_0              (0x01UL << DSI_GPDR_DATA4_Pos)            /*!< 0x01000000 */
+#define DSI_GPDR_DATA4_1              (0x02UL << DSI_GPDR_DATA4_Pos)            /*!< 0x02000000 */
+#define DSI_GPDR_DATA4_2              (0x04UL << DSI_GPDR_DATA4_Pos)            /*!< 0x04000000 */
+#define DSI_GPDR_DATA4_3              (0x08UL << DSI_GPDR_DATA4_Pos)            /*!< 0x08000000 */
+#define DSI_GPDR_DATA4_4              (0x10UL << DSI_GPDR_DATA4_Pos)            /*!< 0x10000000 */
+#define DSI_GPDR_DATA4_5              (0x20UL << DSI_GPDR_DATA4_Pos)            /*!< 0x20000000 */
+#define DSI_GPDR_DATA4_6              (0x40UL << DSI_GPDR_DATA4_Pos)            /*!< 0x40000000 */
+#define DSI_GPDR_DATA4_7              (0x80UL << DSI_GPDR_DATA4_Pos)            /*!< 0x80000000 */
+
+/*******************  Bit definition for DSI_GPSR register  ***************/
+#define DSI_GPSR_CMDFE_Pos            (0U)
+#define DSI_GPSR_CMDFE_Msk            (0x1UL << DSI_GPSR_CMDFE_Pos)            /*!< 0x00000001 */
+#define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */
+#define DSI_GPSR_CMDFF_Pos            (1U)
+#define DSI_GPSR_CMDFF_Msk            (0x1UL << DSI_GPSR_CMDFF_Pos)            /*!< 0x00000002 */
+#define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */
+#define DSI_GPSR_PWRFE_Pos            (2U)
+#define DSI_GPSR_PWRFE_Msk            (0x1UL << DSI_GPSR_PWRFE_Pos)            /*!< 0x00000004 */
+#define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */
+#define DSI_GPSR_PWRFF_Pos            (3U)
+#define DSI_GPSR_PWRFF_Msk            (0x1UL << DSI_GPSR_PWRFF_Pos)            /*!< 0x00000008 */
+#define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */
+#define DSI_GPSR_PRDFE_Pos            (4U)
+#define DSI_GPSR_PRDFE_Msk            (0x1UL << DSI_GPSR_PRDFE_Pos)            /*!< 0x00000010 */
+#define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */
+#define DSI_GPSR_PRDFF_Pos            (5U)
+#define DSI_GPSR_PRDFF_Msk            (0x1UL << DSI_GPSR_PRDFF_Pos)            /*!< 0x00000020 */
+#define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */
+#define DSI_GPSR_RCB_Pos              (6U)
+#define DSI_GPSR_RCB_Msk              (0x1UL << DSI_GPSR_RCB_Pos)              /*!< 0x00000040 */
+#define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */
+
+/*******************  Bit definition for DSI_TCCR0 register  **************/
+#define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)
+#define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)   /*!< 0x0000FFFF */
+#define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */
+#define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)
+#define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)     /*!< 0x00000001 */
+#define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk
+#define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)
+#define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)     /*!< 0x00000002 */
+#define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk
+#define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)
+#define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)     /*!< 0x00000004 */
+#define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk
+#define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)
+#define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)     /*!< 0x00000008 */
+#define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk
+#define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)
+#define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)     /*!< 0x00000010 */
+#define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk
+#define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)
+#define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)     /*!< 0x00000020 */
+#define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk
+#define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)
+#define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)     /*!< 0x00000040 */
+#define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk
+#define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)
+#define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)     /*!< 0x00000080 */
+#define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk
+#define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)
+#define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)     /*!< 0x00000100 */
+#define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk
+#define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)
+#define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)     /*!< 0x00000200 */
+#define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk
+#define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)
+#define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)    /*!< 0x00000400 */
+#define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk
+#define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)
+#define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)    /*!< 0x00000800 */
+#define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk
+#define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)
+#define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)    /*!< 0x00001000 */
+#define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk
+#define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)
+#define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)    /*!< 0x00002000 */
+#define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk
+#define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)
+#define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)    /*!< 0x00004000 */
+#define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk
+#define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)
+#define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)    /*!< 0x00008000 */
+#define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk
+
+#define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)
+#define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)   /*!< 0xFFFF0000 */
+#define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */
+#define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)
+#define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)     /*!< 0x00010000 */
+#define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk
+#define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)
+#define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)     /*!< 0x00020000 */
+#define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk
+#define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)
+#define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)     /*!< 0x00040000 */
+#define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk
+#define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)
+#define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)     /*!< 0x00080000 */
+#define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk
+#define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)
+#define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)     /*!< 0x00100000 */
+#define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk
+#define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)
+#define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)     /*!< 0x00200000 */
+#define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk
+#define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)
+#define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)     /*!< 0x00400000 */
+#define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk
+#define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)
+#define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)     /*!< 0x00800000 */
+#define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk
+#define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)
+#define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)     /*!< 0x01000000 */
+#define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk
+#define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)
+#define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)     /*!< 0x02000000 */
+#define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk
+#define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)
+#define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)    /*!< 0x04000000 */
+#define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk
+#define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)
+#define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)    /*!< 0x08000000 */
+#define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk
+#define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)
+#define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)    /*!< 0x10000000 */
+#define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk
+#define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)
+#define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)    /*!< 0x20000000 */
+#define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk
+#define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)
+#define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)    /*!< 0x40000000 */
+#define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk
+#define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)
+#define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)    /*!< 0x80000000 */
+#define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk
+
+/*******************  Bit definition for DSI_TCCR1 register  **************/
+#define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)
+#define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)   /*!< 0x0000FFFF */
+#define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */
+#define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)
+#define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)     /*!< 0x00000001 */
+#define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk
+#define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)
+#define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)     /*!< 0x00000002 */
+#define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk
+#define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)
+#define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)     /*!< 0x00000004 */
+#define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk
+#define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)
+#define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)     /*!< 0x00000008 */
+#define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk
+#define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)
+#define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)     /*!< 0x00000010 */
+#define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk
+#define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)
+#define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)     /*!< 0x00000020 */
+#define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk
+#define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)
+#define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)     /*!< 0x00000040 */
+#define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk
+#define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)
+#define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)     /*!< 0x00000080 */
+#define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk
+#define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)
+#define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)     /*!< 0x00000100 */
+#define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk
+#define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)
+#define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)     /*!< 0x00000200 */
+#define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk
+#define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)
+#define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)    /*!< 0x00000400 */
+#define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk
+#define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)
+#define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)    /*!< 0x00000800 */
+#define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk
+#define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)
+#define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)    /*!< 0x00001000 */
+#define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk
+#define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)
+#define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)    /*!< 0x00002000 */
+#define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk
+#define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)
+#define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)    /*!< 0x00004000 */
+#define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk
+#define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)
+#define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)    /*!< 0x00008000 */
+#define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk
+
+/*******************  Bit definition for DSI_TCCR2 register  **************/
+#define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)
+#define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)   /*!< 0x0000FFFF */
+#define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */
+#define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)
+#define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)     /*!< 0x00000001 */
+#define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk
+#define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)
+#define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)     /*!< 0x00000002 */
+#define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk
+#define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)
+#define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)     /*!< 0x00000004 */
+#define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk
+#define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)
+#define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)     /*!< 0x00000008 */
+#define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk
+#define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)
+#define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)     /*!< 0x00000010 */
+#define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk
+#define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)
+#define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)     /*!< 0x00000020 */
+#define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk
+#define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)
+#define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)     /*!< 0x00000040 */
+#define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk
+#define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)
+#define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)     /*!< 0x00000080 */
+#define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk
+#define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)
+#define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)     /*!< 0x00000100 */
+#define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk
+#define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)
+#define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)     /*!< 0x00000200 */
+#define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk
+#define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)
+#define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)    /*!< 0x00000400 */
+#define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk
+#define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)
+#define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)    /*!< 0x00000800 */
+#define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk
+#define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)
+#define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)    /*!< 0x00001000 */
+#define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk
+#define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)
+#define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)    /*!< 0x00002000 */
+#define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk
+#define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)
+#define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)    /*!< 0x00004000 */
+#define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk
+#define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)
+#define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)    /*!< 0x00008000 */
+#define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk
+
+/*******************  Bit definition for DSI_TCCR3 register  **************/
+#define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)
+#define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)   /*!< 0x0000FFFF */
+#define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */
+#define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)
+#define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)     /*!< 0x00000001 */
+#define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk
+#define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)
+#define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)     /*!< 0x00000002 */
+#define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk
+#define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)
+#define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)     /*!< 0x00000004 */
+#define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk
+#define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)
+#define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)     /*!< 0x00000008 */
+#define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk
+#define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)
+#define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)     /*!< 0x00000010 */
+#define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk
+#define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)
+#define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)     /*!< 0x00000020 */
+#define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk
+#define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)
+#define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)     /*!< 0x00000040 */
+#define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk
+#define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)
+#define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)     /*!< 0x00000080 */
+#define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk
+#define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)
+#define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)     /*!< 0x00000100 */
+#define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk
+#define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)
+#define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)     /*!< 0x00000200 */
+#define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk
+#define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)
+#define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)    /*!< 0x00000400 */
+#define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk
+#define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)
+#define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)    /*!< 0x00000800 */
+#define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk
+#define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)
+#define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)    /*!< 0x00001000 */
+#define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk
+#define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)
+#define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)    /*!< 0x00002000 */
+#define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk
+#define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)
+#define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)    /*!< 0x00004000 */
+#define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk
+#define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)
+#define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)    /*!< 0x00008000 */
+#define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk
+
+#define DSI_TCCR3_PM_Pos              (24U)
+#define DSI_TCCR3_PM_Msk              (0x1UL << DSI_TCCR3_PM_Pos)              /*!< 0x01000000 */
+#define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */
+
+/*******************  Bit definition for DSI_TCCR4 register  **************/
+#define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)
+#define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)   /*!< 0x0000FFFF */
+#define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */
+#define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)
+#define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)     /*!< 0x00000001 */
+#define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk
+#define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)
+#define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)     /*!< 0x00000002 */
+#define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk
+#define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)
+#define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)     /*!< 0x00000004 */
+#define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk
+#define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)
+#define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)     /*!< 0x00000008 */
+#define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk
+#define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)
+#define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)     /*!< 0x00000010 */
+#define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk
+#define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)
+#define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)     /*!< 0x00000020 */
+#define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk
+#define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)
+#define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)     /*!< 0x00000040 */
+#define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk
+#define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)
+#define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)     /*!< 0x00000080 */
+#define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk
+#define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)
+#define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)     /*!< 0x00000100 */
+#define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk
+#define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)
+#define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)     /*!< 0x00000200 */
+#define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk
+#define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)
+#define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)    /*!< 0x00000400 */
+#define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk
+#define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)
+#define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)    /*!< 0x00000800 */
+#define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk
+#define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)
+#define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)    /*!< 0x00001000 */
+#define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk
+#define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)
+#define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)    /*!< 0x00002000 */
+#define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk
+#define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)
+#define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)    /*!< 0x00004000 */
+#define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk
+#define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)
+#define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)    /*!< 0x00008000 */
+#define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk
+
+/*******************  Bit definition for DSI_TCCR5 register  **************/
+#define DSI_TCCR5_BTA_TOCNT_Pos       (0U)
+#define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)    /*!< 0x0000FFFF */
+#define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */
+#define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)
+#define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)      /*!< 0x00000001 */
+#define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk
+#define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)
+#define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)      /*!< 0x00000002 */
+#define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk
+#define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)
+#define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)      /*!< 0x00000004 */
+#define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk
+#define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)
+#define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)      /*!< 0x00000008 */
+#define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk
+#define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)
+#define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)      /*!< 0x00000010 */
+#define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk
+#define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)
+#define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)      /*!< 0x00000020 */
+#define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk
+#define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)
+#define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)      /*!< 0x00000040 */
+#define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk
+#define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)
+#define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)      /*!< 0x00000080 */
+#define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk
+#define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)
+#define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)      /*!< 0x00000100 */
+#define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk
+#define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)
+#define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)      /*!< 0x00000200 */
+#define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk
+#define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)
+#define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)     /*!< 0x00000400 */
+#define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk
+#define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)
+#define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)     /*!< 0x00000800 */
+#define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk
+#define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)
+#define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)     /*!< 0x00001000 */
+#define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk
+#define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)
+#define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)     /*!< 0x00002000 */
+#define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk
+#define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)
+#define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)     /*!< 0x00004000 */
+#define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk
+#define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)
+#define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)     /*!< 0x00008000 */
+#define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk
+
+/*******************  Bit definition for DSI_TDCR register  ***************/
+#define DSI_TDCR_3DM                  (0x00000003U)                  /*!< 3D Mode */
+#define DSI_TDCR_3DM0                 (0x00000001U)
+#define DSI_TDCR_3DM1                 (0x00000002U)
+
+#define DSI_TDCR_3DF                  (0x0000000CU)                  /*!< 3D Format */
+#define DSI_TDCR_3DF0                 (0x00000004U)
+#define DSI_TDCR_3DF1                 (0x00000008U)
+
+#define DSI_TDCR_SVS_Pos              (4U)
+#define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)              /*!< 0x00000010 */
+#define DSI_TDCR_SVS                  DSI_TDCR_SVS_Msk                         /*!< Second VSYNC */
+#define DSI_TDCR_RF_Pos               (5U)
+#define DSI_TDCR_RF_Msk               (0x1UL << DSI_TDCR_RF_Pos)               /*!< 0x00000020 */
+#define DSI_TDCR_RF                   DSI_TDCR_RF_Msk                          /*!< Right First */
+#define DSI_TDCR_S3DC_Pos             (16U)
+#define DSI_TDCR_S3DC_Msk             (0x1UL << DSI_TDCR_S3DC_Pos)             /*!< 0x00010000 */
+#define DSI_TDCR_S3DC                 DSI_TDCR_S3DC_Msk                        /*!< Send 3D Control */
+
+/*******************  Bit definition for DSI_CLCR register  ***************/
+#define DSI_CLCR_DPCC_Pos             (0U)
+#define DSI_CLCR_DPCC_Msk             (0x1UL << DSI_CLCR_DPCC_Pos)             /*!< 0x00000001 */
+#define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */
+#define DSI_CLCR_ACR_Pos              (1U)
+#define DSI_CLCR_ACR_Msk              (0x1UL << DSI_CLCR_ACR_Pos)              /*!< 0x00000002 */
+#define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */
+
+/*******************  Bit definition for DSI_CLTCR register  **************/
+#define DSI_CLTCR_LP2HS_TIME_Pos      (0U)
+#define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)    /*!< 0x000003FF */
+#define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */
+#define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)
+#define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)     /*!< 0x00000001 */
+#define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk
+#define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)
+#define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)     /*!< 0x00000002 */
+#define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk
+#define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)
+#define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)     /*!< 0x00000004 */
+#define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk
+#define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)
+#define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)     /*!< 0x00000008 */
+#define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk
+#define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)
+#define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)     /*!< 0x00000010 */
+#define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk
+#define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)
+#define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)     /*!< 0x00000020 */
+#define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk
+#define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)
+#define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)     /*!< 0x00000040 */
+#define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk
+#define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)
+#define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)     /*!< 0x00000080 */
+#define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk
+#define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)
+#define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)     /*!< 0x00000100 */
+#define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk
+#define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)
+#define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)     /*!< 0x00000200 */
+#define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk
+
+#define DSI_CLTCR_HS2LP_TIME_Pos      (16U)
+#define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)    /*!< 0x03FF0000 */
+#define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */
+#define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)
+#define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)     /*!< 0x00010000 */
+#define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk
+#define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)
+#define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)     /*!< 0x00020000 */
+#define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk
+#define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)
+#define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)     /*!< 0x00040000 */
+#define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk
+#define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)
+#define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)     /*!< 0x00080000 */
+#define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk
+#define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)
+#define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)     /*!< 0x00100000 */
+#define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk
+#define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)
+#define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)     /*!< 0x00200000 */
+#define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk
+#define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)
+#define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)     /*!< 0x00400000 */
+#define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk
+#define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)
+#define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)     /*!< 0x00800000 */
+#define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk
+#define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)
+#define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)     /*!< 0x01000000 */
+#define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk
+#define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)
+#define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)     /*!< 0x02000000 */
+#define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk
+
+/*******************  Bit definition for DSI_DLTCR register  **************/
+#define DSI_DLTCR_MRD_TIME_Pos        (0U)
+#define DSI_DLTCR_MRD_TIME_Msk        (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)     /*!< 0x00007FFF */
+#define DSI_DLTCR_MRD_TIME            DSI_DLTCR_MRD_TIME_Msk                   /*!< Maximum Read Time */
+#define DSI_DLTCR_MRD_TIME0_Pos       (0U)
+#define DSI_DLTCR_MRD_TIME0_Msk       (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)       /*!< 0x00000001 */
+#define DSI_DLTCR_MRD_TIME0           DSI_DLTCR_MRD_TIME0_Msk
+#define DSI_DLTCR_MRD_TIME1_Pos       (1U)
+#define DSI_DLTCR_MRD_TIME1_Msk       (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)       /*!< 0x00000002 */
+#define DSI_DLTCR_MRD_TIME1           DSI_DLTCR_MRD_TIME1_Msk
+#define DSI_DLTCR_MRD_TIME2_Pos       (2U)
+#define DSI_DLTCR_MRD_TIME2_Msk       (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)       /*!< 0x00000004 */
+#define DSI_DLTCR_MRD_TIME2           DSI_DLTCR_MRD_TIME2_Msk
+#define DSI_DLTCR_MRD_TIME3_Pos       (3U)
+#define DSI_DLTCR_MRD_TIME3_Msk       (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)       /*!< 0x00000008 */
+#define DSI_DLTCR_MRD_TIME3           DSI_DLTCR_MRD_TIME3_Msk
+#define DSI_DLTCR_MRD_TIME4_Pos       (4U)
+#define DSI_DLTCR_MRD_TIME4_Msk       (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)       /*!< 0x00000010 */
+#define DSI_DLTCR_MRD_TIME4           DSI_DLTCR_MRD_TIME4_Msk
+#define DSI_DLTCR_MRD_TIME5_Pos       (5U)
+#define DSI_DLTCR_MRD_TIME5_Msk       (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)       /*!< 0x00000020 */
+#define DSI_DLTCR_MRD_TIME5           DSI_DLTCR_MRD_TIME5_Msk
+#define DSI_DLTCR_MRD_TIME6_Pos       (6U)
+#define DSI_DLTCR_MRD_TIME6_Msk       (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)       /*!< 0x00000040 */
+#define DSI_DLTCR_MRD_TIME6           DSI_DLTCR_MRD_TIME6_Msk
+#define DSI_DLTCR_MRD_TIME7_Pos       (7U)
+#define DSI_DLTCR_MRD_TIME7_Msk       (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)       /*!< 0x00000080 */
+#define DSI_DLTCR_MRD_TIME7           DSI_DLTCR_MRD_TIME7_Msk
+#define DSI_DLTCR_MRD_TIME8_Pos       (8U)
+#define DSI_DLTCR_MRD_TIME8_Msk       (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)       /*!< 0x00000100 */
+#define DSI_DLTCR_MRD_TIME8           DSI_DLTCR_MRD_TIME8_Msk
+#define DSI_DLTCR_MRD_TIME9_Pos       (9U)
+#define DSI_DLTCR_MRD_TIME9_Msk       (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)       /*!< 0x00000200 */
+#define DSI_DLTCR_MRD_TIME9           DSI_DLTCR_MRD_TIME9_Msk
+#define DSI_DLTCR_MRD_TIME10_Pos      (10U)
+#define DSI_DLTCR_MRD_TIME10_Msk      (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)      /*!< 0x00000400 */
+#define DSI_DLTCR_MRD_TIME10          DSI_DLTCR_MRD_TIME10_Msk
+#define DSI_DLTCR_MRD_TIME11_Pos      (11U)
+#define DSI_DLTCR_MRD_TIME11_Msk      (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)      /*!< 0x00000800 */
+#define DSI_DLTCR_MRD_TIME11          DSI_DLTCR_MRD_TIME11_Msk
+#define DSI_DLTCR_MRD_TIME12_Pos      (12U)
+#define DSI_DLTCR_MRD_TIME12_Msk      (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)      /*!< 0x00001000 */
+#define DSI_DLTCR_MRD_TIME12          DSI_DLTCR_MRD_TIME12_Msk
+#define DSI_DLTCR_MRD_TIME13_Pos      (13U)
+#define DSI_DLTCR_MRD_TIME13_Msk      (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)      /*!< 0x00002000 */
+#define DSI_DLTCR_MRD_TIME13          DSI_DLTCR_MRD_TIME13_Msk
+#define DSI_DLTCR_MRD_TIME14_Pos      (14U)
+#define DSI_DLTCR_MRD_TIME14_Msk      (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)      /*!< 0x00004000 */
+#define DSI_DLTCR_MRD_TIME14          DSI_DLTCR_MRD_TIME14_Msk
+
+#define DSI_DLTCR_LP2HS_TIME_Pos      (16U)
+#define DSI_DLTCR_LP2HS_TIME_Msk      (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)     /*!< 0x00FF0000 */
+#define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */
+#define DSI_DLTCR_LP2HS_TIME0_Pos     (16U)
+#define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)     /*!< 0x00010000 */
+#define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk
+#define DSI_DLTCR_LP2HS_TIME1_Pos     (17U)
+#define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)     /*!< 0x00020000 */
+#define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk
+#define DSI_DLTCR_LP2HS_TIME2_Pos     (18U)
+#define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)     /*!< 0x00040000 */
+#define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk
+#define DSI_DLTCR_LP2HS_TIME3_Pos     (19U)
+#define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)     /*!< 0x00080000 */
+#define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk
+#define DSI_DLTCR_LP2HS_TIME4_Pos     (20U)
+#define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)     /*!< 0x00100000 */
+#define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk
+#define DSI_DLTCR_LP2HS_TIME5_Pos     (21U)
+#define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)     /*!< 0x00200000 */
+#define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk
+#define DSI_DLTCR_LP2HS_TIME6_Pos     (22U)
+#define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)     /*!< 0x00400000 */
+#define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk
+#define DSI_DLTCR_LP2HS_TIME7_Pos     (23U)
+#define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)     /*!< 0x00800000 */
+#define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk
+
+#define DSI_DLTCR_HS2LP_TIME_Pos      (24U)
+#define DSI_DLTCR_HS2LP_TIME_Msk      (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)     /*!< 0xFF000000 */
+#define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */
+#define DSI_DLTCR_HS2LP_TIME0_Pos     (24U)
+#define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)     /*!< 0x01000000 */
+#define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk
+#define DSI_DLTCR_HS2LP_TIME1_Pos     (25U)
+#define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)     /*!< 0x02000000 */
+#define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk
+#define DSI_DLTCR_HS2LP_TIME2_Pos     (26U)
+#define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)     /*!< 0x04000000 */
+#define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk
+#define DSI_DLTCR_HS2LP_TIME3_Pos     (27U)
+#define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)     /*!< 0x08000000 */
+#define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk
+#define DSI_DLTCR_HS2LP_TIME4_Pos     (28U)
+#define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)     /*!< 0x10000000 */
+#define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk
+#define DSI_DLTCR_HS2LP_TIME5_Pos     (29U)
+#define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)     /*!< 0x20000000 */
+#define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk
+#define DSI_DLTCR_HS2LP_TIME6_Pos     (30U)
+#define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)     /*!< 0x40000000 */
+#define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk
+#define DSI_DLTCR_HS2LP_TIME7_Pos     (31U)
+#define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)     /*!< 0x80000000 */
+#define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk
+
+/*******************  Bit definition for DSI_PCTLR register  **************/
+#define DSI_PCTLR_DEN_Pos             (1U)
+#define DSI_PCTLR_DEN_Msk             (0x1UL << DSI_PCTLR_DEN_Pos)             /*!< 0x00000002 */
+#define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */
+#define DSI_PCTLR_CKE_Pos             (2U)
+#define DSI_PCTLR_CKE_Msk             (0x1UL << DSI_PCTLR_CKE_Pos)             /*!< 0x00000004 */
+#define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */
+
+/*******************  Bit definition for DSI_PCONFR register  *************/
+#define DSI_PCONFR_NL_Pos             (0U)
+#define DSI_PCONFR_NL_Msk             (0x3UL << DSI_PCONFR_NL_Pos)             /*!< 0x00000003 */
+#define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */
+#define DSI_PCONFR_NL0_Pos            (0U)
+#define DSI_PCONFR_NL0_Msk            (0x1UL << DSI_PCONFR_NL0_Pos)            /*!< 0x00000001 */
+#define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk
+#define DSI_PCONFR_NL1_Pos            (1U)
+#define DSI_PCONFR_NL1_Msk            (0x1UL << DSI_PCONFR_NL1_Pos)            /*!< 0x00000002 */
+#define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk
+
+#define DSI_PCONFR_SW_TIME_Pos        (8U)
+#define DSI_PCONFR_SW_TIME_Msk        (0xFFUL << DSI_PCONFR_SW_TIME_Pos)       /*!< 0x0000FF00 */
+#define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */
+#define DSI_PCONFR_SW_TIME0_Pos       (8U)
+#define DSI_PCONFR_SW_TIME0_Msk       (0x1UL << DSI_PCONFR_SW_TIME0_Pos)       /*!< 0x00000100 */
+#define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk
+#define DSI_PCONFR_SW_TIME1_Pos       (9U)
+#define DSI_PCONFR_SW_TIME1_Msk       (0x1UL << DSI_PCONFR_SW_TIME1_Pos)       /*!< 0x00000200 */
+#define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk
+#define DSI_PCONFR_SW_TIME2_Pos       (10U)
+#define DSI_PCONFR_SW_TIME2_Msk       (0x1UL << DSI_PCONFR_SW_TIME2_Pos)       /*!< 0x00000400 */
+#define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk
+#define DSI_PCONFR_SW_TIME3_Pos       (11U)
+#define DSI_PCONFR_SW_TIME3_Msk       (0x1UL << DSI_PCONFR_SW_TIME3_Pos)       /*!< 0x00000800 */
+#define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk
+#define DSI_PCONFR_SW_TIME4_Pos       (12U)
+#define DSI_PCONFR_SW_TIME4_Msk       (0x1UL << DSI_PCONFR_SW_TIME4_Pos)       /*!< 0x00001000 */
+#define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk
+#define DSI_PCONFR_SW_TIME5_Pos       (13U)
+#define DSI_PCONFR_SW_TIME5_Msk       (0x1UL << DSI_PCONFR_SW_TIME5_Pos)       /*!< 0x00002000 */
+#define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk
+#define DSI_PCONFR_SW_TIME6_Pos       (14U)
+#define DSI_PCONFR_SW_TIME6_Msk       (0x1UL << DSI_PCONFR_SW_TIME6_Pos)       /*!< 0x00004000 */
+#define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk
+#define DSI_PCONFR_SW_TIME7_Pos       (15U)
+#define DSI_PCONFR_SW_TIME7_Msk       (0x1UL << DSI_PCONFR_SW_TIME7_Pos)       /*!< 0x00008000 */
+#define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk
+
+/*******************  Bit definition for DSI_PUCR register  ***************/
+#define DSI_PUCR_URCL_Pos             (0U)
+#define DSI_PUCR_URCL_Msk             (0x1UL << DSI_PUCR_URCL_Pos)             /*!< 0x00000001 */
+#define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */
+#define DSI_PUCR_UECL_Pos             (1U)
+#define DSI_PUCR_UECL_Msk             (0x1UL << DSI_PUCR_UECL_Pos)             /*!< 0x00000002 */
+#define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */
+#define DSI_PUCR_URDL_Pos             (2U)
+#define DSI_PUCR_URDL_Msk             (0x1UL << DSI_PUCR_URDL_Pos)             /*!< 0x00000004 */
+#define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */
+#define DSI_PUCR_UEDL_Pos             (3U)
+#define DSI_PUCR_UEDL_Msk             (0x1UL << DSI_PUCR_UEDL_Pos)             /*!< 0x00000008 */
+#define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */
+
+/*******************  Bit definition for DSI_PTTCR register  **************/
+#define DSI_PTTCR_TX_TRIG_Pos         (0U)
+#define DSI_PTTCR_TX_TRIG_Msk         (0xFUL << DSI_PTTCR_TX_TRIG_Pos)         /*!< 0x0000000F */
+#define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */
+#define DSI_PTTCR_TX_TRIG0_Pos        (0U)
+#define DSI_PTTCR_TX_TRIG0_Msk        (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)        /*!< 0x00000001 */
+#define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk
+#define DSI_PTTCR_TX_TRIG1_Pos        (1U)
+#define DSI_PTTCR_TX_TRIG1_Msk        (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)        /*!< 0x00000002 */
+#define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk
+#define DSI_PTTCR_TX_TRIG2_Pos        (2U)
+#define DSI_PTTCR_TX_TRIG2_Msk        (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)        /*!< 0x00000004 */
+#define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk
+#define DSI_PTTCR_TX_TRIG3_Pos        (3U)
+#define DSI_PTTCR_TX_TRIG3_Msk        (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)        /*!< 0x00000008 */
+#define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk
+
+/*******************  Bit definition for DSI_PSR register  ****************/
+#define DSI_PSR_PD_Pos                (1U)
+#define DSI_PSR_PD_Msk                (0x1UL << DSI_PSR_PD_Pos)                /*!< 0x00000002 */
+#define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */
+#define DSI_PSR_PSSC_Pos              (2U)
+#define DSI_PSR_PSSC_Msk              (0x1UL << DSI_PSR_PSSC_Pos)              /*!< 0x00000004 */
+#define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */
+#define DSI_PSR_UANC_Pos              (3U)
+#define DSI_PSR_UANC_Msk              (0x1UL << DSI_PSR_UANC_Pos)              /*!< 0x00000008 */
+#define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */
+#define DSI_PSR_PSS0_Pos              (4U)
+#define DSI_PSR_PSS0_Msk              (0x1UL << DSI_PSR_PSS0_Pos)              /*!< 0x00000010 */
+#define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */
+#define DSI_PSR_UAN0_Pos              (5U)
+#define DSI_PSR_UAN0_Msk              (0x1UL << DSI_PSR_UAN0_Pos)              /*!< 0x00000020 */
+#define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */
+#define DSI_PSR_RUE0_Pos              (6U)
+#define DSI_PSR_RUE0_Msk              (0x1UL << DSI_PSR_RUE0_Pos)              /*!< 0x00000040 */
+#define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */
+#define DSI_PSR_PSS1_Pos              (7U)
+#define DSI_PSR_PSS1_Msk              (0x1UL << DSI_PSR_PSS1_Pos)              /*!< 0x00000080 */
+#define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */
+#define DSI_PSR_UAN1_Pos              (8U)
+#define DSI_PSR_UAN1_Msk              (0x1UL << DSI_PSR_UAN1_Pos)              /*!< 0x00000100 */
+#define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */
+
+/*******************  Bit definition for DSI_ISR0 register  ***************/
+#define DSI_ISR0_AE0_Pos              (0U)
+#define DSI_ISR0_AE0_Msk              (0x1UL << DSI_ISR0_AE0_Pos)              /*!< 0x00000001 */
+#define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */
+#define DSI_ISR0_AE1_Pos              (1U)
+#define DSI_ISR0_AE1_Msk              (0x1UL << DSI_ISR0_AE1_Pos)              /*!< 0x00000002 */
+#define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */
+#define DSI_ISR0_AE2_Pos              (2U)
+#define DSI_ISR0_AE2_Msk              (0x1UL << DSI_ISR0_AE2_Pos)              /*!< 0x00000004 */
+#define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */
+#define DSI_ISR0_AE3_Pos              (3U)
+#define DSI_ISR0_AE3_Msk              (0x1UL << DSI_ISR0_AE3_Pos)              /*!< 0x00000008 */
+#define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */
+#define DSI_ISR0_AE4_Pos              (4U)
+#define DSI_ISR0_AE4_Msk              (0x1UL << DSI_ISR0_AE4_Pos)              /*!< 0x00000010 */
+#define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */
+#define DSI_ISR0_AE5_Pos              (5U)
+#define DSI_ISR0_AE5_Msk              (0x1UL << DSI_ISR0_AE5_Pos)              /*!< 0x00000020 */
+#define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */
+#define DSI_ISR0_AE6_Pos              (6U)
+#define DSI_ISR0_AE6_Msk              (0x1UL << DSI_ISR0_AE6_Pos)              /*!< 0x00000040 */
+#define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */
+#define DSI_ISR0_AE7_Pos              (7U)
+#define DSI_ISR0_AE7_Msk              (0x1UL << DSI_ISR0_AE7_Pos)              /*!< 0x00000080 */
+#define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */
+#define DSI_ISR0_AE8_Pos              (8U)
+#define DSI_ISR0_AE8_Msk              (0x1UL << DSI_ISR0_AE8_Pos)              /*!< 0x00000100 */
+#define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */
+#define DSI_ISR0_AE9_Pos              (9U)
+#define DSI_ISR0_AE9_Msk              (0x1UL << DSI_ISR0_AE9_Pos)              /*!< 0x00000200 */
+#define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */
+#define DSI_ISR0_AE10_Pos             (10U)
+#define DSI_ISR0_AE10_Msk             (0x1UL << DSI_ISR0_AE10_Pos)             /*!< 0x00000400 */
+#define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */
+#define DSI_ISR0_AE11_Pos             (11U)
+#define DSI_ISR0_AE11_Msk             (0x1UL << DSI_ISR0_AE11_Pos)             /*!< 0x00000800 */
+#define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */
+#define DSI_ISR0_AE12_Pos             (12U)
+#define DSI_ISR0_AE12_Msk             (0x1UL << DSI_ISR0_AE12_Pos)             /*!< 0x00001000 */
+#define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */
+#define DSI_ISR0_AE13_Pos             (13U)
+#define DSI_ISR0_AE13_Msk             (0x1UL << DSI_ISR0_AE13_Pos)             /*!< 0x00002000 */
+#define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */
+#define DSI_ISR0_AE14_Pos             (14U)
+#define DSI_ISR0_AE14_Msk             (0x1UL << DSI_ISR0_AE14_Pos)             /*!< 0x00004000 */
+#define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */
+#define DSI_ISR0_AE15_Pos             (15U)
+#define DSI_ISR0_AE15_Msk             (0x1UL << DSI_ISR0_AE15_Pos)             /*!< 0x00008000 */
+#define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */
+#define DSI_ISR0_PE0_Pos              (16U)
+#define DSI_ISR0_PE0_Msk              (0x1UL << DSI_ISR0_PE0_Pos)              /*!< 0x00010000 */
+#define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */
+#define DSI_ISR0_PE1_Pos              (17U)
+#define DSI_ISR0_PE1_Msk              (0x1UL << DSI_ISR0_PE1_Pos)              /*!< 0x00020000 */
+#define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */
+#define DSI_ISR0_PE2_Pos              (18U)
+#define DSI_ISR0_PE2_Msk              (0x1UL << DSI_ISR0_PE2_Pos)              /*!< 0x00040000 */
+#define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */
+#define DSI_ISR0_PE3_Pos              (19U)
+#define DSI_ISR0_PE3_Msk              (0x1UL << DSI_ISR0_PE3_Pos)              /*!< 0x00080000 */
+#define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */
+#define DSI_ISR0_PE4_Pos              (20U)
+#define DSI_ISR0_PE4_Msk              (0x1UL << DSI_ISR0_PE4_Pos)              /*!< 0x00100000 */
+#define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */
+
+/*******************  Bit definition for DSI_ISR1 register  ***************/
+#define DSI_ISR1_TOHSTX_Pos           (0U)
+#define DSI_ISR1_TOHSTX_Msk           (0x1UL << DSI_ISR1_TOHSTX_Pos)           /*!< 0x00000001 */
+#define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */
+#define DSI_ISR1_TOLPRX_Pos           (1U)
+#define DSI_ISR1_TOLPRX_Msk           (0x1UL << DSI_ISR1_TOLPRX_Pos)           /*!< 0x00000002 */
+#define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */
+#define DSI_ISR1_ECCSE_Pos            (2U)
+#define DSI_ISR1_ECCSE_Msk            (0x1UL << DSI_ISR1_ECCSE_Pos)            /*!< 0x00000004 */
+#define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */
+#define DSI_ISR1_ECCME_Pos            (3U)
+#define DSI_ISR1_ECCME_Msk            (0x1UL << DSI_ISR1_ECCME_Pos)            /*!< 0x00000008 */
+#define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */
+#define DSI_ISR1_CRCE_Pos             (4U)
+#define DSI_ISR1_CRCE_Msk             (0x1UL << DSI_ISR1_CRCE_Pos)             /*!< 0x00000010 */
+#define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */
+#define DSI_ISR1_PSE_Pos              (5U)
+#define DSI_ISR1_PSE_Msk              (0x1UL << DSI_ISR1_PSE_Pos)              /*!< 0x00000020 */
+#define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */
+#define DSI_ISR1_EOTPE_Pos            (6U)
+#define DSI_ISR1_EOTPE_Msk            (0x1UL << DSI_ISR1_EOTPE_Pos)            /*!< 0x00000040 */
+#define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */
+#define DSI_ISR1_LPWRE_Pos            (7U)
+#define DSI_ISR1_LPWRE_Msk            (0x1UL << DSI_ISR1_LPWRE_Pos)            /*!< 0x00000080 */
+#define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */
+#define DSI_ISR1_GCWRE_Pos            (8U)
+#define DSI_ISR1_GCWRE_Msk            (0x1UL << DSI_ISR1_GCWRE_Pos)            /*!< 0x00000100 */
+#define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */
+#define DSI_ISR1_GPWRE_Pos            (9U)
+#define DSI_ISR1_GPWRE_Msk            (0x1UL << DSI_ISR1_GPWRE_Pos)            /*!< 0x00000200 */
+#define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */
+#define DSI_ISR1_GPTXE_Pos            (10U)
+#define DSI_ISR1_GPTXE_Msk            (0x1UL << DSI_ISR1_GPTXE_Pos)            /*!< 0x00000400 */
+#define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */
+#define DSI_ISR1_GPRDE_Pos            (11U)
+#define DSI_ISR1_GPRDE_Msk            (0x1UL << DSI_ISR1_GPRDE_Pos)            /*!< 0x00000800 */
+#define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */
+#define DSI_ISR1_GPRXE_Pos            (12U)
+#define DSI_ISR1_GPRXE_Msk            (0x1UL << DSI_ISR1_GPRXE_Pos)            /*!< 0x00001000 */
+#define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */
+
+/*******************  Bit definition for DSI_IER0 register  ***************/
+#define DSI_IER0_AE0IE_Pos            (0U)
+#define DSI_IER0_AE0IE_Msk            (0x1UL << DSI_IER0_AE0IE_Pos)            /*!< 0x00000001 */
+#define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */
+#define DSI_IER0_AE1IE_Pos            (1U)
+#define DSI_IER0_AE1IE_Msk            (0x1UL << DSI_IER0_AE1IE_Pos)            /*!< 0x00000002 */
+#define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */
+#define DSI_IER0_AE2IE_Pos            (2U)
+#define DSI_IER0_AE2IE_Msk            (0x1UL << DSI_IER0_AE2IE_Pos)            /*!< 0x00000004 */
+#define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */
+#define DSI_IER0_AE3IE_Pos            (3U)
+#define DSI_IER0_AE3IE_Msk            (0x1UL << DSI_IER0_AE3IE_Pos)            /*!< 0x00000008 */
+#define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */
+#define DSI_IER0_AE4IE_Pos            (4U)
+#define DSI_IER0_AE4IE_Msk            (0x1UL << DSI_IER0_AE4IE_Pos)            /*!< 0x00000010 */
+#define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */
+#define DSI_IER0_AE5IE_Pos            (5U)
+#define DSI_IER0_AE5IE_Msk            (0x1UL << DSI_IER0_AE5IE_Pos)            /*!< 0x00000020 */
+#define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */
+#define DSI_IER0_AE6IE_Pos            (6U)
+#define DSI_IER0_AE6IE_Msk            (0x1UL << DSI_IER0_AE6IE_Pos)            /*!< 0x00000040 */
+#define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */
+#define DSI_IER0_AE7IE_Pos            (7U)
+#define DSI_IER0_AE7IE_Msk            (0x1UL << DSI_IER0_AE7IE_Pos)            /*!< 0x00000080 */
+#define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */
+#define DSI_IER0_AE8IE_Pos            (8U)
+#define DSI_IER0_AE8IE_Msk            (0x1UL << DSI_IER0_AE8IE_Pos)            /*!< 0x00000100 */
+#define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */
+#define DSI_IER0_AE9IE_Pos            (9U)
+#define DSI_IER0_AE9IE_Msk            (0x1UL << DSI_IER0_AE9IE_Pos)            /*!< 0x00000200 */
+#define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */
+#define DSI_IER0_AE10IE_Pos           (10U)
+#define DSI_IER0_AE10IE_Msk           (0x1UL << DSI_IER0_AE10IE_Pos)           /*!< 0x00000400 */
+#define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */
+#define DSI_IER0_AE11IE_Pos           (11U)
+#define DSI_IER0_AE11IE_Msk           (0x1UL << DSI_IER0_AE11IE_Pos)           /*!< 0x00000800 */
+#define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */
+#define DSI_IER0_AE12IE_Pos           (12U)
+#define DSI_IER0_AE12IE_Msk           (0x1UL << DSI_IER0_AE12IE_Pos)           /*!< 0x00001000 */
+#define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */
+#define DSI_IER0_AE13IE_Pos           (13U)
+#define DSI_IER0_AE13IE_Msk           (0x1UL << DSI_IER0_AE13IE_Pos)           /*!< 0x00002000 */
+#define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */
+#define DSI_IER0_AE14IE_Pos           (14U)
+#define DSI_IER0_AE14IE_Msk           (0x1UL << DSI_IER0_AE14IE_Pos)           /*!< 0x00004000 */
+#define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */
+#define DSI_IER0_AE15IE_Pos           (15U)
+#define DSI_IER0_AE15IE_Msk           (0x1UL << DSI_IER0_AE15IE_Pos)           /*!< 0x00008000 */
+#define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */
+#define DSI_IER0_PE0IE_Pos            (16U)
+#define DSI_IER0_PE0IE_Msk            (0x1UL << DSI_IER0_PE0IE_Pos)            /*!< 0x00010000 */
+#define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */
+#define DSI_IER0_PE1IE_Pos            (17U)
+#define DSI_IER0_PE1IE_Msk            (0x1UL << DSI_IER0_PE1IE_Pos)            /*!< 0x00020000 */
+#define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */
+#define DSI_IER0_PE2IE_Pos            (18U)
+#define DSI_IER0_PE2IE_Msk            (0x1UL << DSI_IER0_PE2IE_Pos)            /*!< 0x00040000 */
+#define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */
+#define DSI_IER0_PE3IE_Pos            (19U)
+#define DSI_IER0_PE3IE_Msk            (0x1UL << DSI_IER0_PE3IE_Pos)            /*!< 0x00080000 */
+#define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */
+#define DSI_IER0_PE4IE_Pos            (20U)
+#define DSI_IER0_PE4IE_Msk            (0x1UL << DSI_IER0_PE4IE_Pos)            /*!< 0x00100000 */
+#define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */
+
+/*******************  Bit definition for DSI_IER1 register  ***************/
+#define DSI_IER1_TOHSTXIE_Pos         (0U)
+#define DSI_IER1_TOHSTXIE_Msk         (0x1UL << DSI_IER1_TOHSTXIE_Pos)         /*!< 0x00000001 */
+#define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */
+#define DSI_IER1_TOLPRXIE_Pos         (1U)
+#define DSI_IER1_TOLPRXIE_Msk         (0x1UL << DSI_IER1_TOLPRXIE_Pos)         /*!< 0x00000002 */
+#define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */
+#define DSI_IER1_ECCSEIE_Pos          (2U)
+#define DSI_IER1_ECCSEIE_Msk          (0x1UL << DSI_IER1_ECCSEIE_Pos)          /*!< 0x00000004 */
+#define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */
+#define DSI_IER1_ECCMEIE_Pos          (3U)
+#define DSI_IER1_ECCMEIE_Msk          (0x1UL << DSI_IER1_ECCMEIE_Pos)          /*!< 0x00000008 */
+#define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */
+#define DSI_IER1_CRCEIE_Pos           (4U)
+#define DSI_IER1_CRCEIE_Msk           (0x1UL << DSI_IER1_CRCEIE_Pos)           /*!< 0x00000010 */
+#define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */
+#define DSI_IER1_PSEIE_Pos            (5U)
+#define DSI_IER1_PSEIE_Msk            (0x1UL << DSI_IER1_PSEIE_Pos)            /*!< 0x00000020 */
+#define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */
+#define DSI_IER1_EOTPEIE_Pos          (6U)
+#define DSI_IER1_EOTPEIE_Msk          (0x1UL << DSI_IER1_EOTPEIE_Pos)          /*!< 0x00000040 */
+#define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */
+#define DSI_IER1_LPWREIE_Pos          (7U)
+#define DSI_IER1_LPWREIE_Msk          (0x1UL << DSI_IER1_LPWREIE_Pos)          /*!< 0x00000080 */
+#define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */
+#define DSI_IER1_GCWREIE_Pos          (8U)
+#define DSI_IER1_GCWREIE_Msk          (0x1UL << DSI_IER1_GCWREIE_Pos)          /*!< 0x00000100 */
+#define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */
+#define DSI_IER1_GPWREIE_Pos          (9U)
+#define DSI_IER1_GPWREIE_Msk          (0x1UL << DSI_IER1_GPWREIE_Pos)          /*!< 0x00000200 */
+#define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */
+#define DSI_IER1_GPTXEIE_Pos          (10U)
+#define DSI_IER1_GPTXEIE_Msk          (0x1UL << DSI_IER1_GPTXEIE_Pos)          /*!< 0x00000400 */
+#define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */
+#define DSI_IER1_GPRDEIE_Pos          (11U)
+#define DSI_IER1_GPRDEIE_Msk          (0x1UL << DSI_IER1_GPRDEIE_Pos)          /*!< 0x00000800 */
+#define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */
+#define DSI_IER1_GPRXEIE_Pos          (12U)
+#define DSI_IER1_GPRXEIE_Msk          (0x1UL << DSI_IER1_GPRXEIE_Pos)          /*!< 0x00001000 */
+#define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */
+
+/*******************  Bit definition for DSI_FIR0 register  ***************/
+#define DSI_FIR0_FAE0_Pos             (0U)
+#define DSI_FIR0_FAE0_Msk             (0x1UL << DSI_FIR0_FAE0_Pos)             /*!< 0x00000001 */
+#define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */
+#define DSI_FIR0_FAE1_Pos             (1U)
+#define DSI_FIR0_FAE1_Msk             (0x1UL << DSI_FIR0_FAE1_Pos)             /*!< 0x00000002 */
+#define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */
+#define DSI_FIR0_FAE2_Pos             (2U)
+#define DSI_FIR0_FAE2_Msk             (0x1UL << DSI_FIR0_FAE2_Pos)             /*!< 0x00000004 */
+#define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */
+#define DSI_FIR0_FAE3_Pos             (3U)
+#define DSI_FIR0_FAE3_Msk             (0x1UL << DSI_FIR0_FAE3_Pos)             /*!< 0x00000008 */
+#define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */
+#define DSI_FIR0_FAE4_Pos             (4U)
+#define DSI_FIR0_FAE4_Msk             (0x1UL << DSI_FIR0_FAE4_Pos)             /*!< 0x00000010 */
+#define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */
+#define DSI_FIR0_FAE5_Pos             (5U)
+#define DSI_FIR0_FAE5_Msk             (0x1UL << DSI_FIR0_FAE5_Pos)             /*!< 0x00000020 */
+#define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */
+#define DSI_FIR0_FAE6_Pos             (6U)
+#define DSI_FIR0_FAE6_Msk             (0x1UL << DSI_FIR0_FAE6_Pos)             /*!< 0x00000040 */
+#define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */
+#define DSI_FIR0_FAE7_Pos             (7U)
+#define DSI_FIR0_FAE7_Msk             (0x1UL << DSI_FIR0_FAE7_Pos)             /*!< 0x00000080 */
+#define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */
+#define DSI_FIR0_FAE8_Pos             (8U)
+#define DSI_FIR0_FAE8_Msk             (0x1UL << DSI_FIR0_FAE8_Pos)             /*!< 0x00000100 */
+#define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */
+#define DSI_FIR0_FAE9_Pos             (9U)
+#define DSI_FIR0_FAE9_Msk             (0x1UL << DSI_FIR0_FAE9_Pos)             /*!< 0x00000200 */
+#define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */
+#define DSI_FIR0_FAE10_Pos            (10U)
+#define DSI_FIR0_FAE10_Msk            (0x1UL << DSI_FIR0_FAE10_Pos)            /*!< 0x00000400 */
+#define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */
+#define DSI_FIR0_FAE11_Pos            (11U)
+#define DSI_FIR0_FAE11_Msk            (0x1UL << DSI_FIR0_FAE11_Pos)            /*!< 0x00000800 */
+#define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */
+#define DSI_FIR0_FAE12_Pos            (12U)
+#define DSI_FIR0_FAE12_Msk            (0x1UL << DSI_FIR0_FAE12_Pos)            /*!< 0x00001000 */
+#define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */
+#define DSI_FIR0_FAE13_Pos            (13U)
+#define DSI_FIR0_FAE13_Msk            (0x1UL << DSI_FIR0_FAE13_Pos)            /*!< 0x00002000 */
+#define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */
+#define DSI_FIR0_FAE14_Pos            (14U)
+#define DSI_FIR0_FAE14_Msk            (0x1UL << DSI_FIR0_FAE14_Pos)            /*!< 0x00004000 */
+#define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */
+#define DSI_FIR0_FAE15_Pos            (15U)
+#define DSI_FIR0_FAE15_Msk            (0x1UL << DSI_FIR0_FAE15_Pos)            /*!< 0x00008000 */
+#define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */
+#define DSI_FIR0_FPE0_Pos             (16U)
+#define DSI_FIR0_FPE0_Msk             (0x1UL << DSI_FIR0_FPE0_Pos)             /*!< 0x00010000 */
+#define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */
+#define DSI_FIR0_FPE1_Pos             (17U)
+#define DSI_FIR0_FPE1_Msk             (0x1UL << DSI_FIR0_FPE1_Pos)             /*!< 0x00020000 */
+#define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */
+#define DSI_FIR0_FPE2_Pos             (18U)
+#define DSI_FIR0_FPE2_Msk             (0x1UL << DSI_FIR0_FPE2_Pos)             /*!< 0x00040000 */
+#define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */
+#define DSI_FIR0_FPE3_Pos             (19U)
+#define DSI_FIR0_FPE3_Msk             (0x1UL << DSI_FIR0_FPE3_Pos)             /*!< 0x00080000 */
+#define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */
+#define DSI_FIR0_FPE4_Pos             (20U)
+#define DSI_FIR0_FPE4_Msk             (0x1UL << DSI_FIR0_FPE4_Pos)             /*!< 0x00100000 */
+#define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */
+
+/*******************  Bit definition for DSI_FIR1 register  ***************/
+#define DSI_FIR1_FTOHSTX_Pos          (0U)
+#define DSI_FIR1_FTOHSTX_Msk          (0x1UL << DSI_FIR1_FTOHSTX_Pos)          /*!< 0x00000001 */
+#define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */
+#define DSI_FIR1_FTOLPRX_Pos          (1U)
+#define DSI_FIR1_FTOLPRX_Msk          (0x1UL << DSI_FIR1_FTOLPRX_Pos)          /*!< 0x00000002 */
+#define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */
+#define DSI_FIR1_FECCSE_Pos           (2U)
+#define DSI_FIR1_FECCSE_Msk           (0x1UL << DSI_FIR1_FECCSE_Pos)           /*!< 0x00000004 */
+#define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */
+#define DSI_FIR1_FECCME_Pos           (3U)
+#define DSI_FIR1_FECCME_Msk           (0x1UL << DSI_FIR1_FECCME_Pos)           /*!< 0x00000008 */
+#define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */
+#define DSI_FIR1_FCRCE_Pos            (4U)
+#define DSI_FIR1_FCRCE_Msk            (0x1UL << DSI_FIR1_FCRCE_Pos)            /*!< 0x00000010 */
+#define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */
+#define DSI_FIR1_FPSE_Pos             (5U)
+#define DSI_FIR1_FPSE_Msk             (0x1UL << DSI_FIR1_FPSE_Pos)             /*!< 0x00000020 */
+#define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */
+#define DSI_FIR1_FEOTPE_Pos           (6U)
+#define DSI_FIR1_FEOTPE_Msk           (0x1UL << DSI_FIR1_FEOTPE_Pos)           /*!< 0x00000040 */
+#define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */
+#define DSI_FIR1_FLPWRE_Pos           (7U)
+#define DSI_FIR1_FLPWRE_Msk           (0x1UL << DSI_FIR1_FLPWRE_Pos)           /*!< 0x00000080 */
+#define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */
+#define DSI_FIR1_FGCWRE_Pos           (8U)
+#define DSI_FIR1_FGCWRE_Msk           (0x1UL << DSI_FIR1_FGCWRE_Pos)           /*!< 0x00000100 */
+#define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */
+#define DSI_FIR1_FGPWRE_Pos           (9U)
+#define DSI_FIR1_FGPWRE_Msk           (0x1UL << DSI_FIR1_FGPWRE_Pos)           /*!< 0x00000200 */
+#define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */
+#define DSI_FIR1_FGPTXE_Pos           (10U)
+#define DSI_FIR1_FGPTXE_Msk           (0x1UL << DSI_FIR1_FGPTXE_Pos)           /*!< 0x00000400 */
+#define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */
+#define DSI_FIR1_FGPRDE_Pos           (11U)
+#define DSI_FIR1_FGPRDE_Msk           (0x1UL << DSI_FIR1_FGPRDE_Pos)           /*!< 0x00000800 */
+#define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */
+#define DSI_FIR1_FGPRXE_Pos           (12U)
+#define DSI_FIR1_FGPRXE_Msk           (0x1UL << DSI_FIR1_FGPRXE_Pos)           /*!< 0x00001000 */
+#define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */
+
+/*******************  Bit definition for DSI_VSCR register  ***************/
+#define DSI_VSCR_EN_Pos               (0U)
+#define DSI_VSCR_EN_Msk               (0x1UL << DSI_VSCR_EN_Pos)               /*!< 0x00000001 */
+#define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */
+#define DSI_VSCR_UR_Pos               (8U)
+#define DSI_VSCR_UR_Msk               (0x1UL << DSI_VSCR_UR_Pos)               /*!< 0x00000100 */
+#define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */
+
+/*******************  Bit definition for DSI_LCVCIDR register  ************/
+#define DSI_LCVCIDR_VCID_Pos          (0U)
+#define DSI_LCVCIDR_VCID_Msk          (0x3UL << DSI_LCVCIDR_VCID_Pos)          /*!< 0x00000003 */
+#define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */
+#define DSI_LCVCIDR_VCID0_Pos         (0U)
+#define DSI_LCVCIDR_VCID0_Msk         (0x1UL << DSI_LCVCIDR_VCID0_Pos)         /*!< 0x00000001 */
+#define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk
+#define DSI_LCVCIDR_VCID1_Pos         (1U)
+#define DSI_LCVCIDR_VCID1_Msk         (0x1UL << DSI_LCVCIDR_VCID1_Pos)         /*!< 0x00000002 */
+#define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk
+
+/*******************  Bit definition for DSI_LCCCR register  **************/
+#define DSI_LCCCR_COLC_Pos            (0U)
+#define DSI_LCCCR_COLC_Msk            (0xFUL << DSI_LCCCR_COLC_Pos)            /*!< 0x0000000F */
+#define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */
+#define DSI_LCCCR_COLC0_Pos           (0U)
+#define DSI_LCCCR_COLC0_Msk           (0x1UL << DSI_LCCCR_COLC0_Pos)           /*!< 0x00000001 */
+#define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk
+#define DSI_LCCCR_COLC1_Pos           (1U)
+#define DSI_LCCCR_COLC1_Msk           (0x1UL << DSI_LCCCR_COLC1_Pos)           /*!< 0x00000002 */
+#define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk
+#define DSI_LCCCR_COLC2_Pos           (2U)
+#define DSI_LCCCR_COLC2_Msk           (0x1UL << DSI_LCCCR_COLC2_Pos)           /*!< 0x00000004 */
+#define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk
+#define DSI_LCCCR_COLC3_Pos           (3U)
+#define DSI_LCCCR_COLC3_Msk           (0x1UL << DSI_LCCCR_COLC3_Pos)           /*!< 0x00000008 */
+#define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk
+
+#define DSI_LCCCR_LPE_Pos             (8U)
+#define DSI_LCCCR_LPE_Msk             (0x1UL << DSI_LCCCR_LPE_Pos)             /*!< 0x00000100 */
+#define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */
+
+/*******************  Bit definition for DSI_LPMCCR register  *************/
+#define DSI_LPMCCR_VLPSIZE_Pos        (0U)
+#define DSI_LPMCCR_VLPSIZE_Msk        (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)       /*!< 0x000000FF */
+#define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */
+#define DSI_LPMCCR_VLPSIZE0_Pos       (0U)
+#define DSI_LPMCCR_VLPSIZE0_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)       /*!< 0x00000001 */
+#define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk
+#define DSI_LPMCCR_VLPSIZE1_Pos       (1U)
+#define DSI_LPMCCR_VLPSIZE1_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)       /*!< 0x00000002 */
+#define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk
+#define DSI_LPMCCR_VLPSIZE2_Pos       (2U)
+#define DSI_LPMCCR_VLPSIZE2_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)       /*!< 0x00000004 */
+#define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk
+#define DSI_LPMCCR_VLPSIZE3_Pos       (3U)
+#define DSI_LPMCCR_VLPSIZE3_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)       /*!< 0x00000008 */
+#define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk
+#define DSI_LPMCCR_VLPSIZE4_Pos       (4U)
+#define DSI_LPMCCR_VLPSIZE4_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)       /*!< 0x00000010 */
+#define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk
+#define DSI_LPMCCR_VLPSIZE5_Pos       (5U)
+#define DSI_LPMCCR_VLPSIZE5_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)       /*!< 0x00000020 */
+#define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk
+#define DSI_LPMCCR_VLPSIZE6_Pos       (6U)
+#define DSI_LPMCCR_VLPSIZE6_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)       /*!< 0x00000040 */
+#define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk
+#define DSI_LPMCCR_VLPSIZE7_Pos       (7U)
+#define DSI_LPMCCR_VLPSIZE7_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)       /*!< 0x00000080 */
+#define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk
+
+#define DSI_LPMCCR_LPSIZE_Pos         (16U)
+#define DSI_LPMCCR_LPSIZE_Msk         (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)        /*!< 0x00FF0000 */
+#define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */
+#define DSI_LPMCCR_LPSIZE0_Pos        (16U)
+#define DSI_LPMCCR_LPSIZE0_Msk        (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)        /*!< 0x00010000 */
+#define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk
+#define DSI_LPMCCR_LPSIZE1_Pos        (17U)
+#define DSI_LPMCCR_LPSIZE1_Msk        (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)        /*!< 0x00020000 */
+#define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk
+#define DSI_LPMCCR_LPSIZE2_Pos        (18U)
+#define DSI_LPMCCR_LPSIZE2_Msk        (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)        /*!< 0x00040000 */
+#define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk
+#define DSI_LPMCCR_LPSIZE3_Pos        (19U)
+#define DSI_LPMCCR_LPSIZE3_Msk        (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)        /*!< 0x00080000 */
+#define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk
+#define DSI_LPMCCR_LPSIZE4_Pos        (20U)
+#define DSI_LPMCCR_LPSIZE4_Msk        (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)        /*!< 0x00100000 */
+#define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk
+#define DSI_LPMCCR_LPSIZE5_Pos        (21U)
+#define DSI_LPMCCR_LPSIZE5_Msk        (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)        /*!< 0x00200000 */
+#define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk
+#define DSI_LPMCCR_LPSIZE6_Pos        (22U)
+#define DSI_LPMCCR_LPSIZE6_Msk        (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)        /*!< 0x00400000 */
+#define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk
+#define DSI_LPMCCR_LPSIZE7_Pos        (23U)
+#define DSI_LPMCCR_LPSIZE7_Msk        (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)        /*!< 0x00800000 */
+#define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk
+
+/*******************  Bit definition for DSI_VMCCR register  **************/
+#define DSI_VMCCR_VMT_Pos             (0U)
+#define DSI_VMCCR_VMT_Msk             (0x3UL << DSI_VMCCR_VMT_Pos)             /*!< 0x00000003 */
+#define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */
+#define DSI_VMCCR_VMT0_Pos            (0U)
+#define DSI_VMCCR_VMT0_Msk            (0x1UL << DSI_VMCCR_VMT0_Pos)            /*!< 0x00000001 */
+#define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk
+#define DSI_VMCCR_VMT1_Pos            (1U)
+#define DSI_VMCCR_VMT1_Msk            (0x1UL << DSI_VMCCR_VMT1_Pos)            /*!< 0x00000002 */
+#define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk
+
+#define DSI_VMCCR_LPVSAE_Pos          (8U)
+#define DSI_VMCCR_LPVSAE_Msk          (0x1UL << DSI_VMCCR_LPVSAE_Pos)          /*!< 0x00000100 */
+#define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */
+#define DSI_VMCCR_LPVBPE_Pos          (9U)
+#define DSI_VMCCR_LPVBPE_Msk          (0x1UL << DSI_VMCCR_LPVBPE_Pos)          /*!< 0x00000200 */
+#define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */
+#define DSI_VMCCR_LPVFPE_Pos          (10U)
+#define DSI_VMCCR_LPVFPE_Msk          (0x1UL << DSI_VMCCR_LPVFPE_Pos)          /*!< 0x00000400 */
+#define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */
+#define DSI_VMCCR_LPVAE_Pos           (11U)
+#define DSI_VMCCR_LPVAE_Msk           (0x1UL << DSI_VMCCR_LPVAE_Pos)           /*!< 0x00000800 */
+#define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */
+#define DSI_VMCCR_LPHBPE_Pos          (12U)
+#define DSI_VMCCR_LPHBPE_Msk          (0x1UL << DSI_VMCCR_LPHBPE_Pos)          /*!< 0x00001000 */
+#define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */
+#define DSI_VMCCR_LPHFE_Pos           (13U)
+#define DSI_VMCCR_LPHFE_Msk           (0x1UL << DSI_VMCCR_LPHFE_Pos)           /*!< 0x00002000 */
+#define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */
+#define DSI_VMCCR_FBTAAE_Pos          (14U)
+#define DSI_VMCCR_FBTAAE_Msk          (0x1UL << DSI_VMCCR_FBTAAE_Pos)          /*!< 0x00004000 */
+#define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */
+#define DSI_VMCCR_LPCE_Pos            (15U)
+#define DSI_VMCCR_LPCE_Msk            (0x1UL << DSI_VMCCR_LPCE_Pos)            /*!< 0x00008000 */
+#define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */
+
+/*******************  Bit definition for DSI_VPCCR register  **************/
+#define DSI_VPCCR_VPSIZE_Pos          (0U)
+#define DSI_VPCCR_VPSIZE_Msk          (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)       /*!< 0x00003FFF */
+#define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */
+#define DSI_VPCCR_VPSIZE0_Pos         (0U)
+#define DSI_VPCCR_VPSIZE0_Msk         (0x1UL << DSI_VPCCR_VPSIZE0_Pos)         /*!< 0x00000001 */
+#define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk
+#define DSI_VPCCR_VPSIZE1_Pos         (1U)
+#define DSI_VPCCR_VPSIZE1_Msk         (0x1UL << DSI_VPCCR_VPSIZE1_Pos)         /*!< 0x00000002 */
+#define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk
+#define DSI_VPCCR_VPSIZE2_Pos         (2U)
+#define DSI_VPCCR_VPSIZE2_Msk         (0x1UL << DSI_VPCCR_VPSIZE2_Pos)         /*!< 0x00000004 */
+#define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk
+#define DSI_VPCCR_VPSIZE3_Pos         (3U)
+#define DSI_VPCCR_VPSIZE3_Msk         (0x1UL << DSI_VPCCR_VPSIZE3_Pos)         /*!< 0x00000008 */
+#define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk
+#define DSI_VPCCR_VPSIZE4_Pos         (4U)
+#define DSI_VPCCR_VPSIZE4_Msk         (0x1UL << DSI_VPCCR_VPSIZE4_Pos)         /*!< 0x00000010 */
+#define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk
+#define DSI_VPCCR_VPSIZE5_Pos         (5U)
+#define DSI_VPCCR_VPSIZE5_Msk         (0x1UL << DSI_VPCCR_VPSIZE5_Pos)         /*!< 0x00000020 */
+#define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk
+#define DSI_VPCCR_VPSIZE6_Pos         (6U)
+#define DSI_VPCCR_VPSIZE6_Msk         (0x1UL << DSI_VPCCR_VPSIZE6_Pos)         /*!< 0x00000040 */
+#define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk
+#define DSI_VPCCR_VPSIZE7_Pos         (7U)
+#define DSI_VPCCR_VPSIZE7_Msk         (0x1UL << DSI_VPCCR_VPSIZE7_Pos)         /*!< 0x00000080 */
+#define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk
+#define DSI_VPCCR_VPSIZE8_Pos         (8U)
+#define DSI_VPCCR_VPSIZE8_Msk         (0x1UL << DSI_VPCCR_VPSIZE8_Pos)         /*!< 0x00000100 */
+#define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk
+#define DSI_VPCCR_VPSIZE9_Pos         (9U)
+#define DSI_VPCCR_VPSIZE9_Msk         (0x1UL << DSI_VPCCR_VPSIZE9_Pos)         /*!< 0x00000200 */
+#define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk
+#define DSI_VPCCR_VPSIZE10_Pos        (10U)
+#define DSI_VPCCR_VPSIZE10_Msk        (0x1UL << DSI_VPCCR_VPSIZE10_Pos)        /*!< 0x00000400 */
+#define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk
+#define DSI_VPCCR_VPSIZE11_Pos        (11U)
+#define DSI_VPCCR_VPSIZE11_Msk        (0x1UL << DSI_VPCCR_VPSIZE11_Pos)        /*!< 0x00000800 */
+#define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk
+#define DSI_VPCCR_VPSIZE12_Pos        (12U)
+#define DSI_VPCCR_VPSIZE12_Msk        (0x1UL << DSI_VPCCR_VPSIZE12_Pos)        /*!< 0x00001000 */
+#define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk
+#define DSI_VPCCR_VPSIZE13_Pos        (13U)
+#define DSI_VPCCR_VPSIZE13_Msk        (0x1UL << DSI_VPCCR_VPSIZE13_Pos)        /*!< 0x00002000 */
+#define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk
+
+/*******************  Bit definition for DSI_VCCCR register  **************/
+#define DSI_VCCCR_NUMC_Pos            (0U)
+#define DSI_VCCCR_NUMC_Msk            (0x1FFFUL << DSI_VCCCR_NUMC_Pos)         /*!< 0x00001FFF */
+#define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */
+#define DSI_VCCCR_NUMC0_Pos           (0U)
+#define DSI_VCCCR_NUMC0_Msk           (0x1UL << DSI_VCCCR_NUMC0_Pos)           /*!< 0x00000001 */
+#define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk
+#define DSI_VCCCR_NUMC1_Pos           (1U)
+#define DSI_VCCCR_NUMC1_Msk           (0x1UL << DSI_VCCCR_NUMC1_Pos)           /*!< 0x00000002 */
+#define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk
+#define DSI_VCCCR_NUMC2_Pos           (2U)
+#define DSI_VCCCR_NUMC2_Msk           (0x1UL << DSI_VCCCR_NUMC2_Pos)           /*!< 0x00000004 */
+#define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk
+#define DSI_VCCCR_NUMC3_Pos           (3U)
+#define DSI_VCCCR_NUMC3_Msk           (0x1UL << DSI_VCCCR_NUMC3_Pos)           /*!< 0x00000008 */
+#define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk
+#define DSI_VCCCR_NUMC4_Pos           (4U)
+#define DSI_VCCCR_NUMC4_Msk           (0x1UL << DSI_VCCCR_NUMC4_Pos)           /*!< 0x00000010 */
+#define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk
+#define DSI_VCCCR_NUMC5_Pos           (5U)
+#define DSI_VCCCR_NUMC5_Msk           (0x1UL << DSI_VCCCR_NUMC5_Pos)           /*!< 0x00000020 */
+#define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk
+#define DSI_VCCCR_NUMC6_Pos           (6U)
+#define DSI_VCCCR_NUMC6_Msk           (0x1UL << DSI_VCCCR_NUMC6_Pos)           /*!< 0x00000040 */
+#define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk
+#define DSI_VCCCR_NUMC7_Pos           (7U)
+#define DSI_VCCCR_NUMC7_Msk           (0x1UL << DSI_VCCCR_NUMC7_Pos)           /*!< 0x00000080 */
+#define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk
+#define DSI_VCCCR_NUMC8_Pos           (8U)
+#define DSI_VCCCR_NUMC8_Msk           (0x1UL << DSI_VCCCR_NUMC8_Pos)           /*!< 0x00000100 */
+#define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk
+#define DSI_VCCCR_NUMC9_Pos           (9U)
+#define DSI_VCCCR_NUMC9_Msk           (0x1UL << DSI_VCCCR_NUMC9_Pos)           /*!< 0x00000200 */
+#define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk
+#define DSI_VCCCR_NUMC10_Pos          (10U)
+#define DSI_VCCCR_NUMC10_Msk          (0x1UL << DSI_VCCCR_NUMC10_Pos)          /*!< 0x00000400 */
+#define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk
+#define DSI_VCCCR_NUMC11_Pos          (11U)
+#define DSI_VCCCR_NUMC11_Msk          (0x1UL << DSI_VCCCR_NUMC11_Pos)          /*!< 0x00000800 */
+#define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk
+#define DSI_VCCCR_NUMC12_Pos          (12U)
+#define DSI_VCCCR_NUMC12_Msk          (0x1UL << DSI_VCCCR_NUMC12_Pos)          /*!< 0x00001000 */
+#define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk
+
+/*******************  Bit definition for DSI_VNPCCR register  *************/
+#define DSI_VNPCCR_NPSIZE_Pos         (0U)
+#define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)      /*!< 0x00001FFF */
+#define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */
+#define DSI_VNPCCR_NPSIZE0_Pos        (0U)
+#define DSI_VNPCCR_NPSIZE0_Msk        (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)        /*!< 0x00000001 */
+#define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk
+#define DSI_VNPCCR_NPSIZE1_Pos        (1U)
+#define DSI_VNPCCR_NPSIZE1_Msk        (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)        /*!< 0x00000002 */
+#define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk
+#define DSI_VNPCCR_NPSIZE2_Pos        (2U)
+#define DSI_VNPCCR_NPSIZE2_Msk        (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)        /*!< 0x00000004 */
+#define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk
+#define DSI_VNPCCR_NPSIZE3_Pos        (3U)
+#define DSI_VNPCCR_NPSIZE3_Msk        (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)        /*!< 0x00000008 */
+#define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk
+#define DSI_VNPCCR_NPSIZE4_Pos        (4U)
+#define DSI_VNPCCR_NPSIZE4_Msk        (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)        /*!< 0x00000010 */
+#define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk
+#define DSI_VNPCCR_NPSIZE5_Pos        (5U)
+#define DSI_VNPCCR_NPSIZE5_Msk        (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)        /*!< 0x00000020 */
+#define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk
+#define DSI_VNPCCR_NPSIZE6_Pos        (6U)
+#define DSI_VNPCCR_NPSIZE6_Msk        (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)        /*!< 0x00000040 */
+#define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk
+#define DSI_VNPCCR_NPSIZE7_Pos        (7U)
+#define DSI_VNPCCR_NPSIZE7_Msk        (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)        /*!< 0x00000080 */
+#define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk
+#define DSI_VNPCCR_NPSIZE8_Pos        (8U)
+#define DSI_VNPCCR_NPSIZE8_Msk        (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)        /*!< 0x00000100 */
+#define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk
+#define DSI_VNPCCR_NPSIZE9_Pos        (9U)
+#define DSI_VNPCCR_NPSIZE9_Msk        (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)        /*!< 0x00000200 */
+#define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk
+#define DSI_VNPCCR_NPSIZE10_Pos       (10U)
+#define DSI_VNPCCR_NPSIZE10_Msk       (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)       /*!< 0x00000400 */
+#define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk
+#define DSI_VNPCCR_NPSIZE11_Pos       (11U)
+#define DSI_VNPCCR_NPSIZE11_Msk       (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)       /*!< 0x00000800 */
+#define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk
+#define DSI_VNPCCR_NPSIZE12_Pos       (12U)
+#define DSI_VNPCCR_NPSIZE12_Msk       (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)       /*!< 0x00001000 */
+#define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk
+
+/*******************  Bit definition for DSI_VHSACCR register  ************/
+#define DSI_VHSACCR_HSA_Pos           (0U)
+#define DSI_VHSACCR_HSA_Msk           (0xFFFUL << DSI_VHSACCR_HSA_Pos)         /*!< 0x00000FFF */
+#define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */
+#define DSI_VHSACCR_HSA0_Pos          (0U)
+#define DSI_VHSACCR_HSA0_Msk          (0x1UL << DSI_VHSACCR_HSA0_Pos)          /*!< 0x00000001 */
+#define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk
+#define DSI_VHSACCR_HSA1_Pos          (1U)
+#define DSI_VHSACCR_HSA1_Msk          (0x1UL << DSI_VHSACCR_HSA1_Pos)          /*!< 0x00000002 */
+#define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk
+#define DSI_VHSACCR_HSA2_Pos          (2U)
+#define DSI_VHSACCR_HSA2_Msk          (0x1UL << DSI_VHSACCR_HSA2_Pos)          /*!< 0x00000004 */
+#define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk
+#define DSI_VHSACCR_HSA3_Pos          (3U)
+#define DSI_VHSACCR_HSA3_Msk          (0x1UL << DSI_VHSACCR_HSA3_Pos)          /*!< 0x00000008 */
+#define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk
+#define DSI_VHSACCR_HSA4_Pos          (4U)
+#define DSI_VHSACCR_HSA4_Msk          (0x1UL << DSI_VHSACCR_HSA4_Pos)          /*!< 0x00000010 */
+#define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk
+#define DSI_VHSACCR_HSA5_Pos          (5U)
+#define DSI_VHSACCR_HSA5_Msk          (0x1UL << DSI_VHSACCR_HSA5_Pos)          /*!< 0x00000020 */
+#define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk
+#define DSI_VHSACCR_HSA6_Pos          (6U)
+#define DSI_VHSACCR_HSA6_Msk          (0x1UL << DSI_VHSACCR_HSA6_Pos)          /*!< 0x00000040 */
+#define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk
+#define DSI_VHSACCR_HSA7_Pos          (7U)
+#define DSI_VHSACCR_HSA7_Msk          (0x1UL << DSI_VHSACCR_HSA7_Pos)          /*!< 0x00000080 */
+#define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk
+#define DSI_VHSACCR_HSA8_Pos          (8U)
+#define DSI_VHSACCR_HSA8_Msk          (0x1UL << DSI_VHSACCR_HSA8_Pos)          /*!< 0x00000100 */
+#define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk
+#define DSI_VHSACCR_HSA9_Pos          (9U)
+#define DSI_VHSACCR_HSA9_Msk          (0x1UL << DSI_VHSACCR_HSA9_Pos)          /*!< 0x00000200 */
+#define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk
+#define DSI_VHSACCR_HSA10_Pos         (10U)
+#define DSI_VHSACCR_HSA10_Msk         (0x1UL << DSI_VHSACCR_HSA10_Pos)         /*!< 0x00000400 */
+#define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk
+#define DSI_VHSACCR_HSA11_Pos         (11U)
+#define DSI_VHSACCR_HSA11_Msk         (0x1UL << DSI_VHSACCR_HSA11_Pos)         /*!< 0x00000800 */
+#define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk
+
+/*******************  Bit definition for DSI_VHBPCCR register  ************/
+#define DSI_VHBPCCR_HBP_Pos           (0U)
+#define DSI_VHBPCCR_HBP_Msk           (0xFFFUL << DSI_VHBPCCR_HBP_Pos)         /*!< 0x00000FFF */
+#define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */
+#define DSI_VHBPCCR_HBP0_Pos          (0U)
+#define DSI_VHBPCCR_HBP0_Msk          (0x1UL << DSI_VHBPCCR_HBP0_Pos)          /*!< 0x00000001 */
+#define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk
+#define DSI_VHBPCCR_HBP1_Pos          (1U)
+#define DSI_VHBPCCR_HBP1_Msk          (0x1UL << DSI_VHBPCCR_HBP1_Pos)          /*!< 0x00000002 */
+#define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk
+#define DSI_VHBPCCR_HBP2_Pos          (2U)
+#define DSI_VHBPCCR_HBP2_Msk          (0x1UL << DSI_VHBPCCR_HBP2_Pos)          /*!< 0x00000004 */
+#define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk
+#define DSI_VHBPCCR_HBP3_Pos          (3U)
+#define DSI_VHBPCCR_HBP3_Msk          (0x1UL << DSI_VHBPCCR_HBP3_Pos)          /*!< 0x00000008 */
+#define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk
+#define DSI_VHBPCCR_HBP4_Pos          (4U)
+#define DSI_VHBPCCR_HBP4_Msk          (0x1UL << DSI_VHBPCCR_HBP4_Pos)          /*!< 0x00000010 */
+#define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk
+#define DSI_VHBPCCR_HBP5_Pos          (5U)
+#define DSI_VHBPCCR_HBP5_Msk          (0x1UL << DSI_VHBPCCR_HBP5_Pos)          /*!< 0x00000020 */
+#define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk
+#define DSI_VHBPCCR_HBP6_Pos          (6U)
+#define DSI_VHBPCCR_HBP6_Msk          (0x1UL << DSI_VHBPCCR_HBP6_Pos)          /*!< 0x00000040 */
+#define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk
+#define DSI_VHBPCCR_HBP7_Pos          (7U)
+#define DSI_VHBPCCR_HBP7_Msk          (0x1UL << DSI_VHBPCCR_HBP7_Pos)          /*!< 0x00000080 */
+#define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk
+#define DSI_VHBPCCR_HBP8_Pos          (8U)
+#define DSI_VHBPCCR_HBP8_Msk          (0x1UL << DSI_VHBPCCR_HBP8_Pos)          /*!< 0x00000100 */
+#define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk
+#define DSI_VHBPCCR_HBP9_Pos          (9U)
+#define DSI_VHBPCCR_HBP9_Msk          (0x1UL << DSI_VHBPCCR_HBP9_Pos)          /*!< 0x00000200 */
+#define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk
+#define DSI_VHBPCCR_HBP10_Pos         (10U)
+#define DSI_VHBPCCR_HBP10_Msk         (0x1UL << DSI_VHBPCCR_HBP10_Pos)         /*!< 0x00000400 */
+#define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk
+#define DSI_VHBPCCR_HBP11_Pos         (11U)
+#define DSI_VHBPCCR_HBP11_Msk         (0x1UL << DSI_VHBPCCR_HBP11_Pos)         /*!< 0x00000800 */
+#define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk
+
+/*******************  Bit definition for DSI_VLCCR register  **************/
+#define DSI_VLCCR_HLINE_Pos           (0U)
+#define DSI_VLCCR_HLINE_Msk           (0x7FFFUL << DSI_VLCCR_HLINE_Pos)        /*!< 0x00007FFF */
+#define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */
+#define DSI_VLCCR_HLINE0_Pos          (0U)
+#define DSI_VLCCR_HLINE0_Msk          (0x1UL << DSI_VLCCR_HLINE0_Pos)          /*!< 0x00000001 */
+#define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk
+#define DSI_VLCCR_HLINE1_Pos          (1U)
+#define DSI_VLCCR_HLINE1_Msk          (0x1UL << DSI_VLCCR_HLINE1_Pos)          /*!< 0x00000002 */
+#define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk
+#define DSI_VLCCR_HLINE2_Pos          (2U)
+#define DSI_VLCCR_HLINE2_Msk          (0x1UL << DSI_VLCCR_HLINE2_Pos)          /*!< 0x00000004 */
+#define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk
+#define DSI_VLCCR_HLINE3_Pos          (3U)
+#define DSI_VLCCR_HLINE3_Msk          (0x1UL << DSI_VLCCR_HLINE3_Pos)          /*!< 0x00000008 */
+#define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk
+#define DSI_VLCCR_HLINE4_Pos          (4U)
+#define DSI_VLCCR_HLINE4_Msk          (0x1UL << DSI_VLCCR_HLINE4_Pos)          /*!< 0x00000010 */
+#define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk
+#define DSI_VLCCR_HLINE5_Pos          (5U)
+#define DSI_VLCCR_HLINE5_Msk          (0x1UL << DSI_VLCCR_HLINE5_Pos)          /*!< 0x00000020 */
+#define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk
+#define DSI_VLCCR_HLINE6_Pos          (6U)
+#define DSI_VLCCR_HLINE6_Msk          (0x1UL << DSI_VLCCR_HLINE6_Pos)          /*!< 0x00000040 */
+#define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk
+#define DSI_VLCCR_HLINE7_Pos          (7U)
+#define DSI_VLCCR_HLINE7_Msk          (0x1UL << DSI_VLCCR_HLINE7_Pos)          /*!< 0x00000080 */
+#define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk
+#define DSI_VLCCR_HLINE8_Pos          (8U)
+#define DSI_VLCCR_HLINE8_Msk          (0x1UL << DSI_VLCCR_HLINE8_Pos)          /*!< 0x00000100 */
+#define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk
+#define DSI_VLCCR_HLINE9_Pos          (9U)
+#define DSI_VLCCR_HLINE9_Msk          (0x1UL << DSI_VLCCR_HLINE9_Pos)          /*!< 0x00000200 */
+#define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk
+#define DSI_VLCCR_HLINE10_Pos         (10U)
+#define DSI_VLCCR_HLINE10_Msk         (0x1UL << DSI_VLCCR_HLINE10_Pos)         /*!< 0x00000400 */
+#define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk
+#define DSI_VLCCR_HLINE11_Pos         (11U)
+#define DSI_VLCCR_HLINE11_Msk         (0x1UL << DSI_VLCCR_HLINE11_Pos)         /*!< 0x00000800 */
+#define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk
+#define DSI_VLCCR_HLINE12_Pos         (12U)
+#define DSI_VLCCR_HLINE12_Msk         (0x1UL << DSI_VLCCR_HLINE12_Pos)         /*!< 0x00001000 */
+#define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk
+#define DSI_VLCCR_HLINE13_Pos         (13U)
+#define DSI_VLCCR_HLINE13_Msk         (0x1UL << DSI_VLCCR_HLINE13_Pos)         /*!< 0x00002000 */
+#define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk
+#define DSI_VLCCR_HLINE14_Pos         (14U)
+#define DSI_VLCCR_HLINE14_Msk         (0x1UL << DSI_VLCCR_HLINE14_Pos)         /*!< 0x00004000 */
+#define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk
+
+/*******************  Bit definition for DSI_VVSACCR register  ***************/
+#define DSI_VVSACCR_VSA_Pos           (0U)
+#define DSI_VVSACCR_VSA_Msk           (0x3FFUL << DSI_VVSACCR_VSA_Pos)         /*!< 0x000003FF */
+#define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */
+#define DSI_VVSACCR_VSA0_Pos          (0U)
+#define DSI_VVSACCR_VSA0_Msk          (0x1UL << DSI_VVSACCR_VSA0_Pos)          /*!< 0x00000001 */
+#define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk
+#define DSI_VVSACCR_VSA1_Pos          (1U)
+#define DSI_VVSACCR_VSA1_Msk          (0x1UL << DSI_VVSACCR_VSA1_Pos)          /*!< 0x00000002 */
+#define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk
+#define DSI_VVSACCR_VSA2_Pos          (2U)
+#define DSI_VVSACCR_VSA2_Msk          (0x1UL << DSI_VVSACCR_VSA2_Pos)          /*!< 0x00000004 */
+#define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk
+#define DSI_VVSACCR_VSA3_Pos          (3U)
+#define DSI_VVSACCR_VSA3_Msk          (0x1UL << DSI_VVSACCR_VSA3_Pos)          /*!< 0x00000008 */
+#define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk
+#define DSI_VVSACCR_VSA4_Pos          (4U)
+#define DSI_VVSACCR_VSA4_Msk          (0x1UL << DSI_VVSACCR_VSA4_Pos)          /*!< 0x00000010 */
+#define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk
+#define DSI_VVSACCR_VSA5_Pos          (5U)
+#define DSI_VVSACCR_VSA5_Msk          (0x1UL << DSI_VVSACCR_VSA5_Pos)          /*!< 0x00000020 */
+#define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk
+#define DSI_VVSACCR_VSA6_Pos          (6U)
+#define DSI_VVSACCR_VSA6_Msk          (0x1UL << DSI_VVSACCR_VSA6_Pos)          /*!< 0x00000040 */
+#define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk
+#define DSI_VVSACCR_VSA7_Pos          (7U)
+#define DSI_VVSACCR_VSA7_Msk          (0x1UL << DSI_VVSACCR_VSA7_Pos)          /*!< 0x00000080 */
+#define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk
+#define DSI_VVSACCR_VSA8_Pos          (8U)
+#define DSI_VVSACCR_VSA8_Msk          (0x1UL << DSI_VVSACCR_VSA8_Pos)          /*!< 0x00000100 */
+#define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk
+#define DSI_VVSACCR_VSA9_Pos          (9U)
+#define DSI_VVSACCR_VSA9_Msk          (0x1UL << DSI_VVSACCR_VSA9_Pos)          /*!< 0x00000200 */
+#define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk
+
+/*******************  Bit definition for DSI_VVBPCCR register  ************/
+#define DSI_VVBPCCR_VBP_Pos           (0U)
+#define DSI_VVBPCCR_VBP_Msk           (0x3FFUL << DSI_VVBPCCR_VBP_Pos)         /*!< 0x000003FF */
+#define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */
+#define DSI_VVBPCCR_VBP0_Pos          (0U)
+#define DSI_VVBPCCR_VBP0_Msk          (0x1UL << DSI_VVBPCCR_VBP0_Pos)          /*!< 0x00000001 */
+#define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk
+#define DSI_VVBPCCR_VBP1_Pos          (1U)
+#define DSI_VVBPCCR_VBP1_Msk          (0x1UL << DSI_VVBPCCR_VBP1_Pos)          /*!< 0x00000002 */
+#define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk
+#define DSI_VVBPCCR_VBP2_Pos          (2U)
+#define DSI_VVBPCCR_VBP2_Msk          (0x1UL << DSI_VVBPCCR_VBP2_Pos)          /*!< 0x00000004 */
+#define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk
+#define DSI_VVBPCCR_VBP3_Pos          (3U)
+#define DSI_VVBPCCR_VBP3_Msk          (0x1UL << DSI_VVBPCCR_VBP3_Pos)          /*!< 0x00000008 */
+#define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk
+#define DSI_VVBPCCR_VBP4_Pos          (4U)
+#define DSI_VVBPCCR_VBP4_Msk          (0x1UL << DSI_VVBPCCR_VBP4_Pos)          /*!< 0x00000010 */
+#define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk
+#define DSI_VVBPCCR_VBP5_Pos          (5U)
+#define DSI_VVBPCCR_VBP5_Msk          (0x1UL << DSI_VVBPCCR_VBP5_Pos)          /*!< 0x00000020 */
+#define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk
+#define DSI_VVBPCCR_VBP6_Pos          (6U)
+#define DSI_VVBPCCR_VBP6_Msk          (0x1UL << DSI_VVBPCCR_VBP6_Pos)          /*!< 0x00000040 */
+#define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk
+#define DSI_VVBPCCR_VBP7_Pos          (7U)
+#define DSI_VVBPCCR_VBP7_Msk          (0x1UL << DSI_VVBPCCR_VBP7_Pos)          /*!< 0x00000080 */
+#define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk
+#define DSI_VVBPCCR_VBP8_Pos          (8U)
+#define DSI_VVBPCCR_VBP8_Msk          (0x1UL << DSI_VVBPCCR_VBP8_Pos)          /*!< 0x00000100 */
+#define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk
+#define DSI_VVBPCCR_VBP9_Pos          (9U)
+#define DSI_VVBPCCR_VBP9_Msk          (0x1UL << DSI_VVBPCCR_VBP9_Pos)          /*!< 0x00000200 */
+#define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk
+
+/*******************  Bit definition for DSI_VVFPCCR register  ************/
+#define DSI_VVFPCCR_VFP_Pos           (0U)
+#define DSI_VVFPCCR_VFP_Msk           (0x3FFUL << DSI_VVFPCCR_VFP_Pos)         /*!< 0x000003FF */
+#define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */
+#define DSI_VVFPCCR_VFP0_Pos          (0U)
+#define DSI_VVFPCCR_VFP0_Msk          (0x1UL << DSI_VVFPCCR_VFP0_Pos)          /*!< 0x00000001 */
+#define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk
+#define DSI_VVFPCCR_VFP1_Pos          (1U)
+#define DSI_VVFPCCR_VFP1_Msk          (0x1UL << DSI_VVFPCCR_VFP1_Pos)          /*!< 0x00000002 */
+#define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk
+#define DSI_VVFPCCR_VFP2_Pos          (2U)
+#define DSI_VVFPCCR_VFP2_Msk          (0x1UL << DSI_VVFPCCR_VFP2_Pos)          /*!< 0x00000004 */
+#define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk
+#define DSI_VVFPCCR_VFP3_Pos          (3U)
+#define DSI_VVFPCCR_VFP3_Msk          (0x1UL << DSI_VVFPCCR_VFP3_Pos)          /*!< 0x00000008 */
+#define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk
+#define DSI_VVFPCCR_VFP4_Pos          (4U)
+#define DSI_VVFPCCR_VFP4_Msk          (0x1UL << DSI_VVFPCCR_VFP4_Pos)          /*!< 0x00000010 */
+#define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk
+#define DSI_VVFPCCR_VFP5_Pos          (5U)
+#define DSI_VVFPCCR_VFP5_Msk          (0x1UL << DSI_VVFPCCR_VFP5_Pos)          /*!< 0x00000020 */
+#define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk
+#define DSI_VVFPCCR_VFP6_Pos          (6U)
+#define DSI_VVFPCCR_VFP6_Msk          (0x1UL << DSI_VVFPCCR_VFP6_Pos)          /*!< 0x00000040 */
+#define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk
+#define DSI_VVFPCCR_VFP7_Pos          (7U)
+#define DSI_VVFPCCR_VFP7_Msk          (0x1UL << DSI_VVFPCCR_VFP7_Pos)          /*!< 0x00000080 */
+#define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk
+#define DSI_VVFPCCR_VFP8_Pos          (8U)
+#define DSI_VVFPCCR_VFP8_Msk          (0x1UL << DSI_VVFPCCR_VFP8_Pos)          /*!< 0x00000100 */
+#define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk
+#define DSI_VVFPCCR_VFP9_Pos          (9U)
+#define DSI_VVFPCCR_VFP9_Msk          (0x1UL << DSI_VVFPCCR_VFP9_Pos)          /*!< 0x00000200 */
+#define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk
+
+/*******************  Bit definition for DSI_VVACCR register  *************/
+#define DSI_VVACCR_VA_Pos             (0U)
+#define DSI_VVACCR_VA_Msk             (0x3FFFUL << DSI_VVACCR_VA_Pos)          /*!< 0x00003FFF */
+#define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */
+#define DSI_VVACCR_VA0_Pos            (0U)
+#define DSI_VVACCR_VA0_Msk            (0x1UL << DSI_VVACCR_VA0_Pos)            /*!< 0x00000001 */
+#define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk
+#define DSI_VVACCR_VA1_Pos            (1U)
+#define DSI_VVACCR_VA1_Msk            (0x1UL << DSI_VVACCR_VA1_Pos)            /*!< 0x00000002 */
+#define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk
+#define DSI_VVACCR_VA2_Pos            (2U)
+#define DSI_VVACCR_VA2_Msk            (0x1UL << DSI_VVACCR_VA2_Pos)            /*!< 0x00000004 */
+#define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk
+#define DSI_VVACCR_VA3_Pos            (3U)
+#define DSI_VVACCR_VA3_Msk            (0x1UL << DSI_VVACCR_VA3_Pos)            /*!< 0x00000008 */
+#define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk
+#define DSI_VVACCR_VA4_Pos            (4U)
+#define DSI_VVACCR_VA4_Msk            (0x1UL << DSI_VVACCR_VA4_Pos)            /*!< 0x00000010 */
+#define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk
+#define DSI_VVACCR_VA5_Pos            (5U)
+#define DSI_VVACCR_VA5_Msk            (0x1UL << DSI_VVACCR_VA5_Pos)            /*!< 0x00000020 */
+#define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk
+#define DSI_VVACCR_VA6_Pos            (6U)
+#define DSI_VVACCR_VA6_Msk            (0x1UL << DSI_VVACCR_VA6_Pos)            /*!< 0x00000040 */
+#define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk
+#define DSI_VVACCR_VA7_Pos            (7U)
+#define DSI_VVACCR_VA7_Msk            (0x1UL << DSI_VVACCR_VA7_Pos)            /*!< 0x00000080 */
+#define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk
+#define DSI_VVACCR_VA8_Pos            (8U)
+#define DSI_VVACCR_VA8_Msk            (0x1UL << DSI_VVACCR_VA8_Pos)            /*!< 0x00000100 */
+#define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk
+#define DSI_VVACCR_VA9_Pos            (9U)
+#define DSI_VVACCR_VA9_Msk            (0x1UL << DSI_VVACCR_VA9_Pos)            /*!< 0x00000200 */
+#define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk
+#define DSI_VVACCR_VA10_Pos           (10U)
+#define DSI_VVACCR_VA10_Msk           (0x1UL << DSI_VVACCR_VA10_Pos)           /*!< 0x00000400 */
+#define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk
+#define DSI_VVACCR_VA11_Pos           (11U)
+#define DSI_VVACCR_VA11_Msk           (0x1UL << DSI_VVACCR_VA11_Pos)           /*!< 0x00000800 */
+#define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk
+#define DSI_VVACCR_VA12_Pos           (12U)
+#define DSI_VVACCR_VA12_Msk           (0x1UL << DSI_VVACCR_VA12_Pos)           /*!< 0x00001000 */
+#define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk
+#define DSI_VVACCR_VA13_Pos           (13U)
+#define DSI_VVACCR_VA13_Msk           (0x1UL << DSI_VVACCR_VA13_Pos)           /*!< 0x00002000 */
+#define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk
+
+/*******************  Bit definition for DSI_TDCCR register  **************/
+#define DSI_TDCCR_3DM                 (0x00000003U)                  /*!< 3D Mode */
+#define DSI_TDCCR_3DM0                (0x00000001U)
+#define DSI_TDCCR_3DM1                (0x00000002U)
+
+#define DSI_TDCCR_3DF                 (0x0000000CU)                  /*!< 3D Format */
+#define DSI_TDCCR_3DF0                (0x00000004U)
+#define DSI_TDCCR_3DF1                (0x00000008U)
+
+#define DSI_TDCCR_SVS_Pos             (4U)
+#define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)             /*!< 0x00000010 */
+#define DSI_TDCCR_SVS                 DSI_TDCCR_SVS_Msk                        /*!< Second VSYNC */
+#define DSI_TDCCR_RF_Pos              (5U)
+#define DSI_TDCCR_RF_Msk              (0x1UL << DSI_TDCCR_RF_Pos)              /*!< 0x00000020 */
+#define DSI_TDCCR_RF                  DSI_TDCCR_RF_Msk                         /*!< Right First */
+#define DSI_TDCCR_S3DC_Pos            (16U)
+#define DSI_TDCCR_S3DC_Msk            (0x1UL << DSI_TDCCR_S3DC_Pos)            /*!< 0x00010000 */
+#define DSI_TDCCR_S3DC                DSI_TDCCR_S3DC_Msk                       /*!< Send 3D Control */
+
+/*******************  Bit definition for DSI_WCFGR register  ***************/
+#define DSI_WCFGR_DSIM_Pos            (0U)
+#define DSI_WCFGR_DSIM_Msk            (0x1UL << DSI_WCFGR_DSIM_Pos)            /*!< 0x00000001 */
+#define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */
+#define DSI_WCFGR_COLMUX_Pos          (1U)
+#define DSI_WCFGR_COLMUX_Msk          (0x7UL << DSI_WCFGR_COLMUX_Pos)          /*!< 0x0000000E */
+#define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */
+#define DSI_WCFGR_COLMUX0_Pos         (1U)
+#define DSI_WCFGR_COLMUX0_Msk         (0x1UL << DSI_WCFGR_COLMUX0_Pos)         /*!< 0x00000002 */
+#define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk
+#define DSI_WCFGR_COLMUX1_Pos         (2U)
+#define DSI_WCFGR_COLMUX1_Msk         (0x1UL << DSI_WCFGR_COLMUX1_Pos)         /*!< 0x00000004 */
+#define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk
+#define DSI_WCFGR_COLMUX2_Pos         (3U)
+#define DSI_WCFGR_COLMUX2_Msk         (0x1UL << DSI_WCFGR_COLMUX2_Pos)         /*!< 0x00000008 */
+#define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk
+
+#define DSI_WCFGR_TESRC_Pos           (4U)
+#define DSI_WCFGR_TESRC_Msk           (0x1UL << DSI_WCFGR_TESRC_Pos)           /*!< 0x00000010 */
+#define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */
+#define DSI_WCFGR_TEPOL_Pos           (5U)
+#define DSI_WCFGR_TEPOL_Msk           (0x1UL << DSI_WCFGR_TEPOL_Pos)           /*!< 0x00000020 */
+#define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */
+#define DSI_WCFGR_AR_Pos              (6U)
+#define DSI_WCFGR_AR_Msk              (0x1UL << DSI_WCFGR_AR_Pos)              /*!< 0x00000040 */
+#define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */
+#define DSI_WCFGR_VSPOL_Pos           (7U)
+#define DSI_WCFGR_VSPOL_Msk           (0x1UL << DSI_WCFGR_VSPOL_Pos)           /*!< 0x00000080 */
+#define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */
+
+/*******************  Bit definition for DSI_WCR register  *****************/
+#define DSI_WCR_COLM_Pos              (0U)
+#define DSI_WCR_COLM_Msk              (0x1UL << DSI_WCR_COLM_Pos)              /*!< 0x00000001 */
+#define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */
+#define DSI_WCR_SHTDN_Pos             (1U)
+#define DSI_WCR_SHTDN_Msk             (0x1UL << DSI_WCR_SHTDN_Pos)             /*!< 0x00000002 */
+#define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */
+#define DSI_WCR_LTDCEN_Pos            (2U)
+#define DSI_WCR_LTDCEN_Msk            (0x1UL << DSI_WCR_LTDCEN_Pos)            /*!< 0x00000004 */
+#define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */
+#define DSI_WCR_DSIEN_Pos             (3U)
+#define DSI_WCR_DSIEN_Msk             (0x1UL << DSI_WCR_DSIEN_Pos)             /*!< 0x00000008 */
+#define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */
+
+/*******************  Bit definition for DSI_WIER register  ****************/
+#define DSI_WIER_TEIE_Pos             (0U)
+#define DSI_WIER_TEIE_Msk             (0x1UL << DSI_WIER_TEIE_Pos)             /*!< 0x00000001 */
+#define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */
+#define DSI_WIER_ERIE_Pos             (1U)
+#define DSI_WIER_ERIE_Msk             (0x1UL << DSI_WIER_ERIE_Pos)             /*!< 0x00000002 */
+#define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */
+#define DSI_WIER_PLLLIE_Pos           (9U)
+#define DSI_WIER_PLLLIE_Msk           (0x1UL << DSI_WIER_PLLLIE_Pos)           /*!< 0x00000200 */
+#define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */
+#define DSI_WIER_PLLUIE_Pos           (10U)
+#define DSI_WIER_PLLUIE_Msk           (0x1UL << DSI_WIER_PLLUIE_Pos)           /*!< 0x00000400 */
+#define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */
+#define DSI_WIER_RRIE_Pos             (13U)
+#define DSI_WIER_RRIE_Msk             (0x1UL << DSI_WIER_RRIE_Pos)             /*!< 0x00002000 */
+#define DSI_WIER_RRIE                 DSI_WIER_RRIE_Msk                        /*!< Regulator Ready Interrupt Enable */
+
+/*******************  Bit definition for DSI_WISR register  ****************/
+#define DSI_WISR_TEIF_Pos             (0U)
+#define DSI_WISR_TEIF_Msk             (0x1UL << DSI_WISR_TEIF_Pos)             /*!< 0x00000001 */
+#define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */
+#define DSI_WISR_ERIF_Pos             (1U)
+#define DSI_WISR_ERIF_Msk             (0x1UL << DSI_WISR_ERIF_Pos)             /*!< 0x00000002 */
+#define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */
+#define DSI_WISR_BUSY_Pos             (2U)
+#define DSI_WISR_BUSY_Msk             (0x1UL << DSI_WISR_BUSY_Pos)             /*!< 0x00000004 */
+#define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */
+#define DSI_WISR_PLLLS_Pos            (8U)
+#define DSI_WISR_PLLLS_Msk            (0x1UL << DSI_WISR_PLLLS_Pos)            /*!< 0x00000100 */
+#define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */
+#define DSI_WISR_PLLLIF_Pos           (9U)
+#define DSI_WISR_PLLLIF_Msk           (0x1UL << DSI_WISR_PLLLIF_Pos)           /*!< 0x00000200 */
+#define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */
+#define DSI_WISR_PLLUIF_Pos           (10U)
+#define DSI_WISR_PLLUIF_Msk           (0x1UL << DSI_WISR_PLLUIF_Pos)           /*!< 0x00000400 */
+#define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */
+#define DSI_WISR_RRS_Pos              (12U)
+#define DSI_WISR_RRS_Msk              (0x1UL << DSI_WISR_RRS_Pos)              /*!< 0x00001000 */
+#define DSI_WISR_RRS                  DSI_WISR_RRS_Msk                         /*!< Regulator Ready Flag */
+#define DSI_WISR_RRIF_Pos             (13U)
+#define DSI_WISR_RRIF_Msk             (0x1UL << DSI_WISR_RRIF_Pos)             /*!< 0x00002000 */
+#define DSI_WISR_RRIF                 DSI_WISR_RRIF_Msk                        /*!< Regulator Ready Interrupt Flag */
+
+/*******************  Bit definition for DSI_WIFCR register  ***************/
+#define DSI_WIFCR_CTEIF_Pos           (0U)
+#define DSI_WIFCR_CTEIF_Msk           (0x1UL << DSI_WIFCR_CTEIF_Pos)           /*!< 0x00000001 */
+#define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */
+#define DSI_WIFCR_CERIF_Pos           (1U)
+#define DSI_WIFCR_CERIF_Msk           (0x1UL << DSI_WIFCR_CERIF_Pos)           /*!< 0x00000002 */
+#define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */
+#define DSI_WIFCR_CPLLLIF_Pos         (9U)
+#define DSI_WIFCR_CPLLLIF_Msk         (0x1UL << DSI_WIFCR_CPLLLIF_Pos)         /*!< 0x00000200 */
+#define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */
+#define DSI_WIFCR_CPLLUIF_Pos         (10U)
+#define DSI_WIFCR_CPLLUIF_Msk         (0x1UL << DSI_WIFCR_CPLLUIF_Pos)         /*!< 0x00000400 */
+#define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */
+#define DSI_WIFCR_CRRIF_Pos           (13U)
+#define DSI_WIFCR_CRRIF_Msk           (0x1UL << DSI_WIFCR_CRRIF_Pos)           /*!< 0x00002000 */
+#define DSI_WIFCR_CRRIF               DSI_WIFCR_CRRIF_Msk                      /*!< Clear Regulator Ready Interrupt Flag */
+
+/*******************  Bit definition for DSI_WPCR0 register  ***************/
+#define DSI_WPCR0_UIX4_Pos            (0U)
+#define DSI_WPCR0_UIX4_Msk            (0x3FUL << DSI_WPCR0_UIX4_Pos)           /*!< 0x0000003F */
+#define DSI_WPCR0_UIX4                DSI_WPCR0_UIX4_Msk                       /*!< Unit Interval multiplied by 4 */
+#define DSI_WPCR0_UIX4_0              (0x01UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000001 */
+#define DSI_WPCR0_UIX4_1              (0x02UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000002 */
+#define DSI_WPCR0_UIX4_2              (0x04UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000004 */
+#define DSI_WPCR0_UIX4_3              (0x08UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000008 */
+#define DSI_WPCR0_UIX4_4              (0x10UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000010 */
+#define DSI_WPCR0_UIX4_5              (0x20UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000020 */
+
+#define DSI_WPCR0_SWCL_Pos            (6U)
+#define DSI_WPCR0_SWCL_Msk            (0x1UL << DSI_WPCR0_SWCL_Pos)            /*!< 0x00000040 */
+#define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */
+#define DSI_WPCR0_SWDL0_Pos           (7U)
+#define DSI_WPCR0_SWDL0_Msk           (0x1UL << DSI_WPCR0_SWDL0_Pos)           /*!< 0x00000080 */
+#define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */
+#define DSI_WPCR0_SWDL1_Pos           (8U)
+#define DSI_WPCR0_SWDL1_Msk           (0x1UL << DSI_WPCR0_SWDL1_Pos)           /*!< 0x00000100 */
+#define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */
+#define DSI_WPCR0_HSICL_Pos           (9U)
+#define DSI_WPCR0_HSICL_Msk           (0x1UL << DSI_WPCR0_HSICL_Pos)           /*!< 0x00000200 */
+#define DSI_WPCR0_HSICL               DSI_WPCR0_HSICL_Msk                      /*!< Invert the high-speed data signal on clock lane */
+#define DSI_WPCR0_HSIDL0_Pos          (10U)
+#define DSI_WPCR0_HSIDL0_Msk          (0x1UL << DSI_WPCR0_HSIDL0_Pos)          /*!< 0x00000400 */
+#define DSI_WPCR0_HSIDL0              DSI_WPCR0_HSIDL0_Msk                     /*!< Invert the high-speed data signal on lane 1 */
+#define DSI_WPCR0_HSIDL1_Pos          (11U)
+#define DSI_WPCR0_HSIDL1_Msk          (0x1UL << DSI_WPCR0_HSIDL1_Pos)          /*!< 0x00000800 */
+#define DSI_WPCR0_HSIDL1              DSI_WPCR0_HSIDL1_Msk                     /*!< Invert the high-speed data signal on lane 2 */
+#define DSI_WPCR0_FTXSMCL_Pos         (12U)
+#define DSI_WPCR0_FTXSMCL_Msk         (0x1UL << DSI_WPCR0_FTXSMCL_Pos)         /*!< 0x00001000 */
+#define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */
+#define DSI_WPCR0_FTXSMDL_Pos         (13U)
+#define DSI_WPCR0_FTXSMDL_Msk         (0x1UL << DSI_WPCR0_FTXSMDL_Pos)         /*!< 0x00002000 */
+#define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */
+#define DSI_WPCR0_CDOFFDL_Pos         (14U)
+#define DSI_WPCR0_CDOFFDL_Msk         (0x1UL << DSI_WPCR0_CDOFFDL_Pos)         /*!< 0x00004000 */
+#define DSI_WPCR0_CDOFFDL             DSI_WPCR0_CDOFFDL_Msk                    /*!< Contention detection OFF */
+#define DSI_WPCR0_TDDL_Pos            (16U)
+#define DSI_WPCR0_TDDL_Msk            (0x1UL << DSI_WPCR0_TDDL_Pos)            /*!< 0x00010000 */
+#define DSI_WPCR0_TDDL                DSI_WPCR0_TDDL_Msk                       /*!< Turn Disable Data Lanes */
+#define DSI_WPCR0_PDEN_Pos            (18U)
+#define DSI_WPCR0_PDEN_Msk            (0x1UL << DSI_WPCR0_PDEN_Pos)            /*!< 0x00040000 */
+#define DSI_WPCR0_PDEN                DSI_WPCR0_PDEN_Msk                       /*!< Pull-Down Enable */
+#define DSI_WPCR0_TCLKPREPEN_Pos      (19U)
+#define DSI_WPCR0_TCLKPREPEN_Msk      (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)      /*!< 0x00080000 */
+#define DSI_WPCR0_TCLKPREPEN          DSI_WPCR0_TCLKPREPEN_Msk                 /*!< Timer for t-CLKPREP Enable */
+#define DSI_WPCR0_TCLKZEROEN_Pos      (20U)
+#define DSI_WPCR0_TCLKZEROEN_Msk      (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)      /*!< 0x00100000 */
+#define DSI_WPCR0_TCLKZEROEN          DSI_WPCR0_TCLKZEROEN_Msk                 /*!< Timer for t-CLKZERO Enable */
+#define DSI_WPCR0_THSPREPEN_Pos       (21U)
+#define DSI_WPCR0_THSPREPEN_Msk       (0x1UL << DSI_WPCR0_THSPREPEN_Pos)       /*!< 0x00200000 */
+#define DSI_WPCR0_THSPREPEN           DSI_WPCR0_THSPREPEN_Msk                  /*!< Timer for t-HSPREP Enable */
+#define DSI_WPCR0_THSTRAILEN_Pos      (22U)
+#define DSI_WPCR0_THSTRAILEN_Msk      (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)      /*!< 0x00400000 */
+#define DSI_WPCR0_THSTRAILEN          DSI_WPCR0_THSTRAILEN_Msk                 /*!< Timer for t-HSTRAIL Enable */
+#define DSI_WPCR0_THSZEROEN_Pos       (23U)
+#define DSI_WPCR0_THSZEROEN_Msk       (0x1UL << DSI_WPCR0_THSZEROEN_Pos)       /*!< 0x00800000 */
+#define DSI_WPCR0_THSZEROEN           DSI_WPCR0_THSZEROEN_Msk                  /*!< Timer for t-HSZERO Enable */
+#define DSI_WPCR0_TLPXDEN_Pos         (24U)
+#define DSI_WPCR0_TLPXDEN_Msk         (0x1UL << DSI_WPCR0_TLPXDEN_Pos)         /*!< 0x01000000 */
+#define DSI_WPCR0_TLPXDEN             DSI_WPCR0_TLPXDEN_Msk                    /*!< Timer for t-LPXD Enable */
+#define DSI_WPCR0_THSEXITEN_Pos       (25U)
+#define DSI_WPCR0_THSEXITEN_Msk       (0x1UL << DSI_WPCR0_THSEXITEN_Pos)       /*!< 0x02000000 */
+#define DSI_WPCR0_THSEXITEN           DSI_WPCR0_THSEXITEN_Msk                  /*!< Timer for t-HSEXIT Enable */
+#define DSI_WPCR0_TLPXCEN_Pos         (26U)
+#define DSI_WPCR0_TLPXCEN_Msk         (0x1UL << DSI_WPCR0_TLPXCEN_Pos)         /*!< 0x04000000 */
+#define DSI_WPCR0_TLPXCEN             DSI_WPCR0_TLPXCEN_Msk                    /*!< Timer for t-LPXC Enable */
+#define DSI_WPCR0_TCLKPOSTEN_Pos      (27U)
+#define DSI_WPCR0_TCLKPOSTEN_Msk      (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)      /*!< 0x08000000 */
+#define DSI_WPCR0_TCLKPOSTEN          DSI_WPCR0_TCLKPOSTEN_Msk                 /*!< Timer for t-CLKPOST Enable */
+
+/*******************  Bit definition for DSI_WPCR1 register  ***************/
+#define DSI_WPCR1_HSTXDCL_Pos         (0U)
+#define DSI_WPCR1_HSTXDCL_Msk         (0x3UL << DSI_WPCR1_HSTXDCL_Pos)         /*!< 0x00000003 */
+#define DSI_WPCR1_HSTXDCL             DSI_WPCR1_HSTXDCL_Msk                    /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXDCL0_Pos        (0U)
+#define DSI_WPCR1_HSTXDCL0_Msk        (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)        /*!< 0x00000001 */
+#define DSI_WPCR1_HSTXDCL0            DSI_WPCR1_HSTXDCL0_Msk
+#define DSI_WPCR1_HSTXDCL1_Pos        (1U)
+#define DSI_WPCR1_HSTXDCL1_Msk        (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)        /*!< 0x00000002 */
+#define DSI_WPCR1_HSTXDCL1            DSI_WPCR1_HSTXDCL1_Msk
+
+#define DSI_WPCR1_HSTXDDL_Pos         (2U)
+#define DSI_WPCR1_HSTXDDL_Msk         (0x3UL << DSI_WPCR1_HSTXDDL_Pos)         /*!< 0x0000000C */
+#define DSI_WPCR1_HSTXDDL             DSI_WPCR1_HSTXDDL_Msk                    /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXDDL0_Pos        (2U)
+#define DSI_WPCR1_HSTXDDL0_Msk        (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)        /*!< 0x00000004 */
+#define DSI_WPCR1_HSTXDDL0            DSI_WPCR1_HSTXDDL0_Msk
+#define DSI_WPCR1_HSTXDDL1_Pos        (3U)
+#define DSI_WPCR1_HSTXDDL1_Msk        (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)        /*!< 0x00000008 */
+#define DSI_WPCR1_HSTXDDL1            DSI_WPCR1_HSTXDDL1_Msk
+
+#define DSI_WPCR1_LPSRCCL_Pos         (6U)
+#define DSI_WPCR1_LPSRCCL_Msk         (0x3UL << DSI_WPCR1_LPSRCCL_Pos)         /*!< 0x000000C0 */
+#define DSI_WPCR1_LPSRCCL             DSI_WPCR1_LPSRCCL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
+#define DSI_WPCR1_LPSRCCL0_Pos        (6U)
+#define DSI_WPCR1_LPSRCCL0_Msk        (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)        /*!< 0x00000040 */
+#define DSI_WPCR1_LPSRCCL0            DSI_WPCR1_LPSRCCL0_Msk
+#define DSI_WPCR1_LPSRCCL1_Pos        (7U)
+#define DSI_WPCR1_LPSRCCL1_Msk        (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)        /*!< 0x00000080 */
+#define DSI_WPCR1_LPSRCCL1            DSI_WPCR1_LPSRCCL1_Msk
+
+#define DSI_WPCR1_LPSRCDL_Pos         (8U)
+#define DSI_WPCR1_LPSRCDL_Msk         (0x3UL << DSI_WPCR1_LPSRCDL_Pos)         /*!< 0x00000300 */
+#define DSI_WPCR1_LPSRCDL             DSI_WPCR1_LPSRCDL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
+#define DSI_WPCR1_LPSRCDL0_Pos        (8U)
+#define DSI_WPCR1_LPSRCDL0_Msk        (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)        /*!< 0x00000100 */
+#define DSI_WPCR1_LPSRCDL0            DSI_WPCR1_LPSRCDL0_Msk
+#define DSI_WPCR1_LPSRCDL1_Pos        (9U)
+#define DSI_WPCR1_LPSRCDL1_Msk        (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)        /*!< 0x00000200 */
+#define DSI_WPCR1_LPSRCDL1            DSI_WPCR1_LPSRCDL1_Msk
+
+#define DSI_WPCR1_SDDC_Pos            (12U)
+#define DSI_WPCR1_SDDC_Msk            (0x1UL << DSI_WPCR1_SDDC_Pos)            /*!< 0x00001000 */
+#define DSI_WPCR1_SDDC                DSI_WPCR1_SDDC_Msk                       /*!< SDD Control */
+
+#define DSI_WPCR1_LPRXVCDL_Pos        (14U)
+#define DSI_WPCR1_LPRXVCDL_Msk        (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)        /*!< 0x0000C000 */
+#define DSI_WPCR1_LPRXVCDL            DSI_WPCR1_LPRXVCDL_Msk                   /*!< Low-Power Reception V-IL Compensation on Data Lanes */
+#define DSI_WPCR1_LPRXVCDL0_Pos       (14U)
+#define DSI_WPCR1_LPRXVCDL0_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)       /*!< 0x00004000 */
+#define DSI_WPCR1_LPRXVCDL0           DSI_WPCR1_LPRXVCDL0_Msk
+#define DSI_WPCR1_LPRXVCDL1_Pos       (15U)
+#define DSI_WPCR1_LPRXVCDL1_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)       /*!< 0x00008000 */
+#define DSI_WPCR1_LPRXVCDL1           DSI_WPCR1_LPRXVCDL1_Msk
+
+#define DSI_WPCR1_HSTXSRCCL_Pos       (16U)
+#define DSI_WPCR1_HSTXSRCCL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)       /*!< 0x00030000 */
+#define DSI_WPCR1_HSTXSRCCL           DSI_WPCR1_HSTXSRCCL_Msk                  /*!< High-Speed Transmission Delay on Clock Lane */
+#define DSI_WPCR1_HSTXSRCCL0_Pos      (16U)
+#define DSI_WPCR1_HSTXSRCCL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)      /*!< 0x00010000 */
+#define DSI_WPCR1_HSTXSRCCL0          DSI_WPCR1_HSTXSRCCL0_Msk
+#define DSI_WPCR1_HSTXSRCCL1_Pos      (17U)
+#define DSI_WPCR1_HSTXSRCCL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)      /*!< 0x00020000 */
+#define DSI_WPCR1_HSTXSRCCL1          DSI_WPCR1_HSTXSRCCL1_Msk
+
+#define DSI_WPCR1_HSTXSRCDL_Pos       (18U)
+#define DSI_WPCR1_HSTXSRCDL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)       /*!< 0x000C0000 */
+#define DSI_WPCR1_HSTXSRCDL           DSI_WPCR1_HSTXSRCDL_Msk                  /*!< High-Speed Transmission Delay on Data Lane */
+#define DSI_WPCR1_HSTXSRCDL0_Pos      (18U)
+#define DSI_WPCR1_HSTXSRCDL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)      /*!< 0x00040000 */
+#define DSI_WPCR1_HSTXSRCDL0          DSI_WPCR1_HSTXSRCDL0_Msk
+#define DSI_WPCR1_HSTXSRCDL1_Pos      (19U)
+#define DSI_WPCR1_HSTXSRCDL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)      /*!< 0x00080000 */
+#define DSI_WPCR1_HSTXSRCDL1          DSI_WPCR1_HSTXSRCDL1_Msk
+
+#define DSI_WPCR1_FLPRXLPM_Pos        (22U)
+#define DSI_WPCR1_FLPRXLPM_Msk        (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)        /*!< 0x00400000 */
+#define DSI_WPCR1_FLPRXLPM            DSI_WPCR1_FLPRXLPM_Msk                   /*!< Forces LP Receiver in Low-Power Mode */
+
+#define DSI_WPCR1_LPRXFT_Pos          (25U)
+#define DSI_WPCR1_LPRXFT_Msk          (0x3UL << DSI_WPCR1_LPRXFT_Pos)          /*!< 0x06000000 */
+#define DSI_WPCR1_LPRXFT              DSI_WPCR1_LPRXFT_Msk                     /*!< Low-Power RX low-pass Filtering Tuning */
+#define DSI_WPCR1_LPRXFT0_Pos         (25U)
+#define DSI_WPCR1_LPRXFT0_Msk         (0x1UL << DSI_WPCR1_LPRXFT0_Pos)         /*!< 0x02000000 */
+#define DSI_WPCR1_LPRXFT0             DSI_WPCR1_LPRXFT0_Msk
+#define DSI_WPCR1_LPRXFT1_Pos         (26U)
+#define DSI_WPCR1_LPRXFT1_Msk         (0x1UL << DSI_WPCR1_LPRXFT1_Pos)         /*!< 0x04000000 */
+#define DSI_WPCR1_LPRXFT1             DSI_WPCR1_LPRXFT1_Msk
+
+/*******************  Bit definition for DSI_WPCR2 register  ***************/
+#define DSI_WPCR2_TCLKPREP_Pos        (0U)
+#define DSI_WPCR2_TCLKPREP_Msk        (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)       /*!< 0x000000FF */
+#define DSI_WPCR2_TCLKPREP            DSI_WPCR2_TCLKPREP_Msk                   /*!< t-CLKPREP */
+#define DSI_WPCR2_TCLKPREP0_Pos       (0U)
+#define DSI_WPCR2_TCLKPREP0_Msk       (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)       /*!< 0x00000001 */
+#define DSI_WPCR2_TCLKPREP0           DSI_WPCR2_TCLKPREP0_Msk
+#define DSI_WPCR2_TCLKPREP1_Pos       (1U)
+#define DSI_WPCR2_TCLKPREP1_Msk       (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)       /*!< 0x00000002 */
+#define DSI_WPCR2_TCLKPREP1           DSI_WPCR2_TCLKPREP1_Msk
+#define DSI_WPCR2_TCLKPREP2_Pos       (2U)
+#define DSI_WPCR2_TCLKPREP2_Msk       (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)       /*!< 0x00000004 */
+#define DSI_WPCR2_TCLKPREP2           DSI_WPCR2_TCLKPREP2_Msk
+#define DSI_WPCR2_TCLKPREP3_Pos       (3U)
+#define DSI_WPCR2_TCLKPREP3_Msk       (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)       /*!< 0x00000008 */
+#define DSI_WPCR2_TCLKPREP3           DSI_WPCR2_TCLKPREP3_Msk
+#define DSI_WPCR2_TCLKPREP4_Pos       (4U)
+#define DSI_WPCR2_TCLKPREP4_Msk       (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)       /*!< 0x00000010 */
+#define DSI_WPCR2_TCLKPREP4           DSI_WPCR2_TCLKPREP4_Msk
+#define DSI_WPCR2_TCLKPREP5_Pos       (5U)
+#define DSI_WPCR2_TCLKPREP5_Msk       (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)       /*!< 0x00000020 */
+#define DSI_WPCR2_TCLKPREP5           DSI_WPCR2_TCLKPREP5_Msk
+#define DSI_WPCR2_TCLKPREP6_Pos       (6U)
+#define DSI_WPCR2_TCLKPREP6_Msk       (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)       /*!< 0x00000040 */
+#define DSI_WPCR2_TCLKPREP6           DSI_WPCR2_TCLKPREP6_Msk
+#define DSI_WPCR2_TCLKPREP7_Pos       (7U)
+#define DSI_WPCR2_TCLKPREP7_Msk       (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)       /*!< 0x00000080 */
+#define DSI_WPCR2_TCLKPREP7           DSI_WPCR2_TCLKPREP7_Msk
+
+#define DSI_WPCR2_TCLKZERO_Pos        (8U)
+#define DSI_WPCR2_TCLKZERO_Msk        (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)       /*!< 0x0000FF00 */
+#define DSI_WPCR2_TCLKZERO            DSI_WPCR2_TCLKZERO_Msk                   /*!< t-CLKZERO */
+#define DSI_WPCR2_TCLKZERO0_Pos       (8U)
+#define DSI_WPCR2_TCLKZERO0_Msk       (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)       /*!< 0x00000100 */
+#define DSI_WPCR2_TCLKZERO0           DSI_WPCR2_TCLKZERO0_Msk
+#define DSI_WPCR2_TCLKZERO1_Pos       (9U)
+#define DSI_WPCR2_TCLKZERO1_Msk       (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)       /*!< 0x00000200 */
+#define DSI_WPCR2_TCLKZERO1           DSI_WPCR2_TCLKZERO1_Msk
+#define DSI_WPCR2_TCLKZERO2_Pos       (10U)
+#define DSI_WPCR2_TCLKZERO2_Msk       (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)       /*!< 0x00000400 */
+#define DSI_WPCR2_TCLKZERO2           DSI_WPCR2_TCLKZERO2_Msk
+#define DSI_WPCR2_TCLKZERO3_Pos       (11U)
+#define DSI_WPCR2_TCLKZERO3_Msk       (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)       /*!< 0x00000800 */
+#define DSI_WPCR2_TCLKZERO3           DSI_WPCR2_TCLKZERO3_Msk
+#define DSI_WPCR2_TCLKZERO4_Pos       (12U)
+#define DSI_WPCR2_TCLKZERO4_Msk       (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)       /*!< 0x00001000 */
+#define DSI_WPCR2_TCLKZERO4           DSI_WPCR2_TCLKZERO4_Msk
+#define DSI_WPCR2_TCLKZERO5_Pos       (13U)
+#define DSI_WPCR2_TCLKZERO5_Msk       (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)       /*!< 0x00002000 */
+#define DSI_WPCR2_TCLKZERO5           DSI_WPCR2_TCLKZERO5_Msk
+#define DSI_WPCR2_TCLKZERO6_Pos       (14U)
+#define DSI_WPCR2_TCLKZERO6_Msk       (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)       /*!< 0x00004000 */
+#define DSI_WPCR2_TCLKZERO6           DSI_WPCR2_TCLKZERO6_Msk
+#define DSI_WPCR2_TCLKZERO7_Pos       (15U)
+#define DSI_WPCR2_TCLKZERO7_Msk       (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)       /*!< 0x00008000 */
+#define DSI_WPCR2_TCLKZERO7           DSI_WPCR2_TCLKZERO7_Msk
+
+#define DSI_WPCR2_THSPREP_Pos         (16U)
+#define DSI_WPCR2_THSPREP_Msk         (0xFFUL << DSI_WPCR2_THSPREP_Pos)        /*!< 0x00FF0000 */
+#define DSI_WPCR2_THSPREP             DSI_WPCR2_THSPREP_Msk                    /*!< t-HSPREP */
+#define DSI_WPCR2_THSPREP0_Pos        (16U)
+#define DSI_WPCR2_THSPREP0_Msk        (0x1UL << DSI_WPCR2_THSPREP0_Pos)        /*!< 0x00010000 */
+#define DSI_WPCR2_THSPREP0            DSI_WPCR2_THSPREP0_Msk
+#define DSI_WPCR2_THSPREP1_Pos        (17U)
+#define DSI_WPCR2_THSPREP1_Msk        (0x1UL << DSI_WPCR2_THSPREP1_Pos)        /*!< 0x00020000 */
+#define DSI_WPCR2_THSPREP1            DSI_WPCR2_THSPREP1_Msk
+#define DSI_WPCR2_THSPREP2_Pos        (18U)
+#define DSI_WPCR2_THSPREP2_Msk        (0x1UL << DSI_WPCR2_THSPREP2_Pos)        /*!< 0x00040000 */
+#define DSI_WPCR2_THSPREP2            DSI_WPCR2_THSPREP2_Msk
+#define DSI_WPCR2_THSPREP3_Pos        (19U)
+#define DSI_WPCR2_THSPREP3_Msk        (0x1UL << DSI_WPCR2_THSPREP3_Pos)        /*!< 0x00080000 */
+#define DSI_WPCR2_THSPREP3            DSI_WPCR2_THSPREP3_Msk
+#define DSI_WPCR2_THSPREP4_Pos        (20U)
+#define DSI_WPCR2_THSPREP4_Msk        (0x1UL << DSI_WPCR2_THSPREP4_Pos)        /*!< 0x00100000 */
+#define DSI_WPCR2_THSPREP4            DSI_WPCR2_THSPREP4_Msk
+#define DSI_WPCR2_THSPREP5_Pos        (21U)
+#define DSI_WPCR2_THSPREP5_Msk        (0x1UL << DSI_WPCR2_THSPREP5_Pos)        /*!< 0x00200000 */
+#define DSI_WPCR2_THSPREP5            DSI_WPCR2_THSPREP5_Msk
+#define DSI_WPCR2_THSPREP6_Pos        (22U)
+#define DSI_WPCR2_THSPREP6_Msk        (0x1UL << DSI_WPCR2_THSPREP6_Pos)        /*!< 0x00400000 */
+#define DSI_WPCR2_THSPREP6            DSI_WPCR2_THSPREP6_Msk
+#define DSI_WPCR2_THSPREP7_Pos        (23U)
+#define DSI_WPCR2_THSPREP7_Msk        (0x1UL << DSI_WPCR2_THSPREP7_Pos)        /*!< 0x00800000 */
+#define DSI_WPCR2_THSPREP7            DSI_WPCR2_THSPREP7_Msk
+
+#define DSI_WPCR2_THSTRAIL_Pos        (24U)
+#define DSI_WPCR2_THSTRAIL_Msk        (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)       /*!< 0xFF000000 */
+#define DSI_WPCR2_THSTRAIL            DSI_WPCR2_THSTRAIL_Msk                   /*!< t-HSTRAIL */
+#define DSI_WPCR2_THSTRAIL0_Pos       (24U)
+#define DSI_WPCR2_THSTRAIL0_Msk       (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)       /*!< 0x01000000 */
+#define DSI_WPCR2_THSTRAIL0           DSI_WPCR2_THSTRAIL0_Msk
+#define DSI_WPCR2_THSTRAIL1_Pos       (25U)
+#define DSI_WPCR2_THSTRAIL1_Msk       (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)       /*!< 0x02000000 */
+#define DSI_WPCR2_THSTRAIL1           DSI_WPCR2_THSTRAIL1_Msk
+#define DSI_WPCR2_THSTRAIL2_Pos       (26U)
+#define DSI_WPCR2_THSTRAIL2_Msk       (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)       /*!< 0x04000000 */
+#define DSI_WPCR2_THSTRAIL2           DSI_WPCR2_THSTRAIL2_Msk
+#define DSI_WPCR2_THSTRAIL3_Pos       (27U)
+#define DSI_WPCR2_THSTRAIL3_Msk       (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)       /*!< 0x08000000 */
+#define DSI_WPCR2_THSTRAIL3           DSI_WPCR2_THSTRAIL3_Msk
+#define DSI_WPCR2_THSTRAIL4_Pos       (28U)
+#define DSI_WPCR2_THSTRAIL4_Msk       (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)       /*!< 0x10000000 */
+#define DSI_WPCR2_THSTRAIL4           DSI_WPCR2_THSTRAIL4_Msk
+#define DSI_WPCR2_THSTRAIL5_Pos       (29U)
+#define DSI_WPCR2_THSTRAIL5_Msk       (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)       /*!< 0x20000000 */
+#define DSI_WPCR2_THSTRAIL5           DSI_WPCR2_THSTRAIL5_Msk
+#define DSI_WPCR2_THSTRAIL6_Pos       (30U)
+#define DSI_WPCR2_THSTRAIL6_Msk       (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)       /*!< 0x40000000 */
+#define DSI_WPCR2_THSTRAIL6           DSI_WPCR2_THSTRAIL6_Msk
+#define DSI_WPCR2_THSTRAIL7_Pos       (31U)
+#define DSI_WPCR2_THSTRAIL7_Msk       (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)       /*!< 0x80000000 */
+#define DSI_WPCR2_THSTRAIL7           DSI_WPCR2_THSTRAIL7_Msk
+
+/*******************  Bit definition for DSI_WPCR3 register  ***************/
+#define DSI_WPCR3_THSZERO_Pos         (0U)
+#define DSI_WPCR3_THSZERO_Msk         (0xFFUL << DSI_WPCR3_THSZERO_Pos)        /*!< 0x000000FF */
+#define DSI_WPCR3_THSZERO             DSI_WPCR3_THSZERO_Msk                    /*!< t-HSZERO */
+#define DSI_WPCR3_THSZERO0_Pos        (0U)
+#define DSI_WPCR3_THSZERO0_Msk        (0x1UL << DSI_WPCR3_THSZERO0_Pos)        /*!< 0x00000001 */
+#define DSI_WPCR3_THSZERO0            DSI_WPCR3_THSZERO0_Msk
+#define DSI_WPCR3_THSZERO1_Pos        (1U)
+#define DSI_WPCR3_THSZERO1_Msk        (0x1UL << DSI_WPCR3_THSZERO1_Pos)        /*!< 0x00000002 */
+#define DSI_WPCR3_THSZERO1            DSI_WPCR3_THSZERO1_Msk
+#define DSI_WPCR3_THSZERO2_Pos        (2U)
+#define DSI_WPCR3_THSZERO2_Msk        (0x1UL << DSI_WPCR3_THSZERO2_Pos)        /*!< 0x00000004 */
+#define DSI_WPCR3_THSZERO2            DSI_WPCR3_THSZERO2_Msk
+#define DSI_WPCR3_THSZERO3_Pos        (3U)
+#define DSI_WPCR3_THSZERO3_Msk        (0x1UL << DSI_WPCR3_THSZERO3_Pos)        /*!< 0x00000008 */
+#define DSI_WPCR3_THSZERO3            DSI_WPCR3_THSZERO3_Msk
+#define DSI_WPCR3_THSZERO4_Pos        (4U)
+#define DSI_WPCR3_THSZERO4_Msk        (0x1UL << DSI_WPCR3_THSZERO4_Pos)        /*!< 0x00000010 */
+#define DSI_WPCR3_THSZERO4            DSI_WPCR3_THSZERO4_Msk
+#define DSI_WPCR3_THSZERO5_Pos        (5U)
+#define DSI_WPCR3_THSZERO5_Msk        (0x1UL << DSI_WPCR3_THSZERO5_Pos)        /*!< 0x00000020 */
+#define DSI_WPCR3_THSZERO5            DSI_WPCR3_THSZERO5_Msk
+#define DSI_WPCR3_THSZERO6_Pos        (6U)
+#define DSI_WPCR3_THSZERO6_Msk        (0x1UL << DSI_WPCR3_THSZERO6_Pos)        /*!< 0x00000040 */
+#define DSI_WPCR3_THSZERO6            DSI_WPCR3_THSZERO6_Msk
+#define DSI_WPCR3_THSZERO7_Pos        (7U)
+#define DSI_WPCR3_THSZERO7_Msk        (0x1UL << DSI_WPCR3_THSZERO7_Pos)        /*!< 0x00000080 */
+#define DSI_WPCR3_THSZERO7            DSI_WPCR3_THSZERO7_Msk
+
+#define DSI_WPCR3_TLPXD_Pos           (8U)
+#define DSI_WPCR3_TLPXD_Msk           (0xFFUL << DSI_WPCR3_TLPXD_Pos)          /*!< 0x0000FF00 */
+#define DSI_WPCR3_TLPXD               DSI_WPCR3_TLPXD_Msk                      /*!< t-LPXD */
+#define DSI_WPCR3_TLPXD0_Pos          (8U)
+#define DSI_WPCR3_TLPXD0_Msk          (0x1UL << DSI_WPCR3_TLPXD0_Pos)          /*!< 0x00000100 */
+#define DSI_WPCR3_TLPXD0              DSI_WPCR3_TLPXD0_Msk
+#define DSI_WPCR3_TLPXD1_Pos          (9U)
+#define DSI_WPCR3_TLPXD1_Msk          (0x1UL << DSI_WPCR3_TLPXD1_Pos)          /*!< 0x00000200 */
+#define DSI_WPCR3_TLPXD1              DSI_WPCR3_TLPXD1_Msk
+#define DSI_WPCR3_TLPXD2_Pos          (10U)
+#define DSI_WPCR3_TLPXD2_Msk          (0x1UL << DSI_WPCR3_TLPXD2_Pos)          /*!< 0x00000400 */
+#define DSI_WPCR3_TLPXD2              DSI_WPCR3_TLPXD2_Msk
+#define DSI_WPCR3_TLPXD3_Pos          (11U)
+#define DSI_WPCR3_TLPXD3_Msk          (0x1UL << DSI_WPCR3_TLPXD3_Pos)          /*!< 0x00000800 */
+#define DSI_WPCR3_TLPXD3              DSI_WPCR3_TLPXD3_Msk
+#define DSI_WPCR3_TLPXD4_Pos          (12U)
+#define DSI_WPCR3_TLPXD4_Msk          (0x1UL << DSI_WPCR3_TLPXD4_Pos)          /*!< 0x00001000 */
+#define DSI_WPCR3_TLPXD4              DSI_WPCR3_TLPXD4_Msk
+#define DSI_WPCR3_TLPXD5_Pos          (13U)
+#define DSI_WPCR3_TLPXD5_Msk          (0x1UL << DSI_WPCR3_TLPXD5_Pos)          /*!< 0x00002000 */
+#define DSI_WPCR3_TLPXD5              DSI_WPCR3_TLPXD5_Msk
+#define DSI_WPCR3_TLPXD6_Pos          (14U)
+#define DSI_WPCR3_TLPXD6_Msk          (0x1UL << DSI_WPCR3_TLPXD6_Pos)          /*!< 0x00004000 */
+#define DSI_WPCR3_TLPXD6              DSI_WPCR3_TLPXD6_Msk
+#define DSI_WPCR3_TLPXD7_Pos          (15U)
+#define DSI_WPCR3_TLPXD7_Msk          (0x1UL << DSI_WPCR3_TLPXD7_Pos)          /*!< 0x00008000 */
+#define DSI_WPCR3_TLPXD7              DSI_WPCR3_TLPXD7_Msk
+
+#define DSI_WPCR3_THSEXIT_Pos         (16U)
+#define DSI_WPCR3_THSEXIT_Msk         (0xFFUL << DSI_WPCR3_THSEXIT_Pos)        /*!< 0x00FF0000 */
+#define DSI_WPCR3_THSEXIT             DSI_WPCR3_THSEXIT_Msk                    /*!< t-HSEXIT */
+#define DSI_WPCR3_THSEXIT0_Pos        (16U)
+#define DSI_WPCR3_THSEXIT0_Msk        (0x1UL << DSI_WPCR3_THSEXIT0_Pos)        /*!< 0x00010000 */
+#define DSI_WPCR3_THSEXIT0            DSI_WPCR3_THSEXIT0_Msk
+#define DSI_WPCR3_THSEXIT1_Pos        (17U)
+#define DSI_WPCR3_THSEXIT1_Msk        (0x1UL << DSI_WPCR3_THSEXIT1_Pos)        /*!< 0x00020000 */
+#define DSI_WPCR3_THSEXIT1            DSI_WPCR3_THSEXIT1_Msk
+#define DSI_WPCR3_THSEXIT2_Pos        (18U)
+#define DSI_WPCR3_THSEXIT2_Msk        (0x1UL << DSI_WPCR3_THSEXIT2_Pos)        /*!< 0x00040000 */
+#define DSI_WPCR3_THSEXIT2            DSI_WPCR3_THSEXIT2_Msk
+#define DSI_WPCR3_THSEXIT3_Pos        (19U)
+#define DSI_WPCR3_THSEXIT3_Msk        (0x1UL << DSI_WPCR3_THSEXIT3_Pos)        /*!< 0x00080000 */
+#define DSI_WPCR3_THSEXIT3            DSI_WPCR3_THSEXIT3_Msk
+#define DSI_WPCR3_THSEXIT4_Pos        (20U)
+#define DSI_WPCR3_THSEXIT4_Msk        (0x1UL << DSI_WPCR3_THSEXIT4_Pos)        /*!< 0x00100000 */
+#define DSI_WPCR3_THSEXIT4            DSI_WPCR3_THSEXIT4_Msk
+#define DSI_WPCR3_THSEXIT5_Pos        (21U)
+#define DSI_WPCR3_THSEXIT5_Msk        (0x1UL << DSI_WPCR3_THSEXIT5_Pos)        /*!< 0x00200000 */
+#define DSI_WPCR3_THSEXIT5            DSI_WPCR3_THSEXIT5_Msk
+#define DSI_WPCR3_THSEXIT6_Pos        (22U)
+#define DSI_WPCR3_THSEXIT6_Msk        (0x1UL << DSI_WPCR3_THSEXIT6_Pos)        /*!< 0x00400000 */
+#define DSI_WPCR3_THSEXIT6            DSI_WPCR3_THSEXIT6_Msk
+#define DSI_WPCR3_THSEXIT7_Pos        (23U)
+#define DSI_WPCR3_THSEXIT7_Msk        (0x1UL << DSI_WPCR3_THSEXIT7_Pos)        /*!< 0x00800000 */
+#define DSI_WPCR3_THSEXIT7            DSI_WPCR3_THSEXIT7_Msk
+
+#define DSI_WPCR3_TLPXC_Pos           (24U)
+#define DSI_WPCR3_TLPXC_Msk           (0xFFUL << DSI_WPCR3_TLPXC_Pos)          /*!< 0xFF000000 */
+#define DSI_WPCR3_TLPXC               DSI_WPCR3_TLPXC_Msk                      /*!< t-LPXC */
+#define DSI_WPCR3_TLPXC0_Pos          (24U)
+#define DSI_WPCR3_TLPXC0_Msk          (0x1UL << DSI_WPCR3_TLPXC0_Pos)          /*!< 0x01000000 */
+#define DSI_WPCR3_TLPXC0              DSI_WPCR3_TLPXC0_Msk
+#define DSI_WPCR3_TLPXC1_Pos          (25U)
+#define DSI_WPCR3_TLPXC1_Msk          (0x1UL << DSI_WPCR3_TLPXC1_Pos)          /*!< 0x02000000 */
+#define DSI_WPCR3_TLPXC1              DSI_WPCR3_TLPXC1_Msk
+#define DSI_WPCR3_TLPXC2_Pos          (26U)
+#define DSI_WPCR3_TLPXC2_Msk          (0x1UL << DSI_WPCR3_TLPXC2_Pos)          /*!< 0x04000000 */
+#define DSI_WPCR3_TLPXC2              DSI_WPCR3_TLPXC2_Msk
+#define DSI_WPCR3_TLPXC3_Pos          (27U)
+#define DSI_WPCR3_TLPXC3_Msk          (0x1UL << DSI_WPCR3_TLPXC3_Pos)          /*!< 0x08000000 */
+#define DSI_WPCR3_TLPXC3              DSI_WPCR3_TLPXC3_Msk
+#define DSI_WPCR3_TLPXC4_Pos          (28U)
+#define DSI_WPCR3_TLPXC4_Msk          (0x1UL << DSI_WPCR3_TLPXC4_Pos)          /*!< 0x10000000 */
+#define DSI_WPCR3_TLPXC4              DSI_WPCR3_TLPXC4_Msk
+#define DSI_WPCR3_TLPXC5_Pos          (29U)
+#define DSI_WPCR3_TLPXC5_Msk          (0x1UL << DSI_WPCR3_TLPXC5_Pos)          /*!< 0x20000000 */
+#define DSI_WPCR3_TLPXC5              DSI_WPCR3_TLPXC5_Msk
+#define DSI_WPCR3_TLPXC6_Pos          (30U)
+#define DSI_WPCR3_TLPXC6_Msk          (0x1UL << DSI_WPCR3_TLPXC6_Pos)          /*!< 0x40000000 */
+#define DSI_WPCR3_TLPXC6              DSI_WPCR3_TLPXC6_Msk
+#define DSI_WPCR3_TLPXC7_Pos          (31U)
+#define DSI_WPCR3_TLPXC7_Msk          (0x1UL << DSI_WPCR3_TLPXC7_Pos)          /*!< 0x80000000 */
+#define DSI_WPCR3_TLPXC7              DSI_WPCR3_TLPXC7_Msk
+
+/*******************  Bit definition for DSI_WPCR4 register  ***************/
+#define DSI_WPCR4_TCLKPOST_Pos        (0U)
+#define DSI_WPCR4_TCLKPOST_Msk        (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)       /*!< 0x000000FF */
+#define DSI_WPCR4_TCLKPOST            DSI_WPCR4_TCLKPOST_Msk                   /*!< t-CLKPOST */
+#define DSI_WPCR4_TCLKPOST0_Pos       (0U)
+#define DSI_WPCR4_TCLKPOST0_Msk       (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)       /*!< 0x00000001 */
+#define DSI_WPCR4_TCLKPOST0           DSI_WPCR4_TCLKPOST0_Msk
+#define DSI_WPCR4_TCLKPOST1_Pos       (1U)
+#define DSI_WPCR4_TCLKPOST1_Msk       (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)       /*!< 0x00000002 */
+#define DSI_WPCR4_TCLKPOST1           DSI_WPCR4_TCLKPOST1_Msk
+#define DSI_WPCR4_TCLKPOST2_Pos       (2U)
+#define DSI_WPCR4_TCLKPOST2_Msk       (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)       /*!< 0x00000004 */
+#define DSI_WPCR4_TCLKPOST2           DSI_WPCR4_TCLKPOST2_Msk
+#define DSI_WPCR4_TCLKPOST3_Pos       (3U)
+#define DSI_WPCR4_TCLKPOST3_Msk       (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)       /*!< 0x00000008 */
+#define DSI_WPCR4_TCLKPOST3           DSI_WPCR4_TCLKPOST3_Msk
+#define DSI_WPCR4_TCLKPOST4_Pos       (4U)
+#define DSI_WPCR4_TCLKPOST4_Msk       (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)       /*!< 0x00000010 */
+#define DSI_WPCR4_TCLKPOST4           DSI_WPCR4_TCLKPOST4_Msk
+#define DSI_WPCR4_TCLKPOST5_Pos       (5U)
+#define DSI_WPCR4_TCLKPOST5_Msk       (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)       /*!< 0x00000020 */
+#define DSI_WPCR4_TCLKPOST5           DSI_WPCR4_TCLKPOST5_Msk
+#define DSI_WPCR4_TCLKPOST6_Pos       (6U)
+#define DSI_WPCR4_TCLKPOST6_Msk       (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)       /*!< 0x00000040 */
+#define DSI_WPCR4_TCLKPOST6           DSI_WPCR4_TCLKPOST6_Msk
+#define DSI_WPCR4_TCLKPOST7_Pos       (7U)
+#define DSI_WPCR4_TCLKPOST7_Msk       (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)       /*!< 0x00000080 */
+#define DSI_WPCR4_TCLKPOST7           DSI_WPCR4_TCLKPOST7_Msk
+
+/*******************  Bit definition for DSI_WRPCR register  ***************/
+#define DSI_WRPCR_PLLEN_Pos           (0U)
+#define DSI_WRPCR_PLLEN_Msk           (0x1UL << DSI_WRPCR_PLLEN_Pos)           /*!< 0x00000001 */
+#define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */
+#define DSI_WRPCR_PLL_NDIV_Pos        (2U)
+#define DSI_WRPCR_PLL_NDIV_Msk        (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)       /*!< 0x000001FC */
+#define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */
+#define DSI_WRPCR_PLL_NDIV0_Pos       (2U)
+#define DSI_WRPCR_PLL_NDIV0_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)       /*!< 0x00000004 */
+#define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk
+#define DSI_WRPCR_PLL_NDIV1_Pos       (3U)
+#define DSI_WRPCR_PLL_NDIV1_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)       /*!< 0x00000008 */
+#define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk
+#define DSI_WRPCR_PLL_NDIV2_Pos       (4U)
+#define DSI_WRPCR_PLL_NDIV2_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)       /*!< 0x00000010 */
+#define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk
+#define DSI_WRPCR_PLL_NDIV3_Pos       (5U)
+#define DSI_WRPCR_PLL_NDIV3_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)       /*!< 0x00000020 */
+#define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk
+#define DSI_WRPCR_PLL_NDIV4_Pos       (6U)
+#define DSI_WRPCR_PLL_NDIV4_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)       /*!< 0x00000040 */
+#define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk
+#define DSI_WRPCR_PLL_NDIV5_Pos       (7U)
+#define DSI_WRPCR_PLL_NDIV5_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)       /*!< 0x00000080 */
+#define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk
+#define DSI_WRPCR_PLL_NDIV6_Pos       (8U)
+#define DSI_WRPCR_PLL_NDIV6_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)       /*!< 0x00000100 */
+#define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk
+
+#define DSI_WRPCR_PLL_IDF_Pos         (11U)
+#define DSI_WRPCR_PLL_IDF_Msk         (0xFUL << DSI_WRPCR_PLL_IDF_Pos)         /*!< 0x00007800 */
+#define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */
+#define DSI_WRPCR_PLL_IDF0_Pos        (11U)
+#define DSI_WRPCR_PLL_IDF0_Msk        (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)        /*!< 0x00000800 */
+#define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk
+#define DSI_WRPCR_PLL_IDF1_Pos        (12U)
+#define DSI_WRPCR_PLL_IDF1_Msk        (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)        /*!< 0x00001000 */
+#define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk
+#define DSI_WRPCR_PLL_IDF2_Pos        (13U)
+#define DSI_WRPCR_PLL_IDF2_Msk        (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)        /*!< 0x00002000 */
+#define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk
+#define DSI_WRPCR_PLL_IDF3_Pos        (14U)
+#define DSI_WRPCR_PLL_IDF3_Msk        (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)        /*!< 0x00004000 */
+#define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk
+
+#define DSI_WRPCR_PLL_ODF_Pos         (16U)
+#define DSI_WRPCR_PLL_ODF_Msk         (0x3UL << DSI_WRPCR_PLL_ODF_Pos)         /*!< 0x00030000 */
+#define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */
+#define DSI_WRPCR_PLL_ODF0_Pos        (16U)
+#define DSI_WRPCR_PLL_ODF0_Msk        (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)        /*!< 0x00010000 */
+#define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk
+#define DSI_WRPCR_PLL_ODF1_Pos        (17U)
+#define DSI_WRPCR_PLL_ODF1_Msk        (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)        /*!< 0x00020000 */
+#define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk
+
+#define DSI_WRPCR_REGEN_Pos           (24U)
+#define DSI_WRPCR_REGEN_Msk           (0x1UL << DSI_WRPCR_REGEN_Pos)           /*!< 0x01000000 */
+#define DSI_WRPCR_REGEN               DSI_WRPCR_REGEN_Msk                      /*!< Regulator Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for EXTI_RTSR1 register  *******************/
+#define EXTI_RTSR1_TR_Pos          (0U)
+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR1_TR0_Pos         (0U)
+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR1_TR1_Pos         (1U)
+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR1_TR2_Pos         (2U)
+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR1_TR3_Pos         (3U)
+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR1_TR4_Pos         (4U)
+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR1_TR5_Pos         (5U)
+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR1_TR6_Pos         (6U)
+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR1_TR7_Pos         (7U)
+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR1_TR8_Pos         (8U)
+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR1_TR9_Pos         (9U)
+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR1_TR10_Pos        (10U)
+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR1_TR11_Pos        (11U)
+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR1_TR12_Pos        (12U)
+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR1_TR13_Pos        (13U)
+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR1_TR14_Pos        (14U)
+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR1_TR15_Pos        (15U)
+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR1_TR16_Pos        (16U)
+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR1_TR17_Pos        (17U)
+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR1_TR18_Pos        (18U)
+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR1_TR19_Pos        (19U)
+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR1_TR20_Pos        (20U)
+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR1_TR21_Pos        (21U)
+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_FTSR1 register  *******************/
+#define EXTI_FTSR1_TR_Pos          (0U)
+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */
+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR1_TR0_Pos         (0U)
+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */
+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR1_TR1_Pos         (1U)
+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */
+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR1_TR2_Pos         (2U)
+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */
+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR1_TR3_Pos         (3U)
+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */
+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR1_TR4_Pos         (4U)
+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */
+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR1_TR5_Pos         (5U)
+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */
+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR1_TR6_Pos         (6U)
+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */
+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR1_TR7_Pos         (7U)
+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */
+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR1_TR8_Pos         (8U)
+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */
+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR1_TR9_Pos         (9U)
+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */
+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR1_TR10_Pos        (10U)
+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */
+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR1_TR11_Pos        (11U)
+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */
+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR1_TR12_Pos        (12U)
+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */
+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR1_TR13_Pos        (13U)
+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */
+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR1_TR14_Pos        (14U)
+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */
+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR1_TR15_Pos        (15U)
+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */
+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR1_TR16_Pos        (16U)
+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */
+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR1_TR17_Pos        (17U)
+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR1_TR18_Pos        (18U)
+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR1_TR19_Pos        (19U)
+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR1_TR20_Pos        (20U)
+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR1_TR21_Pos        (21U)
+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */
+
+/******************  Bit definition for EXTI_SWIER1 register  ******************/
+#define EXTI_SWIER1_SWIER0_Pos     (0U)
+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */
+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER1_SWIER1_Pos     (1U)
+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */
+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER1_SWIER2_Pos     (2U)
+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */
+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER1_SWIER3_Pos     (3U)
+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */
+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER1_SWIER4_Pos     (4U)
+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */
+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER1_SWIER5_Pos     (5U)
+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */
+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER1_SWIER6_Pos     (6U)
+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */
+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER1_SWIER7_Pos     (7U)
+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */
+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER1_SWIER8_Pos     (8U)
+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */
+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER1_SWIER9_Pos     (9U)
+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */
+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER1_SWIER10_Pos    (10U)
+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */
+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER1_SWIER11_Pos    (11U)
+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */
+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER1_SWIER12_Pos    (12U)
+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */
+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER1_SWIER13_Pos    (13U)
+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */
+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER1_SWIER14_Pos    (14U)
+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */
+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER1_SWIER15_Pos    (15U)
+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */
+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER1_SWIER16_Pos    (16U)
+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */
+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER1_SWIER17_Pos    (17U)
+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER1_SWIER18_Pos    (18U)
+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER1_SWIER19_Pos    (19U)
+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER1_SWIER20_Pos    (20U)
+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER1_SWIER21_Pos    (21U)
+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */
+
+/******************  Bit definition for EXTI_D3PMR1 register  ******************/
+#define EXTI_D3PMR1_MR0_Pos        (0U)
+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */
+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */
+#define EXTI_D3PMR1_MR1_Pos        (1U)
+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */
+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */
+#define EXTI_D3PMR1_MR2_Pos        (2U)
+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */
+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */
+#define EXTI_D3PMR1_MR3_Pos        (3U)
+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */
+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */
+#define EXTI_D3PMR1_MR4_Pos        (4U)
+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */
+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */
+#define EXTI_D3PMR1_MR5_Pos        (5U)
+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */
+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */
+#define EXTI_D3PMR1_MR6_Pos        (6U)
+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */
+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */
+#define EXTI_D3PMR1_MR7_Pos        (7U)
+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */
+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */
+#define EXTI_D3PMR1_MR8_Pos        (8U)
+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */
+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */
+#define EXTI_D3PMR1_MR9_Pos        (9U)
+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */
+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */
+#define EXTI_D3PMR1_MR10_Pos       (10U)
+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */
+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */
+#define EXTI_D3PMR1_MR11_Pos       (11U)
+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */
+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */
+#define EXTI_D3PMR1_MR12_Pos       (12U)
+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */
+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */
+#define EXTI_D3PMR1_MR13_Pos       (13U)
+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */
+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */
+#define EXTI_D3PMR1_MR14_Pos       (14U)
+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */
+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */
+#define EXTI_D3PMR1_MR15_Pos       (15U)
+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */
+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */
+#define EXTI_D3PMR1_MR19_Pos       (19U)
+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */
+#define EXTI_D3PMR1_MR20_Pos       (20U)
+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */
+#define EXTI_D3PMR1_MR21_Pos       (21U)
+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */
+#define EXTI_D3PMR1_MR25_Pos       (24U)
+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */
+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */
+
+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/
+#define EXTI_D3PCR1L_PCS0_Pos       (0U)
+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */
+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */
+#define EXTI_D3PCR1L_PCS1_Pos       (2U)
+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */
+#define EXTI_D3PCR1L_PCS2_Pos       (4U)
+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */
+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */
+#define EXTI_D3PCR1L_PCS3_Pos       (6U)
+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */
+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */
+#define EXTI_D3PCR1L_PCS4_Pos       (8U)
+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */
+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */
+#define EXTI_D3PCR1L_PCS5_Pos       (10U)
+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */
+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */
+#define EXTI_D3PCR1L_PCS6_Pos       (12U)
+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */
+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */
+#define EXTI_D3PCR1L_PCS7_Pos       (14U)
+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */
+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */
+#define EXTI_D3PCR1L_PCS8_Pos       (16U)
+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */
+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */
+#define EXTI_D3PCR1L_PCS9_Pos       (18U)
+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */
+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */
+#define EXTI_D3PCR1L_PCS10_Pos      (20U)
+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */
+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/
+#define EXTI_D3PCR1L_PCS11_Pos      (22U)
+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */
+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/
+#define EXTI_D3PCR1L_PCS12_Pos      (24U)
+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */
+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/
+#define EXTI_D3PCR1L_PCS13_Pos      (26U)
+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */
+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/
+#define EXTI_D3PCR1L_PCS14_Pos      (28U)
+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */
+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/
+#define EXTI_D3PCR1L_PCS15_Pos      (30U)
+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */
+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/
+
+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/
+#define EXTI_D3PCR1H_PCS19_Pos       (6U)
+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */
+#define EXTI_D3PCR1H_PCS20_Pos       (8U)
+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */
+#define EXTI_D3PCR1H_PCS21_Pos       (10U)
+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */
+#define EXTI_D3PCR1H_PCS25_Pos       (18U)
+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */
+
+/******************  Bit definition for EXTI_RTSR2 register  *******************/
+#define EXTI_RTSR2_TR_Pos          (17U)
+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR2_TR49_Pos        (17U)
+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */
+#define EXTI_RTSR2_TR51_Pos        (19U)
+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_FTSR2 register  *******************/
+#define EXTI_FTSR2_TR_Pos          (17U)
+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */
+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR2_TR49_Pos        (17U)
+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */
+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */
+#define EXTI_FTSR2_TR51_Pos        (19U)
+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */
+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */
+
+/******************  Bit definition for EXTI_SWIER2 register  ******************/
+#define EXTI_SWIER2_SWIER49_Pos    (17U)
+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */
+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */
+#define EXTI_SWIER2_SWIER51_Pos    (19U)
+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */
+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */
+
+/******************  Bit definition for EXTI_D3PMR2 register  ******************/
+#define EXTI_D3PMR2_MR34_Pos       (2U)
+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */
+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */
+#define EXTI_D3PMR2_MR35_Pos       (3U)
+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */
+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */
+#define EXTI_D3PMR2_MR41_Pos       (9U)
+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */
+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */
+#define EXTI_D3PMR2_MR48_Pos       (16U)
+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */
+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */
+#define EXTI_D3PMR2_MR49_Pos       (17U)
+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */
+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */
+#define EXTI_D3PMR2_MR50_Pos       (18U)
+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */
+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */
+#define EXTI_D3PMR2_MR51_Pos       (19U)
+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */
+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */
+#define EXTI_D3PMR2_MR52_Pos       (20U)
+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */
+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */
+#define EXTI_D3PMR2_MR53_Pos       (21U)
+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */
+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */
+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/
+#define EXTI_D3PCR2L_PCS34_Pos       (4U)
+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */
+#define EXTI_D3PCR2L_PCS35_Pos       (6U)
+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */
+#define EXTI_D3PCR2L_PCS41_Pos       (18U)
+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */
+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */
+
+
+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/
+#define EXTI_D3PCR2H_PCS48_Pos       (0U)
+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */
+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */
+#define EXTI_D3PCR2H_PCS49_Pos       (2U)
+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */
+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */
+#define EXTI_D3PCR2H_PCS50_Pos       (4U)
+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */
+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */
+#define EXTI_D3PCR2H_PCS51_Pos       (6U)
+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */
+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */
+#define EXTI_D3PCR2H_PCS52_Pos       (8U)
+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */
+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */
+#define EXTI_D3PCR2H_PCS53_Pos       (10U)
+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */
+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */
+/******************  Bit definition for EXTI_RTSR3 register  *******************/
+#define EXTI_RTSR3_TR_Pos          (18U)
+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */
+#define EXTI_RTSR3_TR82_Pos        (18U)
+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */
+#define EXTI_RTSR3_TR84_Pos        (20U)
+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */
+#define EXTI_RTSR3_TR85_Pos        (21U)
+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */
+#define EXTI_RTSR3_TR86_Pos        (22U)
+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_FTSR3 register  *******************/
+#define EXTI_FTSR3_TR_Pos          (18U)
+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */
+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */
+#define EXTI_FTSR3_TR82_Pos        (18U)
+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */
+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */
+#define EXTI_FTSR3_TR84_Pos        (20U)
+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */
+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */
+#define EXTI_FTSR3_TR85_Pos        (21U)
+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */
+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */
+#define EXTI_FTSR3_TR86_Pos        (22U)
+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */
+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */
+
+/******************  Bit definition for EXTI_SWIER3 register  ******************/
+#define EXTI_SWIER3_SWI_Pos        (18U)
+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */
+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */
+#define EXTI_SWIER3_SWIER82_Pos    (18U)
+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */
+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */
+#define EXTI_SWIER3_SWIER84_Pos    (20U)
+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */
+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */
+#define EXTI_SWIER3_SWIER85_Pos    (21U)
+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */
+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */
+#define EXTI_SWIER3_SWIER86_Pos    (22U)
+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */
+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */
+
+/*******************  Bit definition for EXTI_IMR1 register  *******************/
+#define EXTI_IMR1_IM_Pos           (0U)
+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR1_IM0_Pos          (0U)
+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */
+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR1_IM1_Pos          (1U)
+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */
+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR1_IM2_Pos          (2U)
+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */
+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR1_IM3_Pos          (3U)
+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */
+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR1_IM4_Pos          (4U)
+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */
+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR1_IM5_Pos          (5U)
+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */
+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR1_IM6_Pos          (6U)
+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */
+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR1_IM7_Pos          (7U)
+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */
+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR1_IM8_Pos          (8U)
+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */
+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR1_IM9_Pos          (9U)
+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */
+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR1_IM10_Pos         (10U)
+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR1_IM11_Pos         (11U)
+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR1_IM12_Pos         (12U)
+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR1_IM13_Pos         (13U)
+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR1_IM14_Pos         (14U)
+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR1_IM15_Pos         (15U)
+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR1_IM16_Pos         (16U)
+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR1_IM17_Pos         (17U)
+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR1_IM18_Pos         (18U)
+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR1_IM19_Pos         (19U)
+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR1_IM20_Pos         (20U)
+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR1_IM21_Pos         (21U)
+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR1_IM22_Pos         (22U)
+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR1_IM23_Pos         (23U)
+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */
+#define EXTI_IMR1_IM24_Pos         (24U)
+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */
+#define EXTI_IMR1_IM25_Pos         (25U)
+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */
+#define EXTI_IMR1_IM26_Pos         (26U)
+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */
+#define EXTI_IMR1_IM27_Pos         (27U)
+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */
+#define EXTI_IMR1_IM28_Pos         (28U)
+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */
+#define EXTI_IMR1_IM29_Pos         (29U)
+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */
+#define EXTI_IMR1_IM30_Pos         (30U)
+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */
+#define EXTI_IMR1_IM31_Pos         (31U)
+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */
+
+/*******************  Bit definition for EXTI_EMR1 register  *******************/
+#define EXTI_EMR1_EM_Pos           (0U)
+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */
+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR1_EM0_Pos          (0U)
+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */
+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */
+#define EXTI_EMR1_EM1_Pos          (1U)
+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */
+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */
+#define EXTI_EMR1_EM2_Pos          (2U)
+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */
+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */
+#define EXTI_EMR1_EM3_Pos          (3U)
+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */
+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */
+#define EXTI_EMR1_EM4_Pos          (4U)
+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */
+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */
+#define EXTI_EMR1_EM5_Pos          (5U)
+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */
+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */
+#define EXTI_EMR1_EM6_Pos          (6U)
+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */
+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */
+#define EXTI_EMR1_EM7_Pos          (7U)
+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */
+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */
+#define EXTI_EMR1_EM8_Pos          (8U)
+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */
+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */
+#define EXTI_EMR1_EM9_Pos          (9U)
+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */
+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */
+#define EXTI_EMR1_EM10_Pos         (10U)
+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */
+#define EXTI_EMR1_EM11_Pos         (11U)
+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */
+#define EXTI_EMR1_EM12_Pos         (12U)
+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */
+#define EXTI_EMR1_EM13_Pos         (13U)
+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */
+#define EXTI_EMR1_EM14_Pos         (14U)
+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */
+#define EXTI_EMR1_EM15_Pos         (15U)
+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */
+#define EXTI_EMR1_EM16_Pos         (16U)
+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */
+#define EXTI_EMR1_EM17_Pos         (17U)
+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */
+#define EXTI_EMR1_EM18_Pos         (18U)
+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */
+#define EXTI_EMR1_EM20_Pos         (20U)
+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */
+#define EXTI_EMR1_EM21_Pos         (21U)
+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */
+#define EXTI_EMR1_EM22_Pos         (22U)
+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */
+#define EXTI_EMR1_EM23_Pos         (23U)
+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */
+#define EXTI_EMR1_EM24_Pos         (24U)
+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */
+#define EXTI_EMR1_EM25_Pos         (25U)
+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */
+#define EXTI_EMR1_EM26_Pos         (26U)
+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */
+#define EXTI_EMR1_EM27_Pos         (27U)
+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */
+#define EXTI_EMR1_EM28_Pos         (28U)
+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */
+#define EXTI_EMR1_EM29_Pos         (29U)
+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */
+#define EXTI_EMR1_EM30_Pos         (30U)
+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */
+#define EXTI_EMR1_EM31_Pos         (31U)
+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */
+
+/*******************  Bit definition for EXTI_PR1 register  ********************/
+#define EXTI_PR1_PR_Pos            (0U)
+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */
+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR1_PR0_Pos           (0U)
+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */
+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */
+#define EXTI_PR1_PR1_Pos           (1U)
+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */
+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */
+#define EXTI_PR1_PR2_Pos           (2U)
+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */
+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */
+#define EXTI_PR1_PR3_Pos           (3U)
+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */
+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */
+#define EXTI_PR1_PR4_Pos           (4U)
+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */
+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */
+#define EXTI_PR1_PR5_Pos           (5U)
+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */
+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */
+#define EXTI_PR1_PR6_Pos           (6U)
+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */
+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */
+#define EXTI_PR1_PR7_Pos           (7U)
+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */
+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */
+#define EXTI_PR1_PR8_Pos           (8U)
+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */
+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */
+#define EXTI_PR1_PR9_Pos           (9U)
+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */
+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */
+#define EXTI_PR1_PR10_Pos          (10U)
+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */
+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */
+#define EXTI_PR1_PR11_Pos          (11U)
+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */
+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */
+#define EXTI_PR1_PR12_Pos          (12U)
+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */
+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */
+#define EXTI_PR1_PR13_Pos          (13U)
+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */
+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */
+#define EXTI_PR1_PR14_Pos          (14U)
+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */
+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */
+#define EXTI_PR1_PR15_Pos          (15U)
+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */
+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */
+#define EXTI_PR1_PR16_Pos          (16U)
+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */
+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */
+#define EXTI_PR1_PR17_Pos          (17U)
+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */
+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */
+#define EXTI_PR1_PR18_Pos          (18U)
+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */
+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */
+#define EXTI_PR1_PR19_Pos          (19U)
+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */
+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */
+#define EXTI_PR1_PR20_Pos          (20U)
+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */
+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */
+#define EXTI_PR1_PR21_Pos          (21U)
+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */
+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */
+
+/*******************  Bit definition for EXTI_IMR2 register  *******************/
+#define EXTI_IMR2_IM_Pos           (0U)
+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR2_IM32_Pos         (0U)
+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */
+#define EXTI_IMR2_IM33_Pos         (1U)
+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */
+#define EXTI_IMR2_IM34_Pos         (2U)
+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */
+#define EXTI_IMR2_IM35_Pos         (3U)
+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */
+#define EXTI_IMR2_IM36_Pos         (4U)
+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */
+#define EXTI_IMR2_IM37_Pos         (5U)
+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */
+#define EXTI_IMR2_IM38_Pos         (6U)
+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */
+#define EXTI_IMR2_IM39_Pos         (7U)
+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */
+#define EXTI_IMR2_IM40_Pos         (8U)
+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */
+#define EXTI_IMR2_IM41_Pos         (9U)
+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */
+#define EXTI_IMR2_IM42_Pos         (10U)
+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */
+#define EXTI_IMR2_IM43_Pos         (11U)
+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */
+#define EXTI_IMR2_IM44_Pos         (12U)
+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */
+#define EXTI_IMR2_IM46_Pos         (14U)
+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */
+#define EXTI_IMR2_IM47_Pos         (15U)
+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */
+#define EXTI_IMR2_IM48_Pos         (16U)
+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */
+#define EXTI_IMR2_IM49_Pos         (17U)
+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */
+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */
+#define EXTI_IMR2_IM50_Pos         (18U)
+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */
+#define EXTI_IMR2_IM51_Pos         (19U)
+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */
+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */
+#define EXTI_IMR2_IM52_Pos         (20U)
+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */
+#define EXTI_IMR2_IM53_Pos         (21U)
+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */
+#define EXTI_IMR2_IM54_Pos         (22U)
+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */
+#define EXTI_IMR2_IM55_Pos         (23U)
+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */
+#define EXTI_IMR2_IM56_Pos         (24U)
+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */
+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */
+#define EXTI_IMR2_IM57_Pos         (25U)
+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */
+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */
+#define EXTI_IMR2_IM58_Pos         (26U)
+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */
+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */
+#define EXTI_IMR2_IM59_Pos         (27U)
+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */
+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */
+#define EXTI_IMR2_IM60_Pos         (28U)
+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */
+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */
+#define EXTI_IMR2_IM61_Pos         (29U)
+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */
+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */
+#define EXTI_IMR2_IM62_Pos         (30U)
+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */
+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */
+#define EXTI_IMR2_IM63_Pos         (31U)
+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */
+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */
+
+/*******************  Bit definition for EXTI_EMR2 register  *******************/
+#define EXTI_EMR2_EM_Pos           (0U)
+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */
+#define EXTI_EMR2_EM32_Pos         (0U)
+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/
+#define EXTI_EMR2_EM33_Pos         (1U)
+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/
+#define EXTI_EMR2_EM34_Pos         (2U)
+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/
+#define EXTI_EMR2_EM35_Pos         (3U)
+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/
+#define EXTI_EMR2_EM36_Pos         (4U)
+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/
+#define EXTI_EMR2_EM37_Pos         (5U)
+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/
+#define EXTI_EMR2_EM38_Pos         (6U)
+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/
+#define EXTI_EMR2_EM39_Pos         (7U)
+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/
+#define EXTI_EMR2_EM40_Pos         (8U)
+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/
+#define EXTI_EMR2_EM41_Pos         (9U)
+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/
+#define EXTI_EMR2_EM42_Pos         (10U)
+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */
+#define EXTI_EMR2_EM43_Pos         (11U)
+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */
+#define EXTI_EMR2_EM44_Pos         (12U)
+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */
+#define EXTI_EMR2_EM46_Pos         (14U)
+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */
+#define EXTI_EMR2_EM47_Pos         (15U)
+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */
+#define EXTI_EMR2_EM48_Pos         (16U)
+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */
+#define EXTI_EMR2_EM49_Pos         (17U)
+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */
+#define EXTI_EMR2_EM50_Pos         (18U)
+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */
+#define EXTI_EMR2_EM51_Pos         (19U)
+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */
+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */
+#define EXTI_EMR2_EM52_Pos         (20U)
+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */
+#define EXTI_EMR2_EM53_Pos         (21U)
+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */
+#define EXTI_EMR2_EM54_Pos         (22U)
+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */
+#define EXTI_EMR2_EM55_Pos         (23U)
+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */
+#define EXTI_EMR2_EM56_Pos         (24U)
+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */
+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */
+#define EXTI_EMR2_EM57_Pos         (25U)
+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */
+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */
+#define EXTI_EMR2_EM58_Pos         (26U)
+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */
+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */
+#define EXTI_EMR2_EM59_Pos         (27U)
+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */
+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */
+#define EXTI_EMR2_EM60_Pos         (28U)
+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */
+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */
+#define EXTI_EMR2_EM61_Pos         (29U)
+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */
+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */
+#define EXTI_EMR2_EM62_Pos         (30U)
+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */
+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */
+#define EXTI_EMR2_EM63_Pos         (31U)
+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */
+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */
+
+/*******************  Bit definition for EXTI_PR2 register  ********************/
+#define EXTI_PR2_PR_Pos            (17U)
+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */
+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR2_PR49_Pos          (17U)
+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */
+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */
+#define EXTI_PR2_PR51_Pos          (19U)
+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */
+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */
+
+/*******************  Bit definition for EXTI_IMR3 register  *******************/
+#define EXTI_IMR3_IM_Pos           (0U)
+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */
+#define EXTI_IMR3_IM64_Pos         (0U)
+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */
+#define EXTI_IMR3_IM65_Pos         (1U)
+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */
+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */
+#define EXTI_IMR3_IM66_Pos         (2U)
+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */
+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */
+#define EXTI_IMR3_IM67_Pos         (3U)
+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */
+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */
+#define EXTI_IMR3_IM68_Pos         (4U)
+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */
+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */
+#define EXTI_IMR3_IM69_Pos         (5U)
+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */
+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */
+#define EXTI_IMR3_IM70_Pos         (6U)
+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */
+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */
+#define EXTI_IMR3_IM71_Pos         (7U)
+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */
+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */
+#define EXTI_IMR3_IM72_Pos         (8U)
+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */
+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */
+#define EXTI_IMR3_IM73_Pos         (9U)
+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */
+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */
+#define EXTI_IMR3_IM74_Pos         (10U)
+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */
+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */
+#define EXTI_IMR3_IM75_Pos         (11U)
+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */
+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */
+#define EXTI_IMR3_IM76_Pos         (12U)
+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */
+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */
+#define EXTI_IMR3_IM77_Pos         (13U)
+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */
+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */
+#define EXTI_IMR3_IM78_Pos         (14U)
+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */
+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */
+#define EXTI_IMR3_IM79_Pos         (15U)
+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */
+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */
+#define EXTI_IMR3_IM80_Pos         (16U)
+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */
+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */
+#define EXTI_IMR3_IM82_Pos         (18U)
+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */
+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */
+#define EXTI_IMR3_IM84_Pos         (20U)
+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */
+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */
+#define EXTI_IMR3_IM85_Pos         (21U)
+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */
+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */
+#define EXTI_IMR3_IM86_Pos         (22U)
+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */
+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */
+#define EXTI_IMR3_IM87_Pos         (23U)
+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */
+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */
+
+
+/*******************  Bit definition for EXTI_EMR3 register  *******************/
+#define EXTI_EMR3_EM_Pos           (0U)
+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */
+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */
+#define EXTI_EMR3_EM64_Pos         (0U)
+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */
+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/
+#define EXTI_EMR3_EM65_Pos         (1U)
+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */
+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/
+#define EXTI_EMR3_EM66_Pos         (2U)
+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */
+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/
+#define EXTI_EMR3_EM67_Pos         (3U)
+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */
+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/
+#define EXTI_EMR3_EM68_Pos         (4U)
+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */
+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/
+#define EXTI_EMR3_EM69_Pos         (5U)
+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */
+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/
+#define EXTI_EMR3_EM70_Pos         (6U)
+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */
+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/
+#define EXTI_EMR3_EM71_Pos         (7U)
+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */
+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/
+#define EXTI_EMR3_EM72_Pos         (8U)
+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */
+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/
+#define EXTI_EMR3_EM73_Pos         (9U)
+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */
+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/
+#define EXTI_EMR3_EM74_Pos         (10U)
+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */
+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */
+#define EXTI_EMR3_EM75_Pos         (11U)
+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */
+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */
+#define EXTI_EMR3_EM76_Pos         (12U)
+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */
+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */
+#define EXTI_EMR3_EM77_Pos         (13U)
+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */
+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */
+#define EXTI_EMR3_EM78_Pos         (14U)
+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */
+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */
+#define EXTI_EMR3_EM79_Pos         (15U)
+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */
+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */
+#define EXTI_EMR3_EM80_Pos         (16U)
+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */
+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */
+#define EXTI_EMR3_EM81_Pos         (17U)
+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */
+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */
+#define EXTI_EMR3_EM82_Pos         (18U)
+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */
+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */
+#define EXTI_EMR3_EM84_Pos         (20U)
+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */
+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */
+#define EXTI_EMR3_EM85_Pos         (21U)
+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */
+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */
+#define EXTI_EMR3_EM86_Pos         (22U)
+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */
+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */
+#define EXTI_EMR3_EM87_Pos         (23U)
+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */
+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */
+
+/*******************  Bit definition for EXTI_PR3 register  ********************/
+#define EXTI_PR3_PR_Pos            (18U)
+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */
+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */
+#define EXTI_PR3_PR82_Pos          (18U)
+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */
+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */
+#define EXTI_PR3_PR84_Pos          (20U)
+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */
+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */
+#define EXTI_PR3_PR85_Pos          (21U)
+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */
+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */
+#define EXTI_PR3_PR86_Pos          (22U)
+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */
+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief FLASH Global Defines
+*/
+#if defined(CORE_CM4)
+#define FLASH_SIZE                           0x100000UL            /* 1 MB   */
+#else
+#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
+#define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
+                                             ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
+                                             (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
+#endif /* CORE_CM4 */
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */
+#define DUAL_BANK                                                  /* Dual-bank Flash */
+
+/*******************  Bits definition for FLASH_ACR register  **********************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)
+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)
+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)
+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)
+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)
+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
+/*******************  Bits definition for FLASH_CR register  ***********************/
+#define FLASH_CR_LOCK_Pos                    (0U)
+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */
+#define FLASH_CR_PG_Pos                      (1U)
+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */
+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */
+#define FLASH_CR_SER_Pos                     (2U)
+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */
+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */
+#define FLASH_CR_BER_Pos                     (3U)
+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */
+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */
+#define FLASH_CR_PSIZE_Pos                   (4U)
+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */
+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */
+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */
+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */
+#define FLASH_CR_FW_Pos                      (6U)
+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */
+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */
+#define FLASH_CR_START_Pos                   (7U)
+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */
+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */
+#define FLASH_CR_SNB_Pos                     (8U)
+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */
+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */
+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */
+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */
+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */
+#define FLASH_CR_CRC_EN_Pos                  (15U)
+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */
+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */
+#define FLASH_CR_EOPIE_Pos                   (16U)
+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */
+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */
+#define FLASH_CR_WRPERRIE_Pos                (17U)
+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */
+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */
+#define FLASH_CR_PGSERRIE_Pos                (18U)
+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */
+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */
+#define FLASH_CR_STRBERRIE_Pos               (19U)
+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */
+#define FLASH_CR_INCERRIE_Pos                (21U)
+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */
+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */
+#define FLASH_CR_OPERRIE_Pos                 (22U)
+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */
+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */
+#define FLASH_CR_RDPERRIE_Pos                (23U)
+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */
+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */
+#define FLASH_CR_RDSERRIE_Pos                (24U)
+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */
+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */
+#define FLASH_CR_SNECCERRIE_Pos              (25U)
+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */
+#define FLASH_CR_DBECCERRIE_Pos              (26U)
+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */
+#define FLASH_CR_CRCENDIE_Pos                (27U)
+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */
+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */
+#define FLASH_CR_CRCRDERRIE_Pos              (28U)
+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */
+
+/*******************  Bits definition for FLASH_SR register  ***********************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */
+#define FLASH_SR_WBNE_Pos                    (1U)
+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */
+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */
+#define FLASH_SR_QW_Pos                      (2U)
+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */
+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */
+#define FLASH_SR_CRC_BUSY_Pos                (3U)
+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */
+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */
+#define FLASH_SR_EOP_Pos                     (16U)
+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */
+#define FLASH_SR_WRPERR_Pos                  (17U)
+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */
+#define FLASH_SR_PGSERR_Pos                  (18U)
+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */
+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */
+#define FLASH_SR_STRBERR_Pos                 (19U)
+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */
+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */
+#define FLASH_SR_INCERR_Pos                  (21U)
+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */
+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */
+#define FLASH_SR_OPERR_Pos                   (22U)
+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */
+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */
+#define FLASH_SR_RDPERR_Pos                  (23U)
+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */
+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */
+#define FLASH_SR_RDSERR_Pos                  (24U)
+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */
+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */
+#define FLASH_SR_SNECCERR_Pos                (25U)
+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */
+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */
+#define FLASH_SR_DBECCERR_Pos                (26U)
+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */
+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */
+#define FLASH_SR_CRCEND_Pos                  (27U)
+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */
+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */
+#define FLASH_SR_CRCRDERR_Pos                (28U)
+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */
+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */
+
+/*******************  Bits definition for FLASH_CCR register  *******************/
+#define FLASH_CCR_CLR_EOP_Pos                (16U)
+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */
+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */
+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)
+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */
+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)
+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */
+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)
+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */
+#define FLASH_CCR_CLR_INCERR_Pos             (21U)
+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */
+#define FLASH_CCR_CLR_OPERR_Pos              (22U)
+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */
+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)
+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */
+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)
+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */
+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)
+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */
+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)
+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */
+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)
+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */
+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)
+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */
+
+/*******************  Bits definition for FLASH_OPTCR register  *******************/
+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)
+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */
+#define FLASH_OPTCR_OPTSTART_Pos             (1U)
+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */
+#define FLASH_OPTCR_MER_Pos                  (4U)
+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */
+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */
+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)
+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */
+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)
+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */
+
+/*******************  Bits definition for FLASH_OPTSR register  ***************/
+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)
+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */
+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)
+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */
+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)
+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */
+#define FLASH_OPTSR_IWDG2_SW_Pos             (5U)
+#define FLASH_OPTSR_IWDG2_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */
+#define FLASH_OPTSR_IWDG2_SW                 FLASH_OPTSR_IWDG2_SW_Msk            /*!< IWDG2 control mode option status bit */
+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)
+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)
+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_RDP_Pos                  (8U)
+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */
+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */
+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)
+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)
+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */
+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)
+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */
+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
+#define FLASH_OPTSR_SECURITY_Pos             (21U)
+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */
+#define FLASH_OPTSR_BCM4_Pos                 (22U)
+#define FLASH_OPTSR_BCM4_Msk                 (0x1UL << FLASH_OPTSR_BCM4_Pos)   /*!< 0x00400000 */
+#define FLASH_OPTSR_BCM4                     FLASH_OPTSR_BCM4_Msk              /*!< Arm Cortex-M4 boot option status bit */
+#define FLASH_OPTSR_BCM7_Pos                 (23U)
+#define FLASH_OPTSR_BCM7_Msk                 (0x1UL << FLASH_OPTSR_BCM7_Pos)   /*!< 0x00800000 */
+#define FLASH_OPTSR_BCM7                     FLASH_OPTSR_BCM7_Msk              /*!< Arm Cortex-M7 boot option status bit */
+#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)
+#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */
+#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */
+#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)
+#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */
+#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */
+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)
+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */
+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)
+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */
+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)
+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */
+
+/*******************  Bits definition for FLASH_OPTCCR register  *******************/
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */
+
+/*******************  Bits definition for FLASH_PRAR register  *********************/
+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)
+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */
+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)
+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */
+#define FLASH_PRAR_DMEP_Pos                  (31U)
+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */
+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_SCAR register  *********************/
+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)
+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */
+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)
+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */
+#define FLASH_SCAR_DMES_Pos                  (31U)
+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */
+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */
+
+/*******************  Bits definition for FLASH_WPSN register  *********************/
+#define FLASH_WPSN_WRPSN_Pos                 (0U)
+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */
+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */
+
+/*******************  Bits definition for FLASH_BOOT7_CUR register  ****************/
+#define FLASH_BOOT7_BCM7_ADD0_Pos            (0U)
+#define FLASH_BOOT7_BCM7_ADD0_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT7_BCM7_ADD0                FLASH_BOOT7_BCM7_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */
+#define FLASH_BOOT7_BCM7_ADD1_Pos            (16U)
+#define FLASH_BOOT7_BCM7_ADD1_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT7_BCM7_ADD1                FLASH_BOOT7_BCM7_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */
+
+/*******************  Bits definition for FLASH_BOOT4 register  ********************/
+#define FLASH_BOOT4_BCM4_ADD0_Pos            (0U)
+#define FLASH_BOOT4_BCM4_ADD0_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */
+#define FLASH_BOOT4_BCM4_ADD0                FLASH_BOOT4_BCM4_ADD0_Msk               /*!< Arm Cortex-M4 boot address 0 */
+#define FLASH_BOOT4_BCM4_ADD1_Pos            (16U)
+#define FLASH_BOOT4_BCM4_ADD1_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */
+#define FLASH_BOOT4_BCM4_ADD1                FLASH_BOOT4_BCM4_ADD1_Msk               /*!< Arm Cortex-M4 boot address 1 */
+
+/*******************  Bits definition for FLASH_CRCCR register  ********************/
+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)
+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */
+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)
+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */
+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)
+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */
+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)
+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */
+#define FLASH_CRCCR_START_CRC_Pos            (16U)
+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */
+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)
+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */
+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)
+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */
+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)
+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */
+
+/*******************  Bits definition for FLASH_CRCSADD register  ****************/
+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)
+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */
+
+/*******************  Bits definition for FLASH_CRCEADD register  ****************/
+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)
+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */
+
+/*******************  Bits definition for FLASH_CRCDATA register  ***************/
+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)
+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */
+
+/*******************  Bits definition for FLASH_ECC_FA register  *******************/
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)
+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Flexible Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FMC_BCR1 register  *******************/
+#define FMC_BCR1_CCLKEN_Pos        (20U)
+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */
+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continuous clock enable     */
+#define FMC_BCR1_WFDIS_Pos         (21U)
+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */
+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */
+
+#define FMC_BCR1_BMAP_Pos          (24U)
+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */
+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */
+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */
+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */
+
+#define FMC_BCR1_FMCEN_Pos         (31U)
+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */
+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */
+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/
+#define FMC_BCRx_MBKEN_Pos         (0U)
+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */
+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */
+#define FMC_BCRx_MUXEN_Pos         (1U)
+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */
+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */
+
+#define FMC_BCRx_MTYP_Pos          (2U)
+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */
+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */
+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */
+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */
+
+#define FMC_BCRx_MWID_Pos          (4U)
+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */
+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */
+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */
+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */
+
+#define FMC_BCRx_FACCEN_Pos        (6U)
+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */
+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */
+#define FMC_BCRx_BURSTEN_Pos       (8U)
+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */
+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */
+#define FMC_BCRx_WAITPOL_Pos       (9U)
+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */
+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */
+#define FMC_BCRx_WAITCFG_Pos       (11U)
+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */
+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */
+#define FMC_BCRx_WREN_Pos          (12U)
+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */
+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */
+#define FMC_BCRx_WAITEN_Pos        (13U)
+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */
+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */
+#define FMC_BCRx_EXTMOD_Pos        (14U)
+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */
+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */
+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)
+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */
+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */
+
+#define FMC_BCRx_CPSIZE_Pos        (16U)
+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */
+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */
+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */
+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */
+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */
+
+#define FMC_BCRx_CBURSTRW_Pos      (19U)
+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */
+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */
+
+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/
+#define FMC_BTRx_ADDSET_Pos        (0U)
+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */
+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */
+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */
+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */
+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */
+
+#define FMC_BTRx_ADDHLD_Pos        (4U)
+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */
+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */
+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */
+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */
+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */
+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */
+
+#define FMC_BTRx_DATAST_Pos        (8U)
+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */
+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */
+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */
+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */
+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */
+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */
+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */
+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */
+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */
+
+#define FMC_BTRx_BUSTURN_Pos       (16U)
+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */
+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */
+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */
+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */
+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */
+
+#define FMC_BTRx_CLKDIV_Pos        (20U)
+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */
+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */
+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */
+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */
+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */
+
+#define FMC_BTRx_DATLAT_Pos        (24U)
+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */
+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */
+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */
+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */
+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */
+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */
+
+#define FMC_BTRx_ACCMOD_Pos        (28U)
+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */
+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */
+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/
+#define FMC_BWTRx_ADDSET_Pos       (0U)
+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */
+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */
+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */
+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */
+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */
+
+#define FMC_BWTRx_ADDHLD_Pos       (4U)
+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */
+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */
+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */
+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */
+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */
+
+#define FMC_BWTRx_DATAST_Pos       (8U)
+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */
+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */
+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */
+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */
+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */
+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */
+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */
+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */
+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */
+
+#define FMC_BWTRx_BUSTURN_Pos      (16U)
+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */
+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */
+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */
+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */
+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */
+
+#define FMC_BWTRx_ACCMOD_Pos       (28U)
+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */
+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */
+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */
+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */
+
+/******************  Bit definition for FMC_PCR register  *******************/
+#define FMC_PCR_PWAITEN_Pos        (1U)
+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */
+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */
+#define FMC_PCR_PBKEN_Pos          (2U)
+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */
+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */
+
+#define FMC_PCR_PWID_Pos           (4U)
+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */
+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */
+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */
+
+#define FMC_PCR_ECCEN_Pos          (6U)
+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */
+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */
+
+#define FMC_PCR_TCLR_Pos           (9U)
+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */
+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */
+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */
+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */
+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */
+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */
+
+#define FMC_PCR_TAR_Pos            (13U)
+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */
+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */
+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */
+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */
+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */
+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */
+
+#define FMC_PCR_ECCPS_Pos          (17U)
+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */
+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */
+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */
+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */
+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */
+
+/*******************  Bit definition for FMC_SR register  *******************/
+#define FMC_SR_IRS_Pos             (0U)
+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */
+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */
+#define FMC_SR_ILS_Pos             (1U)
+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */
+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */
+#define FMC_SR_IFS_Pos             (2U)
+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */
+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */
+#define FMC_SR_IREN_Pos            (3U)
+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */
+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */
+#define FMC_SR_ILEN_Pos            (4U)
+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */
+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */
+#define FMC_SR_IFEN_Pos            (5U)
+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */
+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */
+#define FMC_SR_FEMPT_Pos           (6U)
+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */
+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */
+
+/******************  Bit definition for FMC_PMEM register  ******************/
+#define FMC_PMEM_MEMSET_Pos       (0U)
+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */
+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */
+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */
+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */
+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */
+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */
+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */
+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */
+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */
+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PMEM_MEMWAIT_Pos      (8U)
+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */
+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PMEM_MEMHOLD_Pos      (16U)
+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */
+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PMEM_MEMHIZ_Pos       (24U)
+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_PATT register  ******************/
+#define FMC_PATT_ATTSET_Pos       (0U)
+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */
+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */
+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */
+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */
+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */
+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */
+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */
+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */
+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */
+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */
+
+#define FMC_PATT_ATTWAIT_Pos      (8U)
+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */
+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */
+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */
+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */
+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */
+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */
+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */
+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */
+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */
+
+#define FMC_PATT_ATTHOLD_Pos      (16U)
+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */
+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */
+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */
+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */
+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */
+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */
+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */
+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */
+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */
+
+#define FMC_PATT_ATTHIZ_Pos       (24U)
+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */
+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */
+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */
+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */
+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */
+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */
+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */
+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */
+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */
+
+/******************  Bit definition for FMC_ECCR3 register  ******************/
+#define FMC_ECCR3_ECC3_Pos         (0U)
+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */
+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */
+
+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/
+#define FMC_SDCRx_NC_Pos           (0U)
+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */
+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */
+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */
+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */
+
+#define FMC_SDCRx_NR_Pos           (2U)
+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */
+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */
+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */
+
+#define FMC_SDCRx_MWID_Pos         (4U)
+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */
+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */
+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */
+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */
+
+#define FMC_SDCRx_NB_Pos           (6U)
+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */
+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */
+
+#define FMC_SDCRx_CAS_Pos          (7U)
+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */
+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */
+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */
+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */
+
+#define FMC_SDCRx_WP_Pos           (9U)
+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */
+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */
+
+#define FMC_SDCRx_SDCLK_Pos        (10U)
+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */
+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */
+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */
+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */
+
+#define FMC_SDCRx_RBURST_Pos       (12U)
+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */
+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */
+
+#define FMC_SDCRx_RPIPE_Pos        (13U)
+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */
+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */
+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */
+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */
+
+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/
+#define FMC_SDTRx_TMRD_Pos         (0U)
+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */
+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */
+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */
+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */
+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */
+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */
+
+#define FMC_SDTRx_TXSR_Pos         (4U)
+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */
+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */
+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */
+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */
+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */
+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */
+
+#define FMC_SDTRx_TRAS_Pos         (8U)
+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */
+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */
+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */
+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */
+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */
+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */
+
+#define FMC_SDTRx_TRC_Pos          (12U)
+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */
+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */
+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */
+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */
+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */
+
+#define FMC_SDTRx_TWR_Pos          (16U)
+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */
+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */
+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */
+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */
+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */
+
+#define FMC_SDTRx_TRP_Pos          (20U)
+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */
+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */
+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */
+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */
+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */
+
+#define FMC_SDTRx_TRCD_Pos         (24U)
+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */
+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */
+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */
+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */
+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for FMC_SDCMR register  ******************/
+#define FMC_SDCMR_MODE_Pos         (0U)
+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */
+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
+
+#define FMC_SDCMR_CTB2_Pos         (3U)
+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */
+
+#define FMC_SDCMR_CTB1_Pos         (4U)
+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */
+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */
+
+#define FMC_SDCMR_NRFS_Pos         (5U)
+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */
+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */
+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */
+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */
+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */
+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */
+
+#define FMC_SDCMR_MRD_Pos          (9U)
+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */
+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */
+
+/******************  Bit definition for FMC_SDRTR register  ******************/
+#define FMC_SDRTR_CRE_Pos          (0U)
+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */
+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */
+
+#define FMC_SDRTR_COUNT_Pos        (1U)
+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */
+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */
+
+#define FMC_SDRTR_REIE_Pos         (14U)
+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */
+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interrupt enable */
+
+/******************  Bit definition for FMC_SDSR register  ******************/
+#define FMC_SDSR_RE_Pos            (0U)
+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */
+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */
+
+#define FMC_SDSR_MODES1_Pos        (1U)
+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */
+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */
+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */
+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */
+
+#define FMC_SDSR_MODES2_Pos        (3U)
+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */
+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */
+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */
+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODE0_Pos           (0U)
+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */
+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_MODER_MODE1_Pos           (2U)
+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */
+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_MODER_MODE2_Pos           (4U)
+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */
+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_MODER_MODE3_Pos           (6U)
+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */
+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_MODER_MODE4_Pos           (8U)
+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */
+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_MODER_MODE5_Pos           (10U)
+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */
+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_MODER_MODE6_Pos           (12U)
+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */
+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_MODER_MODE7_Pos           (14U)
+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */
+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_MODER_MODE8_Pos           (16U)
+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */
+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_MODER_MODE9_Pos           (18U)
+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */
+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_MODER_MODE10_Pos          (20U)
+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */
+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_MODER_MODE11_Pos          (22U)
+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */
+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_MODER_MODE12_Pos          (24U)
+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */
+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_MODER_MODE13_Pos          (26U)
+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */
+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_MODER_MODE14_Pos          (28U)
+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */
+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_MODER_MODE15_Pos          (30U)
+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */
+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos            (0U)
+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
+#define GPIO_OTYPER_OT1_Pos            (1U)
+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
+#define GPIO_OTYPER_OT2_Pos            (2U)
+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
+#define GPIO_OTYPER_OT3_Pos            (3U)
+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
+#define GPIO_OTYPER_OT4_Pos            (4U)
+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
+#define GPIO_OTYPER_OT5_Pos            (5U)
+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
+#define GPIO_OTYPER_OT6_Pos            (6U)
+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
+#define GPIO_OTYPER_OT7_Pos            (7U)
+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
+#define GPIO_OTYPER_OT8_Pos            (8U)
+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
+#define GPIO_OTYPER_OT9_Pos            (9U)
+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
+#define GPIO_OTYPER_OT10_Pos           (10U)
+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
+#define GPIO_OTYPER_OT11_Pos           (11U)
+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
+#define GPIO_OTYPER_OT12_Pos           (12U)
+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
+#define GPIO_OTYPER_OT13_Pos           (13U)
+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
+#define GPIO_OTYPER_OT14_Pos           (14U)
+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
+#define GPIO_OTYPER_OT15_Pos           (15U)
+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */
+
+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */
+
+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */
+
+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */
+
+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */
+
+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */
+
+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */
+
+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */
+
+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */
+
+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */
+
+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */
+
+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */
+
+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */
+
+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */
+
+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */
+
+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos           (0U)
+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPD1_Pos           (2U)
+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPD2_Pos           (4U)
+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPD3_Pos           (6U)
+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPD4_Pos           (8U)
+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPD5_Pos           (10U)
+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPD6_Pos           (12U)
+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPD7_Pos           (14U)
+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPD8_Pos           (16U)
+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPD9_Pos           (18U)
+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPD10_Pos          (20U)
+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPD11_Pos          (22U)
+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPD12_Pos          (24U)
+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPD13_Pos          (26U)
+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPD14_Pos          (28U)
+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */
+
+#define GPIO_PUPDR_PUPD15_Pos          (30U)
+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos               (0U)
+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
+#define GPIO_IDR_ID1_Pos               (1U)
+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
+#define GPIO_IDR_ID2_Pos               (2U)
+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
+#define GPIO_IDR_ID3_Pos               (3U)
+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
+#define GPIO_IDR_ID4_Pos               (4U)
+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
+#define GPIO_IDR_ID5_Pos               (5U)
+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
+#define GPIO_IDR_ID6_Pos               (6U)
+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
+#define GPIO_IDR_ID7_Pos               (7U)
+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
+#define GPIO_IDR_ID8_Pos               (8U)
+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
+#define GPIO_IDR_ID9_Pos               (9U)
+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
+#define GPIO_IDR_ID10_Pos              (10U)
+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
+#define GPIO_IDR_ID11_Pos              (11U)
+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
+#define GPIO_IDR_ID12_Pos              (12U)
+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
+#define GPIO_IDR_ID13_Pos              (13U)
+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
+#define GPIO_IDR_ID14_Pos              (14U)
+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
+#define GPIO_IDR_ID15_Pos              (15U)
+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos               (0U)
+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
+#define GPIO_ODR_OD1_Pos               (1U)
+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
+#define GPIO_ODR_OD2_Pos               (2U)
+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
+#define GPIO_ODR_OD3_Pos               (3U)
+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
+#define GPIO_ODR_OD4_Pos               (4U)
+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
+#define GPIO_ODR_OD5_Pos               (5U)
+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
+#define GPIO_ODR_OD6_Pos               (6U)
+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
+#define GPIO_ODR_OD7_Pos               (7U)
+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
+#define GPIO_ODR_OD8_Pos               (8U)
+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
+#define GPIO_ODR_OD9_Pos               (9U)
+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
+#define GPIO_ODR_OD10_Pos              (10U)
+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
+#define GPIO_ODR_OD11_Pos              (11U)
+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
+#define GPIO_ODR_OD12_Pos              (12U)
+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
+#define GPIO_ODR_OD13_Pos              (13U)
+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
+#define GPIO_ODR_OD14_Pos              (14U)
+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
+#define GPIO_ODR_OD15_Pos              (15U)
+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos              (0U)
+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
+#define GPIO_BSRR_BS1_Pos              (1U)
+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
+#define GPIO_BSRR_BS2_Pos              (2U)
+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
+#define GPIO_BSRR_BS3_Pos              (3U)
+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
+#define GPIO_BSRR_BS4_Pos              (4U)
+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
+#define GPIO_BSRR_BS5_Pos              (5U)
+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
+#define GPIO_BSRR_BS6_Pos              (6U)
+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
+#define GPIO_BSRR_BS7_Pos              (7U)
+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
+#define GPIO_BSRR_BS8_Pos              (8U)
+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
+#define GPIO_BSRR_BS9_Pos              (9U)
+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
+#define GPIO_BSRR_BS10_Pos             (10U)
+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
+#define GPIO_BSRR_BS11_Pos             (11U)
+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
+#define GPIO_BSRR_BS12_Pos             (12U)
+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
+#define GPIO_BSRR_BS13_Pos             (13U)
+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
+#define GPIO_BSRR_BS14_Pos             (14U)
+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
+#define GPIO_BSRR_BS15_Pos             (15U)
+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
+#define GPIO_BSRR_BR0_Pos              (16U)
+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
+#define GPIO_BSRR_BR1_Pos              (17U)
+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
+#define GPIO_BSRR_BR2_Pos              (18U)
+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
+#define GPIO_BSRR_BR3_Pos              (19U)
+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
+#define GPIO_BSRR_BR4_Pos              (20U)
+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
+#define GPIO_BSRR_BR5_Pos              (21U)
+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
+#define GPIO_BSRR_BR6_Pos              (22U)
+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
+#define GPIO_BSRR_BR7_Pos              (23U)
+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
+#define GPIO_BSRR_BR8_Pos              (24U)
+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
+#define GPIO_BSRR_BR9_Pos              (25U)
+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
+#define GPIO_BSRR_BR10_Pos             (26U)
+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
+#define GPIO_BSRR_BR11_Pos             (27U)
+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
+#define GPIO_BSRR_BR12_Pos             (28U)
+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
+#define GPIO_BSRR_BR13_Pos             (29U)
+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
+#define GPIO_BSRR_BR14_Pos             (30U)
+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
+#define GPIO_BSRR_BR15_Pos             (31U)
+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
+
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos             (0U)
+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos             (1U)
+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos             (2U)
+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos             (3U)
+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos             (4U)
+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos             (5U)
+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos             (6U)
+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos             (7U)
+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos             (8U)
+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos             (9U)
+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos            (10U)
+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos            (11U)
+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos            (12U)
+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos            (13U)
+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos            (14U)
+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos            (15U)
+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos             (16U)
+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos           (0U)
+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos           (4U)
+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos           (8U)
+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos           (12U)
+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos           (16U)
+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos           (20U)
+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos           (24U)
+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos           (28U)
+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos           (0U)
+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos           (4U)
+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos          (8U)
+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos          (12U)
+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos          (16U)
+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos          (20U)
+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos          (24U)
+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos          (28U)
+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15
+
+/******************************************************************************/
+/*                                                                            */
+/*                        HSEM HW Semaphore                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for HSEM_R register  ********************/
+#define HSEM_R_PROCID_Pos         (0U)
+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */
+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */
+#define HSEM_R_COREID_Pos         (8U)
+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */
+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */
+#define HSEM_R_LOCK_Pos           (31U)
+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */
+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_RLR register  ******************/
+#define HSEM_RLR_PROCID_Pos       (0U)
+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */
+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */
+#define HSEM_RLR_COREID_Pos       (8U)
+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */
+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */
+#define HSEM_RLR_LOCK_Pos         (31U)
+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */
+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */
+
+/********************  Bit definition for HSEM_C1IER register  *****************/
+#define HSEM_C1IER_ISE0_Pos       (0U)
+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE1_Pos       (1U)
+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE2_Pos       (2U)
+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE3_Pos       (3U)
+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE4_Pos       (4U)
+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */
+#define HSEM_C1IER_ISE5_Pos       (5U)
+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE6_Pos       (6U)
+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE7_Pos       (7U)
+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE8_Pos       (8U)
+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE9_Pos       (9U)
+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */
+#define HSEM_C1IER_ISE10_Pos      (10U)
+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE11_Pos      (11U)
+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE12_Pos      (12U)
+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE13_Pos      (13U)
+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE14_Pos      (14U)
+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */
+#define HSEM_C1IER_ISE15_Pos      (15U)
+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE16_Pos      (16U)
+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE17_Pos      (17U)
+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE18_Pos      (18U)
+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE19_Pos      (19U)
+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE20_Pos      (20U)
+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE21_Pos      (21U)
+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE22_Pos      (22U)
+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE23_Pos      (23U)
+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE24_Pos      (24U)
+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE25_Pos      (25U)
+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE26_Pos      (26U)
+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE27_Pos      (27U)
+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE28_Pos      (28U)
+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE29_Pos      (29U)
+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE30_Pos      (30U)
+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */
+#define HSEM_C1IER_ISE31_Pos      (31U)
+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */
+
+/********************  Bit definition for HSEM_C1ICR register  *****************/
+#define HSEM_C1ICR_ISC0_Pos       (0U)
+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC1_Pos       (1U)
+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC2_Pos       (2U)
+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC3_Pos       (3U)
+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC4_Pos       (4U)
+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC5_Pos       (5U)
+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC6_Pos       (6U)
+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC7_Pos       (7U)
+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC8_Pos       (8U)
+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC9_Pos       (9U)
+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */
+#define HSEM_C1ICR_ISC10_Pos      (10U)
+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC11_Pos      (11U)
+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC12_Pos      (12U)
+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC13_Pos      (13U)
+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC14_Pos      (14U)
+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC15_Pos      (15U)
+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC16_Pos      (16U)
+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC17_Pos      (17U)
+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC18_Pos      (18U)
+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC19_Pos      (19U)
+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC20_Pos      (20U)
+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC21_Pos      (21U)
+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC22_Pos      (22U)
+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC23_Pos      (23U)
+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC24_Pos      (24U)
+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC25_Pos      (25U)
+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC26_Pos      (26U)
+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC27_Pos      (27U)
+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC28_Pos      (28U)
+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC29_Pos      (29U)
+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC30_Pos      (30U)
+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */
+#define HSEM_C1ICR_ISC31_Pos      (31U)
+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */
+
+/********************  Bit definition for HSEM_C1ISR register  *****************/
+#define HSEM_C1ISR_ISF0_Pos       (0U)
+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF1_Pos       (1U)
+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF2_Pos       (2U)
+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF3_Pos       (3U)
+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF4_Pos       (4U)
+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF5_Pos       (5U)
+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF6_Pos       (6U)
+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF7_Pos       (7U)
+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF8_Pos       (8U)
+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF9_Pos       (9U)
+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */
+#define HSEM_C1ISR_ISF10_Pos      (10U)
+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF11_Pos      (11U)
+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF12_Pos      (12U)
+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF13_Pos      (13U)
+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF14_Pos      (14U)
+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF15_Pos      (15U)
+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF16_Pos      (16U)
+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF17_Pos      (17U)
+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF18_Pos      (18U)
+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF19_Pos      (19U)
+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF20_Pos      (20U)
+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF21_Pos      (21U)
+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF22_Pos      (22U)
+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF23_Pos      (23U)
+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF24_Pos      (24U)
+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF25_Pos      (25U)
+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF26_Pos      (26U)
+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF27_Pos      (27U)
+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF28_Pos      (28U)
+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF29_Pos      (29U)
+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF30_Pos      (30U)
+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */
+#define HSEM_C1ISR_ISF31_Pos      (31U)
+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */
+
+/********************  Bit definition for HSEM_C1MISR register  *****************/
+#define HSEM_C1MISR_MISF0_Pos     (0U)
+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF1_Pos     (1U)
+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF2_Pos     (2U)
+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF3_Pos     (3U)
+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF4_Pos     (4U)
+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF5_Pos     (5U)
+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF6_Pos     (6U)
+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF7_Pos     (7U)
+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF8_Pos     (8U)
+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF9_Pos     (9U)
+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */
+#define HSEM_C1MISR_MISF10_Pos    (10U)
+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF11_Pos    (11U)
+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF12_Pos    (12U)
+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF13_Pos    (13U)
+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF14_Pos    (14U)
+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF15_Pos    (15U)
+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF16_Pos    (16U)
+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF17_Pos    (17U)
+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF18_Pos    (18U)
+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF19_Pos    (19U)
+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF20_Pos    (20U)
+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF21_Pos    (21U)
+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF22_Pos    (22U)
+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF23_Pos    (23U)
+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF24_Pos    (24U)
+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF25_Pos    (25U)
+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF26_Pos    (26U)
+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF27_Pos    (27U)
+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF28_Pos    (28U)
+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF29_Pos    (29U)
+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF30_Pos    (30U)
+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */
+#define HSEM_C1MISR_MISF31_Pos    (31U)
+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */
+
+/********************  Bit definition for HSEM_C2IER register  *****************/
+#define HSEM_C2IER_ISE0_Pos       (0U)
+#define HSEM_C2IER_ISE0_Msk       (0x1UL << HSEM_C2IER_ISE0_Pos)               /*!< 0x00000001 */
+#define HSEM_C2IER_ISE0           HSEM_C2IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE1_Pos       (1U)
+#define HSEM_C2IER_ISE1_Msk       (0x1UL << HSEM_C2IER_ISE1_Pos)               /*!< 0x00000002 */
+#define HSEM_C2IER_ISE1           HSEM_C2IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE2_Pos       (2U)
+#define HSEM_C2IER_ISE2_Msk       (0x1UL << HSEM_C2IER_ISE2_Pos)               /*!< 0x00000004 */
+#define HSEM_C2IER_ISE2           HSEM_C2IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE3_Pos       (3U)
+#define HSEM_C2IER_ISE3_Msk       (0x1UL << HSEM_C2IER_ISE3_Pos)               /*!< 0x00000008 */
+#define HSEM_C2IER_ISE3           HSEM_C2IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE4_Pos       (4U)
+#define HSEM_C2IER_ISE4_Msk       (0x1UL << HSEM_C2IER_ISE4_Pos)               /*!< 0x00000010 */
+#define HSEM_C2IER_ISE4           HSEM_C2IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE5_Pos       (5U)
+#define HSEM_C2IER_ISE5_Msk       (0x1UL << HSEM_C2IER_ISE5_Pos)               /*!< 0x00000020 */
+#define HSEM_C2IER_ISE5           HSEM_C2IER_ISE5_Msk                          /*!<semaphore 5 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE6_Pos       (6U)
+#define HSEM_C2IER_ISE6_Msk       (0x1UL << HSEM_C2IER_ISE6_Pos)               /*!< 0x00000040 */
+#define HSEM_C2IER_ISE6           HSEM_C2IER_ISE6_Msk                          /*!<semaphore 6 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE7_Pos       (7U)
+#define HSEM_C2IER_ISE7_Msk       (0x1UL << HSEM_C2IER_ISE7_Pos)               /*!< 0x00000080 */
+#define HSEM_C2IER_ISE7           HSEM_C2IER_ISE7_Msk                          /*!<semaphore 7 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE8_Pos       (8U)
+#define HSEM_C2IER_ISE8_Msk       (0x1UL << HSEM_C2IER_ISE8_Pos)               /*!< 0x00000100 */
+#define HSEM_C2IER_ISE8           HSEM_C2IER_ISE8_Msk                          /*!<semaphore 8 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE9_Pos       (9U)
+#define HSEM_C2IER_ISE9_Msk       (0x1UL << HSEM_C2IER_ISE9_Pos)               /*!< 0x00000200 */
+#define HSEM_C2IER_ISE9           HSEM_C2IER_ISE9_Msk                          /*!<semaphore 9 interrupt 1 enable bit.  */
+#define HSEM_C2IER_ISE10_Pos      (10U)
+#define HSEM_C2IER_ISE10_Msk      (0x1UL << HSEM_C2IER_ISE10_Pos)              /*!< 0x00000400 */
+#define HSEM_C2IER_ISE10          HSEM_C2IER_ISE10_Msk                         /*!<semaphore 10 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE11_Pos      (11U)
+#define HSEM_C2IER_ISE11_Msk      (0x1UL << HSEM_C2IER_ISE11_Pos)              /*!< 0x00000800 */
+#define HSEM_C2IER_ISE11          HSEM_C2IER_ISE11_Msk                         /*!<semaphore 11 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE12_Pos      (12U)
+#define HSEM_C2IER_ISE12_Msk      (0x1UL << HSEM_C2IER_ISE12_Pos)              /*!< 0x00001000 */
+#define HSEM_C2IER_ISE12          HSEM_C2IER_ISE12_Msk                         /*!<semaphore 12 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE13_Pos      (13U)
+#define HSEM_C2IER_ISE13_Msk      (0x1UL << HSEM_C2IER_ISE13_Pos)              /*!< 0x00002000 */
+#define HSEM_C2IER_ISE13          HSEM_C2IER_ISE13_Msk                         /*!<semaphore 13 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE14_Pos      (14U)
+#define HSEM_C2IER_ISE14_Msk      (0x1UL << HSEM_C2IER_ISE14_Pos)              /*!< 0x00004000 */
+#define HSEM_C2IER_ISE14          HSEM_C2IER_ISE14_Msk                         /*!<semaphore 14 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE15_Pos      (15U)
+#define HSEM_C2IER_ISE15_Msk      (0x1UL << HSEM_C2IER_ISE15_Pos)              /*!< 0x00008000 */
+#define HSEM_C2IER_ISE15          HSEM_C2IER_ISE15_Msk                         /*!<semaphore 15 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE16_Pos      (16U)
+#define HSEM_C2IER_ISE16_Msk      (0x1UL << HSEM_C2IER_ISE16_Pos)              /*!< 0x00010000 */
+#define HSEM_C2IER_ISE16          HSEM_C2IER_ISE16_Msk                         /*!<semaphore 16 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE17_Pos      (17U)
+#define HSEM_C2IER_ISE17_Msk      (0x1UL << HSEM_C2IER_ISE17_Pos)              /*!< 0x00020000 */
+#define HSEM_C2IER_ISE17          HSEM_C2IER_ISE17_Msk                         /*!<semaphore 17 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE18_Pos      (18U)
+#define HSEM_C2IER_ISE18_Msk      (0x1UL << HSEM_C2IER_ISE18_Pos)              /*!< 0x00040000 */
+#define HSEM_C2IER_ISE18          HSEM_C2IER_ISE18_Msk                         /*!<semaphore 18 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE19_Pos      (19U)
+#define HSEM_C2IER_ISE19_Msk      (0x1UL << HSEM_C2IER_ISE19_Pos)              /*!< 0x00080000 */
+#define HSEM_C2IER_ISE19          HSEM_C2IER_ISE19_Msk                         /*!<semaphore 19 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE20_Pos      (20U)
+#define HSEM_C2IER_ISE20_Msk      (0x1UL << HSEM_C2IER_ISE20_Pos)              /*!< 0x00100000 */
+#define HSEM_C2IER_ISE20          HSEM_C2IER_ISE20_Msk                         /*!<semaphore 20 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE21_Pos      (21U)
+#define HSEM_C2IER_ISE21_Msk      (0x1UL << HSEM_C2IER_ISE21_Pos)              /*!< 0x00200000 */
+#define HSEM_C2IER_ISE21          HSEM_C2IER_ISE21_Msk                         /*!<semaphore 21 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE22_Pos      (22U)
+#define HSEM_C2IER_ISE22_Msk      (0x1UL << HSEM_C2IER_ISE22_Pos)              /*!< 0x00400000 */
+#define HSEM_C2IER_ISE22          HSEM_C2IER_ISE22_Msk                         /*!<semaphore 22 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE23_Pos      (23U)
+#define HSEM_C2IER_ISE23_Msk      (0x1UL << HSEM_C2IER_ISE23_Pos)              /*!< 0x00800000 */
+#define HSEM_C2IER_ISE23          HSEM_C2IER_ISE23_Msk                         /*!<semaphore 23 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE24_Pos      (24U)
+#define HSEM_C2IER_ISE24_Msk      (0x1UL << HSEM_C2IER_ISE24_Pos)              /*!< 0x01000000 */
+#define HSEM_C2IER_ISE24          HSEM_C2IER_ISE24_Msk                         /*!<semaphore 24 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE25_Pos      (25U)
+#define HSEM_C2IER_ISE25_Msk      (0x1UL << HSEM_C2IER_ISE25_Pos)              /*!< 0x02000000 */
+#define HSEM_C2IER_ISE25          HSEM_C2IER_ISE25_Msk                         /*!<semaphore 25 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE26_Pos      (26U)
+#define HSEM_C2IER_ISE26_Msk      (0x1UL << HSEM_C2IER_ISE26_Pos)              /*!< 0x04000000 */
+#define HSEM_C2IER_ISE26          HSEM_C2IER_ISE26_Msk                         /*!<semaphore 26 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE27_Pos      (27U)
+#define HSEM_C2IER_ISE27_Msk      (0x1UL << HSEM_C2IER_ISE27_Pos)              /*!< 0x08000000 */
+#define HSEM_C2IER_ISE27          HSEM_C2IER_ISE27_Msk                         /*!<semaphore 27 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE28_Pos      (28U)
+#define HSEM_C2IER_ISE28_Msk      (0x1UL << HSEM_C2IER_ISE28_Pos)              /*!< 0x10000000 */
+#define HSEM_C2IER_ISE28          HSEM_C2IER_ISE28_Msk                         /*!<semaphore 28 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE29_Pos      (29U)
+#define HSEM_C2IER_ISE29_Msk      (0x1UL << HSEM_C2IER_ISE29_Pos)              /*!< 0x20000000 */
+#define HSEM_C2IER_ISE29          HSEM_C2IER_ISE29_Msk                         /*!<semaphore 29 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE30_Pos      (30U)
+#define HSEM_C2IER_ISE30_Msk      (0x1UL << HSEM_C2IER_ISE30_Pos)              /*!< 0x40000000 */
+#define HSEM_C2IER_ISE30          HSEM_C2IER_ISE30_Msk                         /*!<semaphore 30 interrupt 1 enable bit. */
+#define HSEM_C2IER_ISE31_Pos      (31U)
+#define HSEM_C2IER_ISE31_Msk      (0x1UL << HSEM_C2IER_ISE31_Pos)              /*!< 0x80000000 */
+#define HSEM_C2IER_ISE31          HSEM_C2IER_ISE31_Msk                         /*!<semaphore 31 interrupt 1 enable bit. */
+
+/********************  Bit definition for HSEM_C2ICR register  *****************/
+#define HSEM_C2ICR_ISC0_Pos       (0U)
+#define HSEM_C2ICR_ISC0_Msk       (0x1UL << HSEM_C2ICR_ISC0_Pos)               /*!< 0x00000001 */
+#define HSEM_C2ICR_ISC0           HSEM_C2ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC1_Pos       (1U)
+#define HSEM_C2ICR_ISC1_Msk       (0x1UL << HSEM_C2ICR_ISC1_Pos)               /*!< 0x00000002 */
+#define HSEM_C2ICR_ISC1           HSEM_C2ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC2_Pos       (2U)
+#define HSEM_C2ICR_ISC2_Msk       (0x1UL << HSEM_C2ICR_ISC2_Pos)               /*!< 0x00000004 */
+#define HSEM_C2ICR_ISC2           HSEM_C2ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC3_Pos       (3U)
+#define HSEM_C2ICR_ISC3_Msk       (0x1UL << HSEM_C2ICR_ISC3_Pos)               /*!< 0x00000008 */
+#define HSEM_C2ICR_ISC3           HSEM_C2ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC4_Pos       (4U)
+#define HSEM_C2ICR_ISC4_Msk       (0x1UL << HSEM_C2ICR_ISC4_Pos)               /*!< 0x00000010 */
+#define HSEM_C2ICR_ISC4           HSEM_C2ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC5_Pos       (5U)
+#define HSEM_C2ICR_ISC5_Msk       (0x1UL << HSEM_C2ICR_ISC5_Pos)               /*!< 0x00000020 */
+#define HSEM_C2ICR_ISC5           HSEM_C2ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC6_Pos       (6U)
+#define HSEM_C2ICR_ISC6_Msk       (0x1UL << HSEM_C2ICR_ISC6_Pos)               /*!< 0x00000040 */
+#define HSEM_C2ICR_ISC6           HSEM_C2ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC7_Pos       (7U)
+#define HSEM_C2ICR_ISC7_Msk       (0x1UL << HSEM_C2ICR_ISC7_Pos)               /*!< 0x00000080 */
+#define HSEM_C2ICR_ISC7           HSEM_C2ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC8_Pos       (8U)
+#define HSEM_C2ICR_ISC8_Msk       (0x1UL << HSEM_C2ICR_ISC8_Pos)               /*!< 0x00000100 */
+#define HSEM_C2ICR_ISC8           HSEM_C2ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC9_Pos       (9U)
+#define HSEM_C2ICR_ISC9_Msk       (0x1UL << HSEM_C2ICR_ISC9_Pos)               /*!< 0x00000200 */
+#define HSEM_C2ICR_ISC9           HSEM_C2ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 1 clear bit.  */
+#define HSEM_C2ICR_ISC10_Pos      (10U)
+#define HSEM_C2ICR_ISC10_Msk      (0x1UL << HSEM_C2ICR_ISC10_Pos)              /*!< 0x00000400 */
+#define HSEM_C2ICR_ISC10          HSEM_C2ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC11_Pos      (11U)
+#define HSEM_C2ICR_ISC11_Msk      (0x1UL << HSEM_C2ICR_ISC11_Pos)              /*!< 0x00000800 */
+#define HSEM_C2ICR_ISC11          HSEM_C2ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC12_Pos      (12U)
+#define HSEM_C2ICR_ISC12_Msk      (0x1UL << HSEM_C2ICR_ISC12_Pos)              /*!< 0x00001000 */
+#define HSEM_C2ICR_ISC12          HSEM_C2ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC13_Pos      (13U)
+#define HSEM_C2ICR_ISC13_Msk      (0x1UL << HSEM_C2ICR_ISC13_Pos)              /*!< 0x00002000 */
+#define HSEM_C2ICR_ISC13          HSEM_C2ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC14_Pos      (14U)
+#define HSEM_C2ICR_ISC14_Msk      (0x1UL << HSEM_C2ICR_ISC14_Pos)              /*!< 0x00004000 */
+#define HSEM_C2ICR_ISC14          HSEM_C2ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC15_Pos      (15U)
+#define HSEM_C2ICR_ISC15_Msk      (0x1UL << HSEM_C2ICR_ISC15_Pos)              /*!< 0x00008000 */
+#define HSEM_C2ICR_ISC15          HSEM_C2ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC16_Pos      (16U)
+#define HSEM_C2ICR_ISC16_Msk      (0x1UL << HSEM_C2ICR_ISC16_Pos)              /*!< 0x00010000 */
+#define HSEM_C2ICR_ISC16          HSEM_C2ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC17_Pos      (17U)
+#define HSEM_C2ICR_ISC17_Msk      (0x1UL << HSEM_C2ICR_ISC17_Pos)              /*!< 0x00020000 */
+#define HSEM_C2ICR_ISC17          HSEM_C2ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC18_Pos      (18U)
+#define HSEM_C2ICR_ISC18_Msk      (0x1UL << HSEM_C2ICR_ISC18_Pos)              /*!< 0x00040000 */
+#define HSEM_C2ICR_ISC18          HSEM_C2ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC19_Pos      (19U)
+#define HSEM_C2ICR_ISC19_Msk      (0x1UL << HSEM_C2ICR_ISC19_Pos)              /*!< 0x00080000 */
+#define HSEM_C2ICR_ISC19          HSEM_C2ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC20_Pos      (20U)
+#define HSEM_C2ICR_ISC20_Msk      (0x1UL << HSEM_C2ICR_ISC20_Pos)              /*!< 0x00100000 */
+#define HSEM_C2ICR_ISC20          HSEM_C2ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC21_Pos      (21U)
+#define HSEM_C2ICR_ISC21_Msk      (0x1UL << HSEM_C2ICR_ISC21_Pos)              /*!< 0x00200000 */
+#define HSEM_C2ICR_ISC21          HSEM_C2ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC22_Pos      (22U)
+#define HSEM_C2ICR_ISC22_Msk      (0x1UL << HSEM_C2ICR_ISC22_Pos)              /*!< 0x00400000 */
+#define HSEM_C2ICR_ISC22          HSEM_C2ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC23_Pos      (23U)
+#define HSEM_C2ICR_ISC23_Msk      (0x1UL << HSEM_C2ICR_ISC23_Pos)              /*!< 0x00800000 */
+#define HSEM_C2ICR_ISC23          HSEM_C2ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC24_Pos      (24U)
+#define HSEM_C2ICR_ISC24_Msk      (0x1UL << HSEM_C2ICR_ISC24_Pos)              /*!< 0x01000000 */
+#define HSEM_C2ICR_ISC24          HSEM_C2ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC25_Pos      (25U)
+#define HSEM_C2ICR_ISC25_Msk      (0x1UL << HSEM_C2ICR_ISC25_Pos)              /*!< 0x02000000 */
+#define HSEM_C2ICR_ISC25          HSEM_C2ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC26_Pos      (26U)
+#define HSEM_C2ICR_ISC26_Msk      (0x1UL << HSEM_C2ICR_ISC26_Pos)              /*!< 0x04000000 */
+#define HSEM_C2ICR_ISC26          HSEM_C2ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC27_Pos      (27U)
+#define HSEM_C2ICR_ISC27_Msk      (0x1UL << HSEM_C2ICR_ISC27_Pos)              /*!< 0x08000000 */
+#define HSEM_C2ICR_ISC27          HSEM_C2ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC28_Pos      (28U)
+#define HSEM_C2ICR_ISC28_Msk      (0x1UL << HSEM_C2ICR_ISC28_Pos)              /*!< 0x10000000 */
+#define HSEM_C2ICR_ISC28          HSEM_C2ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC29_Pos      (29U)
+#define HSEM_C2ICR_ISC29_Msk      (0x1UL << HSEM_C2ICR_ISC29_Pos)              /*!< 0x20000000 */
+#define HSEM_C2ICR_ISC29          HSEM_C2ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC30_Pos      (30U)
+#define HSEM_C2ICR_ISC30_Msk      (0x1UL << HSEM_C2ICR_ISC30_Pos)              /*!< 0x40000000 */
+#define HSEM_C2ICR_ISC30          HSEM_C2ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 1 clear bit. */
+#define HSEM_C2ICR_ISC31_Pos      (31U)
+#define HSEM_C2ICR_ISC31_Msk      (0x1UL << HSEM_C2ICR_ISC31_Pos)              /*!< 0x80000000 */
+#define HSEM_C2ICR_ISC31          HSEM_C2ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 1 clear bit. */
+
+/********************  Bit definition for HSEM_C2ISR register  *****************/
+#define HSEM_C2ISR_ISF0_Pos       (0U)
+#define HSEM_C2ISR_ISF0_Msk       (0x1UL << HSEM_C2ISR_ISF0_Pos)               /*!< 0x00000001 */
+#define HSEM_C2ISR_ISF0           HSEM_C2ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF1_Pos       (1U)
+#define HSEM_C2ISR_ISF1_Msk       (0x1UL << HSEM_C2ISR_ISF1_Pos)               /*!< 0x00000002 */
+#define HSEM_C2ISR_ISF1           HSEM_C2ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF2_Pos       (2U)
+#define HSEM_C2ISR_ISF2_Msk       (0x1UL << HSEM_C2ISR_ISF2_Pos)               /*!< 0x00000004 */
+#define HSEM_C2ISR_ISF2           HSEM_C2ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF3_Pos       (3U)
+#define HSEM_C2ISR_ISF3_Msk       (0x1UL << HSEM_C2ISR_ISF3_Pos)               /*!< 0x00000008 */
+#define HSEM_C2ISR_ISF3           HSEM_C2ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF4_Pos       (4U)
+#define HSEM_C2ISR_ISF4_Msk       (0x1UL << HSEM_C2ISR_ISF4_Pos)               /*!< 0x00000010 */
+#define HSEM_C2ISR_ISF4           HSEM_C2ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF5_Pos       (5U)
+#define HSEM_C2ISR_ISF5_Msk       (0x1UL << HSEM_C2ISR_ISF5_Pos)               /*!< 0x00000020 */
+#define HSEM_C2ISR_ISF5           HSEM_C2ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF6_Pos       (6U)
+#define HSEM_C2ISR_ISF6_Msk       (0x1UL << HSEM_C2ISR_ISF6_Pos)               /*!< 0x00000040 */
+#define HSEM_C2ISR_ISF6           HSEM_C2ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF7_Pos       (7U)
+#define HSEM_C2ISR_ISF7_Msk       (0x1UL << HSEM_C2ISR_ISF7_Pos)               /*!< 0x00000080 */
+#define HSEM_C2ISR_ISF7           HSEM_C2ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF8_Pos       (8U)
+#define HSEM_C2ISR_ISF8_Msk       (0x1UL << HSEM_C2ISR_ISF8_Pos)               /*!< 0x00000100 */
+#define HSEM_C2ISR_ISF8           HSEM_C2ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF9_Pos       (9U)
+#define HSEM_C2ISR_ISF9_Msk       (0x1UL << HSEM_C2ISR_ISF9_Pos)               /*!< 0x00000200 */
+#define HSEM_C2ISR_ISF9           HSEM_C2ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 1 status bit.  */
+#define HSEM_C2ISR_ISF10_Pos      (10U)
+#define HSEM_C2ISR_ISF10_Msk      (0x1UL << HSEM_C2ISR_ISF10_Pos)              /*!< 0x00000400 */
+#define HSEM_C2ISR_ISF10          HSEM_C2ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF11_Pos      (11U)
+#define HSEM_C2ISR_ISF11_Msk      (0x1UL << HSEM_C2ISR_ISF11_Pos)              /*!< 0x00000800 */
+#define HSEM_C2ISR_ISF11          HSEM_C2ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF12_Pos      (12U)
+#define HSEM_C2ISR_ISF12_Msk      (0x1UL << HSEM_C2ISR_ISF12_Pos)              /*!< 0x00001000 */
+#define HSEM_C2ISR_ISF12          HSEM_C2ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF13_Pos      (13U)
+#define HSEM_C2ISR_ISF13_Msk      (0x1UL << HSEM_C2ISR_ISF13_Pos)              /*!< 0x00002000 */
+#define HSEM_C2ISR_ISF13          HSEM_C2ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF14_Pos      (14U)
+#define HSEM_C2ISR_ISF14_Msk      (0x1UL << HSEM_C2ISR_ISF14_Pos)              /*!< 0x00004000 */
+#define HSEM_C2ISR_ISF14          HSEM_C2ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF15_Pos      (15U)
+#define HSEM_C2ISR_ISF15_Msk      (0x1UL << HSEM_C2ISR_ISF15_Pos)              /*!< 0x00008000 */
+#define HSEM_C2ISR_ISF15          HSEM_C2ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF16_Pos      (16U)
+#define HSEM_C2ISR_ISF16_Msk      (0x1UL << HSEM_C2ISR_ISF16_Pos)              /*!< 0x00010000 */
+#define HSEM_C2ISR_ISF16          HSEM_C2ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF17_Pos      (17U)
+#define HSEM_C2ISR_ISF17_Msk      (0x1UL << HSEM_C2ISR_ISF17_Pos)              /*!< 0x00020000 */
+#define HSEM_C2ISR_ISF17          HSEM_C2ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF18_Pos      (18U)
+#define HSEM_C2ISR_ISF18_Msk      (0x1UL << HSEM_C2ISR_ISF18_Pos)              /*!< 0x00040000 */
+#define HSEM_C2ISR_ISF18          HSEM_C2ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF19_Pos      (19U)
+#define HSEM_C2ISR_ISF19_Msk      (0x1UL << HSEM_C2ISR_ISF19_Pos)              /*!< 0x00080000 */
+#define HSEM_C2ISR_ISF19          HSEM_C2ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF20_Pos      (20U)
+#define HSEM_C2ISR_ISF20_Msk      (0x1UL << HSEM_C2ISR_ISF20_Pos)              /*!< 0x00100000 */
+#define HSEM_C2ISR_ISF20          HSEM_C2ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF21_Pos      (21U)
+#define HSEM_C2ISR_ISF21_Msk      (0x1UL << HSEM_C2ISR_ISF21_Pos)              /*!< 0x00200000 */
+#define HSEM_C2ISR_ISF21          HSEM_C2ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF22_Pos      (22U)
+#define HSEM_C2ISR_ISF22_Msk      (0x1UL << HSEM_C2ISR_ISF22_Pos)              /*!< 0x00400000 */
+#define HSEM_C2ISR_ISF22          HSEM_C2ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF23_Pos      (23U)
+#define HSEM_C2ISR_ISF23_Msk      (0x1UL << HSEM_C2ISR_ISF23_Pos)              /*!< 0x00800000 */
+#define HSEM_C2ISR_ISF23          HSEM_C2ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF24_Pos      (24U)
+#define HSEM_C2ISR_ISF24_Msk      (0x1UL << HSEM_C2ISR_ISF24_Pos)              /*!< 0x01000000 */
+#define HSEM_C2ISR_ISF24          HSEM_C2ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF25_Pos      (25U)
+#define HSEM_C2ISR_ISF25_Msk      (0x1UL << HSEM_C2ISR_ISF25_Pos)              /*!< 0x02000000 */
+#define HSEM_C2ISR_ISF25          HSEM_C2ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF26_Pos      (26U)
+#define HSEM_C2ISR_ISF26_Msk      (0x1UL << HSEM_C2ISR_ISF26_Pos)              /*!< 0x04000000 */
+#define HSEM_C2ISR_ISF26          HSEM_C2ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF27_Pos      (27U)
+#define HSEM_C2ISR_ISF27_Msk      (0x1UL << HSEM_C2ISR_ISF27_Pos)              /*!< 0x08000000 */
+#define HSEM_C2ISR_ISF27          HSEM_C2ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF28_Pos      (28U)
+#define HSEM_C2ISR_ISF28_Msk      (0x1UL << HSEM_C2ISR_ISF28_Pos)              /*!< 0x10000000 */
+#define HSEM_C2ISR_ISF28          HSEM_C2ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF29_Pos      (29U)
+#define HSEM_C2ISR_ISF29_Msk      (0x1UL << HSEM_C2ISR_ISF29_Pos)              /*!< 0x20000000 */
+#define HSEM_C2ISR_ISF29          HSEM_C2ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF30_Pos      (30U)
+#define HSEM_C2ISR_ISF30_Msk      (0x1UL << HSEM_C2ISR_ISF30_Pos)              /*!< 0x40000000 */
+#define HSEM_C2ISR_ISF30          HSEM_C2ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 1 status bit. */
+#define HSEM_C2ISR_ISF31_Pos      (31U)
+#define HSEM_C2ISR_ISF31_Msk      (0x1UL << HSEM_C2ISR_ISF31_Pos)              /*!< 0x80000000 */
+#define HSEM_C2ISR_ISF31          HSEM_C2ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 1 status bit. */
+
+/********************  Bit definition for HSEM_C2MISR register  *****************/
+#define HSEM_C2MISR_MISF0_Pos     (0U)
+#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)             /*!< 0x00000001 */
+#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF1_Pos     (1U)
+#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)             /*!< 0x00000002 */
+#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF2_Pos     (2U)
+#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)             /*!< 0x00000004 */
+#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF3_Pos     (3U)
+#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)             /*!< 0x00000008 */
+#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF4_Pos     (4U)
+#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)             /*!< 0x00000010 */
+#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF5_Pos     (5U)
+#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)             /*!< 0x00000020 */
+#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF6_Pos     (6U)
+#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)             /*!< 0x00000040 */
+#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF7_Pos     (7U)
+#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)             /*!< 0x00000080 */
+#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF8_Pos     (8U)
+#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)             /*!< 0x00000100 */
+#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF9_Pos     (9U)
+#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)             /*!< 0x00000200 */
+#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 1 masked status bit.  */
+#define HSEM_C2MISR_MISF10_Pos    (10U)
+#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)            /*!< 0x00000400 */
+#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF11_Pos    (11U)
+#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)            /*!< 0x00000800 */
+#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF12_Pos    (12U)
+#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)            /*!< 0x00001000 */
+#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF13_Pos    (13U)
+#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)            /*!< 0x00002000 */
+#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF14_Pos    (14U)
+#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)            /*!< 0x00004000 */
+#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF15_Pos    (15U)
+#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)            /*!< 0x00008000 */
+#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF16_Pos    (16U)
+#define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)            /*!< 0x00010000 */
+#define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF17_Pos    (17U)
+#define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)            /*!< 0x00020000 */
+#define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF18_Pos    (18U)
+#define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)            /*!< 0x00040000 */
+#define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF19_Pos    (19U)
+#define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)            /*!< 0x00080000 */
+#define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF20_Pos    (20U)
+#define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)            /*!< 0x00100000 */
+#define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF21_Pos    (21U)
+#define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)            /*!< 0x00200000 */
+#define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF22_Pos    (22U)
+#define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)            /*!< 0x00400000 */
+#define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF23_Pos    (23U)
+#define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)            /*!< 0x00800000 */
+#define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF24_Pos    (24U)
+#define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)            /*!< 0x01000000 */
+#define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF25_Pos    (25U)
+#define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)            /*!< 0x02000000 */
+#define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF26_Pos    (26U)
+#define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)            /*!< 0x04000000 */
+#define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF27_Pos    (27U)
+#define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)            /*!< 0x08000000 */
+#define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF28_Pos    (28U)
+#define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)            /*!< 0x10000000 */
+#define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF29_Pos    (29U)
+#define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)            /*!< 0x20000000 */
+#define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF30_Pos    (30U)
+#define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)            /*!< 0x40000000 */
+#define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 1 masked status bit. */
+#define HSEM_C2MISR_MISF31_Pos    (31U)
+#define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)            /*!< 0x80000000 */
+#define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 1 masked status bit. */
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CR_COREID_Pos        (8U)
+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */
+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */
+#define HSEM_CR_KEY_Pos           (16U)
+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */
+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */
+
+/********************  Bit definition for HSEM_KEYR register  *****************/
+#define HSEM_KEYR_KEY_Pos         (16U)
+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */
+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface (I2C)              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define I2C_CR1_PE_Pos               (0U)
+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
+#define I2C_CR1_TXIE_Pos             (1U)
+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
+#define I2C_CR1_RXIE_Pos             (2U)
+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
+#define I2C_CR1_ADDRIE_Pos           (3U)
+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
+#define I2C_CR1_NACKIE_Pos           (4U)
+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
+#define I2C_CR1_STOPIE_Pos           (5U)
+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
+#define I2C_CR1_TCIE_Pos             (6U)
+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
+#define I2C_CR1_ERRIE_Pos            (7U)
+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
+#define I2C_CR1_DNF_Pos              (8U)
+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
+#define I2C_CR1_ANFOFF_Pos           (12U)
+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
+#define I2C_CR1_TXDMAEN_Pos          (14U)
+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
+#define I2C_CR1_RXDMAEN_Pos          (15U)
+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
+#define I2C_CR1_SBC_Pos              (16U)
+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
+#define I2C_CR1_NOSTRETCH_Pos        (17U)
+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
+#define I2C_CR1_WUPEN_Pos            (18U)
+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
+#define I2C_CR1_GCEN_Pos             (19U)
+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
+#define I2C_CR1_SMBHEN_Pos           (20U)
+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
+#define I2C_CR1_SMBDEN_Pos           (21U)
+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
+#define I2C_CR1_ALERTEN_Pos          (22U)
+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
+#define I2C_CR1_PECEN_Pos            (23U)
+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_SADD_Pos             (0U)
+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
+#define I2C_CR2_RD_WRN_Pos           (10U)
+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
+#define I2C_CR2_ADD10_Pos            (11U)
+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
+#define I2C_CR2_HEAD10R_Pos          (12U)
+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
+#define I2C_CR2_START_Pos            (13U)
+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
+#define I2C_CR2_STOP_Pos             (14U)
+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
+#define I2C_CR2_NACK_Pos             (15U)
+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
+#define I2C_CR2_NBYTES_Pos           (16U)
+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
+#define I2C_CR2_RELOAD_Pos           (24U)
+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
+#define I2C_CR2_AUTOEND_Pos          (25U)
+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
+#define I2C_CR2_PECBYTE_Pos          (26U)
+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define I2C_OAR1_OA1_Pos             (0U)
+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
+#define I2C_OAR1_OA1MODE_Pos         (10U)
+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
+#define I2C_OAR1_OA1EN_Pos           (15U)
+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define I2C_OAR2_OA2_Pos             (1U)
+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
+#define I2C_OAR2_OA2MSK_Pos          (8U)
+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */
+#define I2C_OAR2_OA2MASK01_Pos       (8U)
+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */
+#define I2C_OAR2_OA2MASK02_Pos       (9U)
+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
+#define I2C_OAR2_OA2MASK03_Pos       (8U)
+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
+#define I2C_OAR2_OA2MASK04_Pos       (10U)
+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
+#define I2C_OAR2_OA2MASK05_Pos       (8U)
+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
+#define I2C_OAR2_OA2MASK06_Pos       (9U)
+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */
+#define I2C_OAR2_OA2MASK07_Pos       (8U)
+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */
+#define I2C_OAR2_OA2EN_Pos           (15U)
+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define I2C_TIMINGR_SCLL_Pos         (0U)
+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
+#define I2C_TIMINGR_SCLH_Pos         (8U)
+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
+#define I2C_TIMINGR_SDADEL_Pos       (16U)
+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
+#define I2C_TIMINGR_SCLDEL_Pos       (20U)
+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
+#define I2C_TIMINGR_PRESC_Pos        (28U)
+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define I2C_ISR_TXE_Pos              (0U)
+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
+#define I2C_ISR_TXIS_Pos             (1U)
+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
+#define I2C_ISR_RXNE_Pos             (2U)
+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
+#define I2C_ISR_ADDR_Pos             (3U)
+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
+#define I2C_ISR_NACKF_Pos            (4U)
+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
+#define I2C_ISR_STOPF_Pos            (5U)
+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
+#define I2C_ISR_TC_Pos               (6U)
+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
+#define I2C_ISR_TCR_Pos              (7U)
+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
+#define I2C_ISR_BERR_Pos             (8U)
+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
+#define I2C_ISR_ARLO_Pos             (9U)
+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
+#define I2C_ISR_OVR_Pos              (10U)
+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
+#define I2C_ISR_PECERR_Pos           (11U)
+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
+#define I2C_ISR_TIMEOUT_Pos          (12U)
+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
+#define I2C_ISR_ALERT_Pos            (13U)
+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
+#define I2C_ISR_BUSY_Pos             (15U)
+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
+#define I2C_ISR_DIR_Pos              (16U)
+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
+#define I2C_ISR_ADDCODE_Pos          (17U)
+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define I2C_ICR_ADDRCF_Pos           (3U)
+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
+#define I2C_ICR_NACKCF_Pos           (4U)
+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
+#define I2C_ICR_STOPCF_Pos           (5U)
+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
+#define I2C_ICR_BERRCF_Pos           (8U)
+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
+#define I2C_ICR_ARLOCF_Pos           (9U)
+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
+#define I2C_ICR_OVRCF_Pos            (10U)
+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
+#define I2C_ICR_PECCF_Pos            (11U)
+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
+#define I2C_ICR_TIMOUTCF_Pos         (12U)
+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
+#define I2C_ICR_ALERTCF_Pos          (13U)
+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define I2C_PECR_PEC_Pos             (0U)
+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define I2C_RXDR_RXDATA_Pos          (0U)
+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define I2C_TXDR_TXDATA_Pos          (0U)
+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos      (0U)
+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos       (0U)
+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */
+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */
+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos      (0U)
+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos      (0U)
+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos      (1U)
+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
+#define IWDG_SR_WVU_Pos      (2U)
+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_WINR_WIN_Pos    (0U)
+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        JPEG Encoder/Decoder                                */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for CONFR0 register  ********************/
+#define JPEG_CONFR0_START_Pos           (0U)
+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */
+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */
+
+/********************  Bit definition for CONFR1 register  ********************/
+#define JPEG_CONFR1_NF_Pos              (0U)
+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */
+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */
+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */
+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */
+#define JPEG_CONFR1_DE_Pos              (3U)
+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */
+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */
+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)
+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */
+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */
+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */
+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */
+#define JPEG_CONFR1_NS_Pos              (6U)
+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */
+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */
+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR1_HDR_Pos             (8U)
+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */
+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */
+#define JPEG_CONFR1_YSIZE_Pos           (16U)
+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */
+
+/********************  Bit definition for CONFR2 register  ********************/
+#define JPEG_CONFR2_NMCU_Pos            (0U)
+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */
+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */
+
+/********************  Bit definition for CONFR3 register  ********************/
+#define JPEG_CONFR3_XSIZE_Pos           (16U)
+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */
+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */
+
+/********************  Bit definition for CONFR4 register  ********************/
+#define JPEG_CONFR4_HD_Pos              (0U)
+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR4_HA_Pos              (1U)
+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR4_QT_Pos              (2U)
+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR4_NB_Pos              (4U)
+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR4_VSF_Pos             (8U)
+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */
+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR4_HSF_Pos             (12U)
+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */
+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR5 register  ********************/
+#define JPEG_CONFR5_HD_Pos              (0U)
+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR5_HA_Pos              (1U)
+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR5_QT_Pos              (2U)
+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR5_NB_Pos              (4U)
+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR5_VSF_Pos             (8U)
+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR5_HSF_Pos             (12U)
+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR6 register  ********************/
+#define JPEG_CONFR6_HD_Pos              (0U)
+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR6_HA_Pos              (1U)
+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR6_QT_Pos              (2U)
+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR6_NB_Pos              (4U)
+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR6_VSF_Pos             (8U)
+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR6_HSF_Pos             (12U)
+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CONFR7 register  ********************/
+#define JPEG_CONFR7_HD_Pos              (0U)
+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */
+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */
+#define JPEG_CONFR7_HA_Pos              (1U)
+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */
+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */
+#define JPEG_CONFR7_QT_Pos              (2U)
+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */
+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */
+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */
+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */
+#define JPEG_CONFR7_NB_Pos              (4U)
+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */
+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */
+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */
+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */
+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */
+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */
+#define JPEG_CONFR7_VSF_Pos             (8U)
+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */
+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */
+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */
+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */
+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */
+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */
+#define JPEG_CONFR7_HSF_Pos             (12U)
+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */
+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */
+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */
+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */
+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */
+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */
+
+/********************  Bit definition for CR register  ********************/
+#define JPEG_CR_JCEN_Pos                (0U)
+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */
+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */
+#define JPEG_CR_IFTIE_Pos               (1U)
+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */
+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */
+#define JPEG_CR_IFNFIE_Pos              (2U)
+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */
+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */
+#define JPEG_CR_OFTIE_Pos               (3U)
+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */
+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */
+#define JPEG_CR_OFNEIE_Pos              (4U)
+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */
+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */
+#define JPEG_CR_EOCIE_Pos               (5U)
+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */
+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */
+#define JPEG_CR_HPDIE_Pos               (6U)
+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */
+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */
+#define JPEG_CR_IFF_Pos                 (13U)
+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */
+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */
+#define JPEG_CR_OFF_Pos                 (14U)
+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */
+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */
+
+/********************  Bit definition for SR register  ********************/
+#define JPEG_SR_IFTF_Pos                (1U)
+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
+#define JPEG_SR_IFNFF_Pos               (2U)
+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
+#define JPEG_SR_OFTF_Pos                (3U)
+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */
+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */
+#define JPEG_SR_OFNEF_Pos               (4U)
+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */
+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */
+#define JPEG_SR_EOCF_Pos                (5U)
+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */
+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
+#define JPEG_SR_HPDF_Pos                (6U)
+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */
+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
+#define JPEG_SR_COF_Pos                 (7U)
+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */
+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */
+
+/********************  Bit definition for CFR register  ********************/
+#define JPEG_CFR_CEOCF_Pos              (4U)
+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */
+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */
+#define JPEG_CFR_CHPDF_Pos              (5U)
+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */
+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */
+
+/********************  Bit definition for DIR register  ********************/
+#define JPEG_DIR_DATAIN_Pos             (0U)
+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */
+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */
+
+/********************  Bit definition for DOR register  ********************/
+#define JPEG_DOR_DATAOUT_Pos            (0U)
+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      LCD-TFT Display Controller (LTDC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for LTDC_SSCR register  *****************/
+
+#define LTDC_SSCR_VSH_Pos            (0U)
+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */
+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */
+#define LTDC_SSCR_HSW_Pos            (16U)
+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */
+
+/********************  Bit definition for LTDC_BPCR register  *****************/
+
+#define LTDC_BPCR_AVBP_Pos           (0U)
+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */
+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */
+#define LTDC_BPCR_AHBP_Pos           (16U)
+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */
+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */
+
+/********************  Bit definition for LTDC_AWCR register  *****************/
+
+#define LTDC_AWCR_AAH_Pos            (0U)
+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */
+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active height */
+#define LTDC_AWCR_AAW_Pos            (16U)
+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */
+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */
+
+/********************  Bit definition for LTDC_TWCR register  *****************/
+
+#define LTDC_TWCR_TOTALH_Pos         (0U)
+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */
+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total height */
+#define LTDC_TWCR_TOTALW_Pos         (16U)
+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */
+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */
+
+/********************  Bit definition for LTDC_GCR register  ******************/
+
+#define LTDC_GCR_LTDCEN_Pos          (0U)
+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */
+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */
+#define LTDC_GCR_DBW_Pos             (4U)
+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */
+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */
+#define LTDC_GCR_DGW_Pos             (8U)
+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */
+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */
+#define LTDC_GCR_DRW_Pos             (12U)
+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */
+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */
+#define LTDC_GCR_DEN_Pos             (16U)
+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */
+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */
+#define LTDC_GCR_PCPOL_Pos           (28U)
+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */
+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */
+#define LTDC_GCR_DEPOL_Pos           (29U)
+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */
+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */
+#define LTDC_GCR_VSPOL_Pos           (30U)
+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */
+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */
+#define LTDC_GCR_HSPOL_Pos           (31U)
+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */
+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */
+
+
+/********************  Bit definition for LTDC_SRCR register  *****************/
+
+#define LTDC_SRCR_IMR_Pos            (0U)
+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */
+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */
+#define LTDC_SRCR_VBR_Pos            (1U)
+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */
+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */
+
+/********************  Bit definition for LTDC_BCCR register  *****************/
+
+#define LTDC_BCCR_BCBLUE_Pos         (0U)
+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */
+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */
+#define LTDC_BCCR_BCGREEN_Pos        (8U)
+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */
+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */
+#define LTDC_BCCR_BCRED_Pos          (16U)
+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */
+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */
+
+/********************  Bit definition for LTDC_IER register  ******************/
+
+#define LTDC_IER_LIE_Pos             (0U)
+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */
+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */
+#define LTDC_IER_FUIE_Pos            (1U)
+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */
+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */
+#define LTDC_IER_TERRIE_Pos          (2U)
+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */
+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */
+#define LTDC_IER_RRIE_Pos            (3U)
+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */
+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */
+
+/********************  Bit definition for LTDC_ISR register  ******************/
+
+#define LTDC_ISR_LIF_Pos             (0U)
+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */
+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */
+#define LTDC_ISR_FUIF_Pos            (1U)
+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */
+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */
+#define LTDC_ISR_TERRIF_Pos          (2U)
+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */
+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */
+#define LTDC_ISR_RRIF_Pos            (3U)
+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */
+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_ICR register  ******************/
+
+#define LTDC_ICR_CLIF_Pos            (0U)
+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */
+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */
+#define LTDC_ICR_CFUIF_Pos           (1U)
+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */
+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */
+#define LTDC_ICR_CTERRIF_Pos         (2U)
+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */
+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */
+#define LTDC_ICR_CRRIF_Pos           (3U)
+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */
+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */
+
+/********************  Bit definition for LTDC_LIPCR register  ****************/
+
+#define LTDC_LIPCR_LIPOS_Pos         (0U)
+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */
+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */
+
+/********************  Bit definition for LTDC_CPSR register  *****************/
+
+#define LTDC_CPSR_CYPOS_Pos          (0U)
+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */
+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */
+#define LTDC_CPSR_CXPOS_Pos          (16U)
+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */
+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */
+
+/********************  Bit definition for LTDC_CDSR register  *****************/
+
+#define LTDC_CDSR_VDES_Pos           (0U)
+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */
+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */
+#define LTDC_CDSR_HDES_Pos           (1U)
+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */
+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */
+#define LTDC_CDSR_VSYNCS_Pos         (2U)
+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */
+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */
+#define LTDC_CDSR_HSYNCS_Pos         (3U)
+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */
+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */
+
+/********************  Bit definition for LTDC_LxCR register  *****************/
+
+#define LTDC_LxCR_LEN_Pos            (0U)
+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */
+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */
+#define LTDC_LxCR_COLKEN_Pos         (1U)
+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */
+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */
+#define LTDC_LxCR_CLUTEN_Pos         (4U)
+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */
+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */
+
+/********************  Bit definition for LTDC_LxWHPCR register  **************/
+
+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)
+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */
+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)
+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */
+
+/********************  Bit definition for LTDC_LxWVPCR register  **************/
+
+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)
+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */
+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */
+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)
+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */
+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */
+
+/********************  Bit definition for LTDC_LxCKCR register  ***************/
+
+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)
+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */
+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)
+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */
+#define LTDC_LxCKCR_CKRED_Pos        (16U)
+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */
+
+/********************  Bit definition for LTDC_LxPFCR register  ***************/
+
+#define LTDC_LxPFCR_PF_Pos           (0U)
+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */
+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */
+
+/********************  Bit definition for LTDC_LxCACR register  ***************/
+
+#define LTDC_LxCACR_CONSTA_Pos       (0U)
+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */
+
+/********************  Bit definition for LTDC_LxDCCR register  ***************/
+
+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)
+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */
+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)
+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */
+#define LTDC_LxDCCR_DCRED_Pos        (16U)
+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */
+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)
+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */
+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */
+
+/********************  Bit definition for LTDC_LxBFCR register  ***************/
+
+#define LTDC_LxBFCR_BF2_Pos          (0U)
+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */
+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */
+#define LTDC_LxBFCR_BF1_Pos          (8U)
+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */
+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */
+
+/********************  Bit definition for LTDC_LxCFBAR register  **************/
+
+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)
+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */
+
+/********************  Bit definition for LTDC_LxCFBLR register  **************/
+
+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)
+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */
+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */
+#define LTDC_LxCFBLR_CFBP_Pos        (16U)
+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */
+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */
+
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/
+
+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)
+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */
+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */
+
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/
+
+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)
+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */
+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */
+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)
+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */
+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */
+#define LTDC_LxCLUTWR_RED_Pos        (16U)
+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */
+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */
+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)
+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */
+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                     MDMA                                   */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDMA_GISR0 register  ****************/
+#define MDMA_GISR0_GIF0_Pos       (0U)
+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */
+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */
+#define MDMA_GISR0_GIF1_Pos       (1U)
+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */
+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */
+#define MDMA_GISR0_GIF2_Pos       (2U)
+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */
+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */
+#define MDMA_GISR0_GIF3_Pos       (3U)
+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */
+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */
+#define MDMA_GISR0_GIF4_Pos       (4U)
+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */
+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */
+#define MDMA_GISR0_GIF5_Pos       (5U)
+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */
+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */
+#define MDMA_GISR0_GIF6_Pos       (6U)
+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */
+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */
+#define MDMA_GISR0_GIF7_Pos       (7U)
+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */
+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */
+#define MDMA_GISR0_GIF8_Pos       (8U)
+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */
+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */
+#define MDMA_GISR0_GIF9_Pos       (9U)
+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */
+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */
+#define MDMA_GISR0_GIF10_Pos      (10U)
+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */
+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */
+#define MDMA_GISR0_GIF11_Pos      (11U)
+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */
+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */
+#define MDMA_GISR0_GIF12_Pos      (12U)
+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */
+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */
+#define MDMA_GISR0_GIF13_Pos      (13U)
+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */
+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */
+#define MDMA_GISR0_GIF14_Pos      (14U)
+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */
+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */
+#define MDMA_GISR0_GIF15_Pos      (15U)
+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */
+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */
+
+/********************  Bit definition for MDMA_CxISR register  ****************/
+#define MDMA_CISR_TEIF_Pos        (0U)
+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */
+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */
+#define MDMA_CISR_CTCIF_Pos       (1U)
+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */
+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */
+#define MDMA_CISR_BRTIF_Pos       (2U)
+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */
+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */
+#define MDMA_CISR_BTIF_Pos        (3U)
+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */
+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */
+#define MDMA_CISR_TCIF_Pos        (4U)
+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */
+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */
+#define MDMA_CISR_CRQA_Pos        (16U)
+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */
+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x request Active flag */
+
+/********************  Bit definition for MDMA_CxIFCR register  ****************/
+#define MDMA_CIFCR_CTEIF_Pos      (0U)
+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */
+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */
+#define MDMA_CIFCR_CCTCIF_Pos     (1U)
+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */
+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */
+#define MDMA_CIFCR_CBRTIF_Pos     (2U)
+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */
+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */
+#define MDMA_CIFCR_CBTIF_Pos      (3U)
+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */
+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */
+#define MDMA_CIFCR_CLTCIF_Pos     (4U)
+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */
+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
+
+/********************  Bit definition for MDMA_CxESR register  ****************/
+#define MDMA_CESR_TEA_Pos         (0U)
+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */
+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */
+#define MDMA_CESR_TED_Pos         (7U)
+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */
+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */
+#define MDMA_CESR_TELD_Pos        (8U)
+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */
+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */
+#define MDMA_CESR_TEMD_Pos        (9U)
+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */
+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */
+#define MDMA_CESR_ASE_Pos         (10U)
+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */
+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */
+#define MDMA_CESR_BSE_Pos         (11U)
+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */
+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */
+
+/********************  Bit definition for MDMA_CxCR register  ****************/
+#define MDMA_CCR_EN_Pos           (0U)
+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */
+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */
+#define MDMA_CCR_TEIE_Pos         (1U)
+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */
+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */
+#define MDMA_CCR_CTCIE_Pos        (2U)
+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */
+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */
+#define MDMA_CCR_BRTIE_Pos        (3U)
+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */
+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */
+#define MDMA_CCR_BTIE_Pos         (4U)
+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */
+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */
+#define MDMA_CCR_TCIE_Pos         (5U)
+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */
+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */
+#define MDMA_CCR_PL_Pos           (6U)
+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */
+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */
+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */
+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */
+#define MDMA_CCR_BEX_Pos          (12U)
+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */
+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianness eXchange */
+#define MDMA_CCR_HEX_Pos          (13U)
+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */
+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianness eXchange */
+#define MDMA_CCR_WEX_Pos          (14U)
+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */
+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianness eXchange */
+#define MDMA_CCR_SWRQ_Pos         (16U)
+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */
+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */
+
+/********************  Bit definition for MDMA_CxTCR register  ****************/
+#define MDMA_CTCR_SINC_Pos        (0U)
+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */
+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */
+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */
+#define MDMA_CTCR_DINC_Pos        (2U)
+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */
+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */
+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */
+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */
+#define MDMA_CTCR_SSIZE_Pos       (4U)
+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */
+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */
+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */
+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */
+#define MDMA_CTCR_DSIZE_Pos       (6U)
+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */
+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */
+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */
+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */
+#define MDMA_CTCR_SINCOS_Pos      (8U)
+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */
+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */
+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */
+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */
+#define MDMA_CTCR_DINCOS_Pos      (10U)
+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */
+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */
+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */
+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */
+#define MDMA_CTCR_SBURST_Pos      (12U)
+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */
+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */
+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */
+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */
+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */
+#define MDMA_CTCR_DBURST_Pos      (15U)
+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */
+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */
+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */
+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */
+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */
+#define MDMA_CTCR_TLEN_Pos        (18U)
+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */
+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */
+#define MDMA_CTCR_PKE_Pos         (25U)
+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */
+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */
+#define MDMA_CTCR_PAM_Pos         (26U)
+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */
+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignment Mode */
+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */
+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */
+#define MDMA_CTCR_TRGM_Pos        (28U)
+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */
+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */
+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */
+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */
+#define MDMA_CTCR_SWRM_Pos        (30U)
+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */
+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */
+#define MDMA_CTCR_BWM_Pos         (31U)
+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */
+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */
+
+/********************  Bit definition for MDMA_CxBNDTR register  ****************/
+#define MDMA_CBNDTR_BNDT_Pos      (0U)
+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */
+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */
+#define MDMA_CBNDTR_BRSUM_Pos     (18U)
+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */
+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */
+#define MDMA_CBNDTR_BRDUM_Pos     (19U)
+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */
+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */
+#define MDMA_CBNDTR_BRC_Pos       (20U)
+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */
+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */
+
+/********************  Bit definition for MDMA_CxSAR register  ****************/
+#define MDMA_CSAR_SAR_Pos         (0U)
+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */
+
+/********************  Bit definition for MDMA_CxDAR register  ****************/
+#define MDMA_CDAR_DAR_Pos         (0U)
+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */
+
+/********************  Bit definition for MDMA_CxBRUR  ************************/
+#define MDMA_CBRUR_SUV_Pos        (0U)
+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */
+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */
+#define MDMA_CBRUR_DUV_Pos        (16U)
+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */
+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */
+
+/********************  Bit definition for MDMA_CxLAR  *************************/
+#define MDMA_CLAR_LAR_Pos         (0U)
+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */
+
+/********************  Bit definition for MDMA_CxTBR)  ************************/
+#define MDMA_CTBR_TSEL_Pos        (0U)
+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */
+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */
+#define MDMA_CTBR_SBUS_Pos        (16U)
+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */
+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */
+#define MDMA_CTBR_DBUS_Pos        (17U)
+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */
+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */
+
+/********************  Bit definition for MDMA_CxMAR)  ************************/
+#define MDMA_CMAR_MAR_Pos         (0U)
+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */
+
+/********************  Bit definition for MDMA_CxMDR)  ************************/
+#define MDMA_CMDR_MDR_Pos         (0U)
+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */
+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Operational Amplifier (OPAMP)                      */
+/*                                                                            */
+/******************************************************************************/
+/*********************  Bit definition for OPAMPx_CSR register  ***************/
+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)
+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */
+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */
+#define OPAMP_CSR_FORCEVP_Pos            (1U)
+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */
+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */
+
+#define OPAMP_CSR_VPSEL_Pos              (2U)
+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */
+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */
+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */
+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */
+
+#define OPAMP_CSR_VMSEL_Pos              (5U)
+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */
+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */
+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */
+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */
+
+#define OPAMP_CSR_OPAHSM_Pos             (8U)
+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */
+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */
+#define OPAMP_CSR_CALON_Pos              (11U)
+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */
+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */
+
+#define OPAMP_CSR_CALSEL_Pos             (12U)
+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */
+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */
+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */
+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */
+
+#define OPAMP_CSR_PGGAIN_Pos             (14U)
+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */
+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */
+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */
+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */
+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */
+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */
+
+#define OPAMP_CSR_USERTRIM_Pos           (18U)
+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */
+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */
+#define OPAMP_CSR_TSTREF_Pos             (29U)
+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */
+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */
+#define OPAMP_CSR_CALOUT_Pos             (30U)
+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */
+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */
+
+/*********************  Bit definition for OPAMP1_CSR register  ***************/
+#define OPAMP1_CSR_OPAEN_Pos              (0U)
+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */
+#define OPAMP1_CSR_FORCEVP_Pos            (1U)
+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP1_CSR_VPSEL_Pos              (2U)
+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP1_CSR_VMSEL_Pos              (5U)
+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP1_CSR_OPAHSM_Pos             (8U)
+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */
+#define OPAMP1_CSR_CALON_Pos              (11U)
+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP1_CSR_CALSEL_Pos             (12U)
+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP1_CSR_PGGAIN_Pos             (14U)
+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */
+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP1_CSR_USERTRIM_Pos           (18U)
+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP1_CSR_TSTREF_Pos             (29U)
+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP1_CSR_CALOUT_Pos             (30U)
+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */
+
+/*********************  Bit definition for OPAMP2_CSR register  ***************/
+#define OPAMP2_CSR_OPAEN_Pos              (0U)
+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */
+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */
+#define OPAMP2_CSR_FORCEVP_Pos            (1U)
+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */
+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */
+
+#define OPAMP2_CSR_VPSEL_Pos              (2U)
+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */
+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */
+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */
+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */
+
+#define OPAMP2_CSR_VMSEL_Pos              (5U)
+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */
+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */
+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */
+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */
+
+#define OPAMP2_CSR_OPAHSM_Pos             (8U)
+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */
+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */
+#define OPAMP2_CSR_CALON_Pos              (11U)
+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */
+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */
+
+#define OPAMP2_CSR_CALSEL_Pos             (12U)
+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */
+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */
+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */
+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */
+
+#define OPAMP2_CSR_PGGAIN_Pos             (14U)
+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */
+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */
+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */
+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */
+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */
+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */
+
+#define OPAMP2_CSR_USERTRIM_Pos           (18U)
+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */
+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */
+#define OPAMP2_CSR_TSTREF_Pos             (29U)
+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */
+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */
+#define OPAMP2_CSR_CALOUT_Pos             (30U)
+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */
+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */
+
+/*******************  Bit definition for OPAMP_OTR register  ******************/
+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */
+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_OTR register  ******************/
+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_OTR register  ******************/
+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)
+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */
+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)
+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP_HSOTR register  ****************/
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)
+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/*************************  NUMBER OF POWER DOMAINS  **************************/
+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */
+
+/********************  Bit definition for PWR_CR1 register  *******************/
+#define PWR_CR1_ALS_Pos                (17U)
+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */
+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */
+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */
+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */
+#define PWR_CR1_AVDEN_Pos              (16U)
+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */
+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */
+#define PWR_CR1_SVOS_Pos               (14U)
+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */
+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */
+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */
+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */
+#define PWR_CR1_FLPS_Pos               (9U)
+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */
+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */
+#define PWR_CR1_DBP_Pos                (8U)
+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */
+#define PWR_CR1_PLS_Pos                (5U)
+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */
+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */
+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */
+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */
+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */
+#define PWR_CR1_PVDEN_Pos              (4U)
+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */
+#define PWR_CR1_LPDS_Pos               (0U)
+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */
+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */
+
+/*!< PVD level configuration */
+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */
+#define PWR_CR1_PLS_LEV1_Pos           (5U)
+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */
+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */
+#define PWR_CR1_PLS_LEV2_Pos           (6U)
+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */
+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */
+#define PWR_CR1_PLS_LEV3_Pos           (5U)
+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */
+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */
+#define PWR_CR1_PLS_LEV4_Pos           (7U)
+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */
+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */
+#define PWR_CR1_PLS_LEV5_Pos           (5U)
+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */
+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */
+#define PWR_CR1_PLS_LEV6_Pos           (6U)
+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */
+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */
+#define PWR_CR1_PLS_LEV7_Pos           (5U)
+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */
+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */
+
+/*!< AVD level configuration */
+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */
+#define PWR_CR1_ALS_LEV1_Pos           (17U)
+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */
+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */
+#define PWR_CR1_ALS_LEV2_Pos           (18U)
+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */
+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */
+#define PWR_CR1_ALS_LEV3_Pos           (17U)
+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */
+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */
+
+/********************  Bit definition for PWR_CSR1 register  ******************/
+#define PWR_CSR1_AVDO_Pos              (16U)
+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */
+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */
+#define PWR_CSR1_ACTVOS_Pos            (14U)
+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */
+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */
+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */
+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */
+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)
+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */
+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */
+#define PWR_CSR1_PVDO_Pos              (4U)
+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */
+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */
+
+/********************  Bit definition for PWR_CR2 register  *******************/
+#define PWR_CR2_TEMPH_Pos              (23U)
+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */
+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */
+#define PWR_CR2_TEMPL_Pos              (22U)
+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */
+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */
+#define PWR_CR2_VBATH_Pos              (21U)
+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */
+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */
+#define PWR_CR2_VBATL_Pos              (20U)
+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */
+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */
+#define PWR_CR2_BRRDY_Pos              (16U)
+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */
+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */
+#define PWR_CR2_MONEN_Pos              (4U)
+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */
+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */
+#define PWR_CR2_BREN_Pos               (0U)
+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */
+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */
+
+/********************  Bit definition for PWR_CR3 register  *******************/
+#define PWR_CR3_USB33RDY_Pos           (26U)
+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */
+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */
+#define PWR_CR3_USBREGEN_Pos           (25U)
+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */
+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */
+#define PWR_CR3_USB33DEN_Pos           (24U)
+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */
+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */
+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)
+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */
+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */
+#define PWR_CR3_VBRS_Pos               (9U)
+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */
+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */
+#define PWR_CR3_VBE_Pos                (8U)
+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */
+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */
+#define PWR_CR3_SMPSLEVEL_Pos          (4U)
+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */
+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */
+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */
+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */
+#define PWR_CR3_SMPSEXTHP_Pos          (3U)
+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */
+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */
+#define PWR_CR3_SMPSEN_Pos             (2U)
+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */
+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */
+#define PWR_CR3_LDOEN_Pos              (1U)
+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */
+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */
+#define PWR_CR3_BYPASS_Pos             (0U)
+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */
+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */
+
+/********************  Bit definition for PWR_CPUCR register  *****************/
+#define PWR_CPUCR_RUN_D3_Pos           (11U)
+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */
+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPUCR_HOLD2_Pos            (10U)
+#define PWR_CPUCR_HOLD2_Msk            (0x1UL << PWR_CPUCR_HOLD2_Pos)          /*!< 0x00000400 */
+#define PWR_CPUCR_HOLD2                PWR_CPUCR_HOLD2_Msk                     /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */
+#define PWR_CPUCR_CSSF_Pos             (9U)
+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */
+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
+#define PWR_CPUCR_SBF_D2_Pos           (8U)
+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */
+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_D1_Pos           (7U)
+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */
+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPUCR_SBF_Pos              (6U)
+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */
+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */
+#define PWR_CPUCR_STOPF_Pos            (5U)
+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */
+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */
+#define PWR_CPUCR_HOLD2F_Pos           (4U)
+#define PWR_CPUCR_HOLD2F_Msk           (0x1UL << PWR_CPUCR_HOLD2F_Pos)         /*!< 0x00000010 */
+#define PWR_CPUCR_HOLD2F               PWR_CPUCR_HOLD2F_Msk                    /*!< CPU2 in hold wakeup flag */
+#define PWR_CPUCR_PDDS_D3_Pos          (2U)
+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */
+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D2_Pos          (1U)
+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */
+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPUCR_PDDS_D1_Pos          (0U)
+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */
+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */
+
+/********************  Bit definition for PWR_CPU2CR register  ****************/
+#define PWR_CPU2CR_RUN_D3_Pos          (11U)
+#define PWR_CPU2CR_RUN_D3_Msk          (0x1UL << PWR_CPU2CR_RUN_D3_Pos)        /*!< 0x00000800 */
+#define PWR_CPU2CR_RUN_D3              PWR_CPU2CR_RUN_D3_Msk                   /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
+#define PWR_CPU2CR_HOLD1_Pos           (10U)
+#define PWR_CPU2CR_HOLD1_Msk           (0x1UL << PWR_CPU2CR_HOLD1_Pos)         /*!< 0x00000400 */
+#define PWR_CPU2CR_HOLD1               PWR_CPU2CR_HOLD1_Msk                    /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */
+#define PWR_CPU2CR_CSSF_Pos            (9U)
+#define PWR_CPU2CR_CSSF_Msk            (0x1UL << PWR_CPU2CR_CSSF_Pos)          /*!< 0x00000200 */
+#define PWR_CPU2CR_CSSF                PWR_CPU2CR_CSSF_Msk                     /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */
+#define PWR_CPU2CR_SBF_D2_Pos          (8U)
+#define PWR_CPU2CR_SBF_D2_Msk          (0x1UL << PWR_CPU2CR_SBF_D2_Pos)        /*!< 0x00000100 */
+#define PWR_CPU2CR_SBF_D2              PWR_CPU2CR_SBF_D2_Msk                   /*!< D2 domain DSTANDBY Flag */
+#define PWR_CPU2CR_SBF_D1_Pos          (7U)
+#define PWR_CPU2CR_SBF_D1_Msk          (0x1UL << PWR_CPU2CR_SBF_D1_Pos)        /*!< 0x00000080 */
+#define PWR_CPU2CR_SBF_D1              PWR_CPU2CR_SBF_D1_Msk                   /*!< D1 domain DSTANDBY Flag */
+#define PWR_CPU2CR_SBF_Pos             (6U)
+#define PWR_CPU2CR_SBF_Msk             (0x1UL << PWR_CPU2CR_SBF_Pos)           /*!< 0x00000040 */
+#define PWR_CPU2CR_SBF                 PWR_CPU2CR_SBF_Msk                      /*!< System STANDBY Flag */
+#define PWR_CPU2CR_STOPF_Pos           (5U)
+#define PWR_CPU2CR_STOPF_Msk           (0x1UL << PWR_CPU2CR_STOPF_Pos)         /*!< 0x00000020 */
+#define PWR_CPU2CR_STOPF               PWR_CPU2CR_STOPF_Msk                    /*!< STOP Flag */
+#define PWR_CPU2CR_HOLD1F_Pos          (4U)
+#define PWR_CPU2CR_HOLD1F_Msk          (0x1UL << PWR_CPU2CR_HOLD1F_Pos)        /*!< 0x00000010 */
+#define PWR_CPU2CR_HOLD1F              PWR_CPU2CR_HOLD1F_Msk                   /*!< CPU1 in hold wakeup flag */
+#define PWR_CPU2CR_PDDS_D3_Pos         (2U)
+#define PWR_CPU2CR_PDDS_D3_Msk         (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)       /*!< 0x00000004 */
+#define PWR_CPU2CR_PDDS_D3             PWR_CPU2CR_PDDS_D3_Msk                  /*!< System D3 domain Power Down Deepsleep */
+#define PWR_CPU2CR_PDDS_D2_Pos         (1U)
+#define PWR_CPU2CR_PDDS_D2_Msk         (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)       /*!< 0x00000002 */
+#define PWR_CPU2CR_PDDS_D2             PWR_CPU2CR_PDDS_D2_Msk                  /*!< D2 domain Power Down Deepsleep */
+#define PWR_CPU2CR_PDDS_D1_Pos         (0U)
+#define PWR_CPU2CR_PDDS_D1_Msk         (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)       /*!< 0x00000001 */
+#define PWR_CPU2CR_PDDS_D1             PWR_CPU2CR_PDDS_D1_Msk                  /*!< D1 domain Power Down Deepsleep selection */
+
+
+/********************  Bit definition for PWR_D3CR register  ******************/
+#define PWR_D3CR_VOS_Pos               (14U)
+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */
+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */
+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */
+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */
+#define PWR_D3CR_VOSRDY_Pos            (13U)
+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */
+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
+
+/******************  Bit definition for PWR_WKUPCR register  ******************/
+#define PWR_WKUPCR_WKUPC6_Pos          (5U)
+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */
+#define PWR_WKUPCR_WKUPC5_Pos          (4U)
+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */
+#define PWR_WKUPCR_WKUPC4_Pos          (3U)
+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */
+#define PWR_WKUPCR_WKUPC3_Pos          (2U)
+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */
+#define PWR_WKUPCR_WKUPC2_Pos          (1U)
+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */
+#define PWR_WKUPCR_WKUPC1_Pos          (0U)
+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */
+
+/********************  Bit definition for PWR_WKUPFR register  ****************/
+#define PWR_WKUPFR_WKUPF6_Pos          (5U)
+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */
+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */
+#define PWR_WKUPFR_WKUPF5_Pos          (4U)
+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */
+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */
+#define PWR_WKUPFR_WKUPF4_Pos          (3U)
+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */
+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */
+#define PWR_WKUPFR_WKUPF3_Pos          (2U)
+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */
+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */
+#define PWR_WKUPFR_WKUPF2_Pos          (1U)
+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */
+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */
+#define PWR_WKUPFR_WKUPF1_Pos          (0U)
+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */
+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */
+
+/******************  Bit definition for PWR_WKUPEPR register  *****************/
+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)
+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */
+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */
+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */
+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)
+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */
+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */
+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */
+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */
+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)
+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */
+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */
+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */
+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */
+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)
+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */
+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */
+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */
+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */
+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)
+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */
+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */
+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */
+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */
+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)
+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */
+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */
+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */
+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */
+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)
+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */
+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */
+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)
+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */
+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */
+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)
+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */
+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */
+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)
+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */
+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */
+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)
+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */
+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */
+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)
+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */
+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */
+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)
+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */
+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */
+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)
+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */
+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */
+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)
+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */
+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */
+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)
+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */
+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */
+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)
+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */
+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */
+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)
+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */
+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */
+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)
+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */
+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  RCC VERSION  ********************************/
+#define RCC_VER_X
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                       (0U)
+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */
+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIKERON_Pos                    (1U)
+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */
+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */
+#define RCC_CR_HSIRDY_Pos                      (2U)
+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */
+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */
+#define RCC_CR_HSIDIV_Pos                      (3U)
+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */
+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */
+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */
+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */
+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */
+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */
+
+#define RCC_CR_HSIDIVF_Pos                     (5U)
+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */
+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */
+#define RCC_CR_CSION_Pos                       (7U)
+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */
+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */
+#define RCC_CR_CSIRDY_Pos                      (8U)
+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */
+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */
+#define RCC_CR_CSIKERON_Pos                    (9U)
+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */
+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
+#define RCC_CR_HSI48ON_Pos                     (12U)
+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */
+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */
+#define RCC_CR_HSI48RDY_Pos                    (13U)
+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */
+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */
+
+#define RCC_CR_D1CKRDY_Pos                     (14U)
+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */
+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */
+#define RCC_CR_D2CKRDY_Pos                     (15U)
+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */
+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */
+
+#define RCC_CR_HSEON_Pos                       (16U)
+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */
+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                      (17U)
+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */
+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */
+#define RCC_CR_HSEBYP_Pos                      (18U)
+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */
+#define RCC_CR_CSSHSEON_Pos                    (19U)
+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */
+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */
+
+
+#define RCC_CR_PLL1ON_Pos                      (24U)
+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */
+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */
+#define RCC_CR_PLL1RDY_Pos                     (25U)
+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */
+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */
+#define RCC_CR_PLL2ON_Pos                      (26U)
+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */
+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */
+#define RCC_CR_PLL2RDY_Pos                     (27U)
+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */
+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */
+#define RCC_CR_PLL3ON_Pos                      (28U)
+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */
+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */
+#define RCC_CR_PLL3RDY_Pos                     (29U)
+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */
+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */
+
+/*Legacy */
+#define RCC_CR_PLLON_Pos                       (24U)
+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */
+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */
+#define RCC_CR_PLLRDY_Pos                      (25U)
+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */
+
+/********************  Bit definition for RCC_HSICFGR register  ***************/
+/*!< HSICAL configuration */
+#define RCC_HSICFGR_HSICAL_Pos                 (0U)
+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */
+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
+
+/*!< HSITRIM configuration */
+#define RCC_HSICFGR_HSITRIM_Pos                (24U)
+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */
+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
+
+
+/********************  Bit definition for RCC_CRRCR register  *****************/
+
+/*!< HSI48CAL configuration */
+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)
+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */
+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
+
+
+/********************  Bit definition for RCC_CSICFGR register  *****************/
+/*!< CSICAL configuration */
+#define RCC_CSICFGR_CSICAL_Pos                 (0U)
+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */
+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
+
+/*!< CSITRIM configuration */
+#define RCC_CSICFGR_CSITRIM_Pos                (24U)
+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */
+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                        (0U)
+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */
+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */
+
+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */
+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */
+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */
+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                       (3U)
+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */
+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */
+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */
+
+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */
+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */
+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */
+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */
+
+#define RCC_CFGR_STOPWUCK_Pos                  (6U)
+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */
+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */
+
+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)
+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */
+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                    (8U)
+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)
+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */
+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */
+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */
+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */
+
+/*!< HRTIMSEL configuration */
+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)
+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */
+
+/*!< TIMPRE configuration */
+#define RCC_CFGR_TIMPRE_Pos                    (15U)
+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)
+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                      (22U)
+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)
+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */
+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */
+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */
+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */
+
+#define RCC_CFGR_MCO1PRE_Pos                   (18U)
+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)
+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */
+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */
+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */
+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */
+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */
+
+#define RCC_CFGR_MCO2PRE_Pos                   (25U)
+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)
+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */
+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */
+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */
+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */
+
+#define RCC_CFGR_MCO2_Pos                      (29U)
+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)
+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */
+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */
+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_D1CFGR register  ******************/
+/*!< D1HPRE configuration */
+#define RCC_D1CFGR_HPRE_Pos                    (0U)
+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */
+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */
+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */
+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */
+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
+
+
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)
+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */
+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)
+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */
+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)
+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */
+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)
+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */
+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */
+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)
+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */
+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)
+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */
+
+/*!< D1PPRE configuration */
+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)
+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */
+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)
+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */
+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)
+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */
+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)
+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */
+
+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)
+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
+
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)
+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */
+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)
+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */
+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)
+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */
+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)
+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */
+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */
+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)
+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */
+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)
+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */
+
+/********************  Bit definition for RCC_D2CFGR register  ******************/
+/*!< D2PPRE1 configuration */
+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)
+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
+
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)
+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)
+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */
+
+/*!< D2PPRE2 configuration */
+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)
+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
+
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */
+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)
+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */
+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)
+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */
+
+/********************  Bit definition for RCC_D3CFGR register  ******************/
+/*!< D3PPRE configuration */
+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)
+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
+
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)
+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */
+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)
+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */
+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)
+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */
+
+/********************  Bit definition for RCC_PLLCKSELR register  *************/
+
+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)
+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
+
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)
+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)
+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */
+
+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)
+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk
+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
+
+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)
+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk
+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
+
+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)
+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk
+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+
+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)
+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk
+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)
+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk
+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)
+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk
+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
+
+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)
+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk
+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)
+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk
+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)
+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk
+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
+
+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)
+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk
+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)
+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk
+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)
+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk
+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
+
+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)
+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk
+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)
+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk
+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)
+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk
+
+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)
+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk
+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)
+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk
+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)
+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk
+
+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)
+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk
+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)
+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk
+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)
+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk
+
+
+/********************  Bit definition for RCC_PLL1DIVR register  ***************/
+#define RCC_PLL1DIVR_N1_Pos                    (0U)
+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk
+#define RCC_PLL1DIVR_P1_Pos                    (9U)
+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk
+#define RCC_PLL1DIVR_Q1_Pos                    (16U)
+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk
+#define RCC_PLL1DIVR_R1_Pos                    (24U)
+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk
+
+/********************  Bit definition for RCC_PLL1FRACR register  ***************/
+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)
+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk
+
+/********************  Bit definition for RCC_PLL2DIVR register  ***************/
+#define RCC_PLL2DIVR_N2_Pos                    (0U)
+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk
+#define RCC_PLL2DIVR_P2_Pos                    (9U)
+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk
+#define RCC_PLL2DIVR_Q2_Pos                    (16U)
+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk
+#define RCC_PLL2DIVR_R2_Pos                    (24U)
+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk
+
+/********************  Bit definition for RCC_PLL2FRACR register  ***************/
+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)
+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk
+
+/********************  Bit definition for RCC_PLL3DIVR register  ***************/
+#define RCC_PLL3DIVR_N3_Pos                    (0U)
+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk
+#define RCC_PLL3DIVR_P3_Pos                    (9U)
+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk
+#define RCC_PLL3DIVR_Q3_Pos                    (16U)
+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk
+#define RCC_PLL3DIVR_R3_Pos                    (24U)
+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk
+
+/********************  Bit definition for RCC_PLL3FRACR register  ***************/
+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)
+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ***************/
+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)
+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk
+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)
+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk
+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
+#define RCC_D1CCIPR_DSISEL_Pos                 (8U)
+#define RCC_D1CCIPR_DSISEL_Msk                 (0x1UL << RCC_D1CCIPR_DSISEL_Pos) /*!< 0x00000100 */
+#define RCC_D1CCIPR_DSISEL                     RCC_D1CCIPR_DSISEL_Msk
+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)
+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)
+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk
+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
+
+/********************  Bit definition for RCC_D2CCIP1R register  ***************/
+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)
+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk
+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)
+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk
+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
+
+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)
+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk
+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
+
+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)
+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk
+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
+
+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)
+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk
+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)
+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk
+
+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)
+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk
+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
+
+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)
+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk
+
+/********************  Bit definition for RCC_D2CCIP2R register  ***************/
+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)
+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk
+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
+
+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)
+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk
+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)
+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk
+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)
+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk
+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
+
+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)
+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk
+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
+
+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)
+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk
+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)
+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk
+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for RCC_D3CCIPR register  ***************/
+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)
+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk
+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
+
+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)
+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk
+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
+
+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)
+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk
+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
+
+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)
+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk
+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
+
+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)
+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk
+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
+
+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)
+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk
+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
+
+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)
+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk
+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
+
+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)
+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk
+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
+/********************  Bit definition for RCC_CIER register  ******************/
+#define RCC_CIER_LSIRDYIE_Pos                  (0U)
+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk
+#define RCC_CIER_LSERDYIE_Pos                  (1U)
+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk
+#define RCC_CIER_HSIRDYIE_Pos                  (2U)
+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk
+#define RCC_CIER_HSERDYIE_Pos                  (3U)
+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk
+#define RCC_CIER_CSIRDYIE_Pos                  (4U)
+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk
+#define RCC_CIER_HSI48RDYIE_Pos                (5U)
+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk
+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)
+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk
+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)
+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk
+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)
+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk
+#define RCC_CIER_LSECSSIE_Pos                  (9U)
+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk
+
+/********************  Bit definition for RCC_CIFR register  ******************/
+#define RCC_CIFR_LSIRDYF_Pos                   (0U)
+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk
+#define RCC_CIFR_LSERDYF_Pos                   (1U)
+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk
+#define RCC_CIFR_HSIRDYF_Pos                   (2U)
+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk
+#define RCC_CIFR_HSERDYF_Pos                   (3U)
+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk
+#define RCC_CIFR_CSIRDYF_Pos                   (4U)
+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk
+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)
+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk
+#define RCC_CIFR_PLLRDYF_Pos                   (6U)
+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk
+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)
+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk
+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)
+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk
+#define RCC_CIFR_LSECSSF_Pos                   (9U)
+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk
+#define RCC_CIFR_HSECSSF_Pos                   (10U)
+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk
+
+/********************  Bit definition for RCC_CICR register  ******************/
+#define RCC_CICR_LSIRDYC_Pos                   (0U)
+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk
+#define RCC_CICR_LSERDYC_Pos                   (1U)
+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk
+#define RCC_CICR_HSIRDYC_Pos                   (2U)
+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk
+#define RCC_CICR_HSERDYC_Pos                   (3U)
+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk
+#define RCC_CICR_CSIRDYC_Pos                   (4U)
+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk
+#define RCC_CICR_HSI48RDYC_Pos                 (5U)
+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk
+#define RCC_CICR_PLLRDYC_Pos                   (6U)
+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk
+#define RCC_CICR_PLL2RDYC_Pos                  (7U)
+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk
+#define RCC_CICR_PLL3RDYC_Pos                  (8U)
+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk
+#define RCC_CICR_LSECSSC_Pos                   (9U)
+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk
+#define RCC_CICR_HSECSSC_Pos                   (10U)
+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                     (0U)
+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk
+#define RCC_BDCR_LSERDY_Pos                    (1U)
+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk
+#define RCC_BDCR_LSEBYP_Pos                    (2U)
+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk
+
+#define RCC_BDCR_LSEDRV_Pos                    (3U)
+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */
+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk
+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */
+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */
+
+#define RCC_BDCR_LSECSSON_Pos                  (5U)
+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk
+#define RCC_BDCR_LSECSSD_Pos                   (6U)
+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk
+
+#define RCC_BDCR_RTCSEL_Pos                    (8U)
+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk
+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                     (15U)
+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk
+#define RCC_BDCR_BDRST_Pos                     (16U)
+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                      (0U)
+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */
+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk
+#define RCC_CSR_LSIRDY_Pos                     (1U)
+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk
+
+
+/********************  Bit definition for RCC_AHB3ENR register  **************/
+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)
+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */
+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk
+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)
+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */
+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk
+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)
+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */
+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk
+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)
+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */
+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk
+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)
+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */
+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk
+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)
+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */
+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk
+#define RCC_AHB3ENR_FLASHEN_Pos                (8U)
+#define RCC_AHB3ENR_FLASHEN_Msk                (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)      /*!< 0x00000100 */
+#define RCC_AHB3ENR_FLASHEN                    RCC_AHB3ENR_FLASHEN_Msk
+#define RCC_AHB3ENR_DTCM1EN_Pos                (28U)
+#define RCC_AHB3ENR_DTCM1EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)      /*!< 0x10000000 */
+#define RCC_AHB3ENR_DTCM1EN                    RCC_AHB3ENR_DTCM1EN_Msk
+#define RCC_AHB3ENR_DTCM2EN_Pos                (29U)
+#define RCC_AHB3ENR_DTCM2EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)      /*!< 0x20000000 */
+#define RCC_AHB3ENR_DTCM2EN                    RCC_AHB3ENR_DTCM2EN_Msk
+#define RCC_AHB3ENR_ITCMEN_Pos                 (30U)
+#define RCC_AHB3ENR_ITCMEN_Msk                 (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB3ENR_ITCMEN                     RCC_AHB3ENR_ITCMEN_Msk
+#define RCC_AHB3ENR_AXISRAMEN_Pos              (31U)
+#define RCC_AHB3ENR_AXISRAMEN_Msk              (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)    /*!< 0x80000000 */
+#define RCC_AHB3ENR_AXISRAMEN                  RCC_AHB3ENR_AXISRAMEN_Msk
+
+/* Legacy define */
+#define RCC_AHB3ENR_D1SRAM1EN_Pos              RCC_AHB3ENR_AXISRAMEN_Pos
+#define RCC_AHB3ENR_D1SRAM1EN_Msk              RCC_AHB3ENR_AXISRAMEN_Msk
+#define RCC_AHB3ENR_D1SRAM1EN                  RCC_AHB3ENR_AXISRAMEN
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)
+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk
+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)
+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */
+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk
+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)
+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk
+#define RCC_AHB1ENR_ARTEN_Pos                  (14U)
+#define RCC_AHB1ENR_ARTEN_Msk                  (0x1UL << RCC_AHB1ENR_ARTEN_Pos)           /*!< 0x00004000 */
+#define RCC_AHB1ENR_ARTEN                      RCC_AHB1ENR_ARTEN_Msk
+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)
+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */
+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk
+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)
+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */
+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk
+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)
+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */
+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)
+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */
+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)
+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)
+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */
+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)
+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN
+
+
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)
+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk
+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)
+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk
+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)
+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */
+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk
+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)
+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */
+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)
+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */
+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)
+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */
+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk
+
+/* Legacy define */
+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos
+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk
+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN
+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos
+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk
+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN
+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos
+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk
+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN
+
+/********************  Bit definition for RCC_AHB4ENR register  ******************/
+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)
+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk
+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)
+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */
+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk
+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)
+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */
+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk
+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)
+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */
+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk
+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)
+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */
+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk
+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)
+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */
+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk
+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)
+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */
+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk
+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)
+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */
+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk
+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)
+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */
+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk
+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)
+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */
+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk
+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)
+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */
+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk
+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)
+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */
+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk
+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)
+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */
+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk
+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)
+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */
+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk
+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)
+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */
+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk
+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)
+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk
+
+/********************  Bit definition for RCC_APB3ENR register  ******************/
+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)
+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk
+#define RCC_APB3ENR_DSIEN_Pos                  (4U)
+#define RCC_APB3ENR_DSIEN_Msk                  (0x1UL << RCC_APB3ENR_DSIEN_Pos) /*!< 0x00000010 */
+#define RCC_APB3ENR_DSIEN                      RCC_APB3ENR_DSIEN_Msk
+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)
+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk
+
+/********************  Bit definition for RCC_APB1LENR register  ******************/
+
+#define RCC_APB1LENR_TIM2EN_Pos                (0U)
+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk
+#define RCC_APB1LENR_TIM3EN_Pos                (1U)
+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk
+#define RCC_APB1LENR_TIM4EN_Pos                (2U)
+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk
+#define RCC_APB1LENR_TIM5EN_Pos                (3U)
+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk
+#define RCC_APB1LENR_TIM6EN_Pos                (4U)
+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk
+#define RCC_APB1LENR_TIM7EN_Pos                (5U)
+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk
+#define RCC_APB1LENR_TIM12EN_Pos               (6U)
+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk
+#define RCC_APB1LENR_TIM13EN_Pos               (7U)
+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk
+#define RCC_APB1LENR_TIM14EN_Pos               (8U)
+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk
+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)
+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk
+
+#define RCC_APB1LENR_WWDG2EN_Pos               (11U)
+#define RCC_APB1LENR_WWDG2EN_Msk               (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LENR_WWDG2EN                   RCC_APB1LENR_WWDG2EN_Msk
+
+#define RCC_APB1LENR_SPI2EN_Pos                (14U)
+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk
+#define RCC_APB1LENR_SPI3EN_Pos                (15U)
+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk
+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)
+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk
+#define RCC_APB1LENR_USART2EN_Pos              (17U)
+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk
+#define RCC_APB1LENR_USART3EN_Pos              (18U)
+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk
+#define RCC_APB1LENR_UART4EN_Pos               (19U)
+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk
+#define RCC_APB1LENR_UART5EN_Pos               (20U)
+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk
+#define RCC_APB1LENR_I2C1EN_Pos                (21U)
+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk
+#define RCC_APB1LENR_I2C2EN_Pos                (22U)
+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk
+#define RCC_APB1LENR_I2C3EN_Pos                (23U)
+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk
+#define RCC_APB1LENR_CECEN_Pos                 (27U)
+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_DAC12EN_Pos               (29U)
+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk
+#define RCC_APB1LENR_UART7EN_Pos               (30U)
+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk
+#define RCC_APB1LENR_UART8EN_Pos               (31U)
+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk
+
+/* Legacy define */
+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos
+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk
+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN
+/********************  Bit definition for RCC_APB1HENR register  ******************/
+#define RCC_APB1HENR_CRSEN_Pos                 (1U)
+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk
+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)
+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk
+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)
+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk
+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)
+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk
+#define RCC_APB1HENR_FDCANEN_Pos               (8U)
+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk
+
+/********************  Bit definition for RCC_APB2ENR register  ******************/
+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)
+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk
+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)
+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk
+#define RCC_APB2ENR_USART1EN_Pos               (4U)
+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk
+#define RCC_APB2ENR_USART6EN_Pos               (5U)
+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk
+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)
+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk
+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)
+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk
+#define RCC_APB2ENR_TIM15EN_Pos                (16U)
+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk
+#define RCC_APB2ENR_TIM16EN_Pos                (17U)
+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk
+#define RCC_APB2ENR_TIM17EN_Pos                (18U)
+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk
+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)
+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk
+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)
+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk
+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)
+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk
+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)
+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk
+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)
+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk
+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)
+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk
+
+/********************  Bit definition for RCC_APB4ENR register  ******************/
+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)
+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk
+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)
+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk
+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)
+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk
+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)
+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk
+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)
+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk
+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)
+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk
+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)
+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk
+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)
+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk
+#define RCC_APB4ENR_COMP12EN_Pos               (14U)
+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk
+#define RCC_APB4ENR_VREFEN_Pos                 (15U)
+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk
+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)
+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk
+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)
+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk
+
+
+/********************  Bit definition for RCC_AHB3RSTR register  ***************/
+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)
+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk
+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)
+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */
+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk
+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)
+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */
+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk
+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)
+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */
+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk
+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)
+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */
+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk
+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)
+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */
+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk
+
+
+/********************  Bit definition for RCC_AHB1RSTR register  ***************/
+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)
+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk
+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)
+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk
+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)
+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */
+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk
+#define RCC_AHB1RSTR_ARTRST_Pos                (14U)
+#define RCC_AHB1RSTR_ARTRST_Msk                (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)       /*!< 0x00004000 */
+#define RCC_AHB1RSTR_ARTRST                    RCC_AHB1RSTR_ARTRST_Msk
+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)
+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */
+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk
+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)
+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)
+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk
+
+/* Legacy define */
+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos
+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk
+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST
+
+/********************  Bit definition for RCC_AHB2RSTR register  ***************/
+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)
+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk
+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)
+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk
+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)
+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */
+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk
+
+/********************  Bit definition for RCC_AHB4RSTR register  ******************/
+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)
+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */
+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk
+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)
+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */
+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk
+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)
+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */
+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk
+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)
+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */
+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk
+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)
+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */
+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk
+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)
+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */
+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk
+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)
+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */
+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk
+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)
+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */
+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk
+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)
+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */
+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk
+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)
+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */
+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk
+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)
+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */
+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk
+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)
+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */
+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk
+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)
+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */
+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk
+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)
+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */
+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk
+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)
+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */
+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk
+
+
+/********************  Bit definition for RCC_APB3RSTR register  ******************/
+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)
+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk
+#define RCC_APB3RSTR_DSIRST_Pos                (4U)
+#define RCC_APB3RSTR_DSIRST_Msk                (0x1UL << RCC_APB3RSTR_DSIRST_Pos) /*!< 0x00000010 */
+#define RCC_APB3RSTR_DSIRST                    RCC_APB3RSTR_DSIRST_Msk
+
+/********************  Bit definition for RCC_APB1LRSTR register  ******************/
+
+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)
+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk
+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)
+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk
+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)
+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk
+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)
+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk
+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)
+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk
+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)
+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk
+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)
+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk
+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)
+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk
+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)
+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk
+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)
+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk
+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)
+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk
+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)
+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk
+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)
+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk
+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)
+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk
+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)
+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk
+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)
+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk
+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)
+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk
+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)
+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk
+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)
+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk
+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)
+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk
+#define RCC_APB1LRSTR_CECRST_Pos               (27U)
+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)
+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk
+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)
+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk
+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)
+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk
+
+/* Legacy define */
+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos
+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk
+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST
+/********************  Bit definition for RCC_APB1HRSTR register  ******************/
+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)
+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk
+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)
+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk
+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)
+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk
+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)
+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk
+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)
+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk
+
+/********************  Bit definition for RCC_APB2RSTR register  ******************/
+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)
+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk
+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)
+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk
+#define RCC_APB2RSTR_USART1RST_Pos             (4U)
+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk
+#define RCC_APB2RSTR_USART6RST_Pos             (5U)
+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk
+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk
+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)
+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk
+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)
+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk
+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)
+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk
+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)
+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk
+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)
+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk
+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)
+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk
+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)
+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk
+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)
+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk
+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)
+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk
+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)
+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk
+
+/********************  Bit definition for RCC_APB4RSTR register  ******************/
+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)
+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk
+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)
+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk
+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)
+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk
+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)
+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk
+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)
+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk
+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)
+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk
+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)
+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk
+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)
+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk
+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)
+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk
+#define RCC_APB4RSTR_VREFRST_Pos               (15U)
+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk
+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)
+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk
+
+
+/********************  Bit definition for RCC_GCR register  ********************/
+#define RCC_GCR_WW1RSC_Pos                     (0U)
+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */
+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk
+#define RCC_GCR_WW2RSC_Pos                     (1U)
+#define RCC_GCR_WW2RSC_Msk                     (0x1UL << RCC_GCR_WW2RSC_Pos)   /*!< 0x00000002 */
+#define RCC_GCR_WW2RSC                         RCC_GCR_WW2RSC_Msk
+#define RCC_GCR_BOOT_C1_Pos                    (2U)
+#define RCC_GCR_BOOT_C1_Msk                    (0x1UL << RCC_GCR_BOOT_C1_Pos)  /*!< 0x00000004 */
+#define RCC_GCR_BOOT_C1                        RCC_GCR_BOOT_C1_Msk
+#define RCC_GCR_BOOT_C2_Pos                    (3U)
+#define RCC_GCR_BOOT_C2_Msk                    (0x1UL << RCC_GCR_BOOT_C2_Pos)  /*!< 0x00000008 */
+#define RCC_GCR_BOOT_C2                        RCC_GCR_BOOT_C2_Msk
+
+/********************  Bit definition for RCC_D3AMR register  ********************/
+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)
+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk
+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)
+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk
+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)
+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk
+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)
+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk
+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)
+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk
+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)
+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk
+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)
+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk
+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)
+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk
+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)
+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk
+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)
+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk
+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)
+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk
+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)
+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk
+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)
+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk
+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)
+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk
+
+
+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)
+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk
+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)
+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk
+/********************  Bit definition for RCC_AHB3LPENR register  **************/
+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)
+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */
+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk
+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)
+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */
+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk
+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)
+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */
+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk
+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)
+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */
+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk
+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)
+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */
+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk
+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)
+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */
+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk
+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)
+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */
+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)
+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */
+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk
+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)
+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */
+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk
+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)
+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */
+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk
+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)
+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */
+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk
+
+
+/********************  Bit definition for RCC_AHB1LPENR register  ***************/
+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)
+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk
+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)
+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk
+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)
+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk
+#define RCC_AHB1LPENR_ARTLPEN_Pos              (14U)
+#define RCC_AHB1LPENR_ARTLPEN_Msk              (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */
+#define RCC_AHB1LPENR_ARTLPEN                  RCC_AHB1LPENR_ARTLPEN_Msk
+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)
+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk
+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)
+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk
+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)
+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)
+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)
+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN
+
+/********************  Bit definition for RCC_AHB2LPENR register  ***************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)
+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk
+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)
+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk
+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)
+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)
+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)
+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)
+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos
+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk
+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN
+
+/********************  Bit definition for RCC_AHB4LPENR register  ******************/
+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)
+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk
+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)
+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk
+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)
+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk
+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)
+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk
+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)
+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk
+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)
+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk
+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)
+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk
+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)
+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk
+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)
+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk
+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)
+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk
+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)
+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk
+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)
+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk
+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)
+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk
+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)
+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk
+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)
+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk
+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)
+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk
+
+/* Legacy define */
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos
+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk
+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN
+/********************  Bit definition for RCC_APB3LPENR register  ******************/
+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)
+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk
+#define RCC_APB3LPENR_DSILPEN_Pos              (4U)
+#define RCC_APB3LPENR_DSILPEN_Msk              (0x1UL << RCC_APB3LPENR_DSILPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB3LPENR_DSILPEN                  RCC_APB3LPENR_DSILPEN_Msk
+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)
+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk
+
+/********************  Bit definition for RCC_APB1LLPENR register  ******************/
+
+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)
+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk
+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)
+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk
+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)
+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk
+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)
+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk
+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)
+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk
+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)
+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk
+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)
+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk
+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)
+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk
+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)
+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk
+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)
+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk
+
+#define RCC_APB1LLPENR_WWDG2LPEN_Pos           (11U)
+#define RCC_APB1LLPENR_WWDG2LPEN_Msk           (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LLPENR_WWDG2LPEN               RCC_APB1LLPENR_WWDG2LPEN_Msk
+
+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)
+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk
+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)
+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)
+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk
+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)
+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk
+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)
+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk
+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)
+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk
+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)
+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk
+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)
+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk
+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)
+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk
+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)
+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk
+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)
+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)
+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk
+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)
+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk
+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)
+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk
+
+/* Legacy define */
+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos
+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk
+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN
+/********************  Bit definition for RCC_APB1HLPENR register  ******************/
+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)
+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk
+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)
+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk
+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)
+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk
+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)
+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk
+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)
+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk
+
+/********************  Bit definition for RCC_APB2LPENR register  ******************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)
+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk
+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)
+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk
+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)
+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk
+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)
+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk
+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk
+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)
+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk
+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)
+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk
+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)
+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk
+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)
+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk
+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)
+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk
+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)
+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk
+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)
+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk
+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)
+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk
+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)
+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk
+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)
+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk
+
+/********************  Bit definition for RCC_APB4LPENR register  ******************/
+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)
+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk
+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)
+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk
+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)
+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk
+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)
+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)
+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk
+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)
+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk
+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)
+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk
+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)
+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk
+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)
+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk
+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)
+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk
+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)
+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk
+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)
+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk
+
+/********************  Bit definition for RCC_D1CCIPR register  ****************/
+#define RCC_D1CCIPR_DSISRC_Pos                 (8U)
+#define RCC_D1CCIPR_DSISRC_Msk                 (0x1UL << RCC_D1CCIPR_DSISRC_Pos) /*!< 0x00000100 */
+#define RCC_D1CCIPR_DSISRC                     RCC_D1CCIPR_DSISRC_Msk
+
+/********************  Bit definition for RCC_RSR register  *******************/
+#define RCC_RSR_RMVF_Pos                       (16U)
+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */
+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk
+#define RCC_RSR_C1RSTF_Pos                     (17U)
+#define RCC_RSR_C1RSTF_Msk                     (0x1UL << RCC_RSR_C1RSTF_Pos)   /*!< 0x00020000 */
+#define RCC_RSR_C1RSTF                         RCC_RSR_C1RSTF_Msk
+#define RCC_RSR_D1RSTF_Pos                     (19U)
+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */
+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk
+#define RCC_RSR_D2RSTF_Pos                     (20U)
+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */
+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk
+#define RCC_RSR_BORRSTF_Pos                    (21U)
+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */
+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk
+#define RCC_RSR_PINRSTF_Pos                    (22U)
+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */
+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk
+#define RCC_RSR_PORRSTF_Pos                    (23U)
+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */
+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk
+#define RCC_RSR_SFT1RSTF_Pos                   (24U)
+#define RCC_RSR_SFT1RSTF_Msk                   (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */
+#define RCC_RSR_SFT1RSTF                       RCC_RSR_SFT1RSTF_Msk
+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)
+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk
+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)
+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk
+
+#define RCC_RSR_WWDG2RSTF_Pos                  (29U)
+#define RCC_RSR_WWDG2RSTF_Msk                  (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */
+#define RCC_RSR_WWDG2RSTF                      RCC_RSR_WWDG2RSTF_Msk
+#define RCC_RSR_IWDG2RSTF_Pos                  (27U)
+#define RCC_RSR_IWDG2RSTF_Msk                  (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */
+#define RCC_RSR_IWDG2RSTF                      RCC_RSR_IWDG2RSTF_Msk
+#define RCC_RSR_SFT2RSTF_Pos                   (25U)
+#define RCC_RSR_SFT2RSTF_Msk                   (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */
+#define RCC_RSR_SFT2RSTF                       RCC_RSR_SFT2RSTF_Msk
+#define RCC_RSR_C2RSTF_Pos                     (18U)
+#define RCC_RSR_C2RSTF_Msk                     (0x1UL << RCC_RSR_C2RSTF_Pos)   /*!< 0x00040000 */
+#define RCC_RSR_C2RSTF                         RCC_RSR_C2RSTF_Msk
+#define RCC_RSR_LPWR1RSTF_Pos                  (30U)
+#define RCC_RSR_LPWR1RSTF_Msk                  (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */
+#define RCC_RSR_LPWR1RSTF                      RCC_RSR_LPWR1RSTF_Msk
+#define RCC_RSR_LPWR2RSTF_Pos                  (31U)
+#define RCC_RSR_LPWR2RSTF_Msk                  (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */
+#define RCC_RSR_LPWR2RSTF                      RCC_RSR_LPWR2RSTF_Msk
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk
+#define RNG_CR_IE_Pos       (3U)
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk
+#define RNG_CR_CED_Pos      (5U)
+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */
+#define RNG_CR_CED          RNG_CR_CED_Msk
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
+#define RNG_SR_CECS_Pos     (1U)
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk
+#define RNG_SR_SECS_Pos     (2U)
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk
+#define RNG_SR_CEIS_Pos     (5U)
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
+#define RNG_SR_SEIS_Pos     (6U)
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                  (22U)
+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TR_PM                      RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                  (20U)
+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TR_HT                      RTC_TR_HT_Msk
+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */
+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                  (16U)
+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TR_HU                      RTC_TR_HU_Msk
+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */
+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */
+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */
+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                 (12U)
+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TR_MNT                     RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */
+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */
+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                 (8U)
+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TR_MNU                     RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */
+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */
+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */
+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                  (4U)
+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TR_ST                      RTC_TR_ST_Msk
+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */
+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */
+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                  (0U)
+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TR_SU                      RTC_TR_SU_Msk
+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */
+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */
+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */
+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                  (20U)
+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */
+#define RTC_DR_YT                      RTC_DR_YT_Msk
+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */
+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */
+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */
+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                  (16U)
+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */
+#define RTC_DR_YU                      RTC_DR_YU_Msk
+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */
+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */
+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */
+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                 (13U)
+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_DR_WDU                     RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */
+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */
+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                  (12U)
+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_DR_MT                      RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                  (8U)
+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_DR_MU                      RTC_DR_MU_Msk
+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */
+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */
+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */
+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                  (4U)
+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_DR_DT                      RTC_DR_DT_Msk
+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */
+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                  (0U)
+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_DR_DU                      RTC_DR_DU_Msk
+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */
+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */
+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */
+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_ITSE_Pos                (24U)
+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */
+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk
+#define RTC_CR_COE_Pos                 (23U)
+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */
+#define RTC_CR_COE                     RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                (21U)
+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */
+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                 (20U)
+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */
+#define RTC_CR_POL                     RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos               (19U)
+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */
+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                 (18U)
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos               (17U)
+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */
+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos               (16U)
+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */
+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                (15U)
+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */
+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos               (14U)
+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */
+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos              (13U)
+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos              (12U)
+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                 (11U)
+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */
+#define RTC_CR_TSE                     RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                (10U)
+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */
+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos               (9U)
+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */
+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos               (8U)
+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */
+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk
+#define RTC_CR_FMT_Pos                 (6U)
+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */
+#define RTC_CR_FMT                     RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos             (5U)
+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos             (4U)
+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */
+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos              (3U)
+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos             (0U)
+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_ITSF_Pos               (17U)
+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */
+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk
+#define RTC_ISR_RECALPF_Pos            (16U)
+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos             (15U)
+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos             (14U)
+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos             (13U)
+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos              (12U)
+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                (11U)
+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */
+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos               (10U)
+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */
+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos              (9U)
+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos              (8U)
+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos               (7U)
+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */
+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos              (6U)
+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */
+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                (5U)
+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */
+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos              (4U)
+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */
+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos               (3U)
+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */
+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos              (2U)
+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos             (1U)
+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos             (0U)
+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos          (16U)
+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos          (0U)
+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos               (0U)
+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos            (31U)
+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos           (30U)
+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos              (28U)
+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos              (24U)
+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos            (23U)
+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos              (22U)
+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos              (20U)
+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos              (16U)
+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos            (15U)
+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos             (12U)
+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos             (8U)
+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos            (7U)
+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos              (4U)
+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos              (0U)
+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos            (31U)
+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos           (30U)
+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos              (28U)
+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos              (24U)
+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos            (23U)
+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos              (22U)
+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos              (20U)
+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos              (16U)
+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos            (15U)
+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos             (12U)
+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos             (8U)
+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos            (7U)
+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos              (4U)
+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos              (0U)
+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                (0U)
+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */
+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                 (0U)
+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_SSR_SS                     RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos           (0U)
+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos           (31U)
+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                (22U)
+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                (20U)
+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                (16U)
+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos               (12U)
+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos               (8U)
+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                (4U)
+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                (0U)
+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos               (13U)
+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                (12U)
+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */
+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                (8U)
+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */
+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                (4U)
+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */
+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                (0U)
+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */
+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos               (0U)
+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CALR register  *****************/
+#define RTC_CALR_CALP_Pos              (15U)
+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */
+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos             (14U)
+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */
+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos            (13U)
+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */
+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos              (0U)
+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */
+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAMPCR register  ***************/
+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)
+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */
+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk
+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)
+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */
+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk
+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)
+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */
+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk
+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)
+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */
+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk
+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)
+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */
+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk
+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)
+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */
+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk
+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)
+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */
+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk
+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)
+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */
+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk
+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)
+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */
+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk
+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)
+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */
+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk
+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)
+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */
+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk
+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */
+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */
+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)
+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */
+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk
+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */
+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */
+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)
+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */
+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk
+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */
+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */
+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */
+#define RTC_TAMPCR_TAMPTS_Pos          (7U)
+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */
+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk
+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)
+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */
+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk
+#define RTC_TAMPCR_TAMP3E_Pos          (5U)
+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */
+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk
+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)
+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */
+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk
+#define RTC_TAMPCR_TAMP2E_Pos          (3U)
+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */
+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk
+#define RTC_TAMPCR_TAMPIE_Pos          (2U)
+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */
+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk
+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)
+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */
+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk
+#define RTC_TAMPCR_TAMP1E_Pos          (0U)
+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */
+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos        (24U)
+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos            (0U)
+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos            (0U)
+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_OR register  *******************/
+#define RTC_OR_OUT_RMP_Pos             (1U)
+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */
+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk
+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)
+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */
+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                  (0U)
+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                      RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                  (0U)
+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                      RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                  (0U)
+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                      RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                  (0U)
+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                      RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                  (0U)
+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                      RTC_BKP4R_Msk
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                  (0U)
+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                      RTC_BKP5R_Msk
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                  (0U)
+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                      RTC_BKP6R_Msk
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                  (0U)
+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                      RTC_BKP7R_Msk
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                  (0U)
+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                      RTC_BKP8R_Msk
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                  (0U)
+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                      RTC_BKP9R_Msk
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                 (0U)
+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                     RTC_BKP10R_Msk
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                 (0U)
+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                     RTC_BKP11R_Msk
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                 (0U)
+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                     RTC_BKP12R_Msk
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                 (0U)
+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                     RTC_BKP13R_Msk
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                 (0U)
+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                     RTC_BKP14R_Msk
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                 (0U)
+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                     RTC_BKP15R_Msk
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                 (0U)
+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                     RTC_BKP16R_Msk
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                 (0U)
+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                     RTC_BKP17R_Msk
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                 (0U)
+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                     RTC_BKP18R_Msk
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                 (0U)
+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                     RTC_BKP19R_Msk
+
+/********************  Bits definition for RTC_BKP20R register  ***************/
+#define RTC_BKP20R_Pos                 (0U)
+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP20R                     RTC_BKP20R_Msk
+
+/********************  Bits definition for RTC_BKP21R register  ***************/
+#define RTC_BKP21R_Pos                 (0U)
+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP21R                     RTC_BKP21R_Msk
+
+/********************  Bits definition for RTC_BKP22R register  ***************/
+#define RTC_BKP22R_Pos                 (0U)
+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP22R                     RTC_BKP22R_Msk
+
+/********************  Bits definition for RTC_BKP23R register  ***************/
+#define RTC_BKP23R_Pos                 (0U)
+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP23R                     RTC_BKP23R_Msk
+
+/********************  Bits definition for RTC_BKP24R register  ***************/
+#define RTC_BKP24R_Pos                 (0U)
+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP24R                     RTC_BKP24R_Msk
+
+/********************  Bits definition for RTC_BKP25R register  ***************/
+#define RTC_BKP25R_Pos                 (0U)
+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP25R                     RTC_BKP25R_Msk
+
+/********************  Bits definition for RTC_BKP26R register  ***************/
+#define RTC_BKP26R_Pos                 (0U)
+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP26R                     RTC_BKP26R_Msk
+
+/********************  Bits definition for RTC_BKP27R register  ***************/
+#define RTC_BKP27R_Pos                 (0U)
+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP27R                     RTC_BKP27R_Msk
+
+/********************  Bits definition for RTC_BKP28R register  ***************/
+#define RTC_BKP28R_Pos                 (0U)
+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP28R                     RTC_BKP28R_Msk
+
+/********************  Bits definition for RTC_BKP29R register  ***************/
+#define RTC_BKP29R_Pos                 (0U)
+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP29R                     RTC_BKP29R_Msk
+
+/********************  Bits definition for RTC_BKP30R register  ***************/
+#define RTC_BKP30R_Pos                 (0U)
+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP30R                     RTC_BKP30R_Msk
+
+/********************  Bits definition for RTC_BKP31R register  ***************/
+#define RTC_BKP31R_Pos                 (0U)
+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */
+#define RTC_BKP31R                     RTC_BKP31R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER_Pos             (5U)
+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */
+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk
+
+/******************************************************************************/
+/*                                                                            */
+/*                              SPDIF-RX Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for SPDIF_CR register  ******************/
+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)
+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */
+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */
+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)
+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */
+#define SPDIFRX_CR_RXSTEO_Pos       (3U)
+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */
+#define SPDIFRX_CR_DRFMT_Pos        (4U)
+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */
+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */
+#define SPDIFRX_CR_PMSK_Pos         (6U)
+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */
+#define SPDIFRX_CR_VMSK_Pos         (7U)
+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */
+#define SPDIFRX_CR_CUMSK_Pos        (8U)
+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */
+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */
+#define SPDIFRX_CR_PTMSK_Pos        (9U)
+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */
+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */
+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)
+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */
+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */
+#define SPDIFRX_CR_CHSEL_Pos        (11U)
+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */
+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */
+#define SPDIFRX_CR_NBTR_Pos         (12U)
+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */
+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */
+#define SPDIFRX_CR_WFA_Pos          (14U)
+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */
+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */
+#define SPDIFRX_CR_INSEL_Pos        (16U)
+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */
+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */
+#define SPDIFRX_CR_CKSEN_Pos        (20U)
+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */
+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */
+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)
+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */
+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */
+
+/*******************  Bit definition for SPDIFRX_IMR register  *******************/
+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)
+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */
+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */
+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)
+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */
+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */
+#define SPDIFRX_IMR_PERRIE_Pos      (2U)
+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */
+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */
+#define SPDIFRX_IMR_OVRIE_Pos       (3U)
+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */
+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */
+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)
+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */
+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)
+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */
+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */
+#define SPDIFRX_IMR_IFEIE_Pos       (6U)
+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */
+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */
+
+/*******************  Bit definition for SPDIFRX_SR register  *******************/
+#define SPDIFRX_SR_RXNE_Pos         (0U)
+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */
+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */
+#define SPDIFRX_SR_CSRNE_Pos        (1U)
+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */
+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */
+#define SPDIFRX_SR_PERR_Pos         (2U)
+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */
+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */
+#define SPDIFRX_SR_OVR_Pos          (3U)
+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */
+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */
+#define SPDIFRX_SR_SBD_Pos          (4U)
+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */
+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */
+#define SPDIFRX_SR_SYNCD_Pos        (5U)
+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */
+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */
+#define SPDIFRX_SR_FERR_Pos         (6U)
+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */
+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */
+#define SPDIFRX_SR_SERR_Pos         (7U)
+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */
+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */
+#define SPDIFRX_SR_TERR_Pos         (8U)
+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */
+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */
+#define SPDIFRX_SR_WIDTH5_Pos       (16U)
+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */
+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */
+
+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/
+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)
+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */
+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */
+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)
+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */
+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */
+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)
+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */
+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */
+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)
+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */
+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/
+#define SPDIFRX_DR0_DR_Pos          (0U)
+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */
+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR0_PE_Pos          (24U)
+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */
+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */
+#define SPDIFRX_DR0_V_Pos           (25U)
+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */
+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR0_U_Pos           (26U)
+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */
+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR0_C_Pos           (27U)
+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */
+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR0_PT_Pos          (28U)
+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */
+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/
+#define SPDIFRX_DR1_DR_Pos          (8U)
+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */
+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */
+#define SPDIFRX_DR1_PT_Pos          (4U)
+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */
+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */
+#define SPDIFRX_DR1_C_Pos           (3U)
+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */
+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */
+#define SPDIFRX_DR1_U_Pos           (2U)
+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */
+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */
+#define SPDIFRX_DR1_V_Pos           (1U)
+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */
+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */
+#define SPDIFRX_DR1_PE_Pos          (0U)
+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */
+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */
+
+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/
+#define SPDIFRX_DR1_DRNL1_Pos       (16U)
+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */
+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */
+#define SPDIFRX_DR1_DRNL2_Pos       (0U)
+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */
+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */
+
+/*******************  Bit definition for SPDIFRX_CSR register   *******************/
+#define SPDIFRX_CSR_USR_Pos         (0U)
+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */
+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */
+#define SPDIFRX_CSR_CS_Pos          (16U)
+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */
+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */
+#define SPDIFRX_CSR_SOB_Pos         (24U)
+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */
+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */
+
+/*******************  Bit definition for SPDIFRX_DIR register    *******************/
+#define SPDIFRX_DIR_THI_Pos         (0U)
+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */
+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */
+#define SPDIFRX_DIR_TLO_Pos         (16U)
+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */
+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */
+
+/*******************  Bit definition for SPDIFRX_VERR register    *******************/
+#define SPDIFRX_VERR_MINREV_Pos     (0U)
+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */
+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */
+#define SPDIFRX_VERR_MAJREV_Pos     (4U)
+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */
+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */
+
+/*******************  Bit definition for SPDIFRX_IDR register    *******************/
+#define SPDIFRX_IDR_ID_Pos          (0U)
+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */
+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */
+
+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/
+#define SPDIFRX_SIDR_SID_Pos        (0U)
+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */
+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Serial Audio Interface                            */
+/*                                                                            */
+/******************************************************************************/
+/*******************************  SAI VERSION  ********************************/
+#define SAI_VER_V2_X
+
+/********************  Bit definition for SAI_GCR register  *******************/
+#define SAI_GCR_SYNCIN_Pos         (0U)
+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */
+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */
+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */
+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */
+
+#define SAI_GCR_SYNCOUT_Pos        (4U)
+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */
+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */
+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */
+
+/*******************  Bit definition for SAI_xCR1 register  *******************/
+#define SAI_xCR1_MODE_Pos          (0U)
+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */
+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */
+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */
+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */
+
+#define SAI_xCR1_PRTCFG_Pos        (2U)
+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */
+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */
+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */
+
+#define SAI_xCR1_DS_Pos            (5U)
+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */
+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */
+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */
+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */
+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */
+
+#define SAI_xCR1_LSBFIRST_Pos      (8U)
+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */
+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */
+#define SAI_xCR1_CKSTR_Pos         (9U)
+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */
+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */
+
+#define SAI_xCR1_SYNCEN_Pos        (10U)
+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */
+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */
+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */
+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */
+
+#define SAI_xCR1_MONO_Pos          (12U)
+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */
+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */
+#define SAI_xCR1_OUTDRIV_Pos       (13U)
+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */
+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */
+#define SAI_xCR1_SAIEN_Pos         (16U)
+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */
+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */
+#define SAI_xCR1_DMAEN_Pos         (17U)
+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */
+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */
+#define SAI_xCR1_NODIV_Pos         (19U)
+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */
+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */
+
+#define SAI_xCR1_MCKDIV_Pos        (20U)
+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */
+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */
+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */
+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */
+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */
+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */
+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */
+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */
+
+#define SAI_xCR1_MCKEN_Pos         (27U)
+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */
+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */
+
+#define SAI_xCR1_OSR_Pos           (26U)
+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */
+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */
+
+/* Legacy define */
+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV
+
+/*******************  Bit definition for SAI_xCR2 register  *******************/
+#define SAI_xCR2_FTH_Pos           (0U)
+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */
+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */
+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */
+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */
+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */
+
+#define SAI_xCR2_FFLUSH_Pos        (3U)
+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */
+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */
+#define SAI_xCR2_TRIS_Pos          (4U)
+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */
+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */
+#define SAI_xCR2_MUTE_Pos          (5U)
+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */
+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */
+#define SAI_xCR2_MUTEVAL_Pos       (6U)
+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */
+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */
+
+#define SAI_xCR2_MUTECNT_Pos       (7U)
+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */
+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */
+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */
+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */
+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */
+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */
+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */
+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */
+
+#define SAI_xCR2_CPL_Pos           (13U)
+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */
+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */
+
+#define SAI_xCR2_COMP_Pos          (14U)
+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */
+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */
+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */
+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for SAI_xFRCR register  *******************/
+#define SAI_xFRCR_FRL_Pos          (0U)
+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */
+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */
+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */
+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */
+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */
+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */
+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */
+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */
+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */
+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */
+
+#define SAI_xFRCR_FSALL_Pos        (8U)
+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */
+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */
+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */
+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */
+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */
+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */
+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */
+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */
+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */
+
+#define SAI_xFRCR_FSDEF_Pos        (16U)
+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */
+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */
+#define SAI_xFRCR_FSPOL_Pos        (17U)
+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */
+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */
+#define SAI_xFRCR_FSOFF_Pos        (18U)
+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */
+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */
+
+/* Legacy define */
+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL
+
+/******************  Bit definition for SAI_xSLOTR register  *******************/
+#define SAI_xSLOTR_FBOFF_Pos       (0U)
+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */
+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */
+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */
+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */
+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */
+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */
+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */
+
+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)
+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */
+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */
+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */
+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */
+
+#define SAI_xSLOTR_NBSLOT_Pos      (8U)
+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */
+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */
+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */
+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */
+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */
+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */
+
+#define SAI_xSLOTR_SLOTEN_Pos      (16U)
+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */
+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */
+
+/*******************  Bit definition for SAI_xIMR register  *******************/
+#define SAI_xIMR_OVRUDRIE_Pos      (0U)
+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */
+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */
+#define SAI_xIMR_MUTEDETIE_Pos     (1U)
+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */
+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */
+#define SAI_xIMR_WCKCFGIE_Pos      (2U)
+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */
+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */
+#define SAI_xIMR_FREQIE_Pos        (3U)
+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */
+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */
+#define SAI_xIMR_CNRDYIE_Pos       (4U)
+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */
+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */
+#define SAI_xIMR_AFSDETIE_Pos      (5U)
+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */
+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */
+#define SAI_xIMR_LFSDETIE_Pos      (6U)
+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */
+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */
+
+/********************  Bit definition for SAI_xSR register  *******************/
+#define SAI_xSR_OVRUDR_Pos         (0U)
+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */
+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */
+#define SAI_xSR_MUTEDET_Pos        (1U)
+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */
+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */
+#define SAI_xSR_WCKCFG_Pos         (2U)
+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */
+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */
+#define SAI_xSR_FREQ_Pos           (3U)
+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */
+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */
+#define SAI_xSR_CNRDY_Pos          (4U)
+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */
+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */
+#define SAI_xSR_AFSDET_Pos         (5U)
+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */
+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */
+#define SAI_xSR_LFSDET_Pos         (6U)
+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */
+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */
+
+#define SAI_xSR_FLVL_Pos           (16U)
+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */
+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */
+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */
+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */
+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */
+
+/******************  Bit definition for SAI_xCLRFR register  ******************/
+#define SAI_xCLRFR_COVRUDR_Pos     (0U)
+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */
+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */
+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)
+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */
+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */
+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)
+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */
+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */
+#define SAI_xCLRFR_CFREQ_Pos       (3U)
+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */
+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */
+#define SAI_xCLRFR_CCNRDY_Pos      (4U)
+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */
+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */
+#define SAI_xCLRFR_CAFSDET_Pos     (5U)
+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */
+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */
+#define SAI_xCLRFR_CLFSDET_Pos     (6U)
+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */
+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */
+
+/******************  Bit definition for SAI_xDR register  *********************/
+#define SAI_xDR_DATA_Pos           (0U)
+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */
+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk
+
+/*******************  Bit definition for SAI_PDMCR register  ******************/
+#define SAI_PDMCR_PDMEN_Pos        (0U)
+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */
+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */
+
+#define SAI_PDMCR_MICNBR_Pos       (4U)
+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */
+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */
+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */
+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */
+
+#define SAI_PDMCR_CKEN1_Pos        (8U)
+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */
+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */
+#define SAI_PDMCR_CKEN2_Pos        (9U)
+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */
+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */
+#define SAI_PDMCR_CKEN3_Pos        (10U)
+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */
+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */
+#define SAI_PDMCR_CKEN4_Pos        (11U)
+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */
+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */
+
+/******************  Bit definition for SAI_PDMDLY register  ******************/
+#define SAI_PDMDLY_DLYM1L_Pos      (0U)
+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */
+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */
+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */
+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */
+
+#define SAI_PDMDLY_DLYM1R_Pos      (4U)
+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */
+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */
+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */
+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */
+
+#define SAI_PDMDLY_DLYM2L_Pos      (8U)
+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */
+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */
+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */
+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */
+
+#define SAI_PDMDLY_DLYM2R_Pos      (12U)
+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */
+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */
+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */
+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */
+
+#define SAI_PDMDLY_DLYM3L_Pos      (16U)
+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */
+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */
+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */
+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */
+
+#define SAI_PDMDLY_DLYM3R_Pos      (20U)
+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */
+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */
+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */
+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */
+
+#define SAI_PDMDLY_DLYM4L_Pos      (24U)
+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */
+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */
+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */
+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */
+
+#define SAI_PDMDLY_DLYM4R_Pos      (28U)
+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */
+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */
+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */
+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           SDMMC Interface                                  */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDMMC_POWER register  ******************/
+#define SDMMC_POWER_PWRCTRL_Pos          (0U)
+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */
+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */
+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */
+#define SDMMC_POWER_VSWITCH_Pos          (2U)
+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */
+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */
+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)
+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */
+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */
+#define SDMMC_POWER_DIRPOL_Pos           (4U)
+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */
+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */
+
+/******************  Bit definition for SDMMC_CLKCR register  ******************/
+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)
+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */
+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */
+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)
+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */
+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */
+
+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)
+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */
+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */
+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */
+
+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)
+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */
+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */
+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)
+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */
+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */
+#define SDMMC_CLKCR_DDR_Pos              (18U)
+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */
+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */
+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)
+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */
+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */
+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)
+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */
+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */
+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */
+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */
+
+/*******************  Bit definition for SDMMC_ARG register  *******************/
+#define SDMMC_ARG_CMDARG_Pos             (0U)
+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */
+
+/*******************  Bit definition for SDMMC_CMD register  *******************/
+#define SDMMC_CMD_CMDINDEX_Pos           (0U)
+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */
+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */
+#define SDMMC_CMD_CMDTRANS_Pos           (6U)
+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */
+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */
+#define SDMMC_CMD_CMDSTOP_Pos            (7U)
+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */
+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */
+
+#define SDMMC_CMD_WAITRESP_Pos           (8U)
+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */
+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */
+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */
+
+#define SDMMC_CMD_WAITINT_Pos            (10U)
+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */
+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */
+#define SDMMC_CMD_WAITPEND_Pos           (11U)
+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */
+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDMMC_CMD_CPSMEN_Pos             (12U)
+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */
+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDMMC_CMD_DTHOLD_Pos             (13U)
+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */
+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */
+#define SDMMC_CMD_BOOTMODE_Pos           (14U)
+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */
+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */
+#define SDMMC_CMD_BOOTEN_Pos             (15U)
+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */
+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */
+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)
+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */
+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */
+
+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/
+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)
+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */
+
+/******************  Bit definition for SDMMC_RESP0 register  ******************/
+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)
+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP1 register  ******************/
+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)
+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP2 register  ******************/
+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)
+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP3 register  ******************/
+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)
+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_RESP4 register  ******************/
+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)
+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */
+
+/******************  Bit definition for SDMMC_DTIMER register  *****************/
+#define SDMMC_DTIMER_DATATIME_Pos        (0U)
+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */
+
+/******************  Bit definition for SDMMC_DLEN register  *******************/
+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)
+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */
+
+/******************  Bit definition for SDMMC_DCTRL register  ******************/
+#define SDMMC_DCTRL_DTEN_Pos             (0U)
+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */
+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */
+#define SDMMC_DCTRL_DTDIR_Pos            (1U)
+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */
+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */
+#define SDMMC_DCTRL_DTMODE_Pos           (2U)
+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */
+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */
+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */
+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */
+
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */
+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */
+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */
+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */
+
+#define SDMMC_DCTRL_RWSTART_Pos          (8U)
+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */
+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */
+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)
+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */
+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */
+#define SDMMC_DCTRL_RWMOD_Pos            (10U)
+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */
+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */
+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)
+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */
+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */
+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)
+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */
+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */
+#define SDMMC_DCTRL_FIFORST_Pos          (13U)
+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */
+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */
+
+/******************  Bit definition for SDMMC_DCOUNT register  *****************/
+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)
+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */
+
+/******************  Bit definition for SDMMC_STA register  ********************/
+#define SDMMC_STA_CCRCFAIL_Pos           (0U)
+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */
+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */
+#define SDMMC_STA_DCRCFAIL_Pos           (1U)
+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */
+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */
+#define SDMMC_STA_CTIMEOUT_Pos           (2U)
+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */
+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */
+#define SDMMC_STA_DTIMEOUT_Pos           (3U)
+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */
+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */
+#define SDMMC_STA_TXUNDERR_Pos           (4U)
+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */
+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */
+#define SDMMC_STA_RXOVERR_Pos            (5U)
+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */
+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */
+#define SDMMC_STA_CMDREND_Pos            (6U)
+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */
+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */
+#define SDMMC_STA_CMDSENT_Pos            (7U)
+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */
+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */
+#define SDMMC_STA_DATAEND_Pos            (8U)
+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */
+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDMMC_STA_DHOLD_Pos              (9U)
+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */
+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */
+#define SDMMC_STA_DBCKEND_Pos            (10U)
+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */
+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */
+#define SDMMC_STA_DABORT_Pos             (11U)
+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */
+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */
+#define SDMMC_STA_DPSMACT_Pos            (12U)
+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */
+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */
+#define SDMMC_STA_CPSMACT_Pos            (13U)
+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */
+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */
+#define SDMMC_STA_TXFIFOHE_Pos           (14U)
+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */
+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDMMC_STA_RXFIFOHF_Pos           (15U)
+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */
+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDMMC_STA_TXFIFOF_Pos            (16U)
+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */
+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */
+#define SDMMC_STA_RXFIFOF_Pos            (17U)
+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */
+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */
+#define SDMMC_STA_TXFIFOE_Pos            (18U)
+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */
+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */
+#define SDMMC_STA_RXFIFOE_Pos            (19U)
+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */
+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */
+#define SDMMC_STA_BUSYD0_Pos             (20U)
+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */
+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */
+#define SDMMC_STA_BUSYD0END_Pos          (21U)
+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */
+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */
+#define SDMMC_STA_SDIOIT_Pos             (22U)
+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */
+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */
+#define SDMMC_STA_ACKFAIL_Pos            (23U)
+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */
+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */
+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)
+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */
+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */
+#define SDMMC_STA_VSWEND_Pos             (25U)
+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */
+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */
+#define SDMMC_STA_CKSTOP_Pos             (26U)
+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */
+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */
+#define SDMMC_STA_IDMATE_Pos             (27U)
+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */
+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */
+#define SDMMC_STA_IDMABTC_Pos            (28U)
+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */
+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */
+
+/*******************  Bit definition for SDMMC_ICR register  *******************/
+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)
+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */
+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */
+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)
+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */
+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */
+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)
+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */
+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */
+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)
+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */
+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */
+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)
+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */
+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */
+#define SDMMC_ICR_RXOVERRC_Pos           (5U)
+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */
+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */
+#define SDMMC_ICR_CMDRENDC_Pos           (6U)
+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */
+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */
+#define SDMMC_ICR_CMDSENTC_Pos           (7U)
+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */
+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */
+#define SDMMC_ICR_DATAENDC_Pos           (8U)
+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */
+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */
+#define SDMMC_ICR_DHOLDC_Pos             (9U)
+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */
+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */
+#define SDMMC_ICR_DBCKENDC_Pos           (10U)
+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */
+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */
+#define SDMMC_ICR_DABORTC_Pos            (11U)
+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */
+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */
+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)
+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */
+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */
+#define SDMMC_ICR_SDIOITC_Pos            (22U)
+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */
+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */
+#define SDMMC_ICR_ACKFAILC_Pos           (23U)
+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */
+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */
+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)
+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */
+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */
+#define SDMMC_ICR_VSWENDC_Pos            (25U)
+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */
+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */
+#define SDMMC_ICR_CKSTOPC_Pos            (26U)
+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */
+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */
+#define SDMMC_ICR_IDMATEC_Pos            (27U)
+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */
+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */
+#define SDMMC_ICR_IDMABTCC_Pos           (28U)
+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */
+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */
+
+/******************  Bit definition for SDMMC_MASK register  *******************/
+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)
+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */
+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */
+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)
+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */
+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */
+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)
+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */
+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */
+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)
+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */
+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */
+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)
+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */
+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)
+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */
+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)
+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */
+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */
+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)
+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */
+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */
+#define SDMMC_MASK_DATAENDIE_Pos         (8U)
+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */
+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */
+#define SDMMC_MASK_DHOLDIE_Pos           (9U)
+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */
+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */
+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)
+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */
+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */
+#define SDMMC_MASK_DABORTIE_Pos          (11U)
+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */
+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */
+
+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)
+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */
+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)
+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */
+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */
+
+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)
+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */
+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */
+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)
+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */
+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */
+
+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)
+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */
+#define SDMMC_MASK_SDIOITIE_Pos           (22U)
+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */
+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */
+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)
+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */
+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */
+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)
+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */
+#define SDMMC_MASK_VSWENDIE_Pos          (25U)
+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */
+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */
+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)
+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */
+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */
+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)
+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */
+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */
+
+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/
+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)
+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */
+
+/******************  Bit definition for SDMMC_FIFO register  *******************/
+#define SDMMC_FIFO_FIFODATA_Pos          (0U)
+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */
+
+/******************  Bit definition for SDMMC_IDMACTRL register ****************/
+#define SDMMC_IDMA_IDMAEN_Pos            (0U)
+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */
+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */
+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)
+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */
+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */
+#define SDMMC_IDMA_IDMABACT_Pos          (2U)
+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */
+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */
+
+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/
+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)
+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
+
+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
+
+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Delay Block Interface (DLYB)                        */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for DLYB_CR register  ********************/
+#define DLYB_CR_DEN_Pos         (0U)
+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */
+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */
+#define DLYB_CR_SEN_Pos         (1U)
+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */
+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */
+
+
+/*******************  Bit definition for DLYB_CFGR register  ********************/
+#define DLYB_CFGR_SEL_Pos       (0U)
+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */
+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */
+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */
+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */
+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */
+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */
+
+#define DLYB_CFGR_UNIT_Pos      (8U)
+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */
+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */
+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */
+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */
+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */
+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */
+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */
+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */
+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */
+
+#define DLYB_CFGR_LNG_Pos       (16U)
+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */
+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */
+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */
+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */
+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */
+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */
+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */
+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */
+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */
+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */
+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */
+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */
+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */
+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */
+
+#define DLYB_CFGR_LNGF_Pos      (31U)
+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */
+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Serial Peripheral Interface (SPI/I2S)                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_SPE_Pos             (0U)
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */
+#define SPI_CR1_MASRX_Pos           (8U)
+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */
+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */
+#define SPI_CR1_CSTART_Pos          (9U)
+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */
+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */
+#define SPI_CR1_CSUSP_Pos           (10U)
+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */
+#define SPI_CR1_HDDIR_Pos           (11U)
+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */
+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */
+#define SPI_CR1_SSI_Pos             (12U)
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */
+#define SPI_CR1_CRC33_17_Pos        (13U)
+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */
+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */
+#define SPI_CR1_RCRCINI_Pos         (14U)
+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */
+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */
+#define SPI_CR1_TCRCINI_Pos         (15U)
+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */
+#define SPI_CR1_IOLOCK_Pos          (16U)
+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */
+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_TSER_Pos            (16U)
+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */
+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */
+#define SPI_CR2_TSIZE_Pos           (0U)
+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */
+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */
+
+/*******************  Bit definition for SPI_CFG1 register  ********************/
+#define SPI_CFG1_DSIZE_Pos          (0U)
+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */
+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */
+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */
+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */
+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */
+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */
+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */
+
+#define SPI_CFG1_FTHLV_Pos          (5U)
+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */
+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/
+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */
+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */
+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */
+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */
+
+#define SPI_CFG1_UDRCFG_Pos         (9U)
+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */
+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */
+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */
+
+
+#define SPI_CFG1_UDRDET_Pos         (11U)
+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */
+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */
+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */
+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */
+
+#define SPI_CFG1_RXDMAEN_Pos        (14U)
+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */
+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */
+#define SPI_CFG1_TXDMAEN_Pos        (15U)
+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */
+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */
+
+#define SPI_CFG1_CRCSIZE_Pos        (16U)
+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */
+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/
+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */
+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */
+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */
+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */
+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */
+
+#define SPI_CFG1_CRCEN_Pos          (22U)
+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */
+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */
+
+#define SPI_CFG1_MBR_Pos            (28U)
+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */
+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */
+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */
+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */
+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */
+
+/*******************  Bit definition for SPI_CFG2 register  ********************/
+#define SPI_CFG2_MSSI_Pos           (0U)
+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */
+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */
+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */
+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */
+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */
+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */
+
+#define SPI_CFG2_MIDI_Pos           (4U)
+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */
+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */
+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */
+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */
+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */
+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */
+
+#define SPI_CFG2_IOSWP_Pos          (15U)
+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */
+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */
+
+#define SPI_CFG2_COMM_Pos           (17U)
+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */
+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/
+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */
+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */
+
+#define SPI_CFG2_SP_Pos             (19U)
+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */
+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */
+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */
+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */
+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */
+
+#define SPI_CFG2_MASTER_Pos         (22U)
+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */
+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */
+#define SPI_CFG2_LSBFRST_Pos        (23U)
+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */
+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */
+#define SPI_CFG2_CPHA_Pos           (24U)
+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */
+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */
+#define SPI_CFG2_CPOL_Pos           (25U)
+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */
+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */
+#define SPI_CFG2_SSM_Pos            (26U)
+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */
+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */
+
+#define SPI_CFG2_SSIOP_Pos          (28U)
+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */
+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */
+#define SPI_CFG2_SSOE_Pos           (29U)
+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */
+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */
+#define SPI_CFG2_SSOM_Pos           (30U)
+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */
+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */
+
+#define SPI_CFG2_AFCNTR_Pos         (31U)
+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */
+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */
+
+/*******************  Bit definition for SPI_IER register  ********************/
+#define SPI_IER_RXPIE_Pos           (0U)
+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */
+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */
+#define SPI_IER_TXPIE_Pos           (1U)
+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */
+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */
+#define SPI_IER_DXPIE_Pos           (2U)
+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */
+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */
+#define SPI_IER_EOTIE_Pos           (3U)
+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */
+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */
+#define SPI_IER_TXTFIE_Pos          (4U)
+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */
+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */
+#define SPI_IER_UDRIE_Pos           (5U)
+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */
+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */
+#define SPI_IER_OVRIE_Pos           (6U)
+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */
+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */
+#define SPI_IER_CRCEIE_Pos          (7U)
+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */
+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */
+#define SPI_IER_TIFREIE_Pos         (8U)
+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */
+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */
+#define SPI_IER_MODFIE_Pos          (9U)
+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */
+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */
+#define SPI_IER_TSERFIE_Pos         (10U)
+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */
+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */
+
+/*******************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXP_Pos              (0U)
+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_TXP_Pos              (1U)
+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */
+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */
+#define SPI_SR_DXP_Pos              (2U)
+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */
+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_EOT_Pos              (3U)
+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */
+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */
+#define SPI_SR_TXTF_Pos             (4U)
+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */
+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */
+#define SPI_SR_UDR_Pos              (5U)
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */
+#define SPI_SR_OVR_Pos              (6U)
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */
+#define SPI_SR_CRCE_Pos             (7U)
+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */
+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */
+#define SPI_SR_TIFRE_Pos            (8U)
+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */
+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */
+#define SPI_SR_MODF_Pos             (9U)
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */
+#define SPI_SR_TSERF_Pos            (10U)
+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */
+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */
+#define SPI_SR_SUSP_Pos             (11U)
+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */
+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */
+#define SPI_SR_TXC_Pos              (12U)
+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */
+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */
+#define SPI_SR_RXPLVL_Pos           (13U)
+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */
+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */
+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */
+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */
+#define SPI_SR_RXWNE_Pos            (15U)
+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */
+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */
+#define SPI_SR_CTSIZE_Pos           (16U)
+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */
+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */
+
+/*******************  Bit definition for SPI_IFCR register  ********************/
+#define SPI_IFCR_EOTC_Pos           (3U)
+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */
+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */
+#define SPI_IFCR_TXTFC_Pos          (4U)
+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */
+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */
+#define SPI_IFCR_UDRC_Pos           (5U)
+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */
+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */
+#define SPI_IFCR_OVRC_Pos           (6U)
+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */
+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */
+#define SPI_IFCR_CRCEC_Pos          (7U)
+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */
+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */
+#define SPI_IFCR_TIFREC_Pos         (8U)
+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */
+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */
+#define SPI_IFCR_MODFC_Pos          (9U)
+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */
+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */
+#define SPI_IFCR_TSERFC_Pos         (10U)
+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */
+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */
+#define SPI_IFCR_SUSPC_Pos          (11U)
+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */
+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */
+
+/*******************  Bit definition for SPI_TXDR register  ********************/
+#define SPI_TXDR_TXDR_Pos           (0U)
+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */
+
+/*******************  Bit definition for SPI_RXDR register  ********************/
+#define SPI_RXDR_RXDR_Pos           (0U)
+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */
+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */
+
+/*******************  Bit definition for SPI_CRCPOLY register  ********************/
+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)
+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */
+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */
+
+/*******************  Bit definition for SPI_TXCRC register  ********************/
+#define SPI_TXCRC_TXCRC_Pos         (0U)
+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */
+
+/*******************  Bit definition for SPI_RXCRC register  ********************/
+#define SPI_RXCRC_RXCRC_Pos         (0U)
+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */
+
+/*******************  Bit definition for SPI_UDRDR register  ********************/
+#define SPI_UDRDR_UDRDR_Pos         (0U)
+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */
+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */
+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */
+#define SPI_I2SCFGR_DATLEN_Pos      (8U)
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */
+#define SPI_I2SCFGR_CHLEN_Pos       (10U)
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_CKPOL_Pos       (11U)
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */
+#define SPI_I2SCFGR_FIXCH_Pos       (12U)
+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */
+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */
+#define SPI_I2SCFGR_WSINV_Pos       (13U)
+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */
+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */
+#define SPI_I2SCFGR_DATFMT_Pos      (14U)
+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */
+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */
+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)
+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */
+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */
+#define SPI_I2SCFGR_ODD_Pos         (24U)
+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */
+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */
+#define SPI_I2SCFGR_MCKOE_Pos       (25U)
+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */
+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    QUADSPI                                 */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for QUADSPI_CR register  *******************/
+#define QUADSPI_CR_EN_Pos                (0U)
+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */
+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */
+#define QUADSPI_CR_ABORT_Pos             (1U)
+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */
+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */
+#define QUADSPI_CR_DMAEN_Pos             (2U)
+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */
+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< Reserved: needed for softawre compatibility (DMA Enable) */
+#define QUADSPI_CR_TCEN_Pos              (3U)
+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */
+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */
+#define QUADSPI_CR_SSHIFT_Pos            (4U)
+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */
+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */
+#define QUADSPI_CR_DFM_Pos               (6U)
+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */
+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */
+#define QUADSPI_CR_FSEL_Pos              (7U)
+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
+#define QUADSPI_CR_FTHRES_Pos            (8U)
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
+#define QUADSPI_CR_TEIE_Pos              (16U)
+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
+#define QUADSPI_CR_TCIE_Pos              (17U)
+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */
+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */
+#define QUADSPI_CR_FTIE_Pos              (18U)
+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */
+#define QUADSPI_CR_SMIE_Pos              (19U)
+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */
+#define QUADSPI_CR_TOIE_Pos              (20U)
+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */
+#define QUADSPI_CR_APMS_Pos              (22U)
+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */
+#define QUADSPI_CR_PMM_Pos               (23U)
+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */
+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */
+#define QUADSPI_CR_PRESCALER_Pos         (24U)
+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */
+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */
+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */
+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */
+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */
+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */
+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */
+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */
+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */
+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */
+
+/*****************  Bit definition for QUADSPI_DCR register  ******************/
+#define QUADSPI_DCR_CKMODE_Pos           (0U)
+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */
+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */
+#define QUADSPI_DCR_CSHT_Pos             (8U)
+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */
+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */
+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */
+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */
+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */
+#define QUADSPI_DCR_FSIZE_Pos            (16U)
+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */
+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */
+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */
+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */
+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */
+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */
+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for QUADSPI_SR register  *******************/
+#define QUADSPI_SR_TEF_Pos               (0U)
+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */
+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */
+#define QUADSPI_SR_TCF_Pos               (1U)
+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */
+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */
+#define QUADSPI_SR_FTF_Pos               (2U)
+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */
+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_SMF_Pos               (3U)
+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */
+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */
+#define QUADSPI_SR_TOF_Pos               (4U)
+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */
+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */
+#define QUADSPI_SR_BUSY_Pos              (5U)
+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */
+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */
+#define QUADSPI_SR_FLEVEL_Pos            (8U)
+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */
+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */
+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */
+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */
+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */
+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */
+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */
+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */
+
+/******************  Bit definition for QUADSPI_FCR register  ******************/
+#define QUADSPI_FCR_CTEF_Pos             (0U)
+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */
+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */
+#define QUADSPI_FCR_CTCF_Pos             (1U)
+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */
+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */
+#define QUADSPI_FCR_CSMF_Pos             (3U)
+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */
+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */
+#define QUADSPI_FCR_CTOF_Pos             (4U)
+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */
+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */
+
+/******************  Bit definition for QUADSPI_DLR register  ******************/
+#define QUADSPI_DLR_DL_Pos               (0U)
+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */
+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */
+
+/******************  Bit definition for QUADSPI_CCR register  ******************/
+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)
+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */
+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
+#define QUADSPI_CCR_IMODE_Pos            (8U)
+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */
+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */
+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */
+#define QUADSPI_CCR_ADMODE_Pos           (10U)
+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */
+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */
+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */
+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */
+#define QUADSPI_CCR_ADSIZE_Pos           (12U)
+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */
+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */
+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */
+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */
+#define QUADSPI_CCR_ABMODE_Pos           (14U)
+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */
+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */
+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */
+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */
+#define QUADSPI_CCR_ABSIZE_Pos           (16U)
+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */
+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */
+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */
+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */
+#define QUADSPI_CCR_DCYC_Pos             (18U)
+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */
+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */
+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */
+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */
+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */
+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */
+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */
+#define QUADSPI_CCR_DMODE_Pos            (24U)
+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */
+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */
+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */
+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */
+#define QUADSPI_CCR_FMODE_Pos            (26U)
+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */
+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */
+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */
+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */
+#define QUADSPI_CCR_SIOO_Pos             (28U)
+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */
+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */
+#define QUADSPI_CCR_DHHC_Pos             (30U)
+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */
+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */
+#define QUADSPI_CCR_DDRM_Pos             (31U)
+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */
+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */
+
+/******************  Bit definition for QUADSPI_AR register  *******************/
+#define QUADSPI_AR_ADDRESS_Pos           (0U)
+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */
+
+/******************  Bit definition for QUADSPI_ABR register  ******************/
+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)
+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */
+
+/******************  Bit definition for QUADSPI_DR register  *******************/
+#define QUADSPI_DR_DATA_Pos              (0U)
+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */
+
+/******************  Bit definition for QUADSPI_PSMKR register  ****************/
+#define QUADSPI_PSMKR_MASK_Pos           (0U)
+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */
+
+/******************  Bit definition for QUADSPI_PSMAR register  ****************/
+#define QUADSPI_PSMAR_MATCH_Pos          (0U)
+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */
+
+/******************  Bit definition for QUADSPI_PIR register  *****************/
+#define QUADSPI_PIR_INTERVAL_Pos         (0U)
+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */
+
+/******************  Bit definition for QUADSPI_LPTR register  *****************/
+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)
+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for SYSCFG_PMCR register  ******************/
+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)
+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */
+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */
+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)
+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */
+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */
+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)
+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */
+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */
+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)
+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */
+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)
+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)
+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)
+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)
+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */
+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)
+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */
+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */
+
+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)
+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */
+
+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)
+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */
+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */
+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */
+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */
+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */
+#define SYSCFG_PMCR_PA0SO_Pos           (24U)
+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */
+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */
+#define SYSCFG_PMCR_PA1SO_Pos           (25U)
+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */
+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */
+#define SYSCFG_PMCR_PC2SO_Pos           (26U)
+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */
+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */
+#define SYSCFG_PMCR_PC3SO_Pos           (27U)
+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */
+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
+
+/**
+  * @brief   EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
+/**
+  * @brief   EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
+
+/**
+  * @brief   EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */
+/**
+  * @brief   EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
+/**
+  * @brief   EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
+/**
+  * @brief   EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
+
+/**
+  * @brief   EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
+
+/**
+  * @brief   EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
+
+/**
+  * @brief   EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
+
+/**
+  * @brief   EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */
+/**
+  * @brief   EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
+/**
+  * @brief   EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
+/**
+  * @brief   EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
+/**
+  * @brief   EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
+
+/******************  Bit definition for SYSCFG_CFGR register  ******************/
+#define SYSCFG_CFGR_CM4L_Pos            (0U)
+#define SYSCFG_CFGR_CM4L_Msk            (0x1UL << SYSCFG_CFGR_CM4L_Pos)        /*!< 0x00000001 */
+#define SYSCFG_CFGR_CM4L                SYSCFG_CFGR_CM4L_Msk                   /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_PVDL_Pos            (2U)
+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */
+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */
+#define SYSCFG_CFGR_FLASHL_Pos          (3U)
+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */
+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */
+#define SYSCFG_CFGR_CM7L_Pos            (6U)
+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */
+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
+#define SYSCFG_CFGR_BKRAML_Pos          (7U)
+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */
+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)
+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */
+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)
+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */
+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)
+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */
+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */
+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)
+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */
+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */
+#define SYSCFG_CFGR_DTCML_Pos           (13U)
+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */
+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */
+#define SYSCFG_CFGR_ITCML_Pos           (14U)
+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */
+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */
+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)
+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */
+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */
+
+/******************  Bit definition for SYSCFG_CCCSR register  ******************/
+#define SYSCFG_CCCSR_EN_Pos             (0U)
+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */
+#define SYSCFG_CCCSR_CS_Pos             (1U)
+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */
+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */
+#define SYSCFG_CCCSR_READY_Pos          (8U)
+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */
+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */
+#define SYSCFG_CCCSR_HSLV_Pos           (16U)
+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */
+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */
+
+/******************  Bit definition for SYSCFG_CCVR register  *******************/
+#define SYSCFG_CCVR_NCV_Pos             (0U)
+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */
+#define SYSCFG_CCVR_PCV_Pos             (4U)
+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */
+
+/******************  Bit definition for SYSCFG_CCCR register  *******************/
+#define SYSCFG_CCCR_NCC_Pos             (0U)
+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */
+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */
+#define SYSCFG_CCCR_PCC_Pos             (4U)
+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */
+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */
+/******************  Bit definition for SYSCFG_PWRCR register  *******************/
+#define SYSCFG_PWRCR_ODEN_Pos           (0U)
+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */
+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */
+
+/******************  Bit definition for SYSCFG_PKGR register  *******************/
+#define SYSCFG_PKGR_PKG_Pos             (0U)
+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */
+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */
+
+/******************  Bit definition for SYSCFG_UR0 register  *******************/
+#define SYSCFG_UR0_BKS_Pos              (0U)
+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */
+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */
+#define SYSCFG_UR0_RDP_Pos              (16U)
+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */
+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */
+
+/******************  Bit definition for SYSCFG_UR1 register  *******************/
+#define SYSCFG_UR1_BCM4_Pos             (0U)
+#define SYSCFG_UR1_BCM4_Msk             (0x1UL << SYSCFG_UR1_BCM4_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR1_BCM4                 SYSCFG_UR1_BCM4_Msk                    /*!< Boot Cortex-M4 */
+#define SYSCFG_UR1_BCM7_Pos             (16U)
+#define SYSCFG_UR1_BCM7_Msk             (0x1UL << SYSCFG_UR1_BCM7_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR1_BCM7                 SYSCFG_UR1_BCM7_Msk                    /*!< Boot Cortex-M7 */
+/******************  Bit definition for SYSCFG_UR2 register  *******************/
+#define SYSCFG_UR2_BORH_Pos             (0U)
+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */
+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */
+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */
+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */
+#define SYSCFG_UR2_BCM7_ADD0_Pos        (16U)
+#define SYSCFG_UR2_BCM7_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR2_BCM7_ADD0            SYSCFG_UR2_BCM7_ADD0_Msk               /*!< Boot Cortex-M7 Address 0 */
+/******************  Bit definition for SYSCFG_UR3 register  *******************/
+#define SYSCFG_UR3_BCM7_ADD1_Pos        (0U)
+#define SYSCFG_UR3_BCM7_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR3_BCM7_ADD1            SYSCFG_UR3_BCM7_ADD1_Msk               /*!< Boot Cortex-M7 Address 1 */
+
+#define SYSCFG_UR3_BCM4_ADD0_Pos        (16U)
+#define SYSCFG_UR3_BCM4_ADD0_Msk        (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */
+#define SYSCFG_UR3_BCM4_ADD0            SYSCFG_UR3_BCM4_ADD0_Msk               /*!< Boot Cortex-M4 Address 0 */
+
+/******************  Bit definition for SYSCFG_UR4 register  *******************/
+
+#define SYSCFG_UR4_BCM4_ADD1_Pos        (0U)
+#define SYSCFG_UR4_BCM4_ADD1_Msk        (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */
+#define SYSCFG_UR4_BCM4_ADD1            SYSCFG_UR4_BCM4_ADD1_Msk               /*!< Boot Cortex-M4 Address 1 */
+
+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)
+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR5 register  *******************/
+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)
+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */
+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)
+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */
+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */
+
+/******************  Bit definition for SYSCFG_UR6 register  *******************/
+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */
+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR7 register  *******************/
+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)
+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */
+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)
+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */
+
+/******************  Bit definition for SYSCFG_UR8 register  *******************/
+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)
+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */
+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */
+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)
+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */
+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR9 register  *******************/
+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)
+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */
+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */
+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)
+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR10 register  *******************/
+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */
+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)
+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */
+
+/******************  Bit definition for SYSCFG_UR11 register  *******************/
+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)
+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */
+#define SYSCFG_UR11_IWDG1M_Pos          (16U)
+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */
+
+/******************  Bit definition for SYSCFG_UR12 register  *******************/
+#define SYSCFG_UR12_IWDG2M_Pos          (0U)
+#define SYSCFG_UR12_IWDG2M_Msk          (0x1UL << SYSCFG_UR12_IWDG2M_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR12_IWDG2M              SYSCFG_UR12_IWDG2M_Msk                 /*!< Independent Watchdog 2 mode (SW or HW) */
+
+#define SYSCFG_UR12_SECURE_Pos          (16U)
+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */
+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */
+
+/******************  Bit definition for SYSCFG_UR13 register  *******************/
+#define SYSCFG_UR13_SDRS_Pos            (0U)
+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */
+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */
+#define SYSCFG_UR13_D1SBRST_Pos         (16U)
+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */
+
+/******************  Bit definition for SYSCFG_UR14 register  *******************/
+#define SYSCFG_UR14_D1STPRST_Pos        (0U)
+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */
+#define SYSCFG_UR14_D2SBRST_Pos         (16U)
+#define SYSCFG_UR14_D2SBRST_Msk         (0x1UL << SYSCFG_UR14_D2SBRST_Pos)     /*!< 0x00010000 */
+#define SYSCFG_UR14_D2SBRST             SYSCFG_UR14_D2SBRST_Msk                /*!< D2 Standby Reset */
+
+/******************  Bit definition for SYSCFG_UR15 register  *******************/
+#define SYSCFG_UR15_D2STPRST_Pos        (0U)
+#define SYSCFG_UR15_D2STPRST_Msk        (0x1UL << SYSCFG_UR15_D2STPRST_Pos)    /*!< 0x00000001 */
+#define SYSCFG_UR15_D2STPRST            SYSCFG_UR15_D2STPRST_Msk               /*!< D2 Stop Reset */
+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)
+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */
+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */
+
+/******************  Bit definition for SYSCFG_UR16 register  *******************/
+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)
+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */
+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */
+#define SYSCFG_UR16_PKP_Pos             (16U)
+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */
+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */
+
+/******************  Bit definition for SYSCFG_UR17 register  *******************/
+#define SYSCFG_UR17_IOHSLV_Pos          (0U)
+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */
+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos          (1U)
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
+#define TIM_CR1_URS_Pos           (2U)
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos           (4U)
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
+
+#define TIM_CR1_CMS_Pos           (5U)
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos           (8U)
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */
+
+#define TIM_CR1_UIFREMAP_Pos      (11U)
+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos           (4U)
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
+#define TIM_CR2_OIS1N_Pos         (9U)
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
+#define TIM_CR2_OIS2N_Pos         (11U)
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
+#define TIM_CR2_OIS3N_Pos         (13U)
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS5_Pos          (16U)
+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
+
+#define TIM_CR2_MMS2_Pos          (20U)
+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */
+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */
+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */
+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)
+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */
+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */
+
+#define TIM_SMCR_TS_Pos           (4U)
+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */
+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */
+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */
+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */
+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */
+
+#define TIM_SMCR_MSM_Pos          (7U)
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos          (8U)
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos          (15U)
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos        (2U)
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos        (3U)
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos        (4U)
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_COMIE_Pos        (5U)
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
+#define TIM_DIER_TIE_Pos          (6U)
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
+#define TIM_DIER_BIE_Pos          (7U)
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
+#define TIM_DIER_UDE_Pos          (8U)
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos        (9U)
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos          (14U)
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos          (1U)
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos          (2U)
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos          (3U)
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos          (4U)
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_COMIF_Pos          (5U)
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
+#define TIM_SR_TIF_Pos            (6U)
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
+#define TIM_SR_BIF_Pos            (7U)
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
+#define TIM_SR_B2IF_Pos           (8U)
+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */
+#define TIM_SR_CC1OF_Pos          (9U)
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+#define TIM_SR_CC5IF_Pos          (16U)
+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
+#define TIM_SR_CC6IF_Pos          (17U)
+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
+#define TIM_SR_SBIF_Pos           (13U)
+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos          (1U)
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos          (2U)
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos          (3U)
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos          (4U)
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_COMG_Pos          (5U)
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
+#define TIM_EGR_BG_Pos            (7U)
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
+#define TIM_EGR_B2G_Pos           (8U)
+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */
+
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos       (3U)
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)
+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */
+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos       (11U)
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)
+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */
+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos       (3U)
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos       (11U)
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos         (1U)
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NE_Pos        (2U)
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
+#define TIM_CCER_CC1NP_Pos        (3U)
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos         (5U)
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NE_Pos        (6U)
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
+#define TIM_CCER_CC2NP_Pos        (7U)
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos         (9U)
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NE_Pos        (10U)
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
+#define TIM_CCER_CC3NP_Pos        (11U)
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos         (13U)
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos        (15U)
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+#define TIM_CCER_CC5E_Pos         (16U)
+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
+#define TIM_CCER_CC5P_Pos         (17U)
+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
+#define TIM_CCER_CC6E_Pos         (20U)
+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
+#define TIM_CCER_CC6P_Pos         (21U)
+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
+#define TIM_CNT_UIFCPY_Pos        (31U)
+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_CCR5 register  *******************/
+#define TIM_CCR5_CCR5_Pos         (0U)
+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */
+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
+#define TIM_CCR5_GC5C1_Pos        (29U)
+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
+#define TIM_CCR5_GC5C2_Pos        (30U)
+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
+#define TIM_CCR5_GC5C3_Pos        (31U)
+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
+
+/*******************  Bit definition for TIM_CCR6 register  *******************/
+#define TIM_CCR6_CCR6_Pos         (0U)
+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */
+#define TIM_BDTR_BK2F_Pos         (20U)
+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */
+
+#define TIM_BDTR_BK2E_Pos         (24U)
+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */
+#define TIM_BDTR_BK2P_Pos         (25U)
+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos           (8U)
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
+
+/******************  Bit definition for TIM_CCMR3 register  *******************/
+#define TIM_CCMR3_OC5FE_Pos       (2U)
+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
+#define TIM_CCMR3_OC5PE_Pos       (3U)
+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
+
+#define TIM_CCMR3_OC5M_Pos        (4U)
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */
+
+#define TIM_CCMR3_OC5CE_Pos       (7U)
+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
+
+#define TIM_CCMR3_OC6FE_Pos       (10U)
+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR3_OC6PE_Pos       (11U)
+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR3_OC6M_Pos        (12U)
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
+
+#define TIM_CCMR3_OC6CE_Pos       (15U)
+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */
+/*******************  Bit definition for TIM1_AF1 register  *********************/
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */
+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)
+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM1_AF1_ETRSEL_Pos       (14U)
+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM1_AF2 register  *********************/
+#define TIM1_AF2_BK2INE_Pos       (0U)
+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM1_AF2_BK2CMP1E_Pos     (1U)
+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM1_AF2_BK2CMP2E_Pos     (2U)
+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)
+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */
+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
+#define TIM1_AF2_BK2INP_Pos       (9U)
+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM1_AF2_BK2CMP1P_Pos     (10U)
+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P_Pos     (11U)
+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */
+
+#define TIM_TISEL_TI3SEL_Pos      (16U)
+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */
+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */
+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */
+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */
+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */
+
+#define TIM_TISEL_TI4SEL_Pos      (24U)
+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */
+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */
+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */
+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */
+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */
+
+/*******************  Bit definition for TIM8_AF1 register  *********************/
+#define TIM8_AF1_BKINE_Pos        (0U)
+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */
+#define TIM8_AF1_BKCMP1E_Pos      (1U)
+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM8_AF1_BKCMP2E_Pos      (2U)
+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM8_AF1_BKDFBK2E_Pos     (8U)
+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */
+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */
+#define TIM8_AF1_BKINP_Pos        (9U)
+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */
+#define TIM8_AF1_BKCMP1P_Pos      (10U)
+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM8_AF1_BKCMP2P_Pos      (11U)
+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */
+
+#define TIM8_AF1_ETRSEL_Pos       (14U)
+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */
+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */
+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */
+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */
+/*******************  Bit definition for TIM8_AF2 register  *********************/
+#define TIM8_AF2_BK2INE_Pos       (0U)
+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */
+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */
+#define TIM8_AF2_BK2CMP1E_Pos     (1U)
+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */
+#define TIM8_AF2_BK2CMP2E_Pos     (2U)
+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */
+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)
+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */
+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
+#define TIM8_AF2_BK2INP_Pos       (9U)
+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */
+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */
+#define TIM8_AF2_BK2CMP1P_Pos     (10U)
+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */
+#define TIM8_AF2_BK2CMP2P_Pos     (11U)
+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */
+
+/*******************  Bit definition for TIM2_AF1 register  *********************/
+#define TIM2_AF1_ETRSEL_Pos      (14U)
+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM3_AF1 register  *********************/
+#define TIM3_AF1_ETRSEL_Pos      (14U)
+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM5_AF1 register  *********************/
+#define TIM5_AF1_ETRSEL_Pos      (14U)
+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */
+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */
+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */
+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */
+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */
+
+/*******************  Bit definition for TIM15_AF1 register  *********************/
+#define TIM15_AF1_BKINE_Pos        (0U)
+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM15_AF1_BKCMP1E_Pos      (1U)
+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM15_AF1_BKCMP2E_Pos      (2U)
+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */
+#define TIM15_AF1_BKINP_Pos        (9U)
+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM15_AF1_BKCMP1P_Pos      (10U)
+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM15_AF1_BKCMP2P_Pos      (11U)
+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM16_ register  *********************/
+#define TIM16_AF1_BKINE_Pos        (0U)
+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM16_AF1_BKCMP1E_Pos      (1U)
+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM16_AF1_BKCMP2E_Pos      (2U)
+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */
+#define TIM16_AF1_BKINP_Pos        (9U)
+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM16_AF1_BKCMP1P_Pos      (10U)
+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P_Pos      (11U)
+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/*******************  Bit definition for TIM17_AF1 register  *********************/
+#define TIM17_AF1_BKINE_Pos        (0U)
+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */
+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */
+#define TIM17_AF1_BKCMP1E_Pos      (1U)
+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */
+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */
+#define TIM17_AF1_BKCMP2E_Pos      (2U)
+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */
+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */
+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)
+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */
+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */
+#define TIM17_AF1_BKINP_Pos        (9U)
+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */
+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */
+#define TIM17_AF1_BKCMP1P_Pos      (10U)
+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */
+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P_Pos      (11U)
+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */
+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Low Power Timer (LPTTIM)                           */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for LPTIM_ISR register  *******************/
+#define LPTIM_ISR_CMPM_Pos          (0U)
+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
+#define LPTIM_ISR_ARRM_Pos          (1U)
+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
+#define LPTIM_ISR_EXTTRIG_Pos       (2U)
+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
+#define LPTIM_ISR_CMPOK_Pos         (3U)
+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
+#define LPTIM_ISR_ARROK_Pos         (4U)
+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
+#define LPTIM_ISR_UP_Pos            (5U)
+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
+#define LPTIM_ISR_DOWN_Pos          (6U)
+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
+
+/******************  Bit definition for LPTIM_ICR register  *******************/
+#define LPTIM_ICR_CMPMCF_Pos        (0U)
+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
+#define LPTIM_ICR_ARRMCF_Pos        (1U)
+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
+#define LPTIM_ICR_CMPOKCF_Pos       (3U)
+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
+#define LPTIM_ICR_ARROKCF_Pos       (4U)
+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
+#define LPTIM_ICR_UPCF_Pos          (5U)
+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
+#define LPTIM_ICR_DOWNCF_Pos        (6U)
+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
+
+/******************  Bit definition for LPTIM_IER register ********************/
+#define LPTIM_IER_CMPMIE_Pos        (0U)
+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
+#define LPTIM_IER_ARRMIE_Pos        (1U)
+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
+#define LPTIM_IER_CMPOKIE_Pos       (3U)
+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
+#define LPTIM_IER_ARROKIE_Pos       (4U)
+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
+#define LPTIM_IER_UPIE_Pos          (5U)
+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
+#define LPTIM_IER_DOWNIE_Pos        (6U)
+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
+
+/******************  Bit definition for LPTIM_CFGR register *******************/
+#define LPTIM_CFGR_CKSEL_Pos        (0U)
+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
+
+#define LPTIM_CFGR_CKPOL_Pos        (1U)
+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */
+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */
+
+#define LPTIM_CFGR_CKFLT_Pos        (3U)
+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */
+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */
+
+#define LPTIM_CFGR_TRGFLT_Pos       (6U)
+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */
+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */
+
+#define LPTIM_CFGR_PRESC_Pos        (9U)
+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */
+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */
+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */
+
+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */
+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */
+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */
+
+#define LPTIM_CFGR_TRIGEN_Pos       (17U)
+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */
+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */
+
+#define LPTIM_CFGR_TIMOUT_Pos       (19U)
+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
+#define LPTIM_CFGR_WAVE_Pos         (20U)
+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
+#define LPTIM_CFGR_WAVPOL_Pos       (21U)
+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
+#define LPTIM_CFGR_PRELOAD_Pos      (22U)
+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
+#define LPTIM_CFGR_ENC_Pos          (24U)
+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
+
+/******************  Bit definition for LPTIM_CR register  ********************/
+#define LPTIM_CR_ENABLE_Pos         (0U)
+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
+#define LPTIM_CR_SNGSTRT_Pos        (1U)
+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */
+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
+#define LPTIM_CR_CNTSTRT_Pos        (2U)
+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
+#define LPTIM_CR_COUNTRST_Pos       (3U)
+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/
+#define LPTIM_CR_RSTARE_Pos         (4U)
+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/
+
+
+/******************  Bit definition for LPTIM_CMP register  *******************/
+#define LPTIM_CMP_CMP_Pos           (0U)
+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
+
+/******************  Bit definition for LPTIM_ARR register  *******************/
+#define LPTIM_ARR_ARR_Pos           (0U)
+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
+
+/******************  Bit definition for LPTIM_CNT register  *******************/
+#define LPTIM_CNT_CNT_Pos           (0U)
+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
+
+/******************  Bit definition for LPTIM_CFGR2 register  *****************/
+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)
+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */
+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */
+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */
+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */
+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)
+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */
+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */
+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */
+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for COMP_SR register  ********************/
+#define COMP_SR_C1VAL_Pos            (0U)
+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */
+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk
+#define COMP_SR_C2VAL_Pos            (1U)
+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */
+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk
+#define COMP_SR_C1IF_Pos             (16U)
+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */
+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk
+#define COMP_SR_C2IF_Pos             (17U)
+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */
+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk
+/*******************  Bit definition for COMP_ICFR register  ********************/
+#define COMP_ICFR_C1IF_Pos           (16U)
+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */
+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk
+#define COMP_ICFR_C2IF_Pos           (17U)
+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */
+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk
+/*******************  Bit definition for COMP_OR register  ********************/
+#define COMP_OR_AFOPA6_Pos           (0U)
+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */
+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk
+#define COMP_OR_AFOPA8_Pos           (1U)
+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */
+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk
+#define COMP_OR_AFOPB12_Pos          (2U)
+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */
+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk
+#define COMP_OR_AFOPE6_Pos           (3U)
+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */
+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk
+#define COMP_OR_AFOPE15_Pos          (4U)
+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */
+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk
+#define COMP_OR_AFOPG2_Pos           (5U)
+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */
+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk
+#define COMP_OR_AFOPG3_Pos           (6U)
+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */
+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk
+#define COMP_OR_AFOPG4_Pos           (7U)
+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */
+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk
+#define COMP_OR_AFOPI1_Pos           (8U)
+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */
+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk
+#define COMP_OR_AFOPI4_Pos           (9U)
+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */
+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk
+#define COMP_OR_AFOPK2_Pos           (10U)
+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */
+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk
+
+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/
+#define COMP_CFGRx_EN_Pos            (0U)
+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */
+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */
+#define COMP_CFGRx_BRGEN_Pos         (1U)
+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */
+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */
+#define COMP_CFGRx_SCALEN_Pos        (2U)
+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */
+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */
+#define COMP_CFGRx_POLARITY_Pos      (3U)
+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */
+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */
+#define COMP_CFGRx_WINMODE_Pos       (4U)
+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */
+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */
+#define COMP_CFGRx_ITEN_Pos          (6U)
+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */
+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */
+#define COMP_CFGRx_HYST_Pos          (8U)
+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */
+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */
+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */
+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */
+#define COMP_CFGRx_PWRMODE_Pos       (12U)
+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */
+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */
+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */
+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */
+#define COMP_CFGRx_INMSEL_Pos        (16U)
+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */
+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */
+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */
+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */
+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */
+#define COMP_CFGRx_INPSEL_Pos        (20U)
+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */
+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */
+#define COMP_CFGRx_BLANKING_Pos      (24U)
+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */
+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */
+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */
+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */
+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */
+#define COMP_CFGRx_LOCK_Pos          (31U)
+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */
+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_UE_Pos                (0U)
+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */
+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */
+#define USART_CR1_UESM_Pos              (1U)
+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */
+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */
+#define USART_CR1_RE_Pos                (2U)
+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */
+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                (3U)
+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */
+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos            (4U)
+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)
+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
+#define USART_CR1_TCIE_Pos              (6U)
+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */
+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)
+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */
+#define USART_CR1_PEIE_Pos              (8U)
+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */
+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                (9U)
+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */
+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */
+#define USART_CR1_PCE_Pos               (10U)
+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */
+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos              (11U)
+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */
+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */
+#define USART_CR1_M_Pos                 (12U)
+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */
+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */
+#define USART_CR1_M0_Pos                (12U)
+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */
+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */
+#define USART_CR1_MME_Pos               (13U)
+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */
+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */
+#define USART_CR1_CMIE_Pos              (14U)
+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */
+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */
+#define USART_CR1_OVER8_Pos             (15U)
+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */
+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */
+#define USART_CR1_DEDT_Pos              (16U)
+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */
+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */
+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */
+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */
+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */
+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */
+#define USART_CR1_DEAT_Pos              (21U)
+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */
+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */
+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */
+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */
+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */
+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */
+#define USART_CR1_RTOIE_Pos             (26U)
+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */
+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE_Pos             (27U)
+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */
+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */
+#define USART_CR1_M1_Pos                (28U)
+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */
+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */
+#define USART_CR1_FIFOEN_Pos            (29U)
+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */
+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */
+#define USART_CR1_TXFEIE_Pos            (30U)
+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */
+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE_Pos            (31U)
+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */
+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */
+
+/* Legacy define */
+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE
+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_SLVEN_Pos             (0U)
+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */
+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */
+#define USART_CR2_DIS_NSS_Pos           (3U)
+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */
+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */
+#define USART_CR2_ADDM7_Pos             (4U)
+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */
+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */
+#define USART_CR2_LBDL_Pos              (5U)
+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */
+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos             (6U)
+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */
+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos              (8U)
+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */
+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos              (9U)
+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */
+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos              (10U)
+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */
+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos             (11U)
+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */
+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */
+#define USART_CR2_STOP_Pos              (12U)
+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */
+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */
+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */
+#define USART_CR2_LINEN_Pos             (14U)
+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */
+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */
+#define USART_CR2_SWAP_Pos              (15U)
+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */
+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */
+#define USART_CR2_RXINV_Pos             (16U)
+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */
+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */
+#define USART_CR2_TXINV_Pos             (17U)
+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */
+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */
+#define USART_CR2_DATAINV_Pos           (18U)
+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */
+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */
+#define USART_CR2_MSBFIRST_Pos          (19U)
+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */
+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */
+#define USART_CR2_ABREN_Pos             (20U)
+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */
+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/
+#define USART_CR2_ABRMODE_Pos           (21U)
+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */
+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */
+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */
+#define USART_CR2_RTOEN_Pos             (23U)
+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */
+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */
+#define USART_CR2_ADD_Pos               (24U)
+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */
+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos               (0U)
+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */
+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos              (1U)
+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */
+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos              (2U)
+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */
+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos             (3U)
+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */
+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos              (4U)
+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */
+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */
+#define USART_CR3_SCEN_Pos              (5U)
+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */
+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */
+#define USART_CR3_DMAR_Pos              (6U)
+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */
+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos              (7U)
+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */
+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos              (8U)
+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */
+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos              (9U)
+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */
+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos             (10U)
+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */
+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos            (11U)
+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */
+#define USART_CR3_OVRDIS_Pos            (12U)
+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */
+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */
+#define USART_CR3_DDRE_Pos              (13U)
+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */
+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */
+#define USART_CR3_DEM_Pos               (14U)
+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */
+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */
+#define USART_CR3_DEP_Pos               (15U)
+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */
+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */
+#define USART_CR3_SCARCNT_Pos           (17U)
+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */
+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */
+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */
+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */
+#define USART_CR3_WUS_Pos               (20U)
+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */
+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */
+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */
+#define USART_CR3_WUFIE_Pos             (22U)
+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */
+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */
+#define USART_CR3_TXFTIE_Pos            (23U)
+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */
+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */
+#define USART_CR3_TCBGTIE_Pos           (24U)
+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */
+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */
+#define USART_CR3_RXFTCFG_Pos           (25U)
+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */
+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */
+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */
+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */
+#define USART_CR3_RXFTIE_Pos            (28U)
+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */
+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */
+#define USART_CR3_TXFTCFG_Pos           (29U)
+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */
+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */
+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */
+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */
+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos      (0U)
+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos      (4U)
+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos              (0U)
+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */
+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_GT_Pos               (8U)
+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */
+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define USART_RTOR_RTO_Pos              (0U)
+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */
+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */
+#define USART_RTOR_BLEN_Pos             (24U)
+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */
+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define USART_RQR_ABRRQ_Pos             (0U)
+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */
+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ_Pos             (1U)
+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */
+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */
+#define USART_RQR_MMRQ_Pos              (2U)
+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */
+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */
+#define USART_RQR_RXFRQ_Pos             (3U)
+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */
+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */
+#define USART_RQR_TXFRQ_Pos             (4U)
+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */
+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define USART_ISR_PE_Pos                (0U)
+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */
+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */
+#define USART_ISR_FE_Pos                (1U)
+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */
+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */
+#define USART_ISR_NE_Pos                (2U)
+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */
+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */
+#define USART_ISR_ORE_Pos               (3U)
+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */
+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */
+#define USART_ISR_IDLE_Pos              (4U)
+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */
+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */
+#define USART_ISR_RXNE_RXFNE_Pos        (5U)
+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */
+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */
+#define USART_ISR_TC_Pos                (6U)
+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */
+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */
+#define USART_ISR_TXE_TXFNF_Pos         (7U)
+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */
+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
+#define USART_ISR_LBDF_Pos              (8U)
+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */
+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */
+#define USART_ISR_CTSIF_Pos             (9U)
+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */
+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */
+#define USART_ISR_CTS_Pos               (10U)
+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */
+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */
+#define USART_ISR_RTOF_Pos              (11U)
+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */
+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */
+#define USART_ISR_EOBF_Pos              (12U)
+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */
+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */
+#define USART_ISR_UDR_Pos               (13U)
+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */
+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */
+#define USART_ISR_ABRE_Pos              (14U)
+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */
+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */
+#define USART_ISR_ABRF_Pos              (15U)
+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */
+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */
+#define USART_ISR_BUSY_Pos              (16U)
+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */
+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */
+#define USART_ISR_CMF_Pos               (17U)
+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */
+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */
+#define USART_ISR_SBKF_Pos              (18U)
+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */
+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */
+#define USART_ISR_RWU_Pos               (19U)
+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */
+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */
+#define USART_ISR_WUF_Pos               (20U)
+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */
+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */
+#define USART_ISR_TEACK_Pos             (21U)
+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */
+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK_Pos             (22U)
+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */
+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE_Pos              (23U)
+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */
+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */
+#define USART_ISR_RXFF_Pos              (24U)
+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */
+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */
+#define USART_ISR_TCBGT_Pos             (25U)
+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */
+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */
+#define USART_ISR_RXFT_Pos              (26U)
+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */
+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */
+#define USART_ISR_TXFT_Pos              (27U)
+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */
+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define USART_ICR_PECF_Pos              (0U)
+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */
+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */
+#define USART_ICR_FECF_Pos              (1U)
+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */
+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */
+#define USART_ICR_NECF_Pos              (2U)
+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */
+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */
+#define USART_ICR_ORECF_Pos             (3U)
+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */
+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */
+#define USART_ICR_IDLECF_Pos            (4U)
+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */
+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */
+#define USART_ICR_TXFECF_Pos            (5U)
+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */
+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */
+#define USART_ICR_TCCF_Pos              (6U)
+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */
+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF_Pos           (7U)
+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */
+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */
+#define USART_ICR_LBDCF_Pos             (8U)
+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */
+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF_Pos             (9U)
+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */
+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF_Pos             (11U)
+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */
+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */
+#define USART_ICR_EOBCF_Pos             (12U)
+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */
+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */
+#define USART_ICR_UDRCF_Pos             (13U)
+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */
+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */
+#define USART_ICR_CMCF_Pos              (17U)
+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */
+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */
+#define USART_ICR_WUCF_Pos              (20U)
+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */
+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define USART_RDR_RDR_Pos               (0U)
+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */
+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define USART_TDR_TDR_Pos               (0U)
+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */
+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */
+
+/*******************  Bit definition for USART_PRESC register  ******************/
+#define USART_PRESC_PRESCALER_Pos       (0U)
+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */
+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */
+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */
+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */
+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */
+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */
+
+/******************************************************************************/
+/*                                                                            */
+/*           Single Wire Protocol Master Interface (SWPMI)                    */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for SWPMI_CR register   ********************/
+#define SWPMI_CR_RXDMA_Pos       (0U)
+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */
+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */
+#define SWPMI_CR_TXDMA_Pos       (1U)
+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */
+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */
+#define SWPMI_CR_RXMODE_Pos      (2U)
+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */
+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */
+#define SWPMI_CR_TXMODE_Pos      (3U)
+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */
+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */
+#define SWPMI_CR_LPBK_Pos        (4U)
+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */
+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */
+#define SWPMI_CR_SWPACT_Pos      (5U)
+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */
+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */
+#define SWPMI_CR_DEACT_Pos       (10U)
+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */
+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */
+#define SWPMI_CR_SWPEN_Pos       (11U)
+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */
+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */
+
+/*******************  Bit definition for SWPMI_BRR register  ********************/
+#define SWPMI_BRR_BR_Pos         (0U)
+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */
+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */
+
+/*******************  Bit definition for SWPMI_ISR register  ********************/
+#define SWPMI_ISR_RXBFF_Pos      (0U)
+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */
+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */
+#define SWPMI_ISR_TXBEF_Pos      (1U)
+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */
+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */
+#define SWPMI_ISR_RXBERF_Pos     (2U)
+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */
+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */
+#define SWPMI_ISR_RXOVRF_Pos     (3U)
+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */
+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */
+#define SWPMI_ISR_TXUNRF_Pos     (4U)
+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */
+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */
+#define SWPMI_ISR_RXNE_Pos       (5U)
+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */
+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */
+#define SWPMI_ISR_TXE_Pos        (6U)
+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */
+#define SWPMI_ISR_TCF_Pos        (7U)
+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */
+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */
+#define SWPMI_ISR_SRF_Pos        (8U)
+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */
+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */
+#define SWPMI_ISR_SUSP_Pos       (9U)
+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */
+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */
+#define SWPMI_ISR_DEACTF_Pos     (10U)
+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */
+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */
+#define SWPMI_ISR_RDYF_Pos       (11U)
+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */
+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */
+
+/*******************  Bit definition for SWPMI_ICR register  ********************/
+#define SWPMI_ICR_CRXBFF_Pos     (0U)
+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */
+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */
+#define SWPMI_ICR_CTXBEF_Pos     (1U)
+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */
+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */
+#define SWPMI_ICR_CRXBERF_Pos    (2U)
+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */
+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */
+#define SWPMI_ICR_CRXOVRF_Pos    (3U)
+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */
+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */
+#define SWPMI_ICR_CTXUNRF_Pos    (4U)
+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */
+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */
+#define SWPMI_ICR_CTCF_Pos       (7U)
+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */
+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */
+#define SWPMI_ICR_CSRF_Pos       (8U)
+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */
+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */
+#define SWPMI_ICR_CRDYF_Pos      (11U)
+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */
+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */
+
+/*******************  Bit definition for SWPMI_IER register  ********************/
+#define SWPMI_IER_RXBFIE_Pos     (0U)
+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */
+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */
+#define SWPMI_IER_TXBEIE_Pos     (1U)
+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */
+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */
+#define SWPMI_IER_RXBERIE_Pos    (2U)
+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */
+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */
+#define SWPMI_IER_RXOVRIE_Pos    (3U)
+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */
+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */
+#define SWPMI_IER_TXUNRIE_Pos    (4U)
+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */
+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */
+#define SWPMI_IER_RIE_Pos        (5U)
+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */
+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */
+#define SWPMI_IER_TIE_Pos        (6U)
+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */
+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */
+#define SWPMI_IER_TCIE_Pos       (7U)
+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */
+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */
+#define SWPMI_IER_SRIE_Pos       (8U)
+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */
+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */
+#define SWPMI_IER_RDYIE_Pos      (11U)
+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */
+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */
+
+/*******************  Bit definition for SWPMI_RFL register  ********************/
+#define SWPMI_RFL_RFL_Pos        (0U)
+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+
+/*******************  Bit definition for SWPMI_TDR register  ********************/
+#define SWPMI_TDR_TD_Pos         (0U)
+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */
+
+/*******************  Bit definition for SWPMI_RDR register  ********************/
+#define SWPMI_RDR_RD_Pos         (0U)
+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */
+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Receive Data Register           */
+
+
+/*******************  Bit definition for SWPMI_OR register  ********************/
+#define SWPMI_OR_TBYP_Pos        (0U)
+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */
+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */
+#define SWPMI_OR_CLASS_Pos       (1U)
+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */
+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */
+
+#define WWDG_CR_WDGA_Pos        (7U)
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */
+
+#define WWDG_CFR_EWI_Pos        (9U)
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+#define WWDG_CFR_WDGTB_Pos      (11U)
+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */
+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/*********************************  DEVICE ID  ********************************/
+#define STM32H7_DEV_ID           0x450UL
+
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk
+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)
+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk
+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)
+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk
+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)
+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk
+#define DBGMCU_CR_DBG_SLEEPD2_Pos         (3U)
+#define DBGMCU_CR_DBG_SLEEPD2_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */
+#define DBGMCU_CR_DBG_SLEEPD2             DBGMCU_CR_DBG_SLEEPD2_Msk
+#define DBGMCU_CR_DBG_STOPD2_Pos          (4U)
+#define DBGMCU_CR_DBG_STOPD2_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)  /*!< 0x00000010 */
+#define DBGMCU_CR_DBG_STOPD2              DBGMCU_CR_DBG_STOPD2_Msk
+#define DBGMCU_CR_DBG_STANDBYD2_Pos       (5U)
+#define DBGMCU_CR_DBG_STANDBYD2_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_DBG_STANDBYD2           DBGMCU_CR_DBG_STANDBYD2_Msk
+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)
+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk
+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)
+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */
+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk
+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)
+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */
+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk
+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)
+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */
+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk
+
+/********************  Bit definition for APB3FZ1 register  ************/
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk
+/********************  Bit definition for APB3FZ2 register  ************/
+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos      (6U)
+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB3FZ2_DBG_WWDG1          DBGMCU_APB3FZ2_DBG_WWDG1_Msk
+/********************  Bit definition for APB1LFZ1 register  ************/
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos     (11U)
+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ1_DBG_WWDG2         DBGMCU_APB1LFZ1_DBG_WWDG2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk
+
+/********************  Bit definition for APB1LFZ2 register  ************/
+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos      (0U)
+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1LFZ2_DBG_TIM2          DBGMCU_APB1LFZ2_DBG_TIM2_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos      (1U)
+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1LFZ2_DBG_TIM3          DBGMCU_APB1LFZ2_DBG_TIM3_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos      (2U)
+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1LFZ2_DBG_TIM4          DBGMCU_APB1LFZ2_DBG_TIM4_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos      (3U)
+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1LFZ2_DBG_TIM5          DBGMCU_APB1LFZ2_DBG_TIM5_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos      (4U)
+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1LFZ2_DBG_TIM6          DBGMCU_APB1LFZ2_DBG_TIM6_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos      (5U)
+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1LFZ2_DBG_TIM7          DBGMCU_APB1LFZ2_DBG_TIM7_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos     (6U)
+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1LFZ2_DBG_TIM12         DBGMCU_APB1LFZ2_DBG_TIM12_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos     (7U)
+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1LFZ2_DBG_TIM13         DBGMCU_APB1LFZ2_DBG_TIM13_Msk
+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos     (8U)
+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1LFZ2_DBG_TIM14         DBGMCU_APB1LFZ2_DBG_TIM14_Msk
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos    (9U)
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB1LFZ2_DBG_LPTIM1        DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk
+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos     (11U)
+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1LFZ2_DBG_WWDG2         DBGMCU_APB1LFZ2_DBG_WWDG2_Msk
+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos      (21U)
+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1LFZ2_DBG_I2C1          DBGMCU_APB1LFZ2_DBG_I2C1_Msk
+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos      (22U)
+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1LFZ2_DBG_I2C2          DBGMCU_APB1LFZ2_DBG_I2C2_Msk
+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos      (23U)
+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1LFZ2_DBG_I2C3          DBGMCU_APB1LFZ2_DBG_I2C3_Msk
+/********************  Bit definition for APB1HFZ1 register  ************/
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
+/********************  Bit definition for APB1HFZ2 register  ************/
+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos     (8U)
+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1HFZ2_DBG_FDCAN         DBGMCU_APB1HFZ2_DBG_FDCAN_Msk
+
+/********************  Bit definition for APB2FZ1 register  ************/
+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk
+
+/********************  Bit definition for APB2FZ2 register  ************/
+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos       (0U)
+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2FZ2_DBG_TIM1           DBGMCU_APB2FZ2_DBG_TIM1_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos       (1U)
+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2FZ2_DBG_TIM8           DBGMCU_APB2FZ2_DBG_TIM8_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos      (16U)
+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2FZ2_DBG_TIM15          DBGMCU_APB2FZ2_DBG_TIM15_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos      (17U)
+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2FZ2_DBG_TIM16          DBGMCU_APB2FZ2_DBG_TIM16_Msk
+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos      (18U)
+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2FZ2_DBG_TIM17          DBGMCU_APB2FZ2_DBG_TIM17_Msk
+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos      (29U)
+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */
+#define DBGMCU_APB2FZ2_DBG_HRTIM          DBGMCU_APB2FZ2_DBG_HRTIM_Msk
+/********************  Bit definition for APB4FZ1 register  ************/
+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk
+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos      (19U)
+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */
+#define DBGMCU_APB4FZ1_DBG_IWDG2          DBGMCU_APB4FZ1_DBG_IWDG2_Msk
+/********************  Bit definition for APB4FZ2 register  ************/
+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos       (7U)
+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB4FZ2_DBG_I2C4           DBGMCU_APB4FZ2_DBG_I2C4_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos     (9U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM2         DBGMCU_APB4FZ2_DBG_LPTIM2_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos     (10U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM3         DBGMCU_APB4FZ2_DBG_LPTIM3_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos     (11U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM4         DBGMCU_APB4FZ2_DBG_LPTIM4_Msk
+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos     (12U)
+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB4FZ2_DBG_LPTIM5         DBGMCU_APB4FZ2_DBG_LPTIM5_Msk
+#define DBGMCU_APB4FZ2_DBG_RTC_Pos        (16U)
+#define DBGMCU_APB4FZ2_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB4FZ2_DBG_RTC            DBGMCU_APB4FZ2_DBG_RTC_Msk
+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos      (18U)
+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB4FZ2_DBG_IWDG1          DBGMCU_APB4FZ2_DBG_IWDG1_Msk
+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos      (19U)
+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */
+#define DBGMCU_APB4FZ2_DBG_IWDG2          DBGMCU_APB4FZ2_DBG_IWDG2_Msk
+/******************************************************************************/
+/*                                                                            */
+/*                        High Resolution Timer (HRTIM)                       */
+/*                                                                            */
+/******************************************************************************/
+/******************** Master Timer control register ***************************/
+#define HRTIM_MCR_CK_PSC_Pos          (0U)
+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */
+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */
+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */
+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */
+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */
+
+#define HRTIM_MCR_CONT_Pos            (3U)
+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */
+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */
+#define HRTIM_MCR_RETRIG_Pos          (4U)
+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */
+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */
+#define HRTIM_MCR_HALF_Pos            (5U)
+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */
+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */
+
+#define HRTIM_MCR_SYNC_IN_Pos         (8U)
+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */
+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */
+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */
+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */
+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)
+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */
+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */
+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)
+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */
+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */
+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)
+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */
+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */
+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */
+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */
+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)
+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */
+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */
+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */
+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */
+
+#define HRTIM_MCR_MCEN_Pos            (16U)
+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */
+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */
+#define HRTIM_MCR_TACEN_Pos           (17U)
+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */
+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */
+#define HRTIM_MCR_TBCEN_Pos           (18U)
+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */
+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */
+#define HRTIM_MCR_TCCEN_Pos           (19U)
+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */
+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */
+#define HRTIM_MCR_TDCEN_Pos           (20U)
+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */
+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */
+#define HRTIM_MCR_TECEN_Pos           (21U)
+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */
+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */
+
+#define HRTIM_MCR_DACSYNC_Pos         (25U)
+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
+
+#define HRTIM_MCR_PREEN_Pos           (27U)
+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */
+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */
+#define HRTIM_MCR_MREPU_Pos           (29U)
+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */
+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */
+
+#define HRTIM_MCR_BRSTDMA_Pos         (30U)
+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */
+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */
+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */
+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */
+
+/******************** Master Timer Interrupt status register ******************/
+#define HRTIM_MISR_MCMP1_Pos          (0U)
+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */
+#define HRTIM_MISR_MCMP2_Pos          (1U)
+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */
+#define HRTIM_MISR_MCMP3_Pos          (2U)
+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */
+#define HRTIM_MISR_MCMP4_Pos          (3U)
+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */
+#define HRTIM_MISR_MREP_Pos           (4U)
+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */
+#define HRTIM_MISR_SYNC_Pos           (5U)
+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */
+#define HRTIM_MISR_MUPD_Pos           (6U)
+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */
+
+/******************** Master Timer Interrupt clear register *******************/
+#define HRTIM_MICR_MCMP1_Pos          (0U)
+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */
+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */
+#define HRTIM_MICR_MCMP2_Pos          (1U)
+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */
+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */
+#define HRTIM_MICR_MCMP3_Pos          (2U)
+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */
+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */
+#define HRTIM_MICR_MCMP4_Pos          (3U)
+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */
+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */
+#define HRTIM_MICR_MREP_Pos           (4U)
+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */
+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */
+#define HRTIM_MICR_SYNC_Pos           (5U)
+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */
+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */
+#define HRTIM_MICR_MUPD_Pos           (6U)
+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */
+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */
+
+/******************** Master Timer DMA/Interrupt enable register **************/
+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)
+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */
+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */
+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)
+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */
+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */
+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)
+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */
+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */
+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)
+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */
+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */
+#define HRTIM_MDIER_MREPIE_Pos        (4U)
+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */
+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */
+#define HRTIM_MDIER_SYNCIE_Pos        (5U)
+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */
+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */
+#define HRTIM_MDIER_MUPDIE_Pos        (6U)
+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */
+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */
+
+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)
+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */
+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */
+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)
+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */
+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */
+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)
+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */
+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */
+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)
+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */
+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */
+#define HRTIM_MDIER_MREPDE_Pos        (20U)
+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */
+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */
+#define HRTIM_MDIER_SYNCDE_Pos        (21U)
+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */
+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */
+#define HRTIM_MDIER_MUPDDE_Pos        (22U)
+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */
+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */
+
+/*******************  Bit definition for HRTIM_MCNTR register  ****************/
+#define HRTIM_MCNTR_MCNTR_Pos         (0U)
+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for HRTIM_MPER register  *****************/
+#define HRTIM_MPER_MPER_Pos           (0U)
+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_MREP register  *****************/
+#define HRTIM_MREP_MREP_Pos           (0U)
+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */
+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */
+
+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/
+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/
+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/
+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */
+
+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/
+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)
+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */
+
+/******************** Slave control register **********************************/
+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)
+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */
+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/
+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */
+
+#define HRTIM_TIMCR_CONT_Pos          (3U)
+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */
+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */
+#define HRTIM_TIMCR_RETRIG_Pos        (4U)
+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */
+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */
+#define HRTIM_TIMCR_HALF_Pos          (5U)
+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */
+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */
+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)
+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */
+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */
+
+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)
+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */
+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */
+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)
+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */
+
+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)
+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */
+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */
+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */
+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)
+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */
+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */
+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */
+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */
+
+#define HRTIM_TIMCR_TREPU_Pos         (17U)
+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */
+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */
+#define HRTIM_TIMCR_TRSTU_Pos         (18U)
+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */
+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */
+#define HRTIM_TIMCR_TAU_Pos           (19U)
+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */
+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */
+#define HRTIM_TIMCR_TBU_Pos           (20U)
+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */
+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */
+#define HRTIM_TIMCR_TCU_Pos           (21U)
+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */
+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */
+#define HRTIM_TIMCR_TDU_Pos           (22U)
+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */
+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */
+#define HRTIM_TIMCR_TEU_Pos           (23U)
+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */
+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */
+#define HRTIM_TIMCR_MSTU_Pos          (24U)
+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */
+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */
+
+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)
+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
+#define HRTIM_TIMCR_PREEN_Pos         (27U)
+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */
+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */
+
+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)
+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */
+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */
+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */
+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */
+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */
+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */
+
+/******************** Slave Interrupt status register **************************/
+#define HRTIM_TIMISR_CMP1_Pos         (0U)
+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */
+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */
+#define HRTIM_TIMISR_CMP2_Pos         (1U)
+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */
+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */
+#define HRTIM_TIMISR_CMP3_Pos         (2U)
+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */
+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */
+#define HRTIM_TIMISR_CMP4_Pos         (3U)
+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */
+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */
+#define HRTIM_TIMISR_REP_Pos          (4U)
+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */
+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */
+#define HRTIM_TIMISR_UPD_Pos          (6U)
+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */
+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */
+#define HRTIM_TIMISR_CPT1_Pos         (7U)
+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */
+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */
+#define HRTIM_TIMISR_CPT2_Pos         (8U)
+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */
+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */
+#define HRTIM_TIMISR_SET1_Pos         (9U)
+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */
+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */
+#define HRTIM_TIMISR_RST1_Pos         (10U)
+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */
+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */
+#define HRTIM_TIMISR_SET2_Pos         (11U)
+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */
+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */
+#define HRTIM_TIMISR_RST2_Pos         (12U)
+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */
+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */
+#define HRTIM_TIMISR_RST_Pos          (13U)
+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */
+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */
+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)
+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */
+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */
+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)
+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */
+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)
+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */
+#define HRTIM_TIMISR_O1STAT_Pos       (18U)
+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */
+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */
+#define HRTIM_TIMISR_O2STAT_Pos       (19U)
+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */
+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */
+#define HRTIM_TIMISR_O1CPY_Pos        (20U)
+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */
+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */
+#define HRTIM_TIMISR_O2CPY_Pos        (21U)
+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */
+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */
+
+/******************** Slave Interrupt clear register **************************/
+#define HRTIM_TIMICR_CMP1C_Pos        (0U)
+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */
+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */
+#define HRTIM_TIMICR_CMP2C_Pos        (1U)
+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */
+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */
+#define HRTIM_TIMICR_CMP3C_Pos        (2U)
+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */
+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */
+#define HRTIM_TIMICR_CMP4C_Pos        (3U)
+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */
+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */
+#define HRTIM_TIMICR_REPC_Pos         (4U)
+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */
+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */
+#define HRTIM_TIMICR_UPDC_Pos         (6U)
+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */
+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */
+#define HRTIM_TIMICR_CPT1C_Pos        (7U)
+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */
+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */
+#define HRTIM_TIMICR_CPT2C_Pos        (8U)
+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */
+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */
+#define HRTIM_TIMICR_SET1C_Pos        (9U)
+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */
+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */
+#define HRTIM_TIMICR_RST1C_Pos        (10U)
+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */
+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */
+#define HRTIM_TIMICR_SET2C_Pos        (11U)
+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */
+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */
+#define HRTIM_TIMICR_RST2C_Pos        (12U)
+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */
+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */
+#define HRTIM_TIMICR_RSTC_Pos         (13U)
+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */
+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */
+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)
+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */
+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */
+
+/******************** Slave DMA/Interrupt enable register *********************/
+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)
+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */
+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */
+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)
+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */
+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */
+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)
+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */
+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */
+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)
+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */
+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */
+#define HRTIM_TIMDIER_REPIE_Pos       (4U)
+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */
+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */
+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)
+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */
+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */
+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)
+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */
+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */
+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)
+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */
+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */
+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)
+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */
+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */
+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)
+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */
+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */
+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)
+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */
+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */
+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)
+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */
+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */
+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)
+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */
+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */
+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)
+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */
+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */
+
+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)
+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */
+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */
+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)
+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */
+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */
+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)
+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */
+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */
+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)
+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */
+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */
+#define HRTIM_TIMDIER_REPDE_Pos       (20U)
+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */
+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */
+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)
+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */
+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */
+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)
+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */
+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */
+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)
+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */
+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */
+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)
+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */
+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */
+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)
+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */
+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */
+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)
+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */
+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */
+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)
+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */
+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */
+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)
+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */
+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */
+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)
+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */
+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */
+
+/******************  Bit definition for HRTIM_CNTR register  ****************/
+#define HRTIM_CNTR_CNTR_Pos           (0U)
+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */
+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */
+
+/*******************  Bit definition for HRTIM_PER register  *****************/
+#define HRTIM_PER_PER_Pos             (0U)
+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */
+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */
+
+/*******************  Bit definition for HRTIM_REP register  *****************/
+#define HRTIM_REP_REP_Pos             (0U)
+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */
+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */
+
+/*******************  Bit definition for HRTIM_CMP1R register  *****************/
+#define HRTIM_CMP1R_CMP1R_Pos         (0U)
+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/
+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)
+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP2R register  *****************/
+#define HRTIM_CMP2R_CMP2R_Pos         (0U)
+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP3R register  *****************/
+#define HRTIM_CMP3R_CMP3R_Pos         (0U)
+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CMP4R register  *****************/
+#define HRTIM_CMP4R_CMP4R_Pos         (0U)
+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */
+
+/*******************  Bit definition for HRTIM_CPT1R register  ****************/
+#define HRTIM_CPT1R_CPT1R_Pos         (0U)
+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */
+
+/*******************  Bit definition for HRTIM_CPT2R register  ****************/
+#define HRTIM_CPT2R_CPT2R_Pos         (0U)
+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */
+
+/******************** Bit definition for Slave Deadtime register **************/
+#define HRTIM_DTR_DTR_Pos             (0U)
+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */
+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */
+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */
+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */
+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */
+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */
+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */
+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */
+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */
+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */
+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */
+#define HRTIM_DTR_SDTR_Pos            (9U)
+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */
+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */
+#define HRTIM_DTR_DTPRSC_Pos          (10U)
+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */
+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */
+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */
+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */
+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */
+#define HRTIM_DTR_DTRSLK_Pos          (14U)
+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */
+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */
+#define HRTIM_DTR_DTRLK_Pos           (15U)
+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */
+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */
+#define HRTIM_DTR_DTF_Pos             (16U)
+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */
+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */
+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */
+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */
+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */
+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */
+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */
+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */
+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */
+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */
+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */
+#define HRTIM_DTR_SDTF_Pos            (25U)
+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */
+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */
+#define HRTIM_DTR_DTFSLK_Pos          (30U)
+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */
+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */
+#define HRTIM_DTR_DTFLK_Pos           (31U)
+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */
+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */
+
+/**** Bit definition for Slave Output 1 set register **************************/
+#define HRTIM_SET1R_SST_Pos           (0U)
+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET1R_RESYNC_Pos        (1U)
+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET1R_PER_Pos           (2U)
+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET1R_CMP1_Pos          (3U)
+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET1R_CMP2_Pos          (4U)
+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET1R_CMP3_Pos          (5U)
+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET1R_CMP4_Pos          (6U)
+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET1R_MSTPER_Pos        (7U)
+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET1R_UPDATE_Pos        (31U)
+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 1 reset register ************************/
+#define HRTIM_RST1R_SRT_Pos           (0U)
+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST1R_RESYNC_Pos        (1U)
+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST1R_PER_Pos           (2U)
+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST1R_CMP1_Pos          (3U)
+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST1R_CMP2_Pos          (4U)
+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST1R_CMP3_Pos          (5U)
+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST1R_CMP4_Pos          (6U)
+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST1R_MSTPER_Pos        (7U)
+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST1R_UPDATE_Pos        (31U)
+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+
+/**** Bit definition for Slave Output 2 set register **************************/
+#define HRTIM_SET2R_SST_Pos           (0U)
+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */
+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */
+#define HRTIM_SET2R_RESYNC_Pos        (1U)
+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_SET2R_PER_Pos           (2U)
+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_SET2R_CMP1_Pos          (3U)
+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_SET2R_CMP2_Pos          (4U)
+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_SET2R_CMP3_Pos          (5U)
+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_SET2R_CMP4_Pos          (6U)
+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_SET2R_MSTPER_Pos        (7U)
+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)
+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)
+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)
+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)
+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)
+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)
+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)
+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)
+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)
+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)
+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)
+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)
+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)
+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)
+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_SET2R_UPDATE_Pos        (31U)
+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave Output 2 reset register ************************/
+#define HRTIM_RST2R_SRT_Pos           (0U)
+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */
+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */
+#define HRTIM_RST2R_RESYNC_Pos        (1U)
+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */
+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */
+#define HRTIM_RST2R_PER_Pos           (2U)
+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */
+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */
+#define HRTIM_RST2R_CMP1_Pos          (3U)
+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */
+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */
+#define HRTIM_RST2R_CMP2_Pos          (4U)
+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */
+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */
+#define HRTIM_RST2R_CMP3_Pos          (5U)
+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */
+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */
+#define HRTIM_RST2R_CMP4_Pos          (6U)
+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */
+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */
+
+#define HRTIM_RST2R_MSTPER_Pos        (7U)
+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */
+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */
+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)
+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */
+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */
+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)
+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */
+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */
+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)
+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */
+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */
+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)
+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */
+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */
+
+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)
+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */
+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */
+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)
+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */
+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */
+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)
+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */
+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */
+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)
+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */
+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */
+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)
+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */
+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */
+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)
+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */
+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */
+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)
+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */
+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */
+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)
+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */
+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */
+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)
+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */
+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */
+
+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)
+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */
+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)
+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */
+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)
+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */
+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)
+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)
+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */
+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)
+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */
+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)
+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */
+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)
+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */
+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)
+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */
+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)
+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */
+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */
+
+#define HRTIM_RST2R_UPDATE_Pos        (31U)
+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */
+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */
+
+/**** Bit definition for Slave external event filtering  register 1 ***********/
+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)
+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */
+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)
+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */
+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)
+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */
+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)
+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */
+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)
+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */
+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)
+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */
+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)
+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */
+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)
+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */
+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)
+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */
+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */
+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)
+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */
+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */
+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */
+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */
+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */
+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */
+
+/**** Bit definition for Slave external event filtering  register 2 ***********/
+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)
+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */
+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */
+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)
+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */
+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */
+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */
+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */
+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */
+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */
+
+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)
+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */
+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */
+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)
+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */
+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */
+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */
+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */
+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */
+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */
+
+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)
+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */
+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */
+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)
+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */
+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */
+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */
+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */
+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */
+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */
+
+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)
+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */
+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */
+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)
+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */
+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */
+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */
+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */
+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */
+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */
+
+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)
+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */
+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */
+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)
+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */
+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */
+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */
+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */
+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */
+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */
+
+/**** Bit definition for Slave Timer reset register ***************************/
+#define HRTIM_RSTR_UPDATE_Pos         (1U)
+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */
+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */
+#define HRTIM_RSTR_CMP2_Pos           (2U)
+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */
+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */
+#define HRTIM_RSTR_CMP4_Pos           (3U)
+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */
+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */
+
+#define HRTIM_RSTR_MSTPER_Pos         (4U)
+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */
+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)
+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */
+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */
+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)
+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */
+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */
+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)
+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */
+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */
+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)
+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */
+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */
+
+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)
+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */
+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */
+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)
+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */
+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */
+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)
+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */
+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */
+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)
+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */
+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */
+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)
+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */
+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */
+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)
+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */
+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */
+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)
+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */
+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */
+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)
+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */
+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */
+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)
+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */
+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */
+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)
+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
+
+/* Slave Timer A reset enable bits upon other slave timers events */
+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)
+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */
+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)
+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */
+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */
+
+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */
+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */
+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */
+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */
+
+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */
+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */
+
+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */
+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */
+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
+
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+/**** Bit definition for Slave Timer Chopper register *************************/
+#define HRTIM_CHPR_CARFRQ_Pos         (0U)
+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */
+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */
+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */
+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */
+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */
+
+#define HRTIM_CHPR_CARDTY_Pos         (4U)
+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */
+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */
+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */
+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */
+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */
+
+#define HRTIM_CHPR_STRPW_Pos          (7U)
+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */
+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */
+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */
+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */
+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */
+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */
+
+/**** Bit definition for Slave Timer Capture 1 control register ***************/
+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Capture 2 control register ***************/
+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)
+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */
+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */
+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)
+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */
+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */
+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)
+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */
+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */
+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)
+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */
+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */
+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)
+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */
+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */
+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)
+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */
+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */
+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)
+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */
+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */
+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)
+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */
+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */
+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)
+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */
+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */
+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)
+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */
+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */
+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)
+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */
+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */
+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)
+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */
+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */
+
+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)
+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */
+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */
+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)
+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */
+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */
+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)
+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */
+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)
+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */
+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+
+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)
+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */
+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */
+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)
+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */
+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */
+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)
+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */
+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)
+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */
+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+
+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)
+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */
+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */
+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)
+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */
+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */
+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)
+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)
+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+
+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)
+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */
+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */
+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)
+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */
+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */
+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)
+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */
+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)
+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */
+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+
+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)
+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */
+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */
+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)
+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */
+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */
+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)
+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */
+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)
+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */
+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+
+/**** Bit definition for Slave Timer Output register **************************/
+#define HRTIM_OUTR_POL1_Pos           (1U)
+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */
+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */
+#define HRTIM_OUTR_IDLM1_Pos          (2U)
+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */
+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */
+#define HRTIM_OUTR_IDLES1_Pos         (3U)
+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */
+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */
+#define HRTIM_OUTR_FAULT1_Pos         (4U)
+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */
+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */
+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */
+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */
+#define HRTIM_OUTR_CHP1_Pos           (6U)
+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */
+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */
+#define HRTIM_OUTR_DIDL1_Pos          (7U)
+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */
+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */
+
+#define HRTIM_OUTR_DTEN_Pos           (8U)
+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */
+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */
+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)
+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */
+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */
+#define HRTIM_OUTR_DLYPRT_Pos         (10U)
+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */
+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */
+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */
+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */
+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */
+
+#define HRTIM_OUTR_POL2_Pos           (17U)
+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */
+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */
+#define HRTIM_OUTR_IDLM2_Pos          (18U)
+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */
+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */
+#define HRTIM_OUTR_IDLES2_Pos         (19U)
+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */
+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */
+#define HRTIM_OUTR_FAULT2_Pos         (20U)
+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */
+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */
+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */
+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */
+#define HRTIM_OUTR_CHP2_Pos           (22U)
+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */
+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */
+#define HRTIM_OUTR_DIDL2_Pos          (23U)
+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */
+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */
+
+/**** Bit definition for Slave Timer Fault register ***************************/
+#define HRTIM_FLTR_FLT1EN_Pos         (0U)
+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */
+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */
+#define HRTIM_FLTR_FLT2EN_Pos         (1U)
+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */
+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */
+#define HRTIM_FLTR_FLT3EN_Pos         (2U)
+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */
+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */
+#define HRTIM_FLTR_FLT4EN_Pos         (3U)
+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */
+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */
+#define HRTIM_FLTR_FLT5EN_Pos         (4U)
+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */
+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */
+#define HRTIM_FLTR_FLTLCK_Pos         (31U)
+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */
+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */
+
+/**** Bit definition for Common HRTIM Timer control register 1 ****************/
+#define HRTIM_CR1_MUDIS_Pos           (0U)
+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */
+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/
+#define HRTIM_CR1_TAUDIS_Pos          (1U)
+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */
+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/
+#define HRTIM_CR1_TBUDIS_Pos          (2U)
+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */
+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/
+#define HRTIM_CR1_TCUDIS_Pos          (3U)
+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */
+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/
+#define HRTIM_CR1_TDUDIS_Pos          (4U)
+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */
+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/
+#define HRTIM_CR1_TEUDIS_Pos          (5U)
+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */
+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/
+#define HRTIM_CR1_ADC1USRC_Pos        (16U)
+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */
+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */
+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */
+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */
+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_CR1_ADC2USRC_Pos        (19U)
+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */
+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */
+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */
+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */
+#define HRTIM_CR1_ADC3USRC_Pos        (22U)
+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */
+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */
+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */
+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */
+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_CR1_ADC4USRC_Pos        (25U)
+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */
+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */
+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */
+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */
+
+/**** Bit definition for Common HRTIM Timer control register 2 ****************/
+#define HRTIM_CR2_MSWU_Pos            (0U)
+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */
+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */
+#define HRTIM_CR2_TASWU_Pos           (1U)
+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */
+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */
+#define HRTIM_CR2_TBSWU_Pos           (2U)
+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */
+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */
+#define HRTIM_CR2_TCSWU_Pos           (3U)
+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */
+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */
+#define HRTIM_CR2_TDSWU_Pos           (4U)
+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */
+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */
+#define HRTIM_CR2_TESWU_Pos           (5U)
+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */
+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */
+#define HRTIM_CR2_MRST_Pos            (8U)
+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */
+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */
+#define HRTIM_CR2_TARST_Pos           (9U)
+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */
+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */
+#define HRTIM_CR2_TBRST_Pos           (10U)
+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */
+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */
+#define HRTIM_CR2_TCRST_Pos           (11U)
+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */
+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */
+#define HRTIM_CR2_TDRST_Pos           (12U)
+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */
+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */
+#define HRTIM_CR2_TERST_Pos           (13U)
+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */
+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */
+
+/**** Bit definition for Common HRTIM Timer interrupt status register *********/
+#define HRTIM_ISR_FLT1_Pos            (0U)
+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */
+#define HRTIM_ISR_FLT2_Pos            (1U)
+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */
+#define HRTIM_ISR_FLT3_Pos            (2U)
+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */
+#define HRTIM_ISR_FLT4_Pos            (3U)
+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */
+#define HRTIM_ISR_FLT5_Pos            (4U)
+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */
+#define HRTIM_ISR_SYSFLT_Pos          (5U)
+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */
+#define HRTIM_ISR_BMPER_Pos           (17U)
+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */
+
+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
+#define HRTIM_ICR_FLT1C_Pos           (0U)
+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */
+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */
+#define HRTIM_ICR_FLT2C_Pos           (1U)
+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */
+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */
+#define HRTIM_ICR_FLT3C_Pos           (2U)
+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */
+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */
+#define HRTIM_ICR_FLT4C_Pos           (3U)
+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */
+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */
+#define HRTIM_ICR_FLT5C_Pos           (4U)
+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */
+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */
+#define HRTIM_ICR_SYSFLTC_Pos         (5U)
+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */
+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */
+#define HRTIM_ICR_BMPERC_Pos          (17U)
+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */
+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */
+
+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
+#define HRTIM_IER_FLT1_Pos            (0U)
+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */
+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */
+#define HRTIM_IER_FLT2_Pos            (1U)
+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */
+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */
+#define HRTIM_IER_FLT3_Pos            (2U)
+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */
+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */
+#define HRTIM_IER_FLT4_Pos            (3U)
+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */
+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */
+#define HRTIM_IER_FLT5_Pos            (4U)
+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */
+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */
+#define HRTIM_IER_SYSFLT_Pos          (5U)
+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */
+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */
+#define HRTIM_IER_BMPER_Pos           (17U)
+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */
+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */
+
+/**** Bit definition for Common HRTIM Timer output enable register ************/
+#define HRTIM_OENR_TA1OEN_Pos         (0U)
+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */
+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */
+#define HRTIM_OENR_TA2OEN_Pos         (1U)
+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */
+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */
+#define HRTIM_OENR_TB1OEN_Pos         (2U)
+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */
+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */
+#define HRTIM_OENR_TB2OEN_Pos         (3U)
+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */
+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */
+#define HRTIM_OENR_TC1OEN_Pos         (4U)
+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */
+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */
+#define HRTIM_OENR_TC2OEN_Pos         (5U)
+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */
+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */
+#define HRTIM_OENR_TD1OEN_Pos         (6U)
+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */
+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */
+#define HRTIM_OENR_TD2OEN_Pos         (7U)
+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */
+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */
+#define HRTIM_OENR_TE1OEN_Pos         (8U)
+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */
+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */
+#define HRTIM_OENR_TE2OEN_Pos         (9U)
+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */
+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */
+
+/**** Bit definition for Common HRTIM Timer output disable register ***********/
+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)
+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */
+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */
+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)
+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */
+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */
+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)
+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */
+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */
+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)
+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */
+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */
+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)
+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */
+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */
+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)
+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */
+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */
+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)
+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */
+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */
+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)
+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */
+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */
+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)
+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */
+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */
+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)
+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */
+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */
+
+/**** Bit definition for Common HRTIM Timer output disable status register *****/
+#define HRTIM_ODSR_TA1ODS_Pos         (0U)
+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */
+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */
+#define HRTIM_ODSR_TA2ODS_Pos         (1U)
+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */
+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */
+#define HRTIM_ODSR_TB1ODS_Pos         (2U)
+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */
+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */
+#define HRTIM_ODSR_TB2ODS_Pos         (3U)
+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */
+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */
+#define HRTIM_ODSR_TC1ODS_Pos         (4U)
+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */
+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */
+#define HRTIM_ODSR_TC2ODS_Pos         (5U)
+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */
+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */
+#define HRTIM_ODSR_TD1ODS_Pos         (6U)
+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */
+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */
+#define HRTIM_ODSR_TD2ODS_Pos         (7U)
+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */
+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */
+#define HRTIM_ODSR_TE1ODS_Pos         (8U)
+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */
+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */
+#define HRTIM_ODSR_TE2ODS_Pos         (9U)
+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */
+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
+#define HRTIM_BMCR_BME_Pos            (0U)
+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */
+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enable */
+#define HRTIM_BMCR_BMOM_Pos           (1U)
+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */
+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */
+#define HRTIM_BMCR_BMCLK_Pos          (2U)
+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */
+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */
+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */
+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */
+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */
+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */
+#define HRTIM_BMCR_BMPRSC_Pos         (6U)
+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */
+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */
+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */
+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */
+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */
+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */
+#define HRTIM_BMCR_BMPREN_Pos         (10U)
+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */
+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */
+#define HRTIM_BMCR_MTBM_Pos           (16U)
+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */
+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */
+#define HRTIM_BMCR_TABM_Pos           (17U)
+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */
+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */
+#define HRTIM_BMCR_TBBM_Pos           (18U)
+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */
+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */
+#define HRTIM_BMCR_TCBM_Pos           (19U)
+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */
+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */
+#define HRTIM_BMCR_TDBM_Pos           (20U)
+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */
+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */
+#define HRTIM_BMCR_TEBM_Pos           (21U)
+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */
+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */
+#define HRTIM_BMCR_BMSTAT_Pos         (31U)
+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */
+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */
+
+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
+#define HRTIM_BMTRGR_SW_Pos           (0U)
+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */
+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */
+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)
+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */
+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */
+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)
+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */
+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */
+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)
+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */
+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */
+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)
+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */
+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */
+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)
+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */
+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */
+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)
+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */
+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */
+#define HRTIM_BMTRGR_TARST_Pos        (7U)
+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */
+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */
+#define HRTIM_BMTRGR_TAREP_Pos        (8U)
+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */
+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */
+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)
+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */
+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */
+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)
+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */
+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */
+#define HRTIM_BMTRGR_TBRST_Pos        (11U)
+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */
+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */
+#define HRTIM_BMTRGR_TBREP_Pos        (12U)
+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */
+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */
+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)
+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */
+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */
+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)
+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */
+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */
+#define HRTIM_BMTRGR_TCRST_Pos        (15U)
+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */
+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */
+#define HRTIM_BMTRGR_TCREP_Pos        (16U)
+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */
+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */
+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)
+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */
+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */
+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)
+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */
+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */
+#define HRTIM_BMTRGR_TDRST_Pos        (19U)
+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */
+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */
+#define HRTIM_BMTRGR_TDREP_Pos        (20U)
+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */
+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */
+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)
+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */
+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */
+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)
+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */
+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */
+#define HRTIM_BMTRGR_TERST_Pos        (23U)
+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */
+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */
+#define HRTIM_BMTRGR_TEREP_Pos        (24U)
+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */
+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */
+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)
+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */
+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */
+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)
+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */
+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */
+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)
+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */
+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */
+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)
+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */
+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */
+#define HRTIM_BMTRGR_EEV7_Pos         (29U)
+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */
+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */
+#define HRTIM_BMTRGR_EEV8_Pos         (30U)
+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */
+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */
+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)
+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */
+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */
+
+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/
+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)
+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */
+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */
+
+/*******************  Bit definition for HRTIM_BMPER register  ****************/
+#define HRTIM_BMPER_BMPER_Pos         (0U)
+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */
+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */
+
+/*******************  Bit definition for HRTIM_EECR1 register  ****************/
+#define HRTIM_EECR1_EE1SRC_Pos        (0U)
+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */
+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR1_EE1POL_Pos        (2U)
+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */
+#define HRTIM_EECR1_EE1SNS_Pos        (3U)
+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */
+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */
+#define HRTIM_EECR1_EE1FAST_Pos       (5U)
+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */
+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */
+
+#define HRTIM_EECR1_EE2SRC_Pos        (6U)
+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */
+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR1_EE2POL_Pos        (8U)
+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */
+#define HRTIM_EECR1_EE2SNS_Pos        (9U)
+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */
+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */
+#define HRTIM_EECR1_EE2FAST_Pos       (11U)
+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */
+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */
+
+#define HRTIM_EECR1_EE3SRC_Pos        (12U)
+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */
+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR1_EE3POL_Pos        (14U)
+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */
+#define HRTIM_EECR1_EE3SNS_Pos        (15U)
+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */
+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */
+#define HRTIM_EECR1_EE3FAST_Pos       (17U)
+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */
+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */
+
+#define HRTIM_EECR1_EE4SRC_Pos        (18U)
+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */
+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR1_EE4POL_Pos        (20U)
+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */
+#define HRTIM_EECR1_EE4SNS_Pos        (21U)
+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */
+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */
+#define HRTIM_EECR1_EE4FAST_Pos       (23U)
+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */
+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */
+
+#define HRTIM_EECR1_EE5SRC_Pos        (24U)
+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */
+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */
+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */
+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */
+#define HRTIM_EECR1_EE5POL_Pos        (26U)
+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */
+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */
+#define HRTIM_EECR1_EE5SNS_Pos        (27U)
+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */
+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */
+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */
+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */
+#define HRTIM_EECR1_EE5FAST_Pos       (29U)
+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */
+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */
+
+/*******************  Bit definition for HRTIM_EECR2 register  ****************/
+#define HRTIM_EECR2_EE6SRC_Pos        (0U)
+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */
+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */
+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */
+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */
+#define HRTIM_EECR2_EE6POL_Pos        (2U)
+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */
+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */
+#define HRTIM_EECR2_EE6SNS_Pos        (3U)
+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */
+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */
+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */
+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */
+
+#define HRTIM_EECR2_EE7SRC_Pos        (6U)
+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */
+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */
+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */
+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */
+#define HRTIM_EECR2_EE7POL_Pos        (8U)
+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */
+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */
+#define HRTIM_EECR2_EE7SNS_Pos        (9U)
+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */
+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */
+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */
+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */
+
+#define HRTIM_EECR2_EE8SRC_Pos        (12U)
+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */
+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */
+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */
+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */
+#define HRTIM_EECR2_EE8POL_Pos        (14U)
+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */
+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */
+#define HRTIM_EECR2_EE8SNS_Pos        (15U)
+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */
+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */
+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */
+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */
+
+#define HRTIM_EECR2_EE9SRC_Pos        (18U)
+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */
+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */
+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */
+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */
+#define HRTIM_EECR2_EE9POL_Pos        (20U)
+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */
+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */
+#define HRTIM_EECR2_EE9SNS_Pos        (21U)
+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */
+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */
+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */
+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */
+
+#define HRTIM_EECR2_EE10SRC_Pos       (24U)
+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */
+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */
+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */
+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */
+#define HRTIM_EECR2_EE10POL_Pos       (26U)
+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */
+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */
+#define HRTIM_EECR2_EE10SNS_Pos       (27U)
+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */
+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */
+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */
+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */
+
+/*******************  Bit definition for HRTIM_EECR3 register  ****************/
+#define HRTIM_EECR3_EE6F_Pos          (0U)
+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */
+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */
+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */
+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */
+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */
+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */
+#define HRTIM_EECR3_EE7F_Pos          (6U)
+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */
+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */
+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */
+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */
+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */
+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */
+#define HRTIM_EECR3_EE8F_Pos          (12U)
+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */
+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */
+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */
+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */
+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */
+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */
+#define HRTIM_EECR3_EE9F_Pos          (18U)
+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */
+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */
+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */
+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */
+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */
+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */
+#define HRTIM_EECR3_EE10F_Pos         (24U)
+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */
+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */
+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */
+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */
+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */
+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */
+#define HRTIM_EECR3_EEVSD_Pos         (30U)
+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */
+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */
+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */
+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */
+
+/*******************  Bit definition for HRTIM_ADC1R register  ****************/
+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)
+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */
+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)
+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */
+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)
+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */
+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)
+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */
+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)
+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */
+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)
+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */
+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)
+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */
+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)
+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */
+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)
+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */
+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)
+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */
+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)
+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */
+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)
+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */
+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)
+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */
+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)
+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */
+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)
+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */
+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)
+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */
+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)
+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */
+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)
+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */
+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)
+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */
+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)
+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */
+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)
+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */
+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)
+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */
+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)
+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */
+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)
+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */
+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)
+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */
+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)
+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */
+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)
+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */
+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)
+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */
+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)
+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */
+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)
+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */
+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)
+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */
+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)
+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC2R register  ****************/
+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)
+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */
+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)
+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */
+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)
+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */
+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)
+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */
+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)
+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */
+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)
+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */
+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)
+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */
+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)
+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */
+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)
+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */
+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)
+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */
+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)
+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */
+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)
+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */
+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)
+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/
+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)
+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */
+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)
+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */
+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)
+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */
+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)
+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */
+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)
+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */
+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)
+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */
+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)
+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */
+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)
+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */
+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)
+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */
+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)
+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */
+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)
+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */
+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)
+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */
+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)
+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/
+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)
+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */
+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)
+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */
+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)
+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */
+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)
+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */
+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)
+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */
+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)
+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_ADC3R register  ****************/
+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)
+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */
+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)
+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */
+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)
+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */
+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)
+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */
+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)
+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */
+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)
+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */
+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)
+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */
+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)
+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */
+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)
+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */
+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)
+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */
+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */
+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)
+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */
+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)
+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */
+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)
+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */
+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)
+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */
+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)
+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */
+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */
+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)
+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */
+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)
+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */
+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)
+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */
+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */
+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)
+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */
+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */
+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)
+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */
+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */
+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)
+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */
+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)
+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */
+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */
+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)
+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */
+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */
+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)
+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */
+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */
+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)
+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */
+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)
+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */
+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)
+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */
+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */
+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)
+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */
+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)
+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */
+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)
+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */
+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)
+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */
+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)
+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */
+
+/*******************  Bit definition for HRTIM_ADC4R register  ****************/
+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)
+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */
+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */
+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)
+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */
+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */
+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)
+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */
+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */
+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)
+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */
+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */
+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)
+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */
+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)
+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */
+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */
+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)
+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */
+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */
+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)
+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */
+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */
+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)
+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */
+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */
+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)
+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */
+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */
+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)
+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */
+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */
+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)
+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */
+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */
+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)
+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */
+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/
+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)
+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */
+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */
+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)
+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */
+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */
+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)
+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */
+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */
+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)
+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */
+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */
+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)
+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */
+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */
+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)
+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */
+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */
+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)
+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */
+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */
+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)
+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */
+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */
+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)
+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */
+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */
+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)
+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */
+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */
+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)
+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */
+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */
+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)
+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */
+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */
+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)
+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */
+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/
+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)
+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */
+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */
+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)
+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */
+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */
+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)
+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */
+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */
+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)
+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */
+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */
+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)
+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */
+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */
+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)
+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */
+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */
+
+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/
+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)
+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */
+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)
+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */
+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)
+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */
+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)
+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */
+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)
+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */
+
+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)
+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */
+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */
+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)
+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */
+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */
+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)
+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */
+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */
+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)
+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */
+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */
+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */
+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */
+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */
+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */
+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)
+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */
+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */
+
+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)
+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */
+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */
+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)
+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */
+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */
+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)
+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */
+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */
+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)
+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */
+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */
+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */
+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */
+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */
+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */
+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)
+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */
+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */
+
+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)
+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */
+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */
+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)
+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */
+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */
+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)
+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */
+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */
+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)
+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */
+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */
+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */
+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */
+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */
+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */
+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)
+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */
+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */
+
+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/
+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)
+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */
+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */
+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)
+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */
+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */
+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)
+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */
+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */
+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)
+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */
+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */
+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */
+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */
+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */
+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */
+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)
+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */
+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */
+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)
+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */
+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */
+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */
+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */
+
+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/
+#define HRTIM_BDMUPR_MCR_Pos          (0U)
+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */
+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */
+#define HRTIM_BDMUPR_MICR_Pos         (1U)
+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */
+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */
+#define HRTIM_BDMUPR_MDIER_Pos        (2U)
+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */
+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */
+#define HRTIM_BDMUPR_MCNT_Pos         (3U)
+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */
+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */
+#define HRTIM_BDMUPR_MPER_Pos         (4U)
+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */
+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */
+#define HRTIM_BDMUPR_MREP_Pos         (5U)
+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */
+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */
+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)
+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */
+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */
+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)
+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */
+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */
+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)
+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */
+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */
+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)
+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */
+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */
+
+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/
+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)
+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */
+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */
+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)
+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */
+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */
+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)
+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */
+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */
+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)
+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */
+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */
+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)
+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */
+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */
+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)
+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */
+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */
+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)
+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */
+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */
+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)
+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */
+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */
+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)
+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */
+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */
+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)
+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */
+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */
+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)
+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */
+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */
+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)
+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */
+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */
+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)
+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */
+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */
+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)
+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */
+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */
+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)
+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */
+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */
+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)
+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */
+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */
+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)
+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */
+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */
+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)
+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */
+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */
+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)
+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */
+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */
+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)
+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */
+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */
+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)
+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */
+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */
+
+/*******************  Bit definition for HRTIM_BDMADR register  ***************/
+#define HRTIM_BDMADR_BDMADR_Pos       (0U)
+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                             RAM ECC monitoring                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for RAMECC_IER register  ******************/
+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)
+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */
+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_IER_GECCDEIE_Pos           (2U)
+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */
+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */
+#define RAMECC_IER_GECCSEIE_Pos           (1U)
+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */
+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */
+#define RAMECC_IER_GIE_Pos                (0U)
+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */
+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */
+
+/*******************  Bit definition for RAMECC_CR register  ******************/
+#define RAMECC_CR_ECCELEN_Pos             (5U)
+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */
+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */
+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)
+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */
+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */
+#define RAMECC_CR_ECCDEIE_Pos             (3U)
+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */
+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */
+#define RAMECC_CR_ECCSEIE_Pos             (2U)
+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */
+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */
+
+/*******************  Bit definition for RAMECC_SR register  ******************/
+#define RAMECC_SR_DEBWDF_Pos             (2U)
+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */
+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */
+#define RAMECC_SR_DEDF_Pos               (1U)
+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */
+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */
+#define RAMECC_SR_SEDCF_Pos              (0U)
+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */
+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */
+
+/******************  Bit definition for RAMECC_FAR register  ******************/
+#define RAMECC_FAR_FADD_Pos              (0U)
+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRL register  *****************/
+#define RAMECC_FAR_FDATAL_Pos            (0U)
+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */
+
+/******************  Bit definition for RAMECC_FDRH register  *****************/
+#define RAMECC_FAR_FDATAH_Pos            (0U)
+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */
+
+/*****************  Bit definition for RAMECC_FECR register  ******************/
+#define RAMECC_FECR_FEC_Pos              (0U)
+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */
+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                MDIOS                                        */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for MDIOS_CR register  *******************/
+#define MDIOS_CR_EN_Pos                (0U)
+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */
+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */
+#define MDIOS_CR_WRIE_Pos              (1U)
+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */
+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */
+#define MDIOS_CR_RDIE_Pos              (2U)
+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */
+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */
+#define MDIOS_CR_EIE_Pos               (3U)
+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */
+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */
+#define MDIOS_CR_DPC_Pos               (7U)
+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */
+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */
+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)
+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */
+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */
+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */
+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */
+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */
+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */
+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */
+
+/********************  Bit definition for MDIOS_SR register  *******************/
+#define MDIOS_SR_PERF_Pos              (0U)
+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */
+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/
+#define MDIOS_SR_SERF_Pos              (1U)
+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */
+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */
+#define MDIOS_SR_TERF_Pos              (2U)
+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */
+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */
+
+/********************  Bit definition for MDIOS_CLRFR register  *******************/
+#define MDIOS_SR_CPERF_Pos             (0U)
+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */
+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */
+#define MDIOS_SR_CSERF_Pos             (1U)
+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */
+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */
+#define MDIOS_SR_CTERF_Pos             (2U)
+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */
+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)
+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */
+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)
+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)
+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)
+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */
+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition forUSB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition forUSB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
+
+/********************  Bit definition forUSB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition forUSB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
+
+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition forUSB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */
+
+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)
+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)
+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)
+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)
+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition forUSB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for OTG register  ********************/
+
+#define USB_OTG_CHNUM_Pos                        (0U)
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+
+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)
+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */
+#define USB_OTG_GCCFG_PDET_Pos                   (1U)
+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */
+#define USB_OTG_GCCFG_SDET_Pos                   (2U)
+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */
+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)
+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)
+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */
+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)
+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/
+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)
+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/
+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)
+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */
+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)
+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */
+
+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/
+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)
+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */
+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)
+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition forUSB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/
+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)
+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */
+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)
+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */
+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)
+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */
+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)
+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */
+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)
+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */
+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)
+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */
+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)
+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */
+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)
+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */
+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)
+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */
+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)
+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */
+
+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
+
+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition forUSB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)
+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+
+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
+                                          ((INSTANCE) == ADC3_COMMON))
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                       ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
+/******************** COMP Instances with window mode capability **************/
+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
+
+
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
+
+/******************************* DELAYBLOCK Instances *******************************/
+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \
+                                         ((INSTANCE) == DLYB_SDMMC2) || \
+                                         ((INSTANCE) == DLYB_QUADSPI))
+/****************************** DFSDM Instances *******************************/
+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
+                                               ((INSTANCE) == DFSDM1_Filter1) || \
+                                               ((INSTANCE) == DFSDM1_Filter2) || \
+                                               ((INSTANCE) == DFSDM1_Filter3))
+
+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
+                                                 ((INSTANCE) == DFSDM1_Channel1) || \
+                                                 ((INSTANCE) == DFSDM1_Channel2) || \
+                                                 ((INSTANCE) == DFSDM1_Channel3) || \
+                                                 ((INSTANCE) == DFSDM1_Channel4) || \
+                                                 ((INSTANCE) == DFSDM1_Channel5) || \
+                                                 ((INSTANCE) == DFSDM1_Channel6) || \
+                                                 ((INSTANCE) == DFSDM1_Channel7))
+/****************************** RAMECC Instances ******************************/
+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \
+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \
+                                                  ((INSTANCE) == RAMECC3_Monitor2))
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                       ((INSTANCE) == DMA1_Stream1)   || \
+                                       ((INSTANCE) == DMA1_Stream2)   || \
+                                       ((INSTANCE) == DMA1_Stream3)   || \
+                                       ((INSTANCE) == DMA1_Stream4)   || \
+                                       ((INSTANCE) == DMA1_Stream5)   || \
+                                       ((INSTANCE) == DMA1_Stream6)   || \
+                                       ((INSTANCE) == DMA1_Stream7)   || \
+                                       ((INSTANCE) == DMA2_Stream0)   || \
+                                       ((INSTANCE) == DMA2_Stream1)   || \
+                                       ((INSTANCE) == DMA2_Stream2)   || \
+                                       ((INSTANCE) == DMA2_Stream3)   || \
+                                       ((INSTANCE) == DMA2_Stream4)   || \
+                                       ((INSTANCE) == DMA2_Stream5)   || \
+                                       ((INSTANCE) == DMA2_Stream6)   || \
+                                       ((INSTANCE) == DMA2_Stream7)   || \
+                                       ((INSTANCE) == BDMA_Channel0) || \
+                                       ((INSTANCE) == BDMA_Channel1) || \
+                                       ((INSTANCE) == BDMA_Channel2) || \
+                                       ((INSTANCE) == BDMA_Channel3) || \
+                                       ((INSTANCE) == BDMA_Channel4) || \
+                                       ((INSTANCE) == BDMA_Channel5) || \
+                                       ((INSTANCE) == BDMA_Channel6) || \
+                                       ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA CHANNEL Instances ***************************/
+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
+                                            ((INSTANCE) == BDMA_Channel1) || \
+                                            ((INSTANCE) == BDMA_Channel2) || \
+                                            ((INSTANCE) == BDMA_Channel3) || \
+                                            ((INSTANCE) == BDMA_Channel4) || \
+                                            ((INSTANCE) == BDMA_Channel5) || \
+                                            ((INSTANCE) == BDMA_Channel6) || \
+                                            ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA DMAMUX ALL Instances ***************************/
+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \
+                                               ((INSTANCE) == DMA1_Stream1)    || \
+                                               ((INSTANCE) == DMA1_Stream2)    || \
+                                               ((INSTANCE) == DMA1_Stream3)    || \
+                                               ((INSTANCE) == DMA1_Stream4)    || \
+                                               ((INSTANCE) == DMA1_Stream5)    || \
+                                               ((INSTANCE) == DMA1_Stream6)    || \
+                                               ((INSTANCE) == DMA1_Stream7)    || \
+                                               ((INSTANCE) == DMA2_Stream0)    || \
+                                               ((INSTANCE) == DMA2_Stream1)    || \
+                                               ((INSTANCE) == DMA2_Stream2)    || \
+                                               ((INSTANCE) == DMA2_Stream3)    || \
+                                               ((INSTANCE) == DMA2_Stream4)    || \
+                                               ((INSTANCE) == DMA2_Stream5)    || \
+                                               ((INSTANCE) == DMA2_Stream6)    || \
+                                               ((INSTANCE) == DMA2_Stream7)    || \
+                                               ((INSTANCE) == BDMA_Channel0)   || \
+                                               ((INSTANCE) == BDMA_Channel1)   || \
+                                               ((INSTANCE) == BDMA_Channel2)   || \
+                                               ((INSTANCE) == BDMA_Channel3)   || \
+                                               ((INSTANCE) == BDMA_Channel4)   || \
+                                               ((INSTANCE) == BDMA_Channel5)   || \
+                                               ((INSTANCE) == BDMA_Channel6)   || \
+                                               ((INSTANCE) == BDMA_Channel7))
+
+/****************************** BDMA DMAMUX Instances ***************************/
+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \
+                                                    ((INSTANCE) == BDMA_Channel1) || \
+                                                    ((INSTANCE) == BDMA_Channel2) || \
+                                                    ((INSTANCE) == BDMA_Channel3) || \
+                                                    ((INSTANCE) == BDMA_Channel4) || \
+                                                    ((INSTANCE) == BDMA_Channel5) || \
+                                                    ((INSTANCE) == BDMA_Channel6) || \
+                                                    ((INSTANCE) == BDMA_Channel7))
+
+/****************************** DMA STREAM Instances ***************************/
+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \
+                                          ((INSTANCE) == DMA1_Stream1)   || \
+                                          ((INSTANCE) == DMA1_Stream2)   || \
+                                          ((INSTANCE) == DMA1_Stream3)   || \
+                                          ((INSTANCE) == DMA1_Stream4)   || \
+                                          ((INSTANCE) == DMA1_Stream5)   || \
+                                          ((INSTANCE) == DMA1_Stream6)   || \
+                                          ((INSTANCE) == DMA1_Stream7)   || \
+                                          ((INSTANCE) == DMA2_Stream0)   || \
+                                          ((INSTANCE) == DMA2_Stream1)   || \
+                                          ((INSTANCE) == DMA2_Stream2)   || \
+                                          ((INSTANCE) == DMA2_Stream3)   || \
+                                          ((INSTANCE) == DMA2_Stream4)   || \
+                                          ((INSTANCE) == DMA2_Stream5)   || \
+                                          ((INSTANCE) == DMA2_Stream6)   || \
+                                          ((INSTANCE) == DMA2_Stream7))
+
+/****************************** DMA DMAMUX Instances ***************************/
+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \
+                                                  ((INSTANCE) == DMA1_Stream1)   || \
+                                                  ((INSTANCE) == DMA1_Stream2)   || \
+                                                  ((INSTANCE) == DMA1_Stream3)   || \
+                                                  ((INSTANCE) == DMA1_Stream4)   || \
+                                                  ((INSTANCE) == DMA1_Stream5)   || \
+                                                  ((INSTANCE) == DMA1_Stream6)   || \
+                                                  ((INSTANCE) == DMA1_Stream7)   || \
+                                                  ((INSTANCE) == DMA2_Stream0)   || \
+                                                  ((INSTANCE) == DMA2_Stream1)   || \
+                                                  ((INSTANCE) == DMA2_Stream2)   || \
+                                                  ((INSTANCE) == DMA2_Stream3)   || \
+                                                  ((INSTANCE) == DMA2_Stream4)   || \
+                                                  ((INSTANCE) == DMA2_Stream5)   || \
+                                                  ((INSTANCE) == DMA2_Stream6)   || \
+                                                  ((INSTANCE) == DMA2_Stream7))
+
+/******************************** DMA Request Generator Instances **************/
+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))
+
+/******************************* DMA2D Instances *******************************/
+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
+
+/******************************** MDMA Request Generator Instances **************/
+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \
+                                               ((INSTANCE) == MDMA_Channel1)  || \
+                                               ((INSTANCE) == MDMA_Channel2)  || \
+                                               ((INSTANCE) == MDMA_Channel3)  || \
+                                               ((INSTANCE) == MDMA_Channel4)  || \
+                                               ((INSTANCE) == MDMA_Channel5)  || \
+                                               ((INSTANCE) == MDMA_Channel6)  || \
+                                               ((INSTANCE) == MDMA_Channel7)  || \
+                                               ((INSTANCE) == MDMA_Channel8)  || \
+                                               ((INSTANCE) == MDMA_Channel9)  || \
+                                               ((INSTANCE) == MDMA_Channel10) || \
+                                               ((INSTANCE) == MDMA_Channel11) || \
+                                               ((INSTANCE) == MDMA_Channel12) || \
+                                               ((INSTANCE) == MDMA_Channel13) || \
+                                               ((INSTANCE) == MDMA_Channel14) || \
+                                               ((INSTANCE) == MDMA_Channel15))
+
+/******************************* QUADSPI Instances *******************************/
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
+
+/******************************* FDCAN Instances ******************************/
+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
+                                             ((__INSTANCE__) == FDCAN2))
+
+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI) || \
+                                        ((INSTANCE) == GPIOJ) || \
+                                        ((INSTANCE) == GPIOK))
+
+/******************************* GPIO AF Instances ****************************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On H7, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** HSEM Instances *******************************/
+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
+/********************  Bit definition for HSEM_CR register  *****************/
+#define HSEM_CPU1_COREID    (0x00000003U) /* Semaphore Core CM7 ID */
+#define HSEM_CPU2_COREID    (0x00000001U) /* Semaphore Core CM4 ID */
+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#define HSEM_CR_COREID_CPU2      (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
+#if defined(CORE_CM4)
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
+#else  /* CORE_CM7 */
+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
+#endif /* CORE_CM4 */
+
+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */
+
+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
+
+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3) || \
+                                       ((INSTANCE) == I2C4))
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                         ((INSTANCE) == I2C2) || \
+                                         ((INSTANCE) == I2C3) || \
+                                         ((INSTANCE) == I2C4))
+
+/************** I2C Instances : wakeup capability from stop modes *************/
+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2S Instances *******************************/
+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \
+                                         ((INSTANCE) == SPI2) || \
+                                         ((INSTANCE) == SPI3))
+
+/****************************** LTDC Instances ********************************/
+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/****************************** SDMMC Instances *********************************/
+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
+                                           ((_INSTANCE_) == SDMMC2))
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3) || \
+                                       ((INSTANCE) == SPI4) || \
+                                       ((INSTANCE) == SPI5) || \
+                                       ((INSTANCE) == SPI6))
+
+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                           ((INSTANCE) == SPI2) || \
+                                           ((INSTANCE) == SPI3))
+
+/******************************** SWPMI Instances *****************************/
+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)
+
+/****************** LPTIM Instances : All supported instances *****************/
+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                         ((INSTANCE) == LPTIM2) || \
+                                         ((INSTANCE) == LPTIM3) || \
+                                         ((INSTANCE) == LPTIM4) || \
+                                         ((INSTANCE) == LPTIM5))
+
+/****************** LPTIM Instances : supporting encoder interface **************/
+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
+                                                           ((INSTANCE) == LPTIM2))
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM6)   || \
+                                         ((INSTANCE) == TIM7)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM13)  || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM12)  || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 5 capture/compare channels *************/
+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+/************ TIM Instances : at least 6 capture/compare channels *************/
+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
+                                                ((__INSTANCE__) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+                                         ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM5)   || \
+                                         ((INSTANCE) == TIM8)   || \
+                                         ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM6)   || \
+                                           ((INSTANCE) == TIM7)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM15)  || \
+                                           ((INSTANCE) == TIM16)  || \
+                                           ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM15))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM8))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM8)  || \
+                                          ((INSTANCE) == TIM16) || \
+                                          ((INSTANCE) == TIM17))
+
+/*************** TIM Instances : external trigger reamp input available *******/
+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \
+                                              ((INSTANCE) == TIM2)   || \
+                                              ((INSTANCE) == TIM3)   || \
+                                              ((INSTANCE) == TIM5)   || \
+                                              ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM2)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM4)   || \
+                                            ((INSTANCE) == TIM5)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM8)   || \
+                                            ((INSTANCE) == TIM12)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM2)   || \
+                                           ((INSTANCE) == TIM3)   || \
+                                           ((INSTANCE) == TIM4)   || \
+                                           ((INSTANCE) == TIM5)   || \
+                                           ((INSTANCE) == TIM8)   || \
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
+
+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                           ((INSTANCE) == TIM8))
+
+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \
+                                          ((INSTANCE) == TIM2)   || \
+                                          ((INSTANCE) == TIM3)   || \
+                                          ((INSTANCE) == TIM4)   || \
+                                          ((INSTANCE) == TIM5)   || \
+                                          ((INSTANCE) == TIM8)   || \
+                                          ((INSTANCE) == TIM15)  || \
+                                          ((INSTANCE) == TIM16)  || \
+                                          ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting commutation event *************/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
+                                                     ((INSTANCE) == TIM8)    || \
+                                                     ((INSTANCE) == TIM15)   || \
+                                                     ((INSTANCE) == TIM16)   || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \
+                                                      ((__INSTANCE__) == TIM2)      || \
+                                                      ((__INSTANCE__) == TIM3)      || \
+                                                      ((__INSTANCE__) == TIM4)      || \
+                                                      ((__INSTANCE__) == TIM5)      || \
+                                                      ((__INSTANCE__) == TIM8))
+
+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                                       ((INSTANCE) == TIM8))
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM3) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1)||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM4) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM5) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+  ||                                           \
+      (((INSTANCE) == TIM8) &&                 \
+      (((CHANNEL) == TIM_CHANNEL_1) ||         \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ||          \
+      ((CHANNEL) == TIM_CHANNEL_5) ||          \
+      ((CHANNEL) == TIM_CHANNEL_6)))           \
+  ||                                           \
+     (((INSTANCE) == TIM12) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+  ||                                           \
+     (((INSTANCE) == TIM13) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+     ((CHANNEL) == TIM_CHANNEL_2)))            \
+  ||                                           \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+  ||                                           \
+     (((INSTANCE) == TIM17) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
+      (((INSTANCE) == TIM1)    || \
+      ((INSTANCE) == TIM8)     || \
+       ((INSTANCE) == TIM15)   || \
+       ((INSTANCE) == TIM16)   || \
+       ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+ ||                                             \
+      (((INSTANCE) == TIM8) &&                  \
+      (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+      ((CHANNEL) == TIM_CHANNEL_1))             \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting synchronization ****************/
+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
+    (((__INSTANCE__) == TIM1)    || \
+     ((__INSTANCE__) == TIM2)    || \
+     ((__INSTANCE__) == TIM3)    || \
+     ((__INSTANCE__) == TIM4)    || \
+     ((__INSTANCE__) == TIM5)    || \
+     ((__INSTANCE__) == TIM6)    || \
+     ((__INSTANCE__) == TIM8)    || \
+     ((__INSTANCE__) == TIM12)   || \
+     ((__INSTANCE__) == TIM15))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM15)   || \
+   ((INSTANCE) == TIM16)   || \
+   ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 2 **********/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
+ (((INSTANCE) == TIM1)     || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3)    || \
+   ((INSTANCE) == TIM4)    || \
+   ((INSTANCE) == TIM5)    || \
+   ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
+   ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM3))
+
+/****************** TIM Instances : TIM_32B_COUNTER ***************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM2)    || \
+   ((INSTANCE) == TIM5))
+
+/****************** TIM Instances : TIM_BKIN2 ***************************/
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
+  (((INSTANCE) == TIM1)    || \
+   ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \
+                                                             ((__INSTANCE__) == TIM2)  || \
+                                                             ((__INSTANCE__) == TIM3)  || \
+                                                             ((__INSTANCE__) == TIM4)  || \
+                                                             ((__INSTANCE__) == TIM5)  || \
+                                                             ((__INSTANCE__) == TIM15) || \
+                                                             ((__INSTANCE__) == TIM8))
+
+/****************************** HRTIM Instances *******************************/
+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** USART Instances : SPI slave mode ************************/
+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                              ((INSTANCE) == USART2) || \
+                                              ((INSTANCE) == USART3) || \
+                                              ((INSTANCE) == USART6))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/******************** UART Instances : FIFO mode.******************************/
+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == UART4)  || \
+                                         ((INSTANCE) == UART5)  || \
+                                         ((INSTANCE) == USART6) || \
+                                         ((INSTANCE) == UART7)  || \
+                                         ((INSTANCE) == UART8))
+
+/****************** UART Instances : Auto Baud Rate detection *****************/
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                            ((INSTANCE) == USART2) || \
+                                                            ((INSTANCE) == USART3) || \
+                                                            ((INSTANCE) == UART4)  || \
+                                                            ((INSTANCE) == UART5)  || \
+                                                            ((INSTANCE) == USART6) || \
+                                                            ((INSTANCE) == UART7)  || \
+                                                            ((INSTANCE) == UART8))
+
+/*********************** UART Instances : Driver Enable ***********************/
+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                  ((INSTANCE) == USART2) || \
+                                                  ((INSTANCE) == USART3) || \
+                                                  ((INSTANCE) == UART4)  || \
+                                                  ((INSTANCE) == UART5)  || \
+                                                  ((INSTANCE) == USART6) || \
+                                                  ((INSTANCE) == UART7)  || \
+                                                  ((INSTANCE) == UART8)  || \
+                                                  ((INSTANCE) == LPUART1))
+
+/********************* UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6) || \
+                                               ((INSTANCE) == UART7)  || \
+                                               ((INSTANCE) == UART8)  || \
+                                               ((INSTANCE) == LPUART1))
+
+/******************* UART Instances : Hardware Flow control *******************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == UART4)  || \
+                                           ((INSTANCE) == UART5)  || \
+                                           ((INSTANCE) == USART6) || \
+                                           ((INSTANCE) == UART7)  || \
+                                           ((INSTANCE) == UART8)  || \
+                                           ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : LIN mode **************************/
+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                        ((INSTANCE) == USART2) || \
+                                        ((INSTANCE) == USART3) || \
+                                        ((INSTANCE) == UART4)  || \
+                                        ((INSTANCE) == UART5)  || \
+                                        ((INSTANCE) == USART6) || \
+                                        ((INSTANCE) == UART7)  || \
+                                        ((INSTANCE) == UART8))
+
+/****************** UART Instances : Wake-up from Stop mode *******************/
+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                                    ((INSTANCE) == USART2) || \
+                                                    ((INSTANCE) == USART3) || \
+                                                    ((INSTANCE) == UART4)  || \
+                                                    ((INSTANCE) == UART5)  || \
+                                                    ((INSTANCE) == USART6) || \
+                                                    ((INSTANCE) == UART7)  || \
+                                                    ((INSTANCE) == UART8)  || \
+                                                    ((INSTANCE) == LPUART1))
+
+/************************* UART Instances : IRDA mode *************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6) || \
+                                    ((INSTANCE) == UART7)  || \
+                                    ((INSTANCE) == UART8))
+
+/********************* USART Instances : Smard card mode **********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/****************************** LPUART Instance *******************************/
+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG1) || \
+                                         ((INSTANCE) == WWDG2))
+/****************************** MDIOS Instances ********************************/
+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)
+
+/****************************** CEC Instances *********************************/
+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
+
+/****************************** SAI Instances ********************************/
+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
+                    ((INSTANCE) == SAI1_Block_B) || \
+                     ((INSTANCE) == SAI2_Block_A) || \
+                     ((INSTANCE) == SAI2_Block_B) || \
+                     ((INSTANCE) == SAI3_Block_A) || \
+                     ((INSTANCE) == SAI3_Block_B) || \
+                     ((INSTANCE) == SAI4_Block_A) || \
+                     ((INSTANCE) == SAI4_Block_B))
+
+/****************************** SPDIFRX Instances ********************************/
+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
+
+/****************************** OPAMP Instances *******************************/
+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
+                                         ((INSTANCE) == OPAMP2))
+
+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
+
+/*********************** USB OTG PCD Instances ********************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                        ((INSTANCE) == USB_OTG_HS))
+
+/*********************** USB OTG HCD Instances ********************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32H7xx device product       */
+/*  lines, or with STM32F7xx devices the aliases defined below are put        */
+/*   in place to overcome the differences in the interrupt handlers and IRQn  */
+/*   definitions. No need to update developed interrupt code when moving      */
+/*  across product lines within the same STM32H7 Family                       */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+#define  HASH_RNG_IRQn                  RNG_IRQn
+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn
+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn
+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn
+#define  PVD_IRQn                       PVD_AVD_IRQn
+
+
+
+/* Aliases for __IRQHandler */
+#define  HASH_RNG_IRQHandler           RNG_IRQHandler
+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler
+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler
+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler
+#define PVD_IRQHandler                 PVD_AVD_IRQHandler
+
+/* Aliases for COMP __IRQHandler */
+#define COMP_IRQHandler                COMP1_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* STM32H747xG_H */
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xx.h
index 757117db05..dc32f93944 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h747xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -223,22 +222,22 @@ typedef enum
   * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
    */
 #ifdef CORE_CM4
-#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< CM4 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM4 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
 
 #include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */
 #else  /* CORE_CM7 */
 #ifdef CORE_CM7
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */
 #else  /* UNKNOWN_CORE */
 #error Please #define CORE_CM4 or CORE_CM7
@@ -252,7 +251,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -1014,8 +1012,8 @@ __IO uint32_t C2PR3;               /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1881,7 +1879,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2890,6 +2888,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2939,6 +2946,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4202,7 +4212,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -6159,10 +6169,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6917,7 +6927,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6936,14 +6946,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7054,7 +7064,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7090,21 +7100,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7123,7 +7133,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7148,7 +7158,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7204,7 +7214,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7240,7 +7250,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7273,7 +7283,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7475,7 +7485,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7499,7 +7509,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7656,7 +7666,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7811,12 +7821,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8314,14 +8324,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8356,10 +8366,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8406,10 +8416,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8432,7 +8442,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8445,7 +8455,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8477,14 +8487,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8524,7 +8534,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8546,7 +8556,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8570,11 +8580,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8583,12 +8593,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8606,12 +8616,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -11013,13 +11023,13 @@ typedef struct
 #define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk
 
 /*******************  Bit definition for DSI_TDCR register  ***************/
-#define DSI_TDCR_3DM                  ((uint32_t)0x00000003U)                  /*!< 3D Mode */
-#define DSI_TDCR_3DM0                 ((uint32_t)0x00000001U)
-#define DSI_TDCR_3DM1                 ((uint32_t)0x00000002U)
+#define DSI_TDCR_3DM                  (0x00000003U)                  /*!< 3D Mode */
+#define DSI_TDCR_3DM0                 (0x00000001U)
+#define DSI_TDCR_3DM1                 (0x00000002U)
 
-#define DSI_TDCR_3DF                  ((uint32_t)0x0000000CU)                  /*!< 3D Format */
-#define DSI_TDCR_3DF0                 ((uint32_t)0x00000004U)
-#define DSI_TDCR_3DF1                 ((uint32_t)0x00000008U)
+#define DSI_TDCR_3DF                  (0x0000000CU)                  /*!< 3D Format */
+#define DSI_TDCR_3DF0                 (0x00000004U)
+#define DSI_TDCR_3DF1                 (0x00000008U)
 
 #define DSI_TDCR_SVS_Pos              (4U)
 #define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)              /*!< 0x00000010 */
@@ -12189,13 +12199,13 @@ typedef struct
 #define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk
 
 /*******************  Bit definition for DSI_TDCCR register  **************/
-#define DSI_TDCCR_3DM                 ((uint32_t)0x00000003U)                  /*!< 3D Mode */
-#define DSI_TDCCR_3DM0                ((uint32_t)0x00000001U)
-#define DSI_TDCCR_3DM1                ((uint32_t)0x00000002U)
+#define DSI_TDCCR_3DM                 (0x00000003U)                  /*!< 3D Mode */
+#define DSI_TDCCR_3DM0                (0x00000001U)
+#define DSI_TDCCR_3DM1                (0x00000002U)
 
-#define DSI_TDCCR_3DF                 ((uint32_t)0x0000000CU)                  /*!< 3D Format */
-#define DSI_TDCCR_3DF0                ((uint32_t)0x00000004U)
-#define DSI_TDCCR_3DF1                ((uint32_t)0x00000008U)
+#define DSI_TDCCR_3DF                 (0x0000000CU)                  /*!< 3D Format */
+#define DSI_TDCCR_3DF0                (0x00000004U)
+#define DSI_TDCCR_3DF1                (0x00000008U)
 
 #define DSI_TDCCR_SVS_Pos             (4U)
 #define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)             /*!< 0x00000010 */
@@ -13914,15 +13924,15 @@ typedef struct
 /*
 * @brief FLASH Global Defines
 */
-#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
-#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
-#ifdef CORE_CM4
-#define FLASH_SIZE                           0x200000UL /* 2 MB */
+#if defined(CORE_CM4)
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
 #else
+#define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
 #define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
                                              ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
                                              (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
-#endif
+#endif /* CORE_CM4 */
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
 #define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
 #define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -13931,7 +13941,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -13941,6 +13951,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -13949,12 +13967,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -14741,7 +14753,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -16879,7 +16891,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -18289,7 +18301,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -18323,7 +18335,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -18345,7 +18357,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -18380,7 +18392,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -18402,7 +18414,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -18425,7 +18437,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -18445,7 +18457,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -21869,10 +21881,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -22318,12 +22330,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -22598,61 +22611,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -22670,60 +22683,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -22742,62 +22755,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -22815,59 +22828,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_CM4L_Pos            (0U)
@@ -23181,8 +23194,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -23459,8 +23472,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -23484,12 +23497,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -23729,8 +23742,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -23748,12 +23761,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -24862,7 +24875,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -25240,7 +25253,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -25449,7 +25462,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -26336,6 +26349,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -26376,6 +26390,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -28059,6 +28237,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -28084,7 +28265,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -28095,13 +28276,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -28171,6 +28360,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -28288,7 +28483,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -29896,7 +30091,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -30093,6 +30289,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -30103,6 +30300,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -30334,4 +30532,3 @@ typedef struct
 
 #endif /* STM32H747xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h750xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h750xx.h
index bbe8ba0296..8fce6344e7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h750xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h750xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -215,13 +214,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -230,7 +229,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -889,8 +887,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1795,7 +1793,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2789,6 +2787,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2838,6 +2845,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4088,7 +4098,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5803,7 +5813,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5854,7 +5864,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6162,10 +6172,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6920,7 +6930,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6939,14 +6949,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7057,7 +7067,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7093,21 +7103,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7126,7 +7136,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7151,7 +7161,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7207,7 +7217,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7243,7 +7253,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7276,7 +7286,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7478,7 +7488,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7502,7 +7512,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7659,7 +7669,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7814,12 +7824,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8317,14 +8327,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8359,10 +8369,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8409,10 +8419,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8435,7 +8445,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8448,7 +8458,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8480,14 +8490,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8527,7 +8537,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8549,7 +8559,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8573,11 +8583,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8586,12 +8596,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8609,12 +8619,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10856,7 +10866,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10866,6 +10876,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10874,12 +10892,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11638,7 +11650,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -13461,7 +13473,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -14819,7 +14831,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -14853,7 +14865,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -14875,7 +14887,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -14910,7 +14922,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -14932,7 +14944,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -14955,7 +14967,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -14975,7 +14987,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18342,10 +18354,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18791,12 +18803,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -19071,61 +19084,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19143,60 +19156,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19215,62 +19228,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19288,59 +19301,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19627,8 +19640,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -19905,8 +19918,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -19930,12 +19943,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20175,8 +20188,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20194,12 +20207,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -21308,7 +21321,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -21575,7 +21588,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -21784,7 +21797,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -22671,6 +22684,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -22711,6 +22725,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -24394,6 +24572,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -24419,7 +24600,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -24430,13 +24611,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -24506,6 +24695,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -24623,7 +24818,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -26224,7 +26419,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -26421,6 +26617,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -26431,6 +26628,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -26661,4 +26859,3 @@ typedef struct
 
 #endif /* STM32H750xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h753xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h753xx.h
index afd0d3a5db..40a4bb2e38 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h753xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h753xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -215,13 +214,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -230,7 +229,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -889,8 +887,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1795,7 +1793,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2789,6 +2787,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2838,6 +2845,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4088,7 +4098,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5803,7 +5813,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5854,7 +5864,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6162,10 +6172,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -6920,7 +6930,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -6939,14 +6949,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7057,7 +7067,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7093,21 +7103,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7126,7 +7136,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7151,7 +7161,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7207,7 +7217,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7243,7 +7253,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7276,7 +7286,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7478,7 +7488,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7502,7 +7512,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7659,7 +7669,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7814,12 +7824,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8317,14 +8327,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8359,10 +8369,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8409,10 +8419,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8435,7 +8445,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8448,7 +8458,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8480,14 +8490,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8527,7 +8537,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8549,7 +8559,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8573,11 +8583,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8586,12 +8596,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8609,12 +8619,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10856,7 +10866,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10866,6 +10876,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10874,12 +10892,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11644,7 +11656,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -13467,7 +13479,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -14825,7 +14837,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -14859,7 +14871,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -14881,7 +14893,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -14916,7 +14928,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -14938,7 +14950,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -14961,7 +14973,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -14981,7 +14993,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18348,10 +18360,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -18797,12 +18809,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -19077,61 +19090,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19149,60 +19162,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19221,62 +19234,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19294,59 +19307,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -19633,8 +19646,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -19911,8 +19924,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -19936,12 +19949,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20181,8 +20194,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20200,12 +20213,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -21314,7 +21327,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -21581,7 +21594,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -21790,7 +21803,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -22677,6 +22690,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -22717,6 +22731,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -24400,6 +24578,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -24425,7 +24606,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -24436,13 +24617,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -24512,6 +24701,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -24629,7 +24824,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -26230,7 +26425,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -26427,6 +26623,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -26437,6 +26634,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -26667,4 +26865,3 @@ typedef struct
 
 #endif /* STM32H753xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h755xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h755xx.h
index 41ffb30f20..b191b8ebaa 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h755xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h755xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -223,22 +222,22 @@ typedef enum
   * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
    */
 #ifdef CORE_CM4
-#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< CM4 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM4 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
 
 #include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */
 #else  /* CORE_CM7 */
 #ifdef CORE_CM7
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */
 #else  /* UNKNOWN_CORE */
 #error Please #define CORE_CM4 or CORE_CM7
@@ -252,7 +251,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -934,8 +932,8 @@ __IO uint32_t C2PR3;               /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1870,7 +1868,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2883,6 +2881,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2932,6 +2939,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4195,7 +4205,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5910,7 +5920,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5961,7 +5971,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6269,10 +6279,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -7027,7 +7037,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -7046,14 +7056,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7164,7 +7174,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7200,21 +7210,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7233,7 +7243,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7258,7 +7268,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7314,7 +7324,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7350,7 +7360,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7383,7 +7393,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7585,7 +7595,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7609,7 +7619,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7766,7 +7776,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -7921,12 +7931,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8424,14 +8434,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8466,10 +8476,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8516,10 +8526,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8542,7 +8552,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8555,7 +8565,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8587,14 +8597,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8634,7 +8644,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8656,7 +8666,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8680,11 +8690,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8693,12 +8703,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8716,12 +8726,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -10950,11 +10960,15 @@ typedef struct
 /*
 * @brief FLASH Global Defines
 */
+#if defined(CORE_CM4)
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#else
 #define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
-#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
                                              ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
                                              (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
+#endif /* CORE_CM4 */
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
 #define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
 #define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -10963,7 +10977,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -10973,6 +10987,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -10981,12 +11003,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -11773,7 +11789,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -13987,7 +14003,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -15397,7 +15413,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -15431,7 +15447,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -15453,7 +15469,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -15488,7 +15504,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -15510,7 +15526,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -15533,7 +15549,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -15553,7 +15569,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -18979,10 +18995,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -19428,12 +19444,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -19708,61 +19725,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -19780,60 +19797,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -19852,62 +19869,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -19925,59 +19942,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_CM4L_Pos            (0U)
@@ -20291,8 +20308,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -20569,8 +20586,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -20594,12 +20611,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -20839,8 +20856,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -20858,12 +20875,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -21972,7 +21989,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -22350,7 +22367,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -22559,7 +22576,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -23446,6 +23463,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -23486,6 +23504,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -25169,6 +25351,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -25194,7 +25379,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -25205,13 +25390,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -25281,6 +25474,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -25398,7 +25597,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -27006,7 +27205,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -27203,6 +27403,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -27213,6 +27414,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -27444,4 +27646,3 @@ typedef struct
 
 #endif /* STM32H755xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h757xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h757xx.h
index d125e360f9..339fb95f37 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h757xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h757xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -224,22 +223,22 @@ typedef enum
   * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
    */
 #ifdef CORE_CM4
-#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */
-#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
+#define __CM4_REV                 0x0001U  /*!< Cortex-M4 revision r0p1                       */
+#define __MPU_PRESENT             1U       /*!< CM4 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM4 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
 
 #include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */
 #else  /* CORE_CM7 */
 #ifdef CORE_CM7
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0101U   /*!< Cortex-M7 revision r1p1                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */
 #else  /* UNKNOWN_CORE */
 #error Please #define CORE_CM4 or CORE_CM7
@@ -253,7 +252,6 @@ typedef enum
 
 
 
-
 #include "system_stm32h7xx.h"
 #include <stdint.h>
 
@@ -1015,8 +1013,8 @@ __IO uint32_t C2PR3;               /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -1951,7 +1949,7 @@ typedef struct
   __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */
   __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */
   __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */
-  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */
+  __IO uint32_t BMTRGR;     /*!< HRTIM Burst mode trigger register,                          Address offset: 0x24 */
   __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */
   __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */
   __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */
@@ -2966,6 +2964,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -3015,6 +3022,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4278,7 +4288,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5993,7 +6003,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -6044,7 +6054,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6352,10 +6362,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -7110,7 +7120,7 @@ typedef struct
 #define ETH_MACCR_SARC_Pos                            (28U)
 #define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
 #define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */
-#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
+#define ETH_MACCR_SARC_MTIATI                         (0U)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
 #define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)
 #define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
 #define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
@@ -7129,14 +7139,14 @@ typedef struct
 #define ETH_MACCR_IPG_Pos                             (24U)
 #define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
 #define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */
-#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */
-#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */
-#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */
-#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */
-#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */
-#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */
-#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */
-#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */
+#define ETH_MACCR_IPG_96BIT                           (0U)   /* Minimum IFG between Packets during transmission is 96Bit */
+#define ETH_MACCR_IPG_88BIT                           (0x01000000U)   /* Minimum IFG between Packets during transmission is 88Bit */
+#define ETH_MACCR_IPG_80BIT                           (0x02000000U)   /* Minimum IFG between Packets during transmission is 80Bit */
+#define ETH_MACCR_IPG_72BIT                           (0x03000000U)   /* Minimum IFG between Packets during transmission is 72Bit */
+#define ETH_MACCR_IPG_64BIT                           (0x04000000U)   /* Minimum IFG between Packets during transmission is 64Bit */
+#define ETH_MACCR_IPG_56BIT                           (0x05000000U)   /* Minimum IFG between Packets during transmission is 56Bit */
+#define ETH_MACCR_IPG_48BIT                           (0x06000000U)   /* Minimum IFG between Packets during transmission is 48Bit */
+#define ETH_MACCR_IPG_40BIT                           (0x07000000U)   /* Minimum IFG between Packets during transmission is 40Bit */
 #define ETH_MACCR_GPSLCE_Pos                          (23U)
 #define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
 #define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */
@@ -7247,7 +7257,7 @@ typedef struct
 #define ETH_MACPFR_PCF_Pos                            (6U)
 #define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
 #define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */
-#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */
+#define ETH_MACPFR_PCF_BLOCKALL                       (0U)   /* MAC filters all control frames from reaching the application */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
@@ -7283,21 +7293,21 @@ typedef struct
 #define ETH_MACWTR_WTO_Pos                            (0U)
 #define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
 #define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */
-#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/
-#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */
-#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */
-#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */
-#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */
-#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */
-#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */
-#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */
-#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */
-#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */
-#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */
-#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */
-#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */
-#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */
-#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */
+#define ETH_MACWTR_WTO_2KB                            (0U)   /* Maximum received packet length 2KB*/
+#define ETH_MACWTR_WTO_3KB                            (0x00000001U)   /* Maximum received packet length 3KB */
+#define ETH_MACWTR_WTO_4KB                            (0x00000002U)   /* Maximum received packet length 4KB */
+#define ETH_MACWTR_WTO_5KB                            (0x00000003U)   /* Maximum received packet length 5KB */
+#define ETH_MACWTR_WTO_6KB                            (0x00000004U)   /* Maximum received packet length 6KB */
+#define ETH_MACWTR_WTO_7KB                            (0x00000005U)   /* Maximum received packet length 7KB */
+#define ETH_MACWTR_WTO_8KB                            (0x00000006U)   /* Maximum received packet length 8KB */
+#define ETH_MACWTR_WTO_9KB                            (0x00000007U)   /* Maximum received packet length 9KB */
+#define ETH_MACWTR_WTO_10KB                           (0x00000008U)   /* Maximum received packet length 10KB */
+#define ETH_MACWTR_WTO_11KB                           (0x00000009U)   /* Maximum received packet length 11KB */
+#define ETH_MACWTR_WTO_12KB                           (0x0000000AU)   /* Maximum received packet length 12KB */
+#define ETH_MACWTR_WTO_13KB                           (0x0000000BU)   /* Maximum received packet length 13KB */
+#define ETH_MACWTR_WTO_14KB                           (0x0000000CU)   /* Maximum received packet length 14KB */
+#define ETH_MACWTR_WTO_15KB                           (0x0000000DU)   /* Maximum received packet length 15KB */
+#define ETH_MACWTR_WTO_16KB                           (0x0000000EU)   /* Maximum received packet length 16KB */
 
 /* Bit definition for Ethernet MAC Hash Table High Register */
 #define ETH_MACHTHR_HTH_Pos                           (0U)
@@ -7316,7 +7326,7 @@ typedef struct
 #define ETH_MACVTR_EIVLS_Pos                          (28U)
 #define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
 #define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   (0U)   /* Do not strip */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)
 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
 #define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7341,7 +7351,7 @@ typedef struct
 #define ETH_MACVTR_EVLS_Pos                           (21U)
 #define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
 #define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */
-#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */
+#define ETH_MACVTR_EVLS_DONOTSTRIP                    (0U)   /* Do not strip */
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)
 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
 #define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
@@ -7397,7 +7407,7 @@ typedef struct
 #define ETH_MACVIR_VLC_Pos                            (16U)
 #define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACVIR_VLC_NOVLANTAG                      (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)
 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7433,7 +7443,7 @@ typedef struct
 #define ETH_MACIVIR_VLC_Pos                           (16U)
 #define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
 #define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */
-#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */
+#define ETH_MACIVIR_VLC_NOVLANTAG                     (0U)   /* No VLAN tag deletion, insertion, or replacement */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)
 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
 #define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
@@ -7466,7 +7476,7 @@ typedef struct
 #define ETH_MACTFCR_PLT_Pos                           (4U)
 #define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
 #define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */
-#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */
+#define ETH_MACTFCR_PLT_MINUS4                        (0U)   /* Pause time minus 4 slot times */
 #define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)
 #define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
 #define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
@@ -7668,7 +7678,7 @@ typedef struct
 #define ETH_MACDR_TFCSTS_Pos                          (17U)
 #define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
 #define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */
-#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MACDR_TFCSTS_IDLE                         (0U)   /* Idle state */
 #define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)
 #define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
 #define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
@@ -7692,7 +7702,7 @@ typedef struct
 #define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)
 #define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
 #define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
-#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */
+#define ETH_MACHWF0R_ACTPHYSEL_MII                    (0U)   /* MII */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)
 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
 #define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
@@ -7849,7 +7859,7 @@ typedef struct
 #define ETH_MACMDIOAR_CR_Pos                          (8U)
 #define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
 #define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */
-#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */
+#define ETH_MACMDIOAR_CR_DIV42                        (0U)   /* CSR clock/42 */
 #define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)
 #define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
 #define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
@@ -8004,12 +8014,12 @@ typedef struct
 #define ETH_MACAHR_MBC_Pos                            (24U)
 #define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
 #define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */
-#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */
-#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */
+#define ETH_MACAHR_MBC_HBITS15_8                      (0x20000000U)   /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACAHR_MBC_HBITS7_0                       (0x10000000U)   /* Mask MAC Address high reg bits [7:0] */
+#define ETH_MACAHR_MBC_LBITS31_24                     (0x08000000U)   /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACAHR_MBC_LBITS23_16                     (0x04000000U)   /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACAHR_MBC_LBITS15_8                      (0x02000000U)   /* Mask MAC Address low reg bits [15:8] */
+#define ETH_MACAHR_MBC_LBITS7_0                       (0x01000000U)   /* Mask MAC Address low reg bits [7:0] */
 #define ETH_MACAHR_MACAH_Pos                          (0U)
 #define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
 #define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */
@@ -8507,14 +8517,14 @@ typedef struct
 #define ETH_MTLTQOMR_TTC_Pos                          (4U)
 #define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
 #define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */
-#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */
-#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */
-#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */
-#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */
-#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */
-#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */
-#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */
-#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */
+#define ETH_MTLTQOMR_TTC_32BITS                       (0U)   /* 32 bits Threshold */
+#define ETH_MTLTQOMR_TTC_64BITS                       (0x00000010U)   /* 64  bits Threshold */
+#define ETH_MTLTQOMR_TTC_96BITS                       (0x00000020U)   /* 96 bits Threshold */
+#define ETH_MTLTQOMR_TTC_128BITS                      (0x00000030U)   /* 128 bits Threshold */
+#define ETH_MTLTQOMR_TTC_192BITS                      (0x00000040U)   /* 192 bits Threshold */
+#define ETH_MTLTQOMR_TTC_256BITS                      (0x00000050U)   /* 256 bits Threshold */
+#define ETH_MTLTQOMR_TTC_384BITS                      (0x00000060U)   /* 384 bits Threshold */
+#define ETH_MTLTQOMR_TTC_512BITS                      (0x00000070U)   /* 512 bits Threshold */
 #define ETH_MTLTQOMR_TSF_Pos                          (1U)
 #define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
 #define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */
@@ -8549,10 +8559,10 @@ typedef struct
 #define ETH_MTLTQDR_TRCSTS_Pos                        (1U)
 #define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */
-#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */
-#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */
-#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */
-#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
+#define ETH_MTLTQDR_TRCSTS_IDLE                       (0U)  /* Idle state */
+#define ETH_MTLTQDR_TRCSTS_READ                       (0x00000002U)  /* Read state (transferring data to the MAC transmitter) */
+#define ETH_MTLTQDR_TRCSTS_WAITING                    (0x00000004U)  /* Waiting for pending Tx Status from the MAC transmitter */
+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   (0x00000006U)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */
 #define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)
 #define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
 #define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
@@ -8599,10 +8609,10 @@ typedef struct
 #define ETH_MTLRQOMR_RTC_Pos                          (0U)
 #define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
 #define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */
-#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */
-#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */
-#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */
-#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */
+#define ETH_MTLRQOMR_RTC_64BITS                       (0U)   /* 64 bits Threshold */
+#define ETH_MTLRQOMR_RTC_32BITS                       (0x00000001U)   /* 32 bits Threshold */
+#define ETH_MTLRQOMR_RTC_96BITS                       (0x00000002U)   /* 96 bits Threshold */
+#define ETH_MTLRQOMR_RTC_128BITS                      (0x00000003U)   /* 128 bits Threshold */
 
 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)
@@ -8625,7 +8635,7 @@ typedef struct
 #define ETH_MTLRQDR_RXQSTS_Pos                        (4U)
 #define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
 #define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */
-#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */
+#define ETH_MTLRQDR_RXQSTS_EMPTY                      (0U)   /* Rx Queue empty */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
@@ -8638,7 +8648,7 @@ typedef struct
 #define ETH_MTLRQDR_RRCSTS_Pos                        (1U)
 #define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
 #define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */
-#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */
+#define ETH_MTLRQDR_RRCSTS_IDLE                       (0U)   /* Idle state */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)
 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
 #define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
@@ -8670,14 +8680,14 @@ typedef struct
 #define ETH_DMAMR_PR_Pos                              (12U)
 #define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
 #define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */
-#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */
-#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */
-#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */
-#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */
-#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */
-#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */
-#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */
-#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */
+#define ETH_DMAMR_PR_1_1                              (0U)   /* The priority ratio is 1:1 */
+#define ETH_DMAMR_PR_2_1                              (0x00001000U)   /* The priority ratio is 2:1 */
+#define ETH_DMAMR_PR_3_1                              (0x00002000U)   /* The priority ratio is 3:1 */
+#define ETH_DMAMR_PR_4_1                              (0x00003000U)   /* The priority ratio is 4:1 */
+#define ETH_DMAMR_PR_5_1                              (0x00004000U)   /* The priority ratio is 5:1 */
+#define ETH_DMAMR_PR_6_1                              (0x00005000U)   /* The priority ratio is 6:1 */
+#define ETH_DMAMR_PR_7_1                              (0x00006000U)   /* The priority ratio is 7:1 */
+#define ETH_DMAMR_PR_8_1                              (0x00007000U)   /* The priority ratio is 8:1 */
 #define ETH_DMAMR_TXPR_Pos                            (11U)
 #define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
 #define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */
@@ -8717,7 +8727,7 @@ typedef struct
 #define ETH_DMADSR_TPS_Pos                            (12U)
 #define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
 #define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */
-#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */
+#define ETH_DMADSR_TPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Transmit Command issued) */
 #define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
@@ -8739,7 +8749,7 @@ typedef struct
 #define ETH_DMADSR_RPS_Pos                            (8U)
 #define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
 #define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */
-#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */
+#define ETH_DMADSR_RPS_STOPPED                        (0U)   /* Stopped (Reset or Stop Receive Command issued) */
 #define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)
 #define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
 #define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
@@ -8763,11 +8773,11 @@ typedef struct
 #define ETH_DMACCR_DSL_Pos                            (18U)
 #define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
 #define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)
-#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)
-#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)
-#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)
-#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */
+#define ETH_DMACCR_DSL_0BIT                           (0U)
+#define ETH_DMACCR_DSL_32BIT                          (0x00040000U)
+#define ETH_DMACCR_DSL_64BIT                          (0x00080000U)
+#define ETH_DMACCR_DSL_128BIT                         (0x00100000U)
+#define ETH_DMACCR_8PBL                               (0x00010000U)   /* 8xPBL mode */
 #define ETH_DMACCR_MSS_Pos                            (0U)
 #define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
 #define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */
@@ -8776,12 +8786,12 @@ typedef struct
 #define ETH_DMACTCR_TPBL_Pos                          (16U)
 #define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */
-#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */
-#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */
-#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */
-#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */
-#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */
-#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */
+#define ETH_DMACTCR_TPBL_1PBL                         (0x00010000U)   /* Transmit Programmable Burst Length 1 */
+#define ETH_DMACTCR_TPBL_2PBL                         (0x00020000U)   /* Transmit Programmable Burst Length 2 */
+#define ETH_DMACTCR_TPBL_4PBL                         (0x00040000U)   /* Transmit Programmable Burst Length 4 */
+#define ETH_DMACTCR_TPBL_8PBL                         (0x00080000U)   /* Transmit Programmable Burst Length 8 */
+#define ETH_DMACTCR_TPBL_16PBL                        (0x00100000U)   /* Transmit Programmable Burst Length 16 */
+#define ETH_DMACTCR_TPBL_32PBL                        (0x00200000U)   /* Transmit Programmable Burst Length 32 */
 #define ETH_DMACTCR_TSE_Pos                           (12U)
 #define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
 #define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */
@@ -8799,12 +8809,12 @@ typedef struct
 #define ETH_DMACRCR_RPBL_Pos                          (16U)
 #define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
 #define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */
-#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */
-#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */
-#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */
-#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */
-#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */
-#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */
+#define ETH_DMACRCR_RPBL_1PBL                         (0x00010000U)   /* Receive Programmable Burst Length 1 */
+#define ETH_DMACRCR_RPBL_2PBL                         (0x00020000U)   /* Receive Programmable Burst Length 2 */
+#define ETH_DMACRCR_RPBL_4PBL                         (0x00040000U)   /* Receive Programmable Burst Length 4 */
+#define ETH_DMACRCR_RPBL_8PBL                         (0x00080000U)   /* Receive Programmable Burst Length 8 */
+#define ETH_DMACRCR_RPBL_16PBL                        (0x00100000U)   /* Receive Programmable Burst Length 16 */
+#define ETH_DMACRCR_RPBL_32PBL                        (0x00200000U)   /* Receive Programmable Burst Length 32 */
 #define ETH_DMACRCR_RBSZ_Pos                          (1U)
 #define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
 #define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */
@@ -11206,13 +11216,13 @@ typedef struct
 #define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk
 
 /*******************  Bit definition for DSI_TDCR register  ***************/
-#define DSI_TDCR_3DM                  ((uint32_t)0x00000003U)                  /*!< 3D Mode */
-#define DSI_TDCR_3DM0                 ((uint32_t)0x00000001U)
-#define DSI_TDCR_3DM1                 ((uint32_t)0x00000002U)
+#define DSI_TDCR_3DM                  (0x00000003U)                  /*!< 3D Mode */
+#define DSI_TDCR_3DM0                 (0x00000001U)
+#define DSI_TDCR_3DM1                 (0x00000002U)
 
-#define DSI_TDCR_3DF                  ((uint32_t)0x0000000CU)                  /*!< 3D Format */
-#define DSI_TDCR_3DF0                 ((uint32_t)0x00000004U)
-#define DSI_TDCR_3DF1                 ((uint32_t)0x00000008U)
+#define DSI_TDCR_3DF                  (0x0000000CU)                  /*!< 3D Format */
+#define DSI_TDCR_3DF0                 (0x00000004U)
+#define DSI_TDCR_3DF1                 (0x00000008U)
 
 #define DSI_TDCR_SVS_Pos              (4U)
 #define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)              /*!< 0x00000010 */
@@ -12382,13 +12392,13 @@ typedef struct
 #define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk
 
 /*******************  Bit definition for DSI_TDCCR register  **************/
-#define DSI_TDCCR_3DM                 ((uint32_t)0x00000003U)                  /*!< 3D Mode */
-#define DSI_TDCCR_3DM0                ((uint32_t)0x00000001U)
-#define DSI_TDCCR_3DM1                ((uint32_t)0x00000002U)
+#define DSI_TDCCR_3DM                 (0x00000003U)                  /*!< 3D Mode */
+#define DSI_TDCCR_3DM0                (0x00000001U)
+#define DSI_TDCCR_3DM1                (0x00000002U)
 
-#define DSI_TDCCR_3DF                 ((uint32_t)0x0000000CU)                  /*!< 3D Format */
-#define DSI_TDCCR_3DF0                ((uint32_t)0x00000004U)
-#define DSI_TDCCR_3DF1                ((uint32_t)0x00000008U)
+#define DSI_TDCCR_3DF                 (0x0000000CU)                  /*!< 3D Format */
+#define DSI_TDCCR_3DF0                (0x00000004U)
+#define DSI_TDCCR_3DF1                (0x00000008U)
 
 #define DSI_TDCCR_SVS_Pos             (4U)
 #define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)             /*!< 0x00000010 */
@@ -14107,11 +14117,15 @@ typedef struct
 /*
 * @brief FLASH Global Defines
 */
+#if defined(CORE_CM4)
+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */
+#else
 #define FLASH_SIZE_DATA_REGISTER             0x1FF1E880U
-#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_SIZE                           ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
                                              ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
                                              (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U)))  /* 2 MB   */
+#endif /* CORE_CM4 */
+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */
 #define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */
 #define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */
 #define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
@@ -14120,7 +14134,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -14130,6 +14144,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -14138,12 +14160,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -14930,7 +14946,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -17144,7 +17160,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -18554,7 +18570,7 @@ typedef struct
 #define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */
 
 
-#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */
+#define RCC_D1CFGR_HPRE_DIV1                   (0U)          /*!< AHB3 Clock not divided */
 #define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)
 #define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
 #define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */
@@ -18588,7 +18604,7 @@ typedef struct
 #define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */
+#define RCC_D1CFGR_D1PPRE_DIV1                 (0U)          /*!< APB3 clock not divided */
 #define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)
 #define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */
@@ -18610,7 +18626,7 @@ typedef struct
 #define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
 #define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
 
-#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */
+#define RCC_D1CFGR_D1CPRE_DIV1                 (0U)          /*!< Domain 1 Core clock not divided */
 #define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)
 #define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
 #define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */
@@ -18645,7 +18661,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
 #define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_D2CFGR_D2PPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)
 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -18667,7 +18683,7 @@ typedef struct
 #define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
 #define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_D2CFGR_D2PPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)
 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -18690,7 +18706,7 @@ typedef struct
 #define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
 #define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_D3CFGR_D3PPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)
 #define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -18710,7 +18726,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -22152,10 +22168,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -22601,12 +22617,13 @@ typedef struct
 #define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */
 #define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */
 #define QUADSPI_CR_FTHRES_Pos            (8U)
-#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */
-#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */
+#define QUADSPI_CR_FTHRES_Msk            (0x1FUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00001F00 */
+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[4:0] FIFO Level */
 #define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */
 #define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */
 #define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */
 #define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */
+#define QUADSPI_CR_FTHRES_4              (0x10UL << QUADSPI_CR_FTHRES_Pos)     /*!< 0x00001000 */
 #define QUADSPI_CR_TEIE_Pos              (16U)
 #define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */
 #define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */
@@ -22881,61 +22898,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -22953,60 +22970,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -23025,62 +23042,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -23098,59 +23115,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_CM4L_Pos            (0U)
@@ -23464,8 +23481,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -23742,8 +23759,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -23767,12 +23784,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -24012,8 +24029,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -24031,12 +24048,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -25145,7 +25162,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -25523,7 +25540,7 @@ typedef struct
 
 #define HRTIM_MCR_DACSYNC_Pos         (25U)
 #define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */
-#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */
+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC synchronization mask */
 #define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */
 #define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */
 
@@ -25732,7 +25749,7 @@ typedef struct
 
 #define HRTIM_TIMCR_DACSYNC_Pos       (25U)
 #define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */
-#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */
+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC synchronization mask */
 #define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */
 #define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */
 #define HRTIM_TIMCR_PREEN_Pos         (27U)
@@ -26619,6 +26636,7 @@ typedef struct
 #define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */
 #define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */
 
+/* Slave Timer A reset enable bits upon other slave timers events */
 #define HRTIM_RSTR_TIMBCMP1_Pos       (19U)
 #define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */
 #define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */
@@ -26659,6 +26677,170 @@ typedef struct
 #define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */
 #define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */
 
+/* Slave Timer B reset enable bits upon other slave timers events */
+#define HRTIM_RSTBR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTBR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTBR_TIMACMP1           HRTIM_RSTBR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTBR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTBR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTBR_TIMACMP2           HRTIM_RSTBR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTBR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTBR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTBR_TIMACMP4           HRTIM_RSTBR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTBR_TIMCCMP1_Pos       (22U)
+#define HRTIM_RSTBR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTBR_TIMCCMP1           HRTIM_RSTBR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTBR_TIMCCMP2_Pos       (23U)
+#define HRTIM_RSTBR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTBR_TIMCCMP2           HRTIM_RSTBR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTBR_TIMCCMP4_Pos       (24U)
+#define HRTIM_RSTBR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTBR_TIMCCMP4           HRTIM_RSTBR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTBR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTBR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTBR_TIMDCMP1           HRTIM_RSTBR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTBR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTBR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTBR_TIMDCMP2           HRTIM_RSTBR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTBR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTBR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTBR_TIMDCMP4           HRTIM_RSTBR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTBR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTBR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTBR_TIMECMP1           HRTIM_RSTBR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTBR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTBR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTBR_TIMECMP2           HRTIM_RSTBR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTBR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTBR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTBR_TIMECMP4           HRTIM_RSTBR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer C reset enable bits upon other slave timers events */
+#define HRTIM_RSTCR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTCR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTCR_TIMACMP1           HRTIM_RSTCR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTCR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTCR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTCR_TIMACMP2           HRTIM_RSTCR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTCR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTCR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTCR_TIMACMP4           HRTIM_RSTCR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTCR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTCR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTCR_TIMBCMP1           HRTIM_RSTCR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTCR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTCR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTCR_TIMBCMP2           HRTIM_RSTCR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTCR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTCR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTCR_TIMBCMP4           HRTIM_RSTCR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTCR_TIMDCMP1_Pos       (25U)
+#define HRTIM_RSTCR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTCR_TIMDCMP1           HRTIM_RSTCR_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTCR_TIMDCMP2_Pos       (26U)
+#define HRTIM_RSTCR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTCR_TIMDCMP2           HRTIM_RSTCR_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTCR_TIMDCMP4_Pos       (27U)
+#define HRTIM_RSTCR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTCR_TIMDCMP4           HRTIM_RSTCR_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
+#define HRTIM_RSTCR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTCR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTCR_TIMECMP1           HRTIM_RSTCR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTCR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTCR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTCR_TIMECMP2           HRTIM_RSTCR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTCR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTCR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTCR_TIMECMP4           HRTIM_RSTCR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer D reset enable bits upon other slave timers events */
+#define HRTIM_RSTDR_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTDR_TIMACMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTDR_TIMACMP1           HRTIM_RSTDR_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTDR_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTDR_TIMACMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTDR_TIMACMP2           HRTIM_RSTDR_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTDR_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTDR_TIMACMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTDR_TIMACMP4           HRTIM_RSTDR_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTDR_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTDR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTDR_TIMBCMP1           HRTIM_RSTDR_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTDR_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTDR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTDR_TIMBCMP2           HRTIM_RSTDR_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTDR_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTDR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTDR_TIMBCMP4           HRTIM_RSTDR_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTDR_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTDR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTDR_TIMCCMP1           HRTIM_RSTDR_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTDR_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTDR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTDR_TIMCCMP2           HRTIM_RSTDR_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTDR_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTDR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTDR_TIMCCMP4           HRTIM_RSTDR_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTDR_TIMECMP1_Pos       (28U)
+#define HRTIM_RSTDR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTDR_TIMECMP1           HRTIM_RSTDR_TIMECMP1_Msk                /*!< Timer E compare 1 */
+#define HRTIM_RSTDR_TIMECMP2_Pos       (29U)
+#define HRTIM_RSTDR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTDR_TIMECMP2           HRTIM_RSTDR_TIMECMP2_Msk                /*!< Timer E compare 2 */
+#define HRTIM_RSTDR_TIMECMP4_Pos       (30U)
+#define HRTIM_RSTDR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTDR_TIMECMP4           HRTIM_RSTDR_TIMECMP4_Msk                /*!< Timer E compare 4 */
+
+/* Slave Timer E reset enable bits upon other slave timers events */
+#define HRTIM_RSTER_TIMACMP1_Pos       (19U)
+#define HRTIM_RSTER_TIMACMP1_Msk       (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)     /*!< 0x00080000 */
+#define HRTIM_RSTER_TIMACMP1           HRTIM_RSTER_TIMACMP1_Msk                /*!< Timer A compare 1 */
+#define HRTIM_RSTER_TIMACMP2_Pos       (20U)
+#define HRTIM_RSTER_TIMACMP2_Msk       (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)     /*!< 0x00100000 */
+#define HRTIM_RSTER_TIMACMP2           HRTIM_RSTER_TIMACMP2_Msk                /*!< Timer A compare 2 */
+#define HRTIM_RSTER_TIMACMP4_Pos       (21U)
+#define HRTIM_RSTER_TIMACMP4_Msk       (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)     /*!< 0x00200000 */
+#define HRTIM_RSTER_TIMACMP4           HRTIM_RSTER_TIMACMP4_Msk                /*!< Timer A compare 4 */
+
+#define HRTIM_RSTER_TIMBCMP1_Pos       (22U)
+#define HRTIM_RSTER_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)     /*!< 0x00400000 */
+#define HRTIM_RSTER_TIMBCMP1           HRTIM_RSTER_TIMBCMP1_Msk                /*!< Timer B compare 1 */
+#define HRTIM_RSTER_TIMBCMP2_Pos       (23U)
+#define HRTIM_RSTER_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)     /*!< 0x00800000 */
+#define HRTIM_RSTER_TIMBCMP2           HRTIM_RSTER_TIMBCMP2_Msk                /*!< Timer B compare 2 */
+#define HRTIM_RSTER_TIMBCMP4_Pos       (24U)
+#define HRTIM_RSTER_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)     /*!< 0x01000000 */
+#define HRTIM_RSTER_TIMBCMP4           HRTIM_RSTER_TIMBCMP4_Msk                /*!< Timer B compare 4 */
+
+#define HRTIM_RSTER_TIMCCMP1_Pos       (25U)
+#define HRTIM_RSTER_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)     /*!< 0x02000000 */
+#define HRTIM_RSTER_TIMCCMP1           HRTIM_RSTER_TIMCCMP1_Msk                /*!< Timer C compare 1 */
+#define HRTIM_RSTER_TIMCCMP2_Pos       (26U)
+#define HRTIM_RSTER_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)     /*!< 0x04000000 */
+#define HRTIM_RSTER_TIMCCMP2           HRTIM_RSTER_TIMCCMP2_Msk                /*!< Timer C compare 2 */
+#define HRTIM_RSTER_TIMCCMP4_Pos       (27U)
+#define HRTIM_RSTER_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)     /*!< 0x08000000 */
+#define HRTIM_RSTER_TIMCCMP4           HRTIM_RSTER_TIMCCMP4_Msk                /*!< Timer C compare 4 */
+
+#define HRTIM_RSTER_TIMDCMP1_Pos       (28U)
+#define HRTIM_RSTER_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)     /*!< 0x10000000 */
+#define HRTIM_RSTER_TIMDCMP1           HRTIM_RSTER_TIMDCMP1_Msk                /*!< Timer D compare 1 */
+#define HRTIM_RSTER_TIMDCMP2_Pos       (29U)
+#define HRTIM_RSTER_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)     /*!< 0x20000000 */
+#define HRTIM_RSTER_TIMDCMP2           HRTIM_RSTER_TIMDCMP2_Msk                /*!< Timer D compare 2 */
+#define HRTIM_RSTER_TIMDCMP4_Pos       (30U)
+#define HRTIM_RSTER_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)     /*!< 0x40000000 */
+#define HRTIM_RSTER_TIMDCMP4           HRTIM_RSTER_TIMDCMP4_Msk                /*!< Timer D compare 4 */
+
 /**** Bit definition for Slave Timer Chopper register *************************/
 #define HRTIM_CHPR_CARFRQ_Pos         (0U)
 #define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */
@@ -28342,6 +28524,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -28367,7 +28552,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -28378,13 +28563,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -28454,6 +28647,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -28571,7 +28770,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -30179,7 +30378,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -30376,6 +30576,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -30386,6 +30587,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -30617,4 +30819,3 @@ typedef struct
 
 #endif /* STM32H757xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xx.h
index 98214a9969..998e8ddc56 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -209,13 +208,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -732,8 +731,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2288,7 +2287,6 @@ typedef struct
 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
-#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)
 
 /* GFXMMU virtual buffers base address */
 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
@@ -2596,6 +2594,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2645,6 +2652,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3895,7 +3905,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5852,10 +5862,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -8472,7 +8482,7 @@ typedef struct
 
 /*******************  Bit definition for EXTI_IMR3 register  *******************/
 #define EXTI_IMR3_IM_Pos           (0U)
-#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */
+#define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
 #define EXTI_IMR3_IM64_Pos         (0U)
 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
@@ -8619,7 +8629,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -8629,6 +8639,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -8637,12 +8655,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -9411,7 +9423,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -11301,7 +11313,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -12740,7 +12752,7 @@ typedef struct
 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
 
-#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */
+#define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
@@ -12774,7 +12786,7 @@ typedef struct
 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
 
-#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */
+#define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
@@ -12796,7 +12808,7 @@ typedef struct
 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
 
-#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */
+#define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
@@ -12831,7 +12843,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -12853,7 +12865,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -12876,7 +12888,7 @@ typedef struct
 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -12896,7 +12908,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -16565,10 +16577,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17048,61 +17060,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -17120,60 +17132,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -17192,62 +17204,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -17265,59 +17277,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -17597,8 +17609,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -17875,8 +17887,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -17900,12 +17912,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -18111,6 +18123,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -18145,8 +18169,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -18164,12 +18188,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -18655,9 +18679,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -18671,6 +18692,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -19770,7 +19796,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20168,6 +20194,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -20193,7 +20222,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -20204,13 +20233,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -20280,6 +20317,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -20397,7 +20440,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -22019,7 +22062,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -22216,6 +22260,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -22226,6 +22271,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -22529,4 +22575,3 @@ typedef struct
 
 #endif /* STM32H7A3xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xxq.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xxq.h
index 202ec04914..dad5eef9c3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xxq.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7a3xxq.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -210,13 +209,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -733,8 +732,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2289,7 +2288,6 @@ typedef struct
 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
-#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)
 
 /* GFXMMU virtual buffers base address */
 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
@@ -2597,6 +2595,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2646,6 +2653,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -3896,7 +3906,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5853,10 +5863,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -8473,7 +8483,7 @@ typedef struct
 
 /*******************  Bit definition for EXTI_IMR3 register  *******************/
 #define EXTI_IMR3_IM_Pos           (0U)
-#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */
+#define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
 #define EXTI_IMR3_IM64_Pos         (0U)
 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
@@ -8620,7 +8630,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -8630,6 +8640,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -8638,12 +8656,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -9412,7 +9424,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -11302,7 +11314,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -12752,7 +12764,7 @@ typedef struct
 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
 
-#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */
+#define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
@@ -12786,7 +12798,7 @@ typedef struct
 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
 
-#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */
+#define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
@@ -12808,7 +12820,7 @@ typedef struct
 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
 
-#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */
+#define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
@@ -12843,7 +12855,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -12865,7 +12877,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -12888,7 +12900,7 @@ typedef struct
 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -12908,7 +12920,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -16577,10 +16589,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17060,61 +17072,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -17132,60 +17144,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -17204,62 +17216,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -17277,59 +17289,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -17609,8 +17621,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -17887,8 +17899,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -17912,12 +17924,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -18123,6 +18135,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -18157,8 +18181,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -18176,12 +18200,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -18667,9 +18691,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -18683,6 +18704,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -19782,7 +19808,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20180,6 +20206,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -20205,7 +20234,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -20216,13 +20245,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -20292,6 +20329,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -20409,7 +20452,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -22031,7 +22074,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -22228,6 +22272,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -22238,6 +22283,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -22541,4 +22587,3 @@ typedef struct
 
 #endif /* STM32H7A3xxQ_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xx.h
index 790f0d82d2..29e03e60d6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -212,13 +211,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -735,8 +734,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2408,7 +2407,6 @@ typedef struct
 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
-#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)
 
 /* GFXMMU virtual buffers base address */
 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
@@ -2731,6 +2729,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2780,6 +2787,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4030,7 +4040,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5747,7 +5757,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5798,7 +5808,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6106,10 +6116,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -8726,7 +8736,7 @@ typedef struct
 
 /*******************  Bit definition for EXTI_IMR3 register  *******************/
 #define EXTI_IMR3_IM_Pos           (0U)
-#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */
+#define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
 #define EXTI_IMR3_IM64_Pos         (0U)
 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
@@ -8872,7 +8882,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -8882,6 +8892,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -8890,12 +8908,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -9658,7 +9670,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -11624,7 +11636,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -13184,7 +13196,7 @@ typedef struct
 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
 
-#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */
+#define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
@@ -13218,7 +13230,7 @@ typedef struct
 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
 
-#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */
+#define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
@@ -13240,7 +13252,7 @@ typedef struct
 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
 
-#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */
+#define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
@@ -13275,7 +13287,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -13297,7 +13309,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -13320,7 +13332,7 @@ typedef struct
 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -13340,7 +13352,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -17045,10 +17057,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17528,61 +17540,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -17600,60 +17612,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -17672,62 +17684,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -17745,59 +17757,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -18077,8 +18089,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -18355,8 +18367,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -18380,12 +18392,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -18591,6 +18603,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -18625,8 +18649,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -18644,12 +18668,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -19135,9 +19159,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -19151,6 +19172,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -20250,7 +20276,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20648,6 +20674,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -20673,7 +20702,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -20684,13 +20713,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -20760,6 +20797,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -20877,7 +20920,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -22503,7 +22546,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -22700,6 +22744,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -22710,6 +22755,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -23013,4 +23059,3 @@ typedef struct
 
 #endif /* STM32H7B0xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xxq.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xxq.h
index f21a96a22c..7b84cf6d1e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xxq.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b0xxq.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -213,13 +212,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -736,8 +735,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2409,7 +2408,6 @@ typedef struct
 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
-#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)
 
 /* GFXMMU virtual buffers base address */
 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
@@ -2732,6 +2730,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2781,6 +2788,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4031,7 +4041,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5748,7 +5758,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5799,7 +5809,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6107,10 +6117,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -8727,7 +8737,7 @@ typedef struct
 
 /*******************  Bit definition for EXTI_IMR3 register  *******************/
 #define EXTI_IMR3_IM_Pos           (0U)
-#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */
+#define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
 #define EXTI_IMR3_IM64_Pos         (0U)
 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
@@ -8873,7 +8883,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -8883,6 +8893,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -8891,12 +8909,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -9659,7 +9671,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -11625,7 +11637,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -13196,7 +13208,7 @@ typedef struct
 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
 
-#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */
+#define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
@@ -13230,7 +13242,7 @@ typedef struct
 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
 
-#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */
+#define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
@@ -13252,7 +13264,7 @@ typedef struct
 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
 
-#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */
+#define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
@@ -13287,7 +13299,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -13309,7 +13321,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -13332,7 +13344,7 @@ typedef struct
 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -13352,7 +13364,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -17057,10 +17069,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17540,61 +17552,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -17612,60 +17624,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -17684,62 +17696,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -17757,59 +17769,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -18089,8 +18101,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -18367,8 +18379,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -18392,12 +18404,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -18603,6 +18615,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -18637,8 +18661,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -18656,12 +18680,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -19147,9 +19171,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -19163,6 +19184,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -20262,7 +20288,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20660,6 +20686,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -20685,7 +20714,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -20696,13 +20725,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -20772,6 +20809,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -20889,7 +20932,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -22515,7 +22558,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -22712,6 +22756,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -22722,6 +22767,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -23025,4 +23071,3 @@ typedef struct
 
 #endif /* STM32H7B0xxQ_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xx.h
index 5da94b309a..6210aa57b8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xx.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -212,13 +211,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -735,8 +734,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2408,7 +2407,6 @@ typedef struct
 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
-#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)
 
 /* GFXMMU virtual buffers base address */
 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
@@ -2731,6 +2729,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2780,6 +2787,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4030,7 +4040,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5747,7 +5757,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5798,7 +5808,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6106,10 +6116,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -8726,7 +8736,7 @@ typedef struct
 
 /*******************  Bit definition for EXTI_IMR3 register  *******************/
 #define EXTI_IMR3_IM_Pos           (0U)
-#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */
+#define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
 #define EXTI_IMR3_IM64_Pos         (0U)
 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
@@ -8873,7 +8883,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -8883,6 +8893,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -8891,12 +8909,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -9665,7 +9677,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -11631,7 +11643,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -13191,7 +13203,7 @@ typedef struct
 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
 
-#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */
+#define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
@@ -13225,7 +13237,7 @@ typedef struct
 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
 
-#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */
+#define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
@@ -13247,7 +13259,7 @@ typedef struct
 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
 
-#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */
+#define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
@@ -13282,7 +13294,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -13304,7 +13316,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -13327,7 +13339,7 @@ typedef struct
 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -13347,7 +13359,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -17052,10 +17064,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17535,61 +17547,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -17607,60 +17619,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -17679,62 +17691,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -17752,59 +17764,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -18084,8 +18096,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -18362,8 +18374,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -18387,12 +18399,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -18598,6 +18610,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -18632,8 +18656,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -18651,12 +18675,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -19142,9 +19166,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -19158,6 +19179,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -20257,7 +20283,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20655,6 +20681,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -20680,7 +20709,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -20691,13 +20720,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -20767,6 +20804,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -20884,7 +20927,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -22510,7 +22553,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -22707,6 +22751,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -22717,6 +22762,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -23020,4 +23066,3 @@ typedef struct
 
 #endif /* STM32H7B3xx_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xxq.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xxq.h
index d1c015db87..1242559299 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xxq.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7b3xxq.h
@@ -12,13 +12,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -50,7 +49,7 @@ typedef enum
 {
 /******  Cortex-M Processor Exceptions Numbers *****************************************************************/
   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M Hard Fault Interrupt                                   */
   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */
   BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */
   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */
@@ -213,13 +212,13 @@ typedef enum
 /**
   * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
    */
-#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */
-#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */
-#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */
-#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1       /*!< FPU present                                   */
-#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */
-#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */
+#define __CM7_REV               0x0110U   /*!< Cortex-M7 revision r1p2                       */
+#define __MPU_PRESENT             1U       /*!< CM7 provides an MPU                           */
+#define __NVIC_PRIO_BITS          4U       /*!< CM7 uses 4 Bits for the Priority Levels       */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+#define __ICACHE_PRESENT          1U       /*!< CM7 instruction cache present                 */
+#define __DCACHE_PRESENT          1U       /*!< CM7 data cache present                        */
 #include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */
 
 /**
@@ -736,8 +735,8 @@ __IO uint32_t PR3;                 /*!< EXTI Pending register,
   * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
   *        with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
   *        Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
-  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
-  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
+  *           IMR1   in case of EXTI_D1 that is addressing CPU1 (Cortex-M7)
+  *           C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Cortex-M4)
   *        Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
   */
 
@@ -2409,7 +2408,6 @@ typedef struct
 #define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)
 #define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)
 #define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)
-#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)
 
 /* GFXMMU virtual buffers base address */
 #define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)
@@ -2732,6 +2730,15 @@ typedef struct
   * @{
   */
 
+  /** @addtogroup Hardware_Constant_Definition
+    * @{
+    */
+#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
+
+  /**
+    * @}
+    */
+
   /** @addtogroup Peripheral_Registers_Bits_Definition
   * @{
   */
@@ -2781,6 +2788,9 @@ typedef struct
 #define ADC_ISR_JQOVF_Pos                 (10U)
 #define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */
 #define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */
+#define ADC_ISR_LDORDY_Pos                (12U)
+#define ADC_ISR_LDORDY_Msk                (0x1UL << ADC_ISR_LDORDY_Pos)        /*!< 0x00001000 */
+#define ADC_ISR_LDORDY                    ADC_ISR_LDORDY_Msk                   /*!< ADC LDO output voltage ready bit */
 
 /********************  Bit definition for ADC_IER register  ********************/
 #define ADC_IER_ADRDYIE_Pos               (0U)
@@ -4031,7 +4041,7 @@ typedef struct
 #define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */
 #define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */
 
-#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */
+#define VREFBUF_CSR_VRS_OUT1        (0U)                     /*!<Voltage reference VREF_OUT1     */
 #define VREFBUF_CSR_VRS_OUT2_Pos    (4U)
 #define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */
 #define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */
@@ -5748,7 +5758,7 @@ typedef struct
 #define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */
 #define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */
-#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_TDES_ECB        (0U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)
 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
 #define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk
@@ -5799,7 +5809,7 @@ typedef struct
 #define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk
 #define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */
 #define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */
-#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)
+#define CRYP_CR_ALGOMODE_3               (0x00080000U)
 #define CRYP_CR_NPBLB_Pos                (20U)
 #define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */
 #define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk
@@ -6107,10 +6117,10 @@ typedef struct
 #define DCMI_CR_VSPOL_Pos          (7U)
 #define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */
 #define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk
-#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)
-#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)
-#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)
-#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)
+#define DCMI_CR_FCRC_0             (0x00000100U)
+#define DCMI_CR_FCRC_1             (0x00000200U)
+#define DCMI_CR_EDM_0              (0x00000400U)
+#define DCMI_CR_EDM_1              (0x00000800U)
 #define DCMI_CR_CRE_Pos            (12U)
 #define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */
 #define DCMI_CR_CRE                DCMI_CR_CRE_Msk
@@ -8727,7 +8737,7 @@ typedef struct
 
 /*******************  Bit definition for EXTI_IMR3 register  *******************/
 #define EXTI_IMR3_IM_Pos           (0U)
-#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */
+#define EXTI_IMR3_IM_Msk           (0x01A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x01A527FF */
 #define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */
 #define EXTI_IMR3_IM64_Pos         (0U)
 #define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */
@@ -8874,7 +8884,7 @@ typedef struct
 
 /*******************  Bits definition for FLASH_ACR register  **********************/
 #define FLASH_ACR_LATENCY_Pos                (0U)
-#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */
+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F: bit4 is kept only for legacy purpose */
 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */
 #define FLASH_ACR_LATENCY_0WS                (0x00000000UL)
 #define FLASH_ACR_LATENCY_1WS                (0x00000001UL)
@@ -8884,6 +8894,14 @@ typedef struct
 #define FLASH_ACR_LATENCY_5WS                (0x00000005UL)
 #define FLASH_ACR_LATENCY_6WS                (0x00000006UL)
 #define FLASH_ACR_LATENCY_7WS                (0x00000007UL)
+
+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
+
+/* Legacy FLASH Latency defines */
 #define FLASH_ACR_LATENCY_8WS                (0x00000008UL)
 #define FLASH_ACR_LATENCY_9WS                (0x00000009UL)
 #define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)
@@ -8892,12 +8910,6 @@ typedef struct
 #define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)
 #define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)
 #define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)
-#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)
-#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */
-#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */
-#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */
-#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */
-
 /*******************  Bits definition for FLASH_CR register  ***********************/
 #define FLASH_CR_LOCK_Pos                    (0U)
 #define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */
@@ -9666,7 +9678,7 @@ typedef struct
 #define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */
 #define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */
 #define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */
-#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */
+#define FMC_SDCMR_MODE_2           (0x4UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000004 */
 
 #define FMC_SDCMR_CTB2_Pos         (3U)
 #define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */
@@ -11632,7 +11644,7 @@ typedef struct
 /********************  Bit definition for SR register  ********************/
 #define JPEG_SR_IFTF_Pos                (1U)
 #define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */
-#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is below its threshold flag */
 #define JPEG_SR_IFNFF_Pos               (2U)
 #define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */
 #define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */
@@ -13203,7 +13215,7 @@ typedef struct
 #define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */
 #define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */
 
-#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */
+#define RCC_CDCFGR1_HPRE_DIV1                   (0U)                 /*!< AHB3 Clock not divided */
 #define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)
 #define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */
 #define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */
@@ -13237,7 +13249,7 @@ typedef struct
 #define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */
 #define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */
 
-#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */
+#define RCC_CDCFGR1_CDPPRE_DIV1                 (0U)                 /*!< APB3 clock not divided */
 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)
 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */
@@ -13259,7 +13271,7 @@ typedef struct
 #define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */
 #define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */
 
-#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */
+#define RCC_CDCFGR1_CDCPRE_DIV1                 (0U)                  /*!< Domain 1 Core clock not divided */
 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)
 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */
 #define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */
@@ -13294,7 +13306,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
 #define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
 
-#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */
+#define RCC_CDCFGR2_CDPPRE1_DIV1                (0U)          /*!< APB1 clock not divided */
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)
 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */
@@ -13316,7 +13328,7 @@ typedef struct
 #define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
 #define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
 
-#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */
+#define RCC_CDCFGR2_CDPPRE2_DIV1                (0U)          /*!< APB2 clock not divided */
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)
 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
 #define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */
@@ -13339,7 +13351,7 @@ typedef struct
 #define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
 #define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
 
-#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */
+#define RCC_SRDCFGR_SRDPPRE_DIV1                 (0U)          /*!< APB4 clock not divided */
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)
 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
 #define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */
@@ -13359,7 +13371,7 @@ typedef struct
 #define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
 #define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk
 
-#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */
+#define RCC_PLLCKSELR_PLLSRC_HSI               (0U)          /*!< HSI source clock selected */
 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)
 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
 #define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */
@@ -17064,10 +17076,10 @@ typedef struct
 #define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */
 
 /*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/
-#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */
+#define SDMMC_IDMABASE0_IDMABASE0        (0xFFFFFFFFU)                /*!< Buffer 0 memory base address */
 
 /*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/
-#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */
+#define SDMMC_IDMABASE1_IDMABASE1        (0xFFFFFFFFU)                /*!< Buffer 1 memory base address */
 
 /******************************************************************************/
 /*                                                                            */
@@ -17547,61 +17559,61 @@ typedef struct
 /**
   * @brief   EXTI0 configuration
   */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0U)                 /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                 /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                 /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                 /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                 /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000005U)                 /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000006U)                 /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000007U)                 /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI         (0x00000008U)                 /*!<PI[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PJ         (0x00000009U)                 /*!<PJ[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PK         (0x0000000AU)                 /*!<PK[0] pin */
 
 /**
   * @brief   EXTI1 configuration
   */
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0U)                 /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                 /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                 /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                 /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                 /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000050U)                 /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000060U)                 /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000070U)                 /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI         (0x00000080U)                 /*!<PI[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PJ         (0x00000090U)                 /*!<PJ[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PK         (0x000000A0U)                 /*!<PK[1] pin */
 /**
   * @brief   EXTI2 configuration
   */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0U)                 /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                 /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                 /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                 /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                 /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000500U)                 /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000600U)                 /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000700U)                 /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI         (0x00000800U)                 /*!<PI[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PJ         (0x00000900U)                 /*!<PJ[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PK         (0x00000A00U)                 /*!<PK[2] pin */
 
 /**
   * @brief   EXTI3 configuration
   */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0U)                 /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                 /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                 /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                 /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                 /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00005000U)                 /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00006000U)                 /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH         (0x00007000U)                 /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI         (0x00008000U)                 /*!<PI[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PJ         (0x00009000U)                 /*!<PJ[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PK         (0x0000A000U)                 /*!<PK[3] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
@@ -17619,60 +17631,60 @@ typedef struct
 /**
   * @brief   EXTI4 configuration
   */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0U)                 /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                 /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                 /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                 /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                 /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000005U)                 /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000006U)                 /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH         (0x00000007U)                 /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI         (0x00000008U)                 /*!<PI[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PJ         (0x00000009U)                 /*!<PJ[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PK         (0x0000000AU)                 /*!<PK[4] pin */
 /**
   * @brief   EXTI5 configuration
   */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0U)                 /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                 /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                 /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                 /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                 /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000050U)                 /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000060U)                 /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH         (0x00000070U)                 /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI         (0x00000080U)                 /*!<PI[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PJ         (0x00000090U)                 /*!<PJ[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PK         (0x000000A0U)                 /*!<PK[5] pin */
 /**
   * @brief   EXTI6 configuration
   */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0U)                 /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                 /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                 /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                 /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                 /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000500U)                 /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000600U)                 /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH         (0x00000700U)                 /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI         (0x00000800U)                 /*!<PI[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PJ         (0x00000900U)                 /*!<PJ[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PK         (0x00000A00U)                 /*!<PK[6] pin */
 
 /**
   * @brief   EXTI7 configuration
   */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0U)                 /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                 /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                 /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                 /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                 /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00005000U)                 /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00006000U)                 /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH         (0x00007000U)                 /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI         (0x00008000U)                 /*!<PI[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PJ         (0x00009000U)                 /*!<PJ[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PK         (0x0000A000U)                 /*!<PK[7] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
@@ -17691,62 +17703,62 @@ typedef struct
 /**
   * @brief   EXTI8 configuration
   */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0U)                 /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                 /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                 /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                 /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                 /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000005U)                 /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000006U)                 /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH         (0x00000007U)                 /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI         (0x00000008U)                 /*!<PI[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PJ         (0x00000009U)                 /*!<PJ[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PK         (0x0000000AU)                 /*!<PK[8] pin */
 
 /**
   * @brief   EXTI9 configuration
   */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0U)                 /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                 /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                 /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                 /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                 /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000050U)                 /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000060U)                 /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH         (0x00000070U)                 /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI         (0x00000080U)                 /*!<PI[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PJ         (0x00000090U)                 /*!<PJ[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PK         (0x000000A0U)                 /*!<PK[9] pin */
 
 /**
   * @brief   EXTI10 configuration
   */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0U)                 /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                 /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                 /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                 /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                 /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000500U)                 /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000600U)                 /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH        (0x00000700U)                 /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI        (0x00000800U)                 /*!<PI[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PJ        (0x00000900U)                 /*!<PJ[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PK        (0x00000A00U)                 /*!<PK[10] pin */
 
 /**
   * @brief   EXTI11 configuration
   */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0U)                 /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                 /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                 /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                 /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                 /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00005000U)                 /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00006000U)                 /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH        (0x00007000U)                 /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI        (0x00008000U)                 /*!<PI[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PJ        (0x00009000U)                 /*!<PJ[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PK        (0x0000A000U)                 /*!<PK[11] pin */
 
 /*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
@@ -17764,59 +17776,59 @@ typedef struct
 /**
   * @brief   EXTI12 configuration
   */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0U)                 /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                 /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                 /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                 /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                 /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000005U)                 /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000006U)                 /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH        (0x00000007U)                 /*!<PH[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PI        (0x00000008U)                 /*!<PI[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PJ        (0x00000009U)                 /*!<PJ[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PK        (0x0000000AU)                 /*!<PK[12] pin */
 /**
   * @brief   EXTI13 configuration
   */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0U)                 /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                 /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                 /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                 /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                 /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000050U)                 /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000060U)                 /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH        (0x00000070U)                 /*!<PH[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PI        (0x00000080U)                 /*!<PI[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PJ        (0x00000090U)                 /*!<PJ[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PK        (0x000000A0U)                 /*!<PK[13] pin */
 /**
   * @brief   EXTI14 configuration
   */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0U)                 /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                 /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                 /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                 /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                 /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000500U)                 /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000600U)                 /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH        (0x00000700U)                 /*!<PH[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PI        (0x00000800U)                 /*!<PI[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PJ        (0x00000900U)                 /*!<PJ[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PK        (0x00000A00U)                 /*!<PK[14] pin */
 /**
   * @brief   EXTI15 configuration
   */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0U)                 /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                 /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                 /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                 /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                 /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00005000U)                 /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00006000U)                 /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH        (0x00007000U)                 /*!<PH[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PI        (0x00008000U)                 /*!<PI[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PJ        (0x00009000U)                 /*!<PJ[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PK        (0x0000A000U)                 /*!<PK[15] pin */
 
 /******************  Bit definition for SYSCFG_CFGR register  ******************/
 #define SYSCFG_CFGR_PVDL_Pos            (2U)
@@ -18096,8 +18108,8 @@ typedef struct
 #define TIM_CR2_OIS5_Pos          (16U)
 #define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
 #define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS6_Pos          (17U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */
+#define TIM_CR2_OIS6_Pos          (18U)
+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
 #define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */
 
 #define TIM_CR2_MMS2_Pos          (20U)
@@ -18374,8 +18386,8 @@ typedef struct
 #define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
 
 #define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[3:0] bits (Output Compare 3 Mode) */
 #define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */
@@ -18399,12 +18411,12 @@ typedef struct
 #define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR2_OC4CE_Pos       (15U)
 #define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
@@ -18610,6 +18622,18 @@ typedef struct
 #define TIM_BDTR_BK2P_Pos         (25U)
 #define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
 #define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */
+#define TIM_BDTR_BKDSRM_Pos       (26U)
+#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
+#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break Disarm */
+#define TIM_BDTR_BK2DSRM_Pos      (27U)
+#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
+#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 Disarm */
+#define TIM_BDTR_BKBID_Pos        (28U)
+#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
+#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break Bidirectional */
+#define TIM_BDTR_BK2BID_Pos       (29U)
+#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
+#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 Bidirectional */
 
 /*******************  Bit definition for TIM_DCR register  ********************/
 #define TIM_DCR_DBA_Pos           (0U)
@@ -18644,8 +18668,8 @@ typedef struct
 #define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
 
 #define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
+#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00010070 */
+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
 #define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */
 #define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */
 #define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */
@@ -18663,12 +18687,12 @@ typedef struct
 #define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */
 
 #define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x01007000 */
+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[3:0] bits (Output Compare 4 Mode) */
 #define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */
 #define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */
 #define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */
+#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)              /*!< 0x01000000 */
 
 #define TIM_CCMR3_OC6CE_Pos       (15U)
 #define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
@@ -19154,9 +19178,6 @@ typedef struct
 #define OCTOSPI_DCR1_DLYBYP_Pos        (3U)
 #define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */
 #define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */
-#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
-#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
-#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
 #define OCTOSPI_DCR1_CSHT_Pos          (8U)
 #define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */
 #define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */
@@ -19170,6 +19191,11 @@ typedef struct
 #define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */
 #define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */
 
+/* Legacy define */
+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)
+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */
+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */
+
 /****************  Bit definition for OCTOSPI_DCR2 register  ******************/
 #define OCTOSPI_DCR2_PRESCALER_Pos     (0U)
 #define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */
@@ -20269,7 +20295,7 @@ typedef struct
 #define SWPMI_RFL_RFL_Pos        (0U)
 #define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */
 #define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */
-#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
+#define SWPMI_RFL_RFL_0_1        (0x00000003U)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
 
 /*******************  Bit definition for SWPMI_TDR register  ********************/
 #define SWPMI_TDR_TD_Pos         (0U)
@@ -20667,6 +20693,9 @@ typedef struct
 #define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)
 #define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
 #define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */
+#define USB_OTG_GOTGCTL_CURMOD_Pos               (21U)
+#define USB_OTG_GOTGCTL_CURMOD_Msk               (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
+#define USB_OTG_GOTGCTL_CURMOD                   USB_OTG_GOTGCTL_CURMOD_Msk    /*!< Current mode of operation */
 
 /********************  Bit definition forUSB_OTG_HCFG register  ********************/
 
@@ -20692,7 +20721,7 @@ typedef struct
 
 #define USB_OTG_DCFG_DAD_Pos                     (4U)
 #define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk             /*!< Device address */
 #define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
 #define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
 #define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
@@ -20703,13 +20732,21 @@ typedef struct
 
 #define USB_OTG_DCFG_PFIVL_Pos                   (11U)
 #define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk            /*!< Periodic (micro)frame interval */
 #define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
 
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk            /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk            /*!< Erratic error interrupt mask */
+
 #define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)
 #define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk            /*!< Periodic scheduling interval */
 #define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
 #define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
 
@@ -20779,6 +20816,12 @@ typedef struct
 #define USB_OTG_DCTL_POPRGDNE_Pos                (11U)
 #define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
 #define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+#define USB_OTG_DCTL_ENCONTONBNA_Pos             (17U)
+#define USB_OTG_DCTL_ENCONTONBNA_Msk             (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
+#define USB_OTG_DCTL_ENCONTONBNA                 USB_OTG_DCTL_ENCONTONBNA_Msk  /*!< Enable continue on BNA */
+#define USB_OTG_DCTL_DSBESLRJCT_Pos              (18U)
+#define USB_OTG_DCTL_DSBESLRJCT_Msk              (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
+#define USB_OTG_DCTL_DSBESLRJCT                  USB_OTG_DCTL_DSBESLRJCT_Msk  /*!< Deep sleep BESL reject */
 
 /********************  Bit definition forUSB_OTG_HFIR register  ********************/
 #define USB_OTG_HFIR_FRIVL_Pos                   (0U)
@@ -20896,7 +20939,7 @@ typedef struct
 #define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
 #define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)
 #define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
 
 /********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/
 #define USB_OTG_GRSTCTL_CSRST_Pos                (0U)
@@ -22522,7 +22565,8 @@ typedef struct
                                            ((INSTANCE) == TIM4)   || \
                                            ((INSTANCE) == TIM5)   || \
                                            ((INSTANCE) == TIM8)   || \
-                                           ((INSTANCE) == TIM12))
+                                           ((INSTANCE) == TIM12)  || \
+                                           ((INSTANCE) == TIM15))
 
 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
@@ -22719,6 +22763,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
@@ -22729,6 +22774,7 @@ typedef struct
    ((INSTANCE) == TIM4)    || \
    ((INSTANCE) == TIM5)    || \
    ((INSTANCE) == TIM8)    || \
+   ((INSTANCE) == TIM12)   || \
    ((INSTANCE) == TIM15))
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
@@ -23032,4 +23078,3 @@ typedef struct
 
 #endif /* STM32H7B3xxQ_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h
index 4f3c612417..32997fe359 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h7xx.h
@@ -16,13 +16,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -59,7 +58,7 @@
   */
 
 #if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \
-    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \
+    !defined (STM32H745xx) && !defined (STM32H745xG)  && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H747xG)&& !defined (STM32H757xx) && \
     !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ) && \
     !defined (STM32H735xx) && !defined (STM32H733xx)  && !defined (STM32H730xx) && !defined (STM32H730xxQ)  && !defined (STM32H725xx) && !defined (STM32H723xx)
   /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
@@ -67,10 +66,13 @@
   /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
   /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */
   /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
+  /* #define STM32H747xG */   /*!< STM32H747AG, STM32H747IG, STM32H747BG, STM32H747XG */
   /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
   /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */
+  /* #define STM32H745xG */   /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices  */
   /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */
-  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
+  /* #define STM32H7B0xx */   /*!< STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx Devices */
+  /* #define STM32H7B0xxQ */  /*!< STM32H7B0ABIxQ, STM32H7B0IBKxQ Devices */
   /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
   /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
   /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
@@ -101,11 +103,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.10.0
+  * @brief CMSIS Device version number V1.10.4
   */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x0A) /*!< [23:16] sub1 version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x04) /*!< [15:8]  sub2 version */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN     << 24)\
                                       |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
@@ -116,6 +118,12 @@
   * @}
   */
 
+// MBED: The CMake scripts always define __FPU_PRESENT, but the MCU CMSIS headers below also define it.
+// So, undef it here to prevent multiple definition warning.
+#ifdef __FPU_PRESENT
+#undef __FPU_PRESENT
+#endif
+
 /** @addtogroup Device_Included
   * @{
   */
@@ -130,10 +138,14 @@
   #include "stm32h742xx.h"
 #elif defined(STM32H745xx)
   #include "stm32h745xx.h"
+#elif defined(STM32H745xG)
+  #include "stm32h745xg.h"
 #elif defined(STM32H755xx)
   #include "stm32h755xx.h"
 #elif defined(STM32H747xx)
   #include "stm32h747xx.h"
+#elif defined(STM32H747xG)
+  #include "stm32h747xg.h"
 #elif defined(STM32H757xx)
   #include "stm32h757xx.h"
 #elif defined(STM32H7B0xx)
@@ -214,6 +226,60 @@ typedef enum
 
 #define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
 
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
 
 /**
   * @}
@@ -240,4 +306,3 @@ typedef enum
 
 
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/system_stm32h7xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/system_stm32h7xx.h
index 34f8495ba5..e228ef740f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/system_stm32h7xx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/system_stm32h7xx.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -102,4 +101,3 @@ extern void SystemCoreClockUpdate(void);
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMakeLists.txt
index f914909125..7ef5158145 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMakeLists.txt
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMakeLists.txt
@@ -26,8 +26,11 @@ target_sources(mbed-stm32h7cube-fw
         STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c
         STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c
         STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c
-        STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c
-        STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c
+
+		# Temporary: using legacy Ethernet driver for now
+        STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth.c
+        STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex.c
+
         STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c
         STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c
         STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c
@@ -124,8 +127,6 @@ target_sources(mbed-stm32h7cube-fw
         STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c
         STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c
         STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c
-        system_stm32h7xx_dualcore_boot_cm4_cm7.c
-        system_stm32h7xx_singlecore.c
 )
 
 target_include_directories(mbed-stm32h7cube-fw
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/LICENSE.md b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/LICENSE.md
new file mode 100644
index 0000000000..e94b88c387
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/LICENSE.md
@@ -0,0 +1,27 @@
+Copyright 2017 STMicroelectronics.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors
+may be used to endorse or promote products derived from this software without
+specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32_hal_legacy.h
index 93a925df87..6e2d2d276d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32_hal_legacy.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32_hal_legacy.h
@@ -7,13 +7,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -38,6 +37,12 @@ extern "C" {
 #define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
 #define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
 #define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+#if defined(STM32H7) || defined(STM32MP1)
+#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
+#endif /* STM32H7 || STM32MP1 */
 /**
   * @}
   */
@@ -97,6 +102,16 @@ extern "C" {
 #if defined(STM32H7)
 #define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
 #endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define ADC_CHANNEL_VCORE               ADC_CHANNEL_VDDCORE
+#endif /* STM32H5 */
 /**
   * @}
   */
@@ -124,7 +139,8 @@ extern "C" {
 #define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
 #define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
 #if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM 
+                                                                       input 1 for COMP1, LPTIM input 2 for COMP2 */
 #endif
 #define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
 #if defined(STM32F373xC) || defined(STM32F378xx)
@@ -198,6 +214,11 @@ extern "C" {
 #endif
 
 #endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
 /**
   * @}
   */
@@ -206,6 +227,25 @@ extern "C" {
   * @{
   */
 #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
+#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
+#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#if defined(STM32H5) || defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for 
+                                                                          inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for 
+                                                                          inter STM32 series compatibility */
+#endif
 /**
   * @}
   */
@@ -235,12 +275,25 @@ extern "C" {
 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
 
-#if defined(STM32G4) || defined(STM32H7)
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
 #define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
 #define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
 #endif
 
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32H5)
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM2_OUT       DAC_TRIGGER_LPTIM2_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
+    defined(STM32F4) || defined(STM32G4)
 #define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
 #define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
 #endif
@@ -305,7 +358,8 @@ extern "C" {
 #define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
 
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
+    defined(STM32L4S7xx) || defined(STM32L4S9xx)
 #define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
 #endif
 
@@ -383,7 +437,9 @@ extern "C" {
 
 #endif /* STM32H7 */
 
-
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
 /**
   * @}
   */
@@ -463,7 +519,7 @@ extern "C" {
 #define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
 #define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
 #define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-#if defined(STM32G0)
+#if defined(STM32G0) || defined(STM32C0)
 #define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
 #define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
 #else
@@ -471,15 +527,37 @@ extern "C" {
 #define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
 #endif
 #if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
+#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
 #endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST           OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE          OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE      OB_SRAM_RST_NOT_ERASE
+#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL             OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_USER_nBOOT1                OB_USER_NBOOT1
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#endif /* STM32U0 */
 
 /**
   * @}
@@ -522,6 +600,107 @@ extern "C" {
 #define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
 #define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
 #endif /* STM32G4 */
+
+#if defined(STM32H5)
+#define SYSCFG_IT_FPU_IOC         SBS_IT_FPU_IOC
+#define SYSCFG_IT_FPU_DZC         SBS_IT_FPU_DZC
+#define SYSCFG_IT_FPU_UFC         SBS_IT_FPU_UFC
+#define SYSCFG_IT_FPU_OFC         SBS_IT_FPU_OFC
+#define SYSCFG_IT_FPU_IDC         SBS_IT_FPU_IDC
+#define SYSCFG_IT_FPU_IXC         SBS_IT_FPU_IXC
+
+#define SYSCFG_BREAK_FLASH_ECC    SBS_BREAK_FLASH_ECC
+#define SYSCFG_BREAK_PVD          SBS_BREAK_PVD
+#define SYSCFG_BREAK_SRAM_ECC     SBS_BREAK_SRAM_ECC
+#define SYSCFG_BREAK_LOCKUP       SBS_BREAK_LOCKUP
+
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_VOLTAGE_SCALE0
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_VOLTAGE_SCALE1
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_VOLTAGE_SCALE2
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_VOLTAGE_SCALE3
+
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   VREFBUF_HIGH_IMPEDANCE_DISABLE
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_HIGH_IMPEDANCE_ENABLE
+
+#define SYSCFG_FASTMODEPLUS_PB6   SBS_FASTMODEPLUS_PB6
+#define SYSCFG_FASTMODEPLUS_PB7   SBS_FASTMODEPLUS_PB7
+#define SYSCFG_FASTMODEPLUS_PB8   SBS_FASTMODEPLUS_PB8
+#define SYSCFG_FASTMODEPLUS_PB9   SBS_FASTMODEPLUS_PB9
+
+#define SYSCFG_ETH_MII   SBS_ETH_MII
+#define SYSCFG_ETH_RMII  SBS_ETH_RMII
+#define IS_SYSCFG_ETHERNET_CONFIG  IS_SBS_ETHERNET_CONFIG
+
+#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE   SBS_MEMORIES_ERASE_FLAG_IPMEE
+#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR    SBS_MEMORIES_ERASE_FLAG_MCLR
+#define IS_SYSCFG_MEMORIES_ERASE_FLAG      IS_SBS_MEMORIES_ERASE_FLAG
+
+#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
+
+#define SYSCFG_MPU_NSEC   SBS_MPU_NSEC
+#define SYSCFG_VTOR_NSEC  SBS_VTOR_NSEC
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define SYSCFG_SAU              SBS_SAU
+#define SYSCFG_MPU_SEC          SBS_MPU_SEC
+#define SYSCFG_VTOR_AIRCR_SEC   SBS_VTOR_AIRCR_SEC
+#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
+#else
+#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
+#endif /* __ARM_FEATURE_CMSE */
+
+#define SYSCFG_CLK      SBS_CLK
+#define SYSCFG_CLASSB   SBS_CLASSB
+#define SYSCFG_FPU      SBS_FPU
+#define SYSCFG_ALL      SBS_ALL
+
+#define SYSCFG_SEC      SBS_SEC
+#define SYSCFG_NSEC     SBS_NSEC
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE   __HAL_SBS_FPU_INTERRUPT_ENABLE
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE  __HAL_SBS_FPU_INTERRUPT_DISABLE
+
+#define __HAL_SYSCFG_BREAK_ECC_LOCK        __HAL_SBS_BREAK_ECC_LOCK
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK     __HAL_SBS_BREAK_LOCKUP_LOCK
+#define __HAL_SYSCFG_BREAK_PVD_LOCK        __HAL_SBS_BREAK_PVD_LOCK
+#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK   __HAL_SBS_BREAK_SRAM_ECC_LOCK
+
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE   __HAL_SBS_FASTMODEPLUS_ENABLE
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE  __HAL_SBS_FASTMODEPLUS_DISABLE
+
+#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS    __HAL_SBS_GET_MEMORIES_ERASE_STATUS
+#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS  __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
+
+#define IS_SYSCFG_FPU_INTERRUPT    IS_SBS_FPU_INTERRUPT
+#define IS_SYSCFG_BREAK_CONFIG     IS_SBS_BREAK_CONFIG
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE     IS_VREFBUF_VOLTAGE_SCALE
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE    IS_VREFBUF_HIGH_IMPEDANCE
+#define IS_SYSCFG_VREFBUF_TRIMMING  IS_VREFBUF_TRIMMING
+#define IS_SYSCFG_FASTMODEPLUS      IS_SBS_FASTMODEPLUS
+#define IS_SYSCFG_ITEMS_ATTRIBUTES  IS_SBS_ITEMS_ATTRIBUTES
+#define IS_SYSCFG_ATTRIBUTES        IS_SBS_ATTRIBUTES
+#define IS_SYSCFG_LOCK_ITEMS        IS_SBS_LOCK_ITEMS
+
+#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig   HAL_VREFBUF_VoltageScalingConfig
+#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig    HAL_VREFBUF_HighImpedanceConfig
+#define HAL_SYSCFG_VREFBUF_TrimmingConfig         HAL_VREFBUF_TrimmingConfig
+#define HAL_SYSCFG_EnableVREFBUF                  HAL_EnableVREFBUF
+#define HAL_SYSCFG_DisableVREFBUF                 HAL_DisableVREFBUF
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SBS_EnableIOAnalogSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SBS_DisableIOAnalogSwitchBooster
+#define HAL_SYSCFG_ETHInterfaceSelect             HAL_SBS_ETHInterfaceSelect
+
+#define HAL_SYSCFG_Lock     HAL_SBS_Lock
+#define HAL_SYSCFG_GetLock  HAL_SBS_GetLock
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+#define HAL_SYSCFG_ConfigAttributes     HAL_SBS_ConfigAttributes
+#define HAL_SYSCFG_GetConfigAttributes  HAL_SBS_GetConfigAttributes
+#endif /* __ARM_FEATURE_CMSE */
+
+#endif /* STM32H5 */
+
+
 /**
   * @}
   */
@@ -589,19 +768,21 @@ extern "C" {
 #define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
 #define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
 #define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
+         STM32H757xx */
 #endif /* STM32H7 */
 
 #define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
 #define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
 
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
+    defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
 #define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
 #define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
 #define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
 #define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
 
 #if defined(STM32L1)
 #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
@@ -617,6 +798,42 @@ extern "C" {
 #endif /* STM32F0 || STM32F3 || STM32F1 */
 
 #define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+
+#if defined(STM32U5) || defined(STM32H5)
+#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 || STM32H5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC                      GTZC_PERIPH_LTDCUSB
+#endif /* STM32U5 */
+#if defined(STM32H5)
+#define GTZC_PERIPH_DAC12                     GTZC_PERIPH_DAC1
+#define GTZC_PERIPH_ADC12                     GTZC_PERIPH_ADC
+#define GTZC_PERIPH_USBFS                     GTZC_PERIPH_USB
+#endif /* STM32H5 */
+#if defined(STM32H5) || defined(STM32U5)
+#define GTZC_MCPBB_NB_VCTR_REG_MAX            GTZC_MPCBB_NB_VCTR_REG_MAX
+#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX        GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
+#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED        GTZC_MPCBB_SUPERBLOCK_UNLOCKED
+#define GTZC_MCPBB_SUPERBLOCK_LOCKED          GTZC_MPCBB_SUPERBLOCK_LOCKED
+#define GTZC_MCPBB_BLOCK_NSEC                 GTZC_MPCBB_BLOCK_NSEC
+#define GTZC_MCPBB_BLOCK_SEC                  GTZC_MPCBB_BLOCK_SEC
+#define GTZC_MCPBB_BLOCK_NPRIV                GTZC_MPCBB_BLOCK_NPRIV
+#define GTZC_MCPBB_BLOCK_PRIV                 GTZC_MPCBB_BLOCK_PRIV
+#define GTZC_MCPBB_LOCK_OFF                   GTZC_MPCBB_LOCK_OFF
+#define GTZC_MCPBB_LOCK_ON                    GTZC_MPCBB_LOCK_ON
+#endif /* STM32H5 || STM32U5 */
 /**
   * @}
   */
@@ -797,7 +1014,8 @@ extern "C" {
 #define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
 #define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
 #define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
+    defined(STM32L1) || defined(STM32F7)
 #define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
 #define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
 #define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
@@ -854,6 +1072,20 @@ extern "C" {
 #define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
 #define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
 
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
+/**
+  * @}
+  */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL    0x00000000U
+#endif /* STM32U5 */
 /**
   * @}
   */
@@ -921,7 +1153,7 @@ extern "C" {
 #define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
 #define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
 
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
 #define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
 #define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
 #endif
@@ -1005,8 +1237,8 @@ extern "C" {
 #define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
 
 #define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8   RTC_TIMESTAMPPIN_POS1
 #define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
 
 #define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
@@ -1017,15 +1249,42 @@ extern "C" {
 #define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
 #define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
 
+#if defined(STM32H5) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_NONE        TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM    TAMP_DEVICESECRETS_ERASE_BKPSRAM
+#endif /* STM32H5 || STM32H7RS */
+
+#if defined(STM32WBA)
+#define TAMP_SECRETDEVICE_ERASE_NONE            TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_SRAM2           TAMP_DEVICESECRETS_ERASE_SRAM2
+#define TAMP_SECRETDEVICE_ERASE_RHUK            TAMP_DEVICESECRETS_ERASE_RHUK
+#define TAMP_SECRETDEVICE_ERASE_ICACHE          TAMP_DEVICESECRETS_ERASE_ICACHE
+#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH   TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
+#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM        TAMP_DEVICESECRETS_ERASE_PKA_SRAM
+#define TAMP_SECRETDEVICE_ERASE_ALL             TAMP_DEVICESECRETS_ERASE_ALL
+#endif /* STM32WBA */
+
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define TAMP_SECRETDEVICE_ERASE_DISABLE     TAMP_DEVICESECRETS_ERASE_NONE
+#define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
 #if defined(STM32H7)
 #define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
 #define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
 
+#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
 #define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
 #define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
 #define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
-#endif /* STM32H7 */
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 || STM32L0 */
 
 /**
   * @}
@@ -1192,6 +1451,10 @@ extern "C" {
 #define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
 #endif
 
+#if defined(STM32U5)
+#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
+#endif
 /**
   * @}
   */
@@ -1301,30 +1564,40 @@ extern "C" {
 #define ETH_MMCRFAECR          0x00000198U
 #define ETH_MMCRGUFCR          0x000001C4U
 
-#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_TXFIFO_FULL                           0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                           0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to 
+                                                                      the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from 
+                                                                      MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                        0x00300000U  /* Tx FIFO read status: Writing the received TxStatus
+                                                                      or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status 
+                                                                   of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and 
+                                                             transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input 
+                                                                      frame for transmission */
 #define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
 #define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control 
+                                                              de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control 
+                                                              activate threshold */
 #define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
 #if defined(STM32F1)
 #else
 #define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
 #define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status 
+                                                             (or time-stamp) */
 #endif
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and 
+                                                              status */
 #define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
 #define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
@@ -1332,6 +1605,8 @@ extern "C" {
 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
 
+#define ETH_TxPacketConfig        ETH_TxPacketConfigTypeDef   /* Transmit Packet Configuration structure definition */
+
 /**
   * @}
   */
@@ -1380,6 +1655,20 @@ extern "C" {
   */
 #endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
 
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+                                                                        for compatibility with legacy code */
+/**
+  * @}
+  */
+
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
+
 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -1398,6 +1687,29 @@ extern "C" {
   * @}
   */
 
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
+/**
+  *
+  * @}
+  */
+#endif /* STM32F2 */
 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
   * @{
   */
@@ -1458,7 +1770,8 @@ extern "C" {
 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
-                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
+                                             HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
 #define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
 #if defined(STM32L0)
@@ -1467,8 +1780,10 @@ extern "C" {
 #endif
 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
-                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : \
+                                             HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
+    defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
 #define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
 #define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
 #define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
@@ -1502,16 +1817,21 @@ extern "C" {
 #define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
 #define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
 
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
-                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
+                                                                HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
+                                                                HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
 
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
+    defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
+    defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
 #define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
 #define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
 #define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
 #define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
+          STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
+    defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
 #define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
 #define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
@@ -1585,10 +1905,111 @@ extern "C" {
 
 #define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
 
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
+
+#define PWR_SRAM6_PAGE1_STOP_RETENTION                PWR_SRAM6_PAGE1_STOP
+#define PWR_SRAM6_PAGE2_STOP_RETENTION                PWR_SRAM6_PAGE2_STOP
+#define PWR_SRAM6_PAGE3_STOP_RETENTION                PWR_SRAM6_PAGE3_STOP
+#define PWR_SRAM6_PAGE4_STOP_RETENTION                PWR_SRAM6_PAGE4_STOP
+#define PWR_SRAM6_PAGE5_STOP_RETENTION                PWR_SRAM6_PAGE5_STOP
+#define PWR_SRAM6_PAGE6_STOP_RETENTION                PWR_SRAM6_PAGE6_STOP
+#define PWR_SRAM6_PAGE7_STOP_RETENTION                PWR_SRAM6_PAGE7_STOP
+#define PWR_SRAM6_PAGE8_STOP_RETENTION                PWR_SRAM6_PAGE8_STOP
+#define PWR_SRAM6_FULL_STOP_RETENTION                 PWR_SRAM6_FULL_STOP
+
+
+#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
+#define PWR_JPEGRAM_FULL_STOP_RETENTION               PWR_JPEGRAM_FULL_STOP
+
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
+#define PWR_SRAM6_FULL_RUN_RETENTION                  PWR_SRAM6_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
+#endif
+
 /**
   * @}
  */
 
+/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
+#define HAL_RTCEx_SetBoothardwareKey            HAL_RTCEx_LockBootHardwareKey
+#define HAL_RTCEx_BKUPBlock_Enable              HAL_RTCEx_BKUPBlock
+#define HAL_RTCEx_BKUPBlock_Disable             HAL_RTCEx_BKUPUnblock
+#define HAL_RTCEx_Erase_SecretDev_Conf          HAL_RTCEx_ConfigEraseDeviceSecrets
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
+
+/**
+  * @}
+  */
+
 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
   * @{
   */
@@ -1614,7 +2035,8 @@ extern "C" {
 #define HAL_TIM_DMAError                                TIM_DMAError
 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
+    defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
 #define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
 #define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
 #define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
@@ -1871,7 +2293,8 @@ extern "C" {
 #define COMP_STOP                                        __HAL_COMP_DISABLE
 #define COMP_LOCK                                        __HAL_COMP_LOCK
 
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
+    defined(STM32F334x8) || defined(STM32F328xx)
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
                                                           __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
@@ -1896,8 +2319,8 @@ extern "C" {
 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
                                                           __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -1930,8 +2353,8 @@ extern "C" {
                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
                                                           __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
                                                           ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -1988,8 +2411,8 @@ extern "C" {
                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
                                                           ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
                                                           __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2006,7 +2429,7 @@ extern "C" {
                                                           __HAL_COMP_COMP2_EXTI_GET_FLAG())
 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
                                                           __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
+#endif
 #else
 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
                                                           __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2043,8 +2466,10 @@ extern "C" {
 /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
   * @{
   */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is 
+                                                  done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is 
+                                                  done into HAL_COMP_Init() */
 /**
   * @}
   */
@@ -2203,7 +2628,9 @@ extern "C" {
 #define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
+                                                                      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+                                                                    } while(0)
 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
@@ -2212,8 +2639,12 @@ extern "C" {
 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
+                                                                      HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
+                                                                    } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
+                                                                      HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
+                                                                    } while(0)
 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
 #define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
@@ -2249,8 +2680,8 @@ extern "C" {
 #define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
 
 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
-                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
+                                        HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
 
 #define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
 #define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
@@ -2754,6 +3185,11 @@ extern "C" {
 
 #define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
 #define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define  RCC_SPI4CLKSOURCE_D2PCLK1       RCC_SPI4CLKSOURCE_D2PCLK2
+#define  RCC_SPI5CLKSOURCE_D2PCLK1       RCC_SPI5CLKSOURCE_D2PCLK2
+#define  RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_D2PCLK2
+#define  RCC_SPI45CLKSOURCE_CDPCLK1      RCC_SPI45CLKSOURCE_CDPCLK2
+#define  RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_PCLK2
 #endif
 
 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3218,7 +3654,12 @@ extern "C" {
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR   RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+    defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
 #define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
 #else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
@@ -3320,8 +3761,10 @@ extern "C" {
 #define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
 #define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
 #define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
 #define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
 #define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
 
 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3330,6 +3773,124 @@ extern "C" {
 #define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
 #define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
 #define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL                        RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL                        RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE             __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE            __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED         __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED        __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET            __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET          __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE       __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE      __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE            __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE             __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE            __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG             __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE                 IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+#if defined(STM32H5)
+#define __HAL_RCC_PLLFRACN_ENABLE       __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE      __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG       __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE           IS_RCC_PLL_FRACN_VALUE
+
+#define RCC_PLLSOURCE_NONE              RCC_PLL1_SOURCE_NONE
+#define RCC_PLLSOURCE_HSI               RCC_PLL1_SOURCE_HSI
+#define RCC_PLLSOURCE_CSI               RCC_PLL1_SOURCE_CSI
+#define RCC_PLLSOURCE_HSE               RCC_PLL1_SOURCE_HSE
+#define RCC_PLLVCIRANGE_0               RCC_PLL1_VCIRANGE_0
+#define RCC_PLLVCIRANGE_1               RCC_PLL1_VCIRANGE_1
+#define RCC_PLLVCIRANGE_2               RCC_PLL1_VCIRANGE_2
+#define RCC_PLLVCIRANGE_3               RCC_PLL1_VCIRANGE_3
+#define RCC_PLL1VCOWIDE                 RCC_PLL1_VCORANGE_WIDE
+#define RCC_PLL1VCOMEDIUM               RCC_PLL1_VCORANGE_MEDIUM
+
+#define IS_RCC_PLLSOURCE                IS_RCC_PLL1_SOURCE
+#define IS_RCC_PLLRGE_VALUE             IS_RCC_PLL1_VCIRGE_VALUE
+#define IS_RCC_PLLVCORGE_VALUE          IS_RCC_PLL1_VCORGE_VALUE
+#define IS_RCC_PLLCLOCKOUT_VALUE        IS_RCC_PLL1_CLOCKOUT_VALUE
+#define IS_RCC_PLL_FRACN_VALUE          IS_RCC_PLL1_FRACN_VALUE
+#define IS_RCC_PLLM_VALUE               IS_RCC_PLL1_DIVM_VALUE
+#define IS_RCC_PLLN_VALUE               IS_RCC_PLL1_MULN_VALUE
+#define IS_RCC_PLLP_VALUE               IS_RCC_PLL1_DIVP_VALUE
+#define IS_RCC_PLLQ_VALUE               IS_RCC_PLL1_DIVQ_VALUE
+#define IS_RCC_PLLR_VALUE               IS_RCC_PLL1_DIVR_VALUE
+
+#define __HAL_RCC_PLL_ENABLE            __HAL_RCC_PLL1_ENABLE
+#define __HAL_RCC_PLL_DISABLE           __HAL_RCC_PLL1_DISABLE
+#define __HAL_RCC_PLL_FRACN_ENABLE      __HAL_RCC_PLL1_FRACN_ENABLE
+#define __HAL_RCC_PLL_FRACN_DISABLE     __HAL_RCC_PLL1_FRACN_DISABLE
+#define __HAL_RCC_PLL_CONFIG            __HAL_RCC_PLL1_CONFIG
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG  __HAL_RCC_PLL1_PLLSOURCE_CONFIG
+#define __HAL_RCC_PLL_DIVM_CONFIG       __HAL_RCC_PLL1_DIVM_CONFIG
+#define __HAL_RCC_PLL_FRACN_CONFIG      __HAL_RCC_PLL1_FRACN_CONFIG
+#define __HAL_RCC_PLL_VCIRANGE          __HAL_RCC_PLL1_VCIRANGE
+#define __HAL_RCC_PLL_VCORANGE          __HAL_RCC_PLL1_VCORANGE
+#define __HAL_RCC_GET_PLL_OSCSOURCE     __HAL_RCC_GET_PLL1_OSCSOURCE
+#define __HAL_RCC_PLLCLKOUT_ENABLE      __HAL_RCC_PLL1_CLKOUT_ENABLE
+#define __HAL_RCC_PLLCLKOUT_DISABLE     __HAL_RCC_PLL1_CLKOUT_DISABLE
+#define __HAL_RCC_GET_PLLCLKOUT_CONFIG  __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL2FRACN_ENABLE      __HAL_RCC_PLL2_FRACN_ENABLE
+#define __HAL_RCC_PLL2FRACN_DISABLE     __HAL_RCC_PLL2_FRACN_DISABLE
+#define __HAL_RCC_PLL2CLKOUT_ENABLE     __HAL_RCC_PLL2_CLKOUT_ENABLE
+#define __HAL_RCC_PLL2CLKOUT_DISABLE    __HAL_RCC_PLL2_CLKOUT_DISABLE
+#define __HAL_RCC_PLL2FRACN_CONFIG      __HAL_RCC_PLL2_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
+
+#define __HAL_RCC_PLL3FRACN_ENABLE      __HAL_RCC_PLL3_FRACN_ENABLE
+#define __HAL_RCC_PLL3FRACN_DISABLE     __HAL_RCC_PLL3_FRACN_DISABLE
+#define __HAL_RCC_PLL3CLKOUT_ENABLE     __HAL_RCC_PLL3_CLKOUT_ENABLE
+#define __HAL_RCC_PLL3CLKOUT_DISABLE    __HAL_RCC_PLL3_CLKOUT_DISABLE
+#define __HAL_RCC_PLL3FRACN_CONFIG      __HAL_RCC_PLL3_FRACN_CONFIG
+#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
+
+#define RCC_PLL2VCIRANGE_0              RCC_PLL2_VCIRANGE_0
+#define RCC_PLL2VCIRANGE_1              RCC_PLL2_VCIRANGE_1
+#define RCC_PLL2VCIRANGE_2              RCC_PLL2_VCIRANGE_2
+#define RCC_PLL2VCIRANGE_3              RCC_PLL2_VCIRANGE_3
+
+#define RCC_PLL2VCOWIDE                 RCC_PLL2_VCORANGE_WIDE
+#define RCC_PLL2VCOMEDIUM               RCC_PLL2_VCORANGE_MEDIUM
+
+#define RCC_PLL2SOURCE_NONE             RCC_PLL2_SOURCE_NONE
+#define RCC_PLL2SOURCE_HSI              RCC_PLL2_SOURCE_HSI
+#define RCC_PLL2SOURCE_CSI              RCC_PLL2_SOURCE_CSI
+#define RCC_PLL2SOURCE_HSE              RCC_PLL2_SOURCE_HSE
+
+#define RCC_PLL3VCIRANGE_0              RCC_PLL3_VCIRANGE_0
+#define RCC_PLL3VCIRANGE_1              RCC_PLL3_VCIRANGE_1
+#define RCC_PLL3VCIRANGE_2              RCC_PLL3_VCIRANGE_2
+#define RCC_PLL3VCIRANGE_3              RCC_PLL3_VCIRANGE_3
+
+#define RCC_PLL3VCOWIDE                 RCC_PLL3_VCORANGE_WIDE
+#define RCC_PLL3VCOMEDIUM               RCC_PLL3_VCORANGE_MEDIUM
+
+#define RCC_PLL3SOURCE_NONE             RCC_PLL3_SOURCE_NONE
+#define RCC_PLL3SOURCE_HSI              RCC_PLL3_SOURCE_HSI
+#define RCC_PLL3SOURCE_CSI              RCC_PLL3_SOURCE_CSI
+#define RCC_PLL3SOURCE_HSE              RCC_PLL3_SOURCE_HSE
+
+
+#endif /* STM32H5 */
 
 /**
   * @}
@@ -3347,7 +3908,9 @@ extern "C" {
 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
   * @{
   */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
+    defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) ||  defined (STM32U0) 
 #else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 #endif
@@ -3382,6 +3945,13 @@ extern "C" {
                                                         __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
 #endif   /* STM32F1 */
 
+#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
+    defined (STM32H7) || \
+    defined (STM32L0) || defined (STM32L1) || \
+    defined (STM32WB)
+#define __HAL_RTC_TAMPER_GET_IT                   __HAL_RTC_TAMPER_GET_FLAG
+#endif
+
 #define IS_ALARM                                  IS_RTC_ALARM
 #define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
 #define IS_TAMPER                                 IS_RTC_TAMPER
@@ -3400,17 +3970,31 @@ extern "C" {
 #define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
 #define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
 
+#if defined (STM32H5)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE   __HAL_RCC_RTC_CLK_ENABLE
+#define __HAL_RCC_RTCAPB_CLK_DISABLE  __HAL_RCC_RTC_CLK_DISABLE
+#endif   /* STM32H5 */
+
 /**
   * @}
   */
 
-/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
   * @{
   */
 
 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
 
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
+#endif
+
 #if defined(STM32F4) || defined(STM32F2)
 #define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
 #define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
@@ -3649,6 +4233,9 @@ extern "C" {
 #define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
 
 #define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+
+#define TIM_OCMODE_ASSYMETRIC_PWM1      TIM_OCMODE_ASYMMETRIC_PWM1
+#define TIM_OCMODE_ASSYMETRIC_PWM2      TIM_OCMODE_ASYMMETRIC_PWM2
 /**
   * @}
   */
@@ -3739,6 +4326,16 @@ extern "C" {
   * @}
   */
 
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+  * @}
+  */
+
 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -3753,5 +4350,4 @@ extern "C" {
 
 #endif /* STM32_HAL_LEGACY */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth.c
new file mode 100644
index 0000000000..547b7e87a3
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth.c
@@ -0,0 +1,3028 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_eth.c
+  * @author  MCD Application Team
+  * @brief   ETH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Ethernet (ETH) peripheral:
+  *           + Initialization and deinitialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### How to use this driver #####
+  ==============================================================================
+     [..]
+     The ETH HAL driver can be used as follows:
+
+      (#)Declare a ETH_HandleTypeDef handle structure, for example:
+         ETH_HandleTypeDef  heth;
+
+      (#)Fill parameters of Init structure in heth handle
+
+      (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
+
+      (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
+          (##) Enable the Ethernet interface clock using
+                (+++)  __HAL_RCC_ETH1MAC_CLK_ENABLE()
+                (+++)  __HAL_RCC_ETH1TX_CLK_ENABLE()
+                (+++)  __HAL_RCC_ETH1RX_CLK_ENABLE()
+
+          (##) Initialize the related GPIO clocks
+          (##) Configure Ethernet pinout
+          (##) Configure Ethernet NVIC interrupt (in Interrupt mode)
+
+      (#) Ethernet data reception is asynchronous, so call the following API
+          to start the listening mode:
+          (##) HAL_ETH_Start():
+               This API starts the MAC and DMA transmission and reception process,
+               without enabling end of transfer interrupts, in this mode user
+               has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
+          (##) HAL_ETH_Start_IT():
+               This API starts the MAC and DMA transmission and reception process,
+               end of transfer interrupts are enabled in this mode,
+               HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
+
+      (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
+          occurred), user can call the following APIs to get received data:
+          (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
+          (##) HAL_ETH_GetRxDataLength(): Get received frame length
+          (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
+               please refer to ETH_RxPacketInfo typedef structure
+
+      (#) For transmission path, two APIs are available:
+         (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
+         (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode,
+              HAL_ETH_TxCpltCallback() will be executed when end of transfer occur
+
+      (#) Communication with an external PHY device:
+         (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY
+         (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register
+
+      (#) Configure the Ethernet MAC after ETH peripheral initialization
+          (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef
+          (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef
+
+      (#) Configure the Ethernet DMA after ETH peripheral initialization
+          (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
+          (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
+
+      -@- The PTP protocol offload APIs are not supported in this driver.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+
+  Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+    (+) TxCpltCallback   : Tx Complete Callback.
+    (+) RxCpltCallback   : Rx Complete Callback.
+    (+) DMAErrorCallback : DMA Error Callback.
+    (+) MACErrorCallback : MAC Error Callback.
+    (+) PMTCallback      : Power Management Callback
+    (+) EEECallback      : EEE Callback.
+    (+) WakeUpCallback   : Wake UP Callback
+    (+) MspInitCallback  : MspInit Callback.
+    (+) MspDeInitCallback: MspDeInit Callback.
+
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxCpltCallback   : Tx Complete Callback.
+    (+) RxCpltCallback   : Rx Complete Callback.
+    (+) DMAErrorCallback : DMA Error Callback.
+    (+) MACErrorCallback : MAC Error Callback.
+    (+) PMTCallback      : Power Management Callback
+    (+) EEECallback      : EEE Callback.
+    (+) WakeUpCallback   : Wake UP Callback
+    (+) MspInitCallback  : MspInit Callback.
+    (+) MspDeInitCallback: MspDeInit Callback.
+
+  By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
+  all callbacks are set to the corresponding weak functions:
+  examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+  or HAL_ETH_Init function.
+
+  When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+
+#if defined(ETH)
+
+/** @defgroup ETH ETH
+  * @brief ETH HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup ETH_Private_Constants ETH Private Constants
+  * @{
+  */
+#define ETH_MACCR_MASK       ((uint32_t)0xFFFB7F7CU)
+#define ETH_MACECR_MASK      ((uint32_t)0x3F077FFFU)
+#define ETH_MACPFR_MASK      ((uint32_t)0x800007FFU)
+#define ETH_MACWTR_MASK      ((uint32_t)0x0000010FU)
+#define ETH_MACTFCR_MASK     ((uint32_t)0xFFFF00F2U)
+#define ETH_MACRFCR_MASK     ((uint32_t)0x00000003U)
+#define ETH_MTLTQOMR_MASK    ((uint32_t)0x00000072U)
+#define ETH_MTLRQOMR_MASK    ((uint32_t)0x0000007BU)
+
+#define ETH_DMAMR_MASK       ((uint32_t)0x00007802U)
+#define ETH_DMASBMR_MASK     ((uint32_t)0x0000D001U)
+#define ETH_DMACCR_MASK      ((uint32_t)0x00013FFFU)
+#define ETH_DMACTCR_MASK     ((uint32_t)0x003F1010U)
+#define ETH_DMACRCR_MASK     ((uint32_t)0x803F0000U)
+#define ETH_MACPCSR_MASK     (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
+                              ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
+                              ETH_MACPCSR_RWKPFE)
+
+/* Timeout values */
+#define ETH_SWRESET_TIMEOUT                 ((uint32_t)500U)
+#define ETH_MDIO_BUS_TIMEOUT                ((uint32_t)1000U)
+
+#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
+                                                  ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
+                                                  ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
+
+#define ETH_MAC_US_TICK               ((uint32_t)1000000U)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ETH_Private_Macros ETH Private Macros
+  * @{
+  */
+/* Helper macros for TX descriptor handling */
+#define INCR_TX_DESC_INDEX(inx, offset) do {\
+	(inx) += (offset);\
+          if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
+            (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
+} while (0)
+
+/* Helper macros for RX descriptor handling */
+#define INCR_RX_DESC_INDEX(inx, offset) do {\
+	(inx) += (offset);\
+          if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
+            (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
+} while (0)
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ETH_Private_Functions   ETH Private Functions
+  * @{
+  */
+static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf);
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf);
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup ETH_Exported_Functions ETH Exported Functions
+  * @{
+  */
+
+/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This subsection provides a set of functions allowing to initialize and
+          deinitialize the ETH peripheral:
+
+      (+) User must Implement HAL_ETH_MspInit() function in which he configures
+          all related peripherals resources (CLOCK, GPIO and NVIC ).
+
+      (+) Call the function HAL_ETH_Init() to configure the selected device with
+          the selected configuration:
+        (++) MAC address
+        (++) Media interface (MII or RMII)
+        (++) Rx DMA Descriptors Tab
+        (++) Tx DMA Descriptors Tab
+        (++) Length of Rx Buffers
+
+      (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
+          for each Rx DMA Descriptor
+
+      (+) Call the function HAL_ETH_DeInit() to restore the default configuration
+          of the selected ETH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the Ethernet peripheral registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
+{
+  uint32_t tickstart;
+
+  if(heth == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+  if(heth->gState == HAL_ETH_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    heth->Lock = HAL_UNLOCKED;
+
+    ETH_InitCallbacksToDefault(heth);
+
+    if(heth->MspInitCallback == NULL)
+    {
+      heth->MspInitCallback = HAL_ETH_MspInit;
+    }
+
+    /* Init the low level hardware */
+    heth->MspInitCallback(heth);
+  }
+
+#else
+
+  /* Check the ETH peripheral state */
+  if(heth->gState == HAL_ETH_STATE_RESET)
+  {
+    /* Init the low level hardware : GPIO, CLOCK, NVIC. */
+    HAL_ETH_MspInit(heth);
+  }
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+
+  heth->gState = HAL_ETH_STATE_BUSY;
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+  {
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
+  }
+  else
+  {
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
+  }
+
+  /* Ethernet Software reset */
+  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
+  /* After reset all the registers holds their respective reset values */
+  SET_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for software reset */
+  while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
+  {
+    if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
+    {
+      /* Set Error Code */
+      heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
+      /* Set State as Error */
+      heth->gState = HAL_ETH_STATE_ERROR;
+      /* Return Error */
+      return HAL_ERROR;
+    }
+  }
+
+  /*------------------ MDIO CSR Clock Range Configuration --------------------*/
+  ETH_MAC_MDIO_ClkConfig(heth);
+
+  /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
+  WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
+
+  /*------------------ MAC, MTL and DMA default Configuration ----------------*/
+  ETH_MACDMAConfig(heth);
+
+  /* SET DSL to 64 bit */
+  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_DSL, ETH_DMACCR_DSL_64BIT);
+
+  /* Set Receive Buffers Length (must be a multiple of 4) */
+  if ((heth->Init.RxBuffLen % 0x4U) != 0x0U)
+  {
+    /* Set Error Code */
+    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+    /* Set State as Error */
+    heth->gState = HAL_ETH_STATE_ERROR;
+    /* Return Error */
+    return HAL_ERROR;
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_RBSZ, ((heth->Init.RxBuffLen) << 1));
+  }
+
+  /*------------------ DMA Tx Descriptors Configuration ----------------------*/
+  ETH_DMATxDescListInit(heth);
+
+  /*------------------ DMA Rx Descriptors Configuration ----------------------*/
+  ETH_DMARxDescListInit(heth);
+
+  /*--------------------- ETHERNET MAC Address Configuration ------------------*/
+  /* Set MAC addr bits 32 to 47 */
+  heth->Instance->MACA0HR = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]);
+  /* Set MAC addr bits 0 to 31 */
+  heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
+                             ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
+
+  heth->ErrorCode = HAL_ETH_ERROR_NONE;
+  heth->gState = HAL_ETH_STATE_READY;
+  heth->RxState = HAL_ETH_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the ETH peripheral.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
+{
+  /* Set the ETH peripheral state to BUSY */
+  heth->gState = HAL_ETH_STATE_BUSY;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+  if(heth->MspDeInitCallback == NULL)
+  {
+    heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  heth->MspDeInitCallback(heth);
+#else
+
+  /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
+  HAL_ETH_MspDeInit(heth);
+
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+
+  /* Set ETH HAL state to Disabled */
+  heth->gState= HAL_ETH_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the ETH MSP.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MspInit could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  DeInitializes ETH MSP.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MspDeInit could be implemented in the user file
+  */
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ETH Callback
+  *         To be used instead of the weak predefined callback
+  * @param heth eth handle
+  * @param CallbackID ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
+  *          @arg @ref HAL_ETH_MAC_ERROR_CB_ID   MAC Error Callback ID
+  *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
+  *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
+  *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
+  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
+  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
+  * @param pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(pCallback == NULL)
+  {
+    /* Update the error code */
+    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(heth);
+
+  if(heth->gState == HAL_ETH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+    case HAL_ETH_TX_COMPLETE_CB_ID :
+      heth->TxCpltCallback = pCallback;
+      break;
+
+    case HAL_ETH_RX_COMPLETE_CB_ID :
+      heth->RxCpltCallback = pCallback;
+      break;
+
+    case HAL_ETH_DMA_ERROR_CB_ID :
+      heth->DMAErrorCallback = pCallback;
+      break;
+
+    case HAL_ETH_MAC_ERROR_CB_ID :
+      heth->MACErrorCallback = pCallback;
+      break;
+
+    case HAL_ETH_PMT_CB_ID :
+      heth->PMTCallback = pCallback;
+      break;
+
+    case HAL_ETH_EEE_CB_ID :
+      heth->EEECallback = pCallback;
+      break;
+
+    case HAL_ETH_WAKEUP_CB_ID :
+      heth->WakeUpCallback = pCallback;
+      break;
+
+    case HAL_ETH_MSPINIT_CB_ID :
+      heth->MspInitCallback = pCallback;
+      break;
+
+   case HAL_ETH_MSPDEINIT_CB_ID :
+      heth->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+      /* Update the error code */
+      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(heth->gState == HAL_ETH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+    case HAL_ETH_MSPINIT_CB_ID :
+      heth->MspInitCallback = pCallback;
+      break;
+
+   case HAL_ETH_MSPDEINIT_CB_ID :
+      heth->MspDeInitCallback = pCallback;
+      break;
+
+    default :
+      /* Update the error code */
+      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(heth);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an ETH Callback
+  *         ETH callabck is redirected to the weak predefined callback
+  * @param heth eth handle
+  * @param CallbackID ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
+  *          @arg @ref HAL_ETH_MAC_ERROR_CB_ID   MAC Error Callback ID
+  *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
+  *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
+  *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
+  *          @arg @ref HAL_ETH_MSPINIT_CB_ID     MspInit callback ID
+  *          @arg @ref HAL_ETH_MSPDEINIT_CB_ID   MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(heth);
+
+  if(heth->gState == HAL_ETH_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+    case HAL_ETH_TX_COMPLETE_CB_ID :
+      heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+      break;
+
+    case HAL_ETH_RX_COMPLETE_CB_ID :
+      heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+      break;
+
+    case HAL_ETH_DMA_ERROR_CB_ID :
+      heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
+      break;
+
+    case HAL_ETH_MAC_ERROR_CB_ID :
+      heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
+      break;
+
+    case HAL_ETH_PMT_CB_ID :
+      heth->PMTCallback = HAL_ETH_PMTCallback;
+      break;
+
+    case HAL_ETH_EEE_CB_ID :
+      heth->EEECallback = HAL_ETH_EEECallback;
+      break;
+
+    case HAL_ETH_WAKEUP_CB_ID :
+      heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
+      break;
+
+    case HAL_ETH_MSPINIT_CB_ID :
+      heth->MspInitCallback = HAL_ETH_MspInit;
+      break;
+
+   case HAL_ETH_MSPDEINIT_CB_ID :
+      heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+      break;
+
+    default :
+      /* Update the error code */
+      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else if(heth->gState == HAL_ETH_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+    case HAL_ETH_MSPINIT_CB_ID :
+      heth->MspInitCallback = HAL_ETH_MspInit;
+      break;
+
+   case HAL_ETH_MSPDEINIT_CB_ID :
+      heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+      break;
+
+    default :
+      /* Update the error code */
+      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+     /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(heth);
+
+  return status;
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Assign memory buffers to a DMA Rx descriptor
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Index : index of the DMA Rx descriptor
+  *                  this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
+  * @param  pBuffer1: address of buffer 1
+  * @param  pBuffer2: address of buffer 2 if available
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
+{
+  ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
+
+  if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
+  {
+    /* Set Error Code */
+    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+    /* Return Error */
+    return HAL_ERROR;
+  }
+
+  /* write buffer address to RDES0 */
+  WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
+  /* store buffer address */
+  WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
+  /* set buffer address valid bit to RDES3 */
+  SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+
+  if(pBuffer2 != NULL)
+  {
+    /* write buffer 2 address to RDES1 */
+    WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
+     /* store buffer 2 address */
+    WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
+    /* set buffer 2 address valid bit to RDES3 */
+    SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+  }
+  /* set OWN bit to RDES3 */
+  SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions_Group2 IO operation functions
+  *  @brief ETH Transmit and Receive functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the ETH
+    data transfer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables Ethernet MAC and DMA reception and transmission
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
+{
+  if(heth->gState == HAL_ETH_STATE_READY)
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* Enable the MAC transmission */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+    /* Enable the DMA transmission */
+    SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+    /* Enable the DMA reception */
+    SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+    /* Clear Tx and Rx process stopped flags */
+    heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+
+    heth->gState = HAL_ETH_STATE_READY;
+    heth->RxState = HAL_ETH_STATE_BUSY_RX;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enables Ethernet MAC and DMA reception/transmission in Interrupt mode
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
+{
+  uint32_t descindex;
+
+  ETH_DMADescTypeDef *dmarxdesc;
+
+  if(heth->gState == HAL_ETH_STATE_READY)
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* Set IOC bit to all Rx descriptors */
+    for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+    {
+      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+    }
+
+    /* save IT mode to ETH Handle */
+    heth->RxDescList.ItMode = 1U;
+
+    /* Enable the MAC transmission */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+    /* Enable the DMA transmission */
+    SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+    /* Enable the DMA reception */
+    SET_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+    /* Clear Tx and Rx process stopped flags */
+    heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
+
+    /* Enable ETH DMA interrupts:
+    - Tx complete interrupt
+    - Rx complete interrupt
+    - Fatal bus interrupt
+    */
+    __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
+                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+
+    heth->gState = HAL_ETH_STATE_READY;
+    heth->RxState = HAL_ETH_STATE_BUSY_RX;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop Ethernet MAC and DMA reception/transmission
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
+{
+  if(heth->gState != HAL_ETH_STATE_RESET)
+  {
+     /* Set the ETH peripheral state to BUSY */
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* Disable the DMA transmission */
+    CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+    /* Disable the DMA reception */
+    CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+    /* Disable the MAC reception */
+    CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+    /* Disable the MAC transmission */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    heth->gState = HAL_ETH_STATE_READY;
+    heth->RxState = HAL_ETH_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop Ethernet MAC and DMA reception/transmission in Interrupt mode
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
+{
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t descindex;
+
+  if(heth->gState != HAL_ETH_STATE_RESET)
+  {
+    /* Set the ETH peripheral state to BUSY */
+    heth->gState = HAL_ETH_STATE_BUSY;
+
+    /* Disable interrupts:
+    - Tx complete interrupt
+    - Rx complete interrupt
+    - Fatal bus interrupt
+    */
+    __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
+                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+
+    /* Disable the DMA transmission */
+    CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
+
+    /* Disable the DMA reception */
+    CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
+
+    /* Disable the MAC reception */
+    CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+    /* Disable the MAC transmission */
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    /* Clear IOC bit to all Rx descriptors */
+    for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+    {
+      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
+      CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+    }
+
+    heth->RxDescList.ItMode = 0U;
+
+    heth->gState = HAL_ETH_STATE_READY;
+    heth->RxState = HAL_ETH_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sends an Ethernet Packet in polling mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Hold the configuration of packet to be transmitted
+  * @param  Timeout: timeout value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  const ETH_DMADescTypeDef *dmatxdesc;
+
+  if(pTxConfig == NULL)
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(heth->gState == HAL_ETH_STATE_READY)
+  {
+    /* Config DMA Tx descriptor by Tx Packet info */
+    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
+    {
+      /* Set the ETH error code */
+      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+      return HAL_ERROR;
+    }
+
+    dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
+
+    /* Incr current tx desc index */
+    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
+
+    /* Start transmission */
+    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+    WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
+
+    tickstart = HAL_GetTick();
+
+    /* Wait for data to be transmitted or timeout occurred */
+    while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
+    {
+      if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
+      {
+        heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+        heth->DMAErrorCode = heth->Instance->DMACSR;
+        /* Set ETH HAL State to Ready */
+        heth->gState = HAL_ETH_STATE_ERROR;
+        /* Return function status */
+        return HAL_ERROR;
+      }
+
+      /* Check for the Timeout */
+      if(Timeout != HAL_MAX_DELAY)
+      {
+        if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+        {
+          heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
+          heth->gState = HAL_ETH_STATE_ERROR;
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Sends an Ethernet Packet in interrupt mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Hold the configuration of packet to be transmitted
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
+{
+  if(pTxConfig == NULL)
+  {
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(heth->gState == HAL_ETH_STATE_READY)
+  {
+    /* Config DMA Tx descriptor by Tx Packet info */
+    if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
+    {
+      heth->ErrorCode |= HAL_ETH_ERROR_BUSY;
+      return HAL_ERROR;
+    }
+
+    /* Incr current tx desc index */
+    INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
+
+    /* Start transmission */
+    /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */
+    WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc]));
+
+    return HAL_OK;
+
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Checks for received Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval  1: A Packet is received
+  *          0: no Packet received
+  */
+uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
+{
+  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+  uint32_t descidx = dmarxdesclist->CurRxDesc;
+  ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+  uint32_t descscancnt = 0;
+  uint32_t appdesccnt = 0, firstappdescidx = 0;
+
+  if(dmarxdesclist->AppDescNbr != 0U)
+  {
+    /* data already received by not yet processed*/
+    return 0;
+  }
+
+  /* Check if descriptor is not owned by DMA */
+  while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
+  {
+    descscancnt++;
+
+    /* Check if last descriptor */
+    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
+    {
+      /* Increment the number of descriptors to be passed to the application */
+      appdesccnt += 1U;
+
+      if(appdesccnt == 1U)
+      {
+        WRITE_REG(firstappdescidx, descidx);
+      }
+
+      /* Increment current rx descriptor index */
+      INCR_RX_DESC_INDEX(descidx, 1U);
+
+      /* Check for Context descriptor */
+      /* Get current descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+      if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_OWN)  == (uint32_t)RESET)
+      {
+        if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
+        {
+          /* Increment the number of descriptors to be passed to the application */
+          dmarxdesclist->AppContextDesc = 1;
+          /* Increment current rx descriptor index */
+          INCR_RX_DESC_INDEX(descidx, 1U);
+        }
+      }
+      /* Fill information to Rx descriptors list */
+      dmarxdesclist->CurRxDesc = descidx;
+      dmarxdesclist->FirstAppDesc = firstappdescidx;
+      dmarxdesclist->AppDescNbr = appdesccnt;
+
+      /* Return function status */
+      return 1;
+    }
+    /* Check if first descriptor */
+    else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
+    {
+      WRITE_REG(firstappdescidx, descidx);
+      /* Increment the number of descriptors to be passed to the application */
+      appdesccnt = 1U;
+
+      /* Increment current rx descriptor index */
+      INCR_RX_DESC_INDEX(descidx, 1U);
+      /* Get current descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+    }
+    /* It should be an intermediate descriptor */
+    else
+    {
+      /* Increment the number of descriptors to be passed to the application */
+      appdesccnt += 1U;
+
+      /* Increment current rx descriptor index */
+      INCR_RX_DESC_INDEX(descidx, 1U);
+      /* Get current descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+    }
+  }
+
+  /* Build Descriptors if an incomplete Packet is received */
+  if(appdesccnt > 0U)
+  {
+    dmarxdesclist->CurRxDesc = descidx;
+    dmarxdesclist->FirstAppDesc = firstappdescidx;
+    descidx = firstappdescidx;
+    dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+    for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
+    {
+      WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
+      WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+
+      if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
+      {
+        WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
+        SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+      }
+
+      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+
+      if(dmarxdesclist->ItMode != ((uint32_t)RESET))
+      {
+        SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+      }
+      if(descscancnt < (appdesccnt - 1U))
+      {
+        /* Increment rx descriptor index */
+        INCR_RX_DESC_INDEX(descidx, 1U);
+        /* Get descriptor address */
+        dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+      }
+    }
+
+    /* Set the Tail pointer address to the last rx descriptor hold by the app */
+    WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
+  }
+
+  /* Fill information to Rx descriptors list: No received Packet */
+  dmarxdesclist->AppDescNbr = 0U;
+
+  return 0;
+}
+
+/**
+  * @brief  This function gets the buffer address of last received Packet.
+  * @note   Please insure to allocate the RxBuffer structure before calling this function
+  *         how to use example:
+  *           HAL_ETH_GetRxDataLength(heth, &Length);
+  *           BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
+  *           RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
+  *           HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  RxBuffer: Pointer to a ETH_BufferTypeDef structure
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
+{
+  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+  uint32_t descidx = dmarxdesclist->FirstAppDesc;
+  uint32_t index, accumulatedlen = 0, lastdesclen;
+  __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+  ETH_BufferTypeDef *rxbuff = RxBuffer;
+
+  if(rxbuff == NULL)
+  {
+    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+
+  if(dmarxdesclist->AppDescNbr == 0U)
+  {
+    if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+    {
+      /* No data to be transferred to the application */
+      return HAL_ERROR;
+    }
+    else
+    {
+      descidx = dmarxdesclist->FirstAppDesc;
+      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+    }
+  }
+
+  /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */
+  for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
+  {
+    /* Get Address and length of the first buffer address */
+    rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
+    rxbuff->len =  heth->Init.RxBuffLen;
+
+    /* Check if the second buffer address of this descriptor is valid */
+    if(dmarxdesc->BackupAddr1 != 0U)
+    {
+      /* Point to next buffer */
+      rxbuff = rxbuff->next;
+      /* Get Address and length of the second buffer address */
+      rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
+      rxbuff->len =  heth->Init.RxBuffLen;
+    }
+    else
+    {
+      /* Nothing to do here */
+    }
+
+    /* get total length until this descriptor */
+    accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
+
+    /* Increment to next descriptor */
+    INCR_RX_DESC_INDEX(descidx, 1U);
+    dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+    /* Point to next buffer */
+    rxbuff = rxbuff->next;
+  }
+
+  /* last descriptor data length */
+  lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
+
+  /* Get Address of the first buffer address */
+  rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
+
+  /* data is in only one buffer */
+  if(lastdesclen <= heth->Init.RxBuffLen)
+  {
+    rxbuff->len = lastdesclen;
+  }
+  /* data is in two buffers */
+  else if(dmarxdesc->BackupAddr1 != 0U)
+  {
+    /* Get the Length of the first buffer address */
+    rxbuff->len = heth->Init.RxBuffLen;
+    /* Point to next buffer */
+    rxbuff = rxbuff->next;
+    /* Get the Address the Length of the second buffer address */
+    rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
+    rxbuff->len =  lastdesclen - (heth->Init.RxBuffLen);
+  }
+  else /* Buffer 2 not valid*/
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function gets the length of last received Packet.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Length: parameter to hold Rx packet length
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
+{
+  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+  uint32_t descidx = dmarxdesclist->FirstAppDesc;
+  __IO const ETH_DMADescTypeDef *dmarxdesc;
+
+  if(dmarxdesclist->AppDescNbr == 0U)
+  {
+    if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+    {
+      /* No data to be transferred to the application */
+      return HAL_ERROR;
+    }
+  }
+
+  /* Get index of last descriptor */
+  INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
+  /* Point to last descriptor */
+  dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+  *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  RxPacketInfo: parameter to hold info of received buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
+{
+  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+  uint32_t descidx = dmarxdesclist->FirstAppDesc;
+  __IO const ETH_DMADescTypeDef *dmarxdesc;
+
+  if(dmarxdesclist->AppDescNbr == 0U)
+  {
+    if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+    {
+      /* No data to be transferred to the application */
+      return HAL_ERROR;
+    }
+  }
+
+  /* Get index of last descriptor */
+  INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
+  /* Point to last descriptor */
+  dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
+
+  if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
+  {
+    RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
+  }
+  else
+  {
+    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
+    {
+
+      if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
+      {
+        RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
+        RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
+      }
+      else
+      {
+        RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
+      }
+    }
+
+    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
+    {
+      /* Get Payload type */
+      RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
+      /* Get Header type */
+      RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
+      /* Get Checksum status */
+      RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
+    }
+
+    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
+    {
+      RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
+      RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2,  (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
+      RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
+    }
+  }
+
+  /* Get the segment count */
+  WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
+
+  return HAL_OK;
+}
+
+/**
+* @brief  This function gives back Rx Desc of the last received Packet
+*         to the DMA, so ETH DMA will be able to use these descriptors
+*         to receive next Packets.
+*         It should be called after processing the received Packet.
+* @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+*         the configuration information for ETHERNET module
+* @retval HAL status.
+*/
+HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
+{
+  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
+  uint32_t descindex = dmarxdesclist->FirstAppDesc;
+  __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
+  uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
+  uint32_t descscan;
+
+  if(dmarxdesclist->AppDescNbr == 0U)
+  {
+    /* No Rx descriptors to build */
+    return HAL_ERROR;
+  }
+
+  if(dmarxdesclist->AppContextDesc != 0U)
+  {
+    /* A context descriptor is available */
+    totalappdescnbr += 1U;
+  }
+
+  for(descscan =0; descscan < totalappdescnbr; descscan++)
+  {
+    WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
+    WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
+
+    if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
+    {
+      WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
+      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+    }
+
+    SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+
+    if(dmarxdesclist->ItMode != 0U)
+    {
+      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
+    }
+
+    if(descscan < (totalappdescnbr - 1U))
+    {
+      /* Increment rx descriptor index */
+      INCR_RX_DESC_INDEX(descindex, 1U);
+      /* Get descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
+    }
+  }
+
+  /* Set the Tail pointer address to the last rx descriptor hold by the app */
+  WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
+
+  /* reset the Application desc number */
+  WRITE_REG(dmarxdesclist->AppDescNbr, 0);
+
+  /*  reset the application context descriptor */
+  WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  This function handles ETH interrupt request.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
+{
+  /* Packet received */
+  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
+  {
+    if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
+    {
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Receive complete callback*/
+      heth->RxCpltCallback(heth);
+#else
+      /* Receive complete callback */
+      HAL_ETH_RxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+      /* Clear the Eth DMA Rx IT pending bits */
+      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
+    }
+  }
+
+  /* Packet transmitted */
+  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
+  {
+    if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
+    {
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+        /*Call registered Transmit complete callback*/
+        heth->TxCpltCallback(heth);
+#else
+      /* Transfer complete callback */
+      HAL_ETH_TxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+      /* Clear the Eth DMA Tx IT pending bits */
+      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
+    }
+  }
+
+
+  /* ETH DMA Error */
+  if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
+  {
+    if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
+    {
+      heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+
+      /* if fatal bus error occurred */
+      if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
+      {
+        /* Get DMA error code  */
+        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
+
+        /* Disable all interrupts */
+        __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
+
+        /* Set HAL state to ERROR */
+        heth->gState = HAL_ETH_STATE_ERROR;
+      }
+      else
+      {
+        /* Get DMA error status  */
+       heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+                                                       ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+
+        /* Clear the interrupt summary flag */
+        __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+                                    ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+      }
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /* Call registered DMA Error callback*/
+      heth->DMAErrorCallback(heth);
+#else
+      /* Ethernet DMA Error callback */
+      HAL_ETH_DMAErrorCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    }
+  }
+
+  /* ETH MAC Error IT */
+  if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
+  {
+    /* Get MAC Rx Tx status and clear Status register pending bit */
+    heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
+
+    heth->gState = HAL_ETH_STATE_ERROR;
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered MAC Error callback*/
+    heth->DMAErrorCallback(heth);
+#else
+    /* Ethernet MAC Error callback */
+    HAL_ETH_MACErrorCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACErrorCode = (uint32_t)(0x0U);
+  }
+
+  /* ETH PMT IT */
+  if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
+  {
+    /* Get MAC Wake-up source and clear the status register pending bit */
+    heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered PMT callback*/
+    heth->PMTCallback(heth);
+#else
+    /* Ethernet PMT callback */
+    HAL_ETH_PMTCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACWakeUpEvent = (uint32_t)(0x0U);
+  }
+
+  /* ETH EEE IT */
+  if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
+  {
+    /* Get MAC LPI interrupt source and clear the status register pending bit */
+    heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered EEE callback*/
+    heth->EEECallback(heth);
+#else
+    /* Ethernet EEE callback */
+    HAL_ETH_EEECallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+    heth->MACLPIEvent = (uint32_t)(0x0U);
+  }
+
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    /* check ETH WAKEUP exti flag */
+    if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+    {
+      /* Clear ETH WAKEUP Exti pending bit */
+      __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /* Call registered WakeUp callback*/
+      heth->WakeUpCallback(heth);
+#else
+      /* ETH WAKEUP callback */
+      HAL_ETH_WakeUpCallback(heth);
+#endif
+    }
+  }
+  else
+  {
+    /* check ETH WAKEUP exti flag */
+    if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+    {
+      /* Clear ETH WAKEUP Exti pending bit */
+      __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /* Call registered WakeUp callback*/
+      heth->WakeUpCallback(heth);
+#else
+      /* ETH WAKEUP callback */
+      HAL_ETH_WakeUpCallback(heth);
+#endif
+    }
+  }
+#else
+  /* check ETH WAKEUP exti flag */
+  if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+  {
+    /* Clear ETH WAKEUP Exti pending bit */
+    __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /* Call registered WakeUp callback*/
+      heth->WakeUpCallback(heth);
+#else
+      /* ETH WAKEUP callback */
+      HAL_ETH_WakeUpCallback(heth);
+#endif
+  }
+#endif
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxCpltCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Ethernet DMA transfer error callbacks
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_DMAErrorCallback could be implemented in the user file
+  */
+}
+
+/**
+* @brief  Ethernet MAC transfer error callbacks
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_MACErrorCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Ethernet Power Management module IT callback
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_PMTCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Energy Efficient Etherent IT callback
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_EEECallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  ETH WAKEUP interrupt callback
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(heth);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_ETH_WakeUpCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Read a PHY register
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  PHYAddr: PHY port address, must be a value from 0 to 31
+  * @param  PHYReg: PHY register address, must be a value from 0 to 31
+  * @param pRegValue: parameter to hold read value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
+{
+  uint32_t tmpreg, tickstart;
+
+  /* Check for the Busy flag */
+  if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the  MACMDIOAR value */
+  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+
+  /* Prepare the MDIO Address Register value
+     - Set the PHY device address
+     - Set the PHY register address
+     - Set the read mode
+     - Set the MII Busy bit */
+
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
+  SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
+
+  /* Write the result value into the MDII Address register */
+  WRITE_REG(heth->Instance->MACMDIOAR, tmpreg);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait for the Busy flag */
+  while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+  {
+    if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /* Get MACMIIDR value */
+  WRITE_REG(*pRegValue, (uint16_t)heth->Instance->MACMDIODR);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Writes to a PHY register.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  PHYAddr: PHY port address, must be a value from 0 to 31
+  * @param  PHYReg: PHY register address, must be a value from 0 to 31
+  * @param  RegValue: the value to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
+{
+  uint32_t tmpreg, tickstart;
+
+  /* Check for the Busy flag */
+  if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get the  MACMDIOAR value */
+  WRITE_REG(tmpreg, heth->Instance->MACMDIOAR);
+
+  /* Prepare the MDIO Address Register value
+     - Set the PHY device address
+     - Set the PHY register address
+     - Set the write mode
+     - Set the MII Busy bit */
+
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
+  SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
+
+
+  /* Give the value to the MII data register */
+  WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
+
+  /* Write the result value into the MII Address register */
+  WRITE_REG(ETH->MACMDIOAR, tmpreg);
+
+  tickstart = HAL_GetTick();
+
+  /* Wait for the Busy flag */
+  while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+  {
+    if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   ETH control functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the ETH
+    peripheral.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Get the configuration of the MAC and MTL subsystems.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that will hold
+  *         the configuration of the MAC.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+{
+  if (macconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get MAC parameters */
+  macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
+  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
+  macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
+  macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
+  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
+  macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
+  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
+  macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
+  macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
+  macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
+  macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
+  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
+  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
+  macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
+  macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
+  macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
+  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
+  macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
+  macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
+  macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
+
+  macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
+  macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
+  macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
+  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
+  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
+  macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
+
+
+  macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
+  macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
+
+  macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_TFE) >> 1) > 0U) ? ENABLE : DISABLE;
+  macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
+  macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
+  macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
+
+
+  macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
+  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
+
+  macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
+
+  macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
+  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
+  macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
+  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the configuration of the DMA.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
+  *         the configuration of the ETH DMA.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+{
+  if (dmaconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
+  dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
+  dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
+
+  dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
+
+  dmaconf->PBLx8Mode =  ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
+  dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
+
+  dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR,  ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
+  dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_RPBL);
+
+  dmaconf->SecondPacketOperate = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_OSP) >> 4) > 0U) ? ENABLE : DISABLE;
+  dmaconf->TCPSegmentation = ((READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TSE) >> 12) > 0U) ? ENABLE : DISABLE;
+  dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_TPBL);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the MAC configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  macconf: pointer to a ETH_MACConfigTypeDef structure that contains
+  *         the configuration of the MAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
+{
+  if(macconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(heth->RxState == HAL_ETH_STATE_READY)
+  {
+    ETH_SetMACConfig(heth, macconf);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Set the ETH DMA configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold
+  *         the configuration of the ETH DMA.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
+{
+  if(dmaconf == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(heth->RxState == HAL_ETH_STATE_READY)
+  {
+    ETH_SetDMAConfig(heth, dmaconf);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Configures the Clock range of ETH MDIO interface.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
+{
+  uint32_t tmpreg, hclk;
+
+  /* Get the ETHERNET MACMDIOAR value */
+  tmpreg = (heth->Instance)->MACMDIOAR;
+
+	/* Clear CSR Clock Range bits */
+  tmpreg &= ~ETH_MACMDIOAR_CR;
+
+	/* Get hclk frequency value */
+  hclk = HAL_RCC_GetHCLKFreq();
+
+	/* Set CR bits depending on hclk value */
+  if((hclk >= 20000000U)&&(hclk < 35000000U))
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+  }
+  else if((hclk >= 35000000U)&&(hclk < 60000000U))
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+  }
+  else if((hclk >= 60000000U)&&(hclk < 100000000U))
+  {
+    /* CSR Clock Range between 60-100 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+  }
+  else if((hclk >= 100000000U)&&(hclk < 150000000U))
+  {
+    /* CSR Clock Range between 100-150 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+  }
+  else /* (hclk >= 150000000)&&(hclk <= 200000000) */
+  {
+    /* CSR Clock Range between 150-200 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+  }
+
+  /* Configure the CSR Clock Range */
+  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+}
+
+/**
+  * @brief  Set the ETH MAC (L2) Filters configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains
+  *         the configuration of the ETH MAC filters.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+{
+  uint32_t filterconfig;
+
+  if(pFilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
+                  ((uint32_t)pFilterConfig->HashUnicast << 1) |
+                    ((uint32_t)pFilterConfig->HashMulticast << 2)  |
+                      ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
+                        ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
+                          ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
+                            ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
+                              ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
+                                ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
+                                  ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
+                                    pFilterConfig->ControlPacketsFilter);
+
+  MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the ETH MAC (L2) Filters configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold
+  *         the configuration of the ETH MAC filters.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+{
+  if(pFilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
+  pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
+  pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the source MAC Address to be matched.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  AddrNbr: The MAC address to configure
+  *          This parameter must be a value of the following:
+  *            ETH_MAC_ADDRESS1
+  *            ETH_MAC_ADDRESS2
+  *            ETH_MAC_ADDRESS3
+  * @param  pMACAddr: Pointer to MAC address buffer data (6 bytes)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
+{
+  uint32_t macaddrhr, macaddrlr;
+
+  if(pMACAddr == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get mac addr high reg offset */
+  macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
+  /* Get mac addr low reg offset */
+  macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
+
+  /* Set MAC addr bits 32 to 47 */
+  (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
+  /* Set MAC addr bits 0 to 31 */
+  (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
+                                   ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
+
+   /* Enable address and set source address bit */
+  (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the ETH Hash Table Value.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pHashTable: pointer to a table of two 32 bit values, that contains
+  *         the 64 bits of the hash table.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
+{
+  if(pHashTable == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  heth->Instance->MACHT0R = pHashTable[0];
+  heth->Instance->MACHT1R = pHashTable[1];
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Identifier for Rx packets
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  ComparisonBits: 12 or 16 bit comparison mode
+            must be a value of @ref ETH_VLAN_Tag_Comparison
+  * @param  VLANIdentifier: VLAN Identifier value
+  * @retval None
+  */
+void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
+{
+  if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
+  {
+    MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
+    CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
+    SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
+  }
+}
+
+/**
+  * @brief  Enters the Power down mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure
+  *         that contains the Power Down configuration
+  * @retval None.
+  */
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
+{
+  uint32_t powerdownconfig;
+
+  powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
+                     ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
+                       ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
+                         ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
+                           ETH_MACPCSR_PWRDWN);
+
+  /* Enable PMT interrupt */
+  __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
+
+  MODIFY_REG(heth->Instance->MACPCSR, ETH_MACPCSR_MASK, powerdownconfig);
+}
+
+/**
+  * @brief  Exits from the Power down mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
+{
+  /* clear wake up sources */
+  CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
+
+  if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
+  {
+    /* Exit power down mode */
+    CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
+  }
+
+  /* Disable PMT interrupt */
+  __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_PMTIE);
+}
+
+/**
+  * @brief  Set the WakeUp filter.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pFilter: pointer to filter registers values
+  * @param  Count: number of filter registers, must be from 1 to 8.
+  * @retval None.
+  */
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count)
+{
+  uint32_t regindex;
+
+  if(pFilter == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Reset Filter Pointer */
+  SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
+
+  /* Wake up packet filter config */
+  for(regindex = 0; regindex < Count; regindex++)
+  {
+    /* Write filter regs */
+    WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   ETH State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Peripheral State and Errors functions #####
+  ==============================================================================
+ [..]
+   This subsection provides a set of functions allowing to return the State of
+   ETH communication process, return Peripheral Errors occurred during communication
+   process
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the ETH state.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL state
+  */
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+{
+  HAL_ETH_StateTypeDef ret;
+  HAL_ETH_StateTypeDef gstate = heth->gState;
+  HAL_ETH_StateTypeDef rxstate =heth->RxState;
+
+  ret = gstate;
+  ret |= rxstate;
+  return ret;
+}
+
+/**
+  * @brief  Returns the ETH error code
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH Error Code
+  */
+uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
+{
+  return heth->ErrorCode;
+}
+
+/**
+  * @brief  Returns the ETH DMA error code
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH DMA Error Code
+  */
+uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
+{
+  return heth->DMAErrorCode;
+}
+
+/**
+  * @brief  Returns the ETH MAC error code
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MAC Error Code
+  */
+uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
+{
+  return heth->MACErrorCode;
+}
+
+/**
+  * @brief  Returns the ETH MAC WakeUp event source
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MAC WakeUp event source
+  */
+uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
+{
+  return heth->MACWakeUpEvent;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Private_Functions   ETH Private Functions
+  * @{
+  */
+
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
+{
+  uint32_t macregval;
+
+  /*------------------------ MACCR Configuration --------------------*/
+  macregval =(macconf->InterPacketGapVal |
+              macconf->SourceAddrControl |
+                ((uint32_t)macconf->ChecksumOffload<< 27) |
+                  ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+                    ((uint32_t)macconf->Support2KPacket  << 22) |
+                      ((uint32_t)macconf->CRCStripTypePacket << 21) |
+                        ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+                          ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+                            ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+                              ((uint32_t)macconf->JumboPacket << 16) |
+                                macconf->Speed |
+                                  macconf->DuplexMode |
+                                    ((uint32_t)macconf->LoopbackMode << 12) |
+                                      ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
+                                        ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
+                                          ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
+                                            ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
+                                              macconf->BackOffLimit |
+                                                ((uint32_t)macconf->DeferralCheck << 4)|
+                                                  macconf->PreambleLength);
+
+  /* Write to MACCR */
+  MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
+
+  /*------------------------ MACECR Configuration --------------------*/
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
+                 ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
+                   ((uint32_t)macconf->SlowProtocolDetect << 17)|
+                     ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
+                       macconf->GiantPacketSizeLimit);
+
+  /* Write to MACECR */
+  MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
+
+  /*------------------------ MACWTR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) |
+               macconf->WatchdogTimeout);
+
+  /* Write to MACWTR */
+  MODIFY_REG(heth->Instance->MACWTR, ETH_MACWTR_MASK, macregval);
+
+  /*------------------------ MACTFCR Configuration --------------------*/
+  macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
+               macconf->PauseLowThreshold |
+                 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
+                   (macconf->PauseTime << 16));
+
+  /* Write to MACTFCR */
+  MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
+
+  /*------------------------ MACRFCR Configuration --------------------*/
+  macregval = ((uint32_t)macconf->ReceiveFlowControl |
+               ((uint32_t)macconf->UnicastPausePacketDetect << 1));
+
+  /* Write to MACRFCR */
+  MODIFY_REG(heth->Instance->MACRFCR, ETH_MACRFCR_MASK, macregval);
+
+  /*------------------------ MTLTQOMR Configuration --------------------*/
+  /* Write to MTLTQOMR */
+  MODIFY_REG(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_MASK, macconf->TransmitQueueMode);
+
+  /*------------------------ MTLRQOMR Configuration --------------------*/
+  macregval = (macconf->ReceiveQueueMode |
+               ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
+                 ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
+                   ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
+
+  /* Write to MTLRQOMR */
+  MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
+}
+
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
+{
+  uint32_t dmaregval;
+
+  /*------------------------ DMAMR Configuration --------------------*/
+  MODIFY_REG(heth->Instance->DMAMR, ETH_DMAMR_MASK, dmaconf->DMAArbitration);
+
+  /*------------------------ DMASBMR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
+               dmaconf->BurstMode |
+                 ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
+
+  MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
+
+  /*------------------------ DMACCR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
+               dmaconf->MaximumSegmentSize);
+
+  MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
+
+  /*------------------------ DMACTCR Configuration --------------------*/
+  dmaregval = (dmaconf->TxDMABurstLength |
+               ((uint32_t)dmaconf->SecondPacketOperate << 4)|
+                 ((uint32_t)dmaconf->TCPSegmentation << 12));
+
+  MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
+
+  /*------------------------ DMACRCR Configuration --------------------*/
+  dmaregval = (((uint32_t)dmaconf->FlushRxPacket  << 31) |
+               dmaconf->RxDMABurstLength);
+
+  /* Write to DMACRCR */
+  MODIFY_REG(heth->Instance->DMACRCR, ETH_DMACRCR_MASK, dmaregval);
+}
+
+/**
+  * @brief  Configures Ethernet MAC and DMA with default parameters.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
+{
+  ETH_MACConfigTypeDef macDefaultConf;
+  ETH_DMAConfigTypeDef dmaDefaultConf;
+
+  /*--------------- ETHERNET MAC registers default Configuration --------------*/
+  macDefaultConf.AutomaticPadCRCStrip = ENABLE;
+  macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10;
+  macDefaultConf.CarrierSenseBeforeTransmit = DISABLE;
+  macDefaultConf.CarrierSenseDuringTransmit = DISABLE;
+  macDefaultConf.ChecksumOffload = ENABLE;
+  macDefaultConf.CRCCheckingRxPackets = ENABLE;
+  macDefaultConf.CRCStripTypePacket = ENABLE;
+  macDefaultConf.DeferralCheck = DISABLE;
+  macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
+  macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
+  macDefaultConf.ExtendedInterPacketGap = DISABLE;
+  macDefaultConf.ExtendedInterPacketGapVal = 0x0;
+  macDefaultConf.ForwardRxErrorPacket = DISABLE;
+  macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
+  macDefaultConf.GiantPacketSizeLimit = 0x618;
+  macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
+  macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
+  macDefaultConf.Jabber = ENABLE;
+  macDefaultConf.JumboPacket = DISABLE;
+  macDefaultConf.LoopbackMode = DISABLE;
+  macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
+  macDefaultConf.PauseTime = 0x0;
+  macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
+  macDefaultConf.ProgrammableWatchdog = DISABLE;
+  macDefaultConf.ReceiveFlowControl = DISABLE;
+  macDefaultConf.ReceiveOwn = ENABLE;
+  macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD;
+  macDefaultConf.RetryTransmission = ENABLE;
+  macDefaultConf.SlowProtocolDetect = DISABLE;
+  macDefaultConf.SourceAddrControl = ETH_SOURCEADDRESS_REPLACE_ADDR0;
+  macDefaultConf.Speed = ETH_SPEED_100M;
+  macDefaultConf.Support2KPacket = DISABLE;
+  macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD;
+  macDefaultConf.TransmitFlowControl = DISABLE;
+  macDefaultConf.UnicastPausePacketDetect = DISABLE;
+  macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE;
+  macDefaultConf.Watchdog = ENABLE;
+  macDefaultConf.WatchdogTimeout =  ETH_MACWTR_WTO_2KB;
+  macDefaultConf.ZeroQuantaPause = ENABLE;
+
+  /* MAC default configuration */
+  ETH_SetMACConfig(heth, &macDefaultConf);
+
+  /*--------------- ETHERNET DMA registers default Configuration --------------*/
+  dmaDefaultConf.AddressAlignedBeats = ENABLE;
+  dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED;
+  dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1;
+  dmaDefaultConf.FlushRxPacket = DISABLE;
+  dmaDefaultConf.PBLx8Mode = DISABLE;
+  dmaDefaultConf.RebuildINCRxBurst = DISABLE;
+  dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
+  dmaDefaultConf.SecondPacketOperate = DISABLE;
+  dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
+  dmaDefaultConf.TCPSegmentation = DISABLE;
+  dmaDefaultConf.MaximumSegmentSize = 536;
+
+  /* DMA default configuration */
+  ETH_SetDMAConfig(heth, &dmaDefaultConf);
+}
+
+/**
+  * @brief  Configures the Clock range of SMI interface.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
+{
+  uint32_t tmpreg, hclk;
+
+  /* Get the ETHERNET MACMDIOAR value */
+  tmpreg = (heth->Instance)->MACMDIOAR;
+
+  /* Clear CSR Clock Range bits */
+  tmpreg &= ~ETH_MACMDIOAR_CR;
+
+  /* Get hclk frequency value */
+  hclk = HAL_RCC_GetHCLKFreq();
+
+  /* Set CR bits depending on hclk value */
+  if((hclk >= 20000000U)&&(hclk < 35000000U))
+  {
+    /* CSR Clock Range between 20-35 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
+  }
+  else if((hclk >= 35000000U)&&(hclk < 60000000U))
+  {
+    /* CSR Clock Range between 35-60 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
+  }
+  else if((hclk >= 60000000U)&&(hclk < 100000000U))
+  {
+    /* CSR Clock Range between 60-100 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
+  }
+  else if((hclk >= 100000000U)&&(hclk < 150000000U))
+  {
+    /* CSR Clock Range between 100-150 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
+  }
+  else /* (hclk >= 150000000)&&(hclk <= 200000000) */
+  {
+    /* CSR Clock Range between 150-200 MHz */
+    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
+  }
+
+  /* Configure the CSR Clock Range */
+  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
+}
+
+/**
+  * @brief  Initializes the DMA Tx descriptors.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
+{
+  ETH_DMADescTypeDef *dmatxdesc;
+  uint32_t i;
+
+  /* Fill each DMATxDesc descriptor with the right values */
+  for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+  {
+    dmatxdesc = heth->Init.TxDesc + i;
+
+    WRITE_REG(dmatxdesc->DESC0, 0x0);
+    WRITE_REG(dmatxdesc->DESC1, 0x0);
+    WRITE_REG(dmatxdesc->DESC2, 0x0);
+    WRITE_REG(dmatxdesc->DESC3, 0x0);
+
+    WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
+  }
+
+  heth->TxDescList.CurTxDesc = 0;
+
+  /* Set Transmit Descriptor Ring Length */
+  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
+
+  /* Set Transmit Descriptor List Address */
+  WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
+
+  /* Set Transmit Descriptor Tail pointer */
+  WRITE_REG(heth->Instance->DMACTDTPR, (uint32_t) heth->Init.TxDesc);
+}
+
+/**
+  * @brief  Initializes the DMA Rx descriptors in chain mode.
+  *         called by HAL_ETH_Init() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
+{
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t i;
+
+  for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+  {
+    dmarxdesc =  heth->Init.RxDesc + i;
+
+    WRITE_REG(dmarxdesc->DESC0, 0x0);
+    WRITE_REG(dmarxdesc->DESC1, 0x0);
+    WRITE_REG(dmarxdesc->DESC2, 0x0);
+    WRITE_REG(dmarxdesc->DESC3, 0x0);
+    WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
+    WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
+
+    /* Set Rx descritors addresses */
+    WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
+  }
+
+  WRITE_REG(heth->RxDescList.CurRxDesc, 0);
+  WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
+  WRITE_REG(heth->RxDescList.AppDescNbr, 0);
+  WRITE_REG(heth->RxDescList.ItMode, 0);
+  WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+
+  /* Set Receive Descriptor Ring Length */
+  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
+
+  /* Set Receive Descriptor List Address */
+  WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
+
+  /* Set Receive Descriptor Tail pointer Address */
+  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));
+}
+
+/**
+  * @brief  Prepare Tx DMA descriptor before transmission.
+  *         called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pTxConfig: Tx packet configuration
+  * @param  ItMode: Enable or disable Tx EOT interrept
+  * @retval Status
+  */
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
+{
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+  uint32_t descidx = dmatxdesclist->CurTxDesc;
+  uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
+  uint32_t descnbr = 0, idx;
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+  ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
+  uint32_t           bd_count = 0;
+
+  /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+  if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+  {
+    return HAL_ETH_ERROR_BUSY;
+  }
+
+  /***************************************************************************/
+  /*****************    Context descriptor configuration (Optional) **********/
+  /***************************************************************************/
+  /* If VLAN tag is enabled for this packet */
+  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+  {
+    /* Set vlan tag value */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
+    /* Set vlan tag valid bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_VLTV);
+    /* Set the descriptor as the vlan input source */
+    SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
+
+    /* if inner VLAN is enabled */
+    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
+    {
+      /* Set inner vlan tag value */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
+      /* Set inner vlan tag valid bit */
+      SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_IVLTV);
+
+      /* Set Vlan Tag control */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_IVTIR, pTxConfig->InnerVlanCtrl);
+
+      /* Set the descriptor as the inner vlan input source */
+      SET_BIT(heth->Instance->MACIVIR, ETH_MACIVIR_VLTI);
+      /* Enable double VLAN processing */
+      SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
+    }
+  }
+
+  /* if tcp segmentation is enabled for this packet */
+  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+  {
+    /* Set MSS value */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
+    /* Set MSS valid bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
+  }
+
+  if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
+  {
+    /* Set as context descriptor */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
+    /* Set own bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+    /* Increment current tx descriptor index */
+    INCR_TX_DESC_INDEX(descidx, 1U);
+    /* Get current descriptor address */
+    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+    descnbr += 1U;
+
+    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+    if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+    {
+      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
+      /* Clear own bit */
+      CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
+
+      return HAL_ETH_ERROR_BUSY;
+    }
+  }
+
+  /***************************************************************************/
+  /*****************    Normal descriptors configuration     *****************/
+  /***************************************************************************/
+
+  descnbr += 1U;
+
+  /* Set header or buffer 1 address */
+  WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+  /* Set header or buffer 1 Length */
+  MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+
+  if(txbuffer->next != NULL)
+  {
+    txbuffer = txbuffer->next;
+    /* Set buffer 2 address */
+    WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+    /* Set buffer 2 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+  }
+  else
+  {
+    WRITE_REG(dmatxdesc->DESC1, 0x0);
+    /* Set buffer 2 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+  }
+
+  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+  {
+    /* Set TCP Header length */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
+    /* Set TCP payload length */
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+    /* Set TCP Segmentation Enabled bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+  }
+  else
+  {
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+
+    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+    {
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+    }
+
+    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
+    {
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
+    }
+  }
+
+  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+  {
+    /* Set Vlan Tag control */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
+  }
+
+  /* Mark it as First Descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+  /* Mark it as NORMAL descriptor */
+  CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+  /* set OWN bit of FIRST descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+
+  /* If source address insertion/replacement is enabled for this packet */
+  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
+  {
+    MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
+  }
+
+  /* only if the packet is split into more than one descriptors > 1 */
+  while (txbuffer->next != NULL)
+  {
+    /* Clear the LD bit of previous descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+    /* Increment current tx descriptor index */
+    INCR_TX_DESC_INDEX(descidx, 1U);
+    /* Get current descriptor address */
+    dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+    /* Clear the FD bit of new Descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
+
+    /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
+    if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+    {
+      descidx = firstdescidx;
+      dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+      /* clear previous desc own bit */
+      for(idx = 0; idx < descnbr; idx ++)
+      {
+        CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+
+        /* Increment current tx descriptor index */
+        INCR_TX_DESC_INDEX(descidx, 1U);
+        /* Get current descriptor address */
+        dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+      }
+
+      return HAL_ETH_ERROR_BUSY;
+    }
+
+    descnbr += 1U;
+
+    /* Get the next Tx buffer in the list */
+    txbuffer = txbuffer->next;
+
+    /* Set header or buffer 1 address */
+    WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer);
+    /* Set header or buffer 1 Length */
+    MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
+
+    if (txbuffer->next != NULL)
+    {
+      /* Get the next Tx buffer in the list */
+      txbuffer = txbuffer->next;
+      /* Set buffer 2 address */
+      WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer);
+      /* Set buffer 2 Length */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16));
+    }
+    else
+    {
+      WRITE_REG(dmatxdesc->DESC1, 0x0);
+      /* Set buffer 2 Length */
+      MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
+    }
+
+    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+    {
+      /* Set TCP payload length */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
+      /* Set TCP Segmentation Enabled bit */
+      SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE);
+    }
+    else
+    {
+      /* Set the packet length */
+      MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
+
+      if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+      {
+        /* Checksum Insertion Control */
+        MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
+      }
+    }
+
+    bd_count += 1U;
+    /* Set Own bit */
+    SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
+    /* Mark it as NORMAL descriptor */
+    CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+  }
+
+  if(ItMode != ((uint32_t)RESET))
+  {
+    /* Set Interrupt on completion bit */
+    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+  }
+  else
+  {
+    /* Clear Interrupt on completion bit */
+    CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
+  }
+
+  /* Mark it as LAST descriptor */
+  SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
+  /* Save the current packet address to expose it to the application */
+  dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress;
+
+  dmatxdesclist->CurTxDesc = descidx;
+
+  /* disable the interrupt */
+  __disable_irq();
+
+  dmatxdesclist->BuffersInUse += bd_count + 1U;
+
+  /* Enable interrupts back */
+  __enable_irq();
+
+
+  /* Return function status */
+  return HAL_ETH_ERROR_NONE;
+}
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
+{
+  /* Init the ETH Callback settings */
+  heth->TxCpltCallback   = HAL_ETH_TxCpltCallback;    /* Legacy weak TxCpltCallback   */
+  heth->RxCpltCallback   = HAL_ETH_RxCpltCallback;    /* Legacy weak RxCpltCallback   */
+  heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;  /* Legacy weak DMAErrorCallback */
+  heth->MACErrorCallback = HAL_ETH_MACErrorCallback;  /* Legacy weak MACErrorCallback */
+  heth->PMTCallback      = HAL_ETH_PMTCallback;       /* Legacy weak PMTCallback      */
+  heth->EEECallback      = HAL_ETH_EEECallback;       /* Legacy weak EEECallback      */
+  heth->WakeUpCallback   = HAL_ETH_WakeUpCallback;    /* Legacy weak WakeUpCallback   */
+}
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH */
+
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex.c
new file mode 100644
index 0000000000..d22a0d33b0
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex.c
@@ -0,0 +1,556 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_eth_ex.c
+  * @author  MCD Application Team
+  * @brief   ETH HAL Extended module driver.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+
+#if defined(ETH)
+
+/** @defgroup ETHEx ETHEx
+  * @brief ETH HAL Extended module driver
+  * @{
+  */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup ETHEx_Private_Constants ETHEx Private Constants
+  * @{
+  */
+#define ETH_MACL4CR_MASK     (ETH_MACL3L4CR_L4PEN | ETH_MACL3L4CR_L4SPM | \
+                              ETH_MACL3L4CR_L4SPIM | ETH_MACL3L4CR_L4DPM | \
+                              ETH_MACL3L4CR_L4DPIM)
+
+#define ETH_MACL3CR_MASK     (ETH_MACL3L4CR_L3PEN | ETH_MACL3L4CR_L3SAM | \
+                              ETH_MACL3L4CR_L3SAIM | ETH_MACL3L4CR_L3DAM | \
+                              ETH_MACL3L4CR_L3DAIM | ETH_MACL3L4CR_L3HSBM | \
+                              ETH_MACL3L4CR_L3HDBM)
+
+#define ETH_MACRXVLAN_MASK (ETH_MACVTR_EIVLRXS | ETH_MACVTR_EIVLS | \
+                            ETH_MACVTR_ERIVLT | ETH_MACVTR_EDVLP | \
+                            ETH_MACVTR_VTHM | ETH_MACVTR_EVLRXS | \
+                            ETH_MACVTR_EVLS | ETH_MACVTR_DOVLTC | \
+                            ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL | \
+                            ETH_MACVTR_VTIM | ETH_MACVTR_ETV)
+
+#define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
+                            ETH_MACVIR_VLP | ETH_MACVIR_VLC)
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Functions ETH Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure ARP offload module
+      (+) Configure L3 and L4 filters
+      (+) Configure Extended VLAN features
+      (+) Configure Energy Efficient Ethernet module
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables ARP Offload.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
+{
+  SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
+}
+
+/**
+  * @brief  Disables ARP Offload.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth)
+{
+  CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
+}
+
+/**
+  * @brief  Set the ARP Match IP address
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  IpAddress: IP Address to be matched for incoming ARP requests
+  * @retval None
+  */
+void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
+{
+  WRITE_REG(heth->Instance->MACARPAR, IpAddress);
+}
+
+/**
+  * @brief  Configures the L4 Filter, this function allow to:
+  *         set the layer 4 protocol to be matched (TCP or UDP)
+  *         enable/disable L4 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L4 filter to configured, this parameter must be one of the following
+  *           ETH_L4_FILTER_0
+  *           ETH_L4_FILTER_1
+  * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
+  *         that contains L4 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef const *pL4FilterConfig)
+{
+  __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
+
+  if(pL4FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Write configuration to (MACL3L4C0R + filter )register */
+  MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
+                                            pL4FilterConfig->SrcPortFilterMatch |
+                                              pL4FilterConfig->DestPortFilterMatch));
+
+  configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
+
+  /* Write configuration to (MACL4A0R + filter )register */
+  MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
+                                                                                                                  (pL4FilterConfig->DestinationPort << 16)));
+
+  /* Enable L4 filter */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the L4 Filter, this function allow to:
+  *         set the layer 4 protocol to be matched (TCP or UDP)
+  *         enable/disable L4 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L4 filter to configured, this parameter must be one of the following
+  *           ETH_L4_FILTER_0
+  *           ETH_L4_FILTER_1
+  * @param  pL4FilterConfig: pointer to a ETH_L4FilterConfigTypeDef structure
+  *         that contains L4 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef const *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+{
+  if(pL4FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Get configuration to (MACL3L4C0R + filter )register */
+  pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
+  pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+  pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+
+  /* Get configuration to (MACL3L4C0R + filter )register */
+  pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
+  pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the L3 Filter, this function allow to:
+  *         set the layer 3 protocol to be matched (IPv4 or IPv6)
+  *         enable/disable L3 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L3 filter to configured, this parameter must be one of the following
+  *           ETH_L3_FILTER_0
+  *           ETH_L3_FILTER_1
+  * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
+  *         that contains L3 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef const *pL3FilterConfig)
+{
+  __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
+
+  if(pL3FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Write configuration to (MACL3L4C0R + filter )register */
+  MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+                                            pL3FilterConfig->SrcAddrFilterMatch |
+                                              pL3FilterConfig->DestAddrFilterMatch |
+                                                (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+                                                  (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+
+  /* Check if IPv6 protocol is selected */
+  if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+  {
+    /* Set the IPv6 address match */
+    /* Set Bits[31:0] of 128-bit IP addr */
+    *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
+    /* Set Bits[63:32] of 128-bit IP addr */
+    *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
+    /* update Bits[95:64] of 128-bit IP addr */
+    *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
+    /* update Bits[127:96] of 128-bit IP addr */
+    *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
+  }
+  else /* IPv4 protocol is selected */
+  {
+    /* Set the IPv4 source address match */
+    *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
+    /* Set the IPv4 destination address match */
+    *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the L3 Filter, this function allow to:
+  *         set the layer 3 protocol to be matched (IPv4 or IPv6)
+  *         enable/disable L3 source/destination port perfect/inverse match.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  Filter: L3 filter to configured, this parameter must be one of the following
+  *           ETH_L3_FILTER_0
+  *           ETH_L3_FILTER_1
+  * @param  pL3FilterConfig: pointer to a ETH_L3FilterConfigTypeDef structure
+  *         that will contain the L3 filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef const *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+{
+  if(pL3FilterConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
+  pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
+  pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
+  pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
+  pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
+
+  if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+  {
+    pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
+    pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
+    pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
+    pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
+  }
+  else
+  {
+    pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
+    pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables L3 and L4 filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth)
+{
+  /* Enable L3/L4 filter */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+}
+
+/**
+  * @brief  Disables L3 and L4 filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
+{
+  /* Disable L3/L4 filter */
+  CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+}
+
+/**
+  * @brief  Get the VLAN Configuration for Receive Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
+  *         that will contain the VLAN filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef const *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+{
+  if(pVlanConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
+  pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
+  pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
+  pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Configuration for Receive Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pVlanConfig: pointer to a ETH_RxVLANConfigTypeDef structure
+  *         that contains VLAN filter configuration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+{
+  if(pVlanConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Write config to MACVTR */
+  MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
+                                                          pVlanConfig->StripInnerVLANTag |
+                                                            ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
+                                                              ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
+                                                                ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
+                                                                  ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
+                                                                    pVlanConfig->StripVLANTag |
+                                                                      pVlanConfig->VLANTypeCheck |
+                                                                        ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Hash Table
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANHashTable: VLAN hash table 16 bit value
+  * @retval None
+  */
+void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
+{
+  MODIFY_REG(heth->Instance->MACVHTR, ETH_MACVHTR_VLHT, VLANHashTable);
+}
+
+/**
+  * @brief  Get the VLAN Configuration for Transmit Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
+  *                 ETH_OUTER_TX_VLANTAG
+  *                 ETH_INNER_TX_VLANTAG
+  * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
+  *         that will contain the Tx VLAN filter configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef const *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+{
+  if (pVlanConfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if(VLANTag == ETH_INNER_TX_VLANTAG)
+  {
+    pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACIVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
+  }
+  else
+  {
+    pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
+    pVlanConfig->VLANTagControl = READ_BIT(heth->Instance->MACVIR, (ETH_MACVIR_VLP | ETH_MACVIR_VLC));
+  }
+
+  return HAL_OK;;
+}
+
+/**
+  * @brief  Set the VLAN Configuration for Transmit Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
+  *                 ETH_OUTER_TX_VLANTAG
+  *                 ETH_INNER_TX_VLANTAG
+  * @param  pVlanConfig: pointer to a ETH_TxVLANConfigTypeDef structure
+  *         that contains Tx VLAN filter configuration.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef const *pVlanConfig)
+{
+  if(VLANTag == ETH_INNER_TX_VLANTAG)
+  {
+    MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
+                                                            ((uint32_t)pVlanConfig->SVLANType << 19) |
+                                                              pVlanConfig->VLANTagControl));
+    /* Enable Double VLAN processing */
+    SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
+                                                            ((uint32_t)pVlanConfig->SVLANType << 19) |
+                                                              pVlanConfig->VLANTagControl));
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the VLAN Tag Identifier for Transmit Packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  VLANTag: Selects the vlan tag, this parameter must be one of the following
+  *                 ETH_OUTER_TX_VLANTAG
+  *                 ETH_INNER_TX_VLANTAG
+  * @param  VLANIdentifier: VLAN Identifier 16 bit value
+  * @retval None
+  */
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
+{
+  if(VLANTag == ETH_INNER_TX_VLANTAG)
+  {
+    MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
+  }
+  else
+  {
+    MODIFY_REG(heth->Instance->MACVIR, ETH_MACVIR_VLT, VLANIdentifier);
+  }
+}
+
+/**
+  * @brief  Enables the VLAN Tag Filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth)
+{
+  /* Enable VLAN processing */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
+}
+
+/**
+  * @brief  Disables the VLAN Tag Filtering process.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None.
+  */
+void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth)
+{
+  /* Disable VLAN processing */
+  CLEAR_BIT(heth->Instance->MACPFR, ETH_MACPFR_VTFE);
+}
+
+/**
+  * @brief  Enters the Low Power Idle (LPI) mode
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  TxAutomate: Enable/Disable automate enter/exit LPI mode.
+  * @param  TxClockStop: Enable/Disable Tx clock stop in LPI mode.
+  * @retval None
+  */
+void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop)
+{
+  /* Enable LPI Interrupts */
+  __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
+
+  /* Write to LPI Control register: Enter low power mode */
+  MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
+                                                                                                       ((uint32_t)TxClockStop << 21) |
+                                                                                                         ETH_MACLCSR_LPIEN));
+}
+
+/**
+  * @brief  Exits the Low Power Idle (LPI) mode.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval None
+  */
+void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
+{
+  /* Clear the LPI Config and exit low power mode */
+  CLEAR_BIT(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE));
+
+  /* Enable LPI Interrupts */
+  __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
+}
+
+
+/**
+  * @brief  Returns the ETH MAC LPI event
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval ETH MAC WakeUp event
+  */
+uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef const *heth)
+{
+  return heth->MACLPIEvent;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH */
+
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED*/
+
+/**
+  * @}
+  */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex_legacy.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex_legacy.h
new file mode 100644
index 0000000000..966f293553
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_ex_legacy.h
@@ -0,0 +1,354 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_eth_ex_legacy.h
+  * @author  MCD Application Team
+  * @brief   Header file of ETH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_ETH_EX_LEGACY_H
+#define STM32H7xx_HAL_ETH_EX_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(ETH)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ETHEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ETH RX VLAN structure definition
+  */
+typedef struct{
+  FunctionalState InnerVLANTagInStatus;      /*!< Enables or disables Inner VLAN Tag in Rx Status  */
+
+  uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive
+                                                  This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
+
+  FunctionalState InnerVLANTag;              /*!< Enables or disables Inner VLAN Tag */
+
+  FunctionalState DoubleVLANProcessing;      /*!< Enable or Disable double VLAN processing */
+
+  FunctionalState VLANTagHashTableMatch;     /*!< Enable or Disable VLAN Tag Hash Table Match */
+
+  FunctionalState VLANTagInStatus;           /*!< Enable or Disable VLAN Tag in Rx status */
+
+  uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive
+                                                  This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
+
+  uint32_t VLANTypeCheck;                    /*!< Enable or Disable VLAN Type Check
+                                                  This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
+
+  FunctionalState VLANTagInverceMatch;       /*!< Enable or disable VLAN Tag Inverse Match */
+}ETH_RxVLANConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH TX VLAN structure definition
+  */
+typedef struct{
+  FunctionalState SourceTxDesc;   /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
+
+  FunctionalState SVLANType;      /*!< Enable or Disable insertion of SVLAN type */
+
+  uint32_t VLANTagControl;        /*!< Sets the VLAN tag control in tx packets
+                                      This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
+}ETH_TxVLANConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH L3 filter structure definition
+  */
+typedef struct{
+  uint32_t Protocol;                /*!< Sets the L3 filter protocol to IPv4 or IPv6
+                                         This parameter can be a value of @ref ETHEx_L3_Protocol */
+
+  uint32_t SrcAddrFilterMatch;      /*!< Sets the L3 filter source address match
+                                         This parameter can be a value of @ref ETHEx_L3_Source_Match */
+
+  uint32_t DestAddrFilterMatch;     /*!< Sets the L3 filter destination address match
+                                         This parameter can be a value of @ref ETHEx_L3_Destination_Match */
+
+  uint32_t SrcAddrHigherBitsMatch;  /*!< Sets the L3 filter source address higher bits match
+                                         This parameter can be a value from 0 to 31 */
+
+  uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
+                                         This parameter can be a value from 0 to 31 */
+
+  uint32_t Ip4SrcAddr;              /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
+                                         This parameter can be a value from 0x0 to 0xFFFFFFFF */
+
+  uint32_t Ip4DestAddr;             /*!< Sets the L3 filter IPv4 destination  address if IPv4 protocol is used
+                                         This parameter can be a value from 0 to 0xFFFFFFFF  */
+
+  uint32_t Ip6Addr[4];                 /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
+                                          This parameter must be a table of 4 words (4* 32 bits) */
+}ETH_L3FilterConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH L4 filter structure definition
+  */
+typedef struct{
+  uint32_t Protocol;               /*!< Sets the L4 filter protocol to TCP or UDP
+                                        This parameter can be a value of @ref ETHEx_L4_Protocol */
+
+  uint32_t SrcPortFilterMatch;     /*!< Sets the L4 filter source port match
+                                        This parameter can be a value of @ref ETHEx_L4_Source_Match */
+
+  uint32_t DestPortFilterMatch;    /*!< Sets the L4 filter destination port match
+                                        This parameter can be a value of @ref ETHEx_L4_Destination_Match */
+
+  uint32_t SourcePort;             /*!< Sets the L4 filter source port
+                                        This parameter must be a value from 0x0 to 0xFFFF */
+
+  uint32_t DestinationPort;        /*!< Sets the L4 filter destination port
+                                        This parameter must be a value from 0x0 to 0xFFFF */
+}ETH_L4FilterConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
+  * @{
+  */
+
+/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
+  * @{
+  */
+#define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN
+#define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX
+#define ETH_RX_LPI_ENTRY    ETH_MACLCSR_RLPIEN
+#define ETH_RX_LPI_EXIT     ETH_MACLCSR_RLPIEX
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
+  * @{
+  */
+#define ETH_L3_FILTER_0                 ((uint32_t)0x00000000)
+#define ETH_L3_FILTER_1                 ((uint32_t)0x0000000C)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
+  * @{
+  */
+#define ETH_L4_FILTER_0                 ((uint32_t)0x00000000)
+#define ETH_L4_FILTER_1                 ((uint32_t)0x0000000C)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
+  * @{
+  */
+#define ETH_L3_IPV6_MATCH                       ETH_MACL3L4CR_L3PEN
+#define ETH_L3_IPV4_MATCH                       ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
+  * @{
+  */
+#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L3SAM
+#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
+#define ETH_L3_SRC_ADDR_MATCH_DISABLE           ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
+  * @{
+  */
+#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L3DAM
+#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
+#define ETH_L3_DEST_ADDR_MATCH_DISABLE          ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
+  * @{
+  */
+#define ETH_L4_UDP_MATCH                        ETH_MACL3L4CR_L4PEN
+#define ETH_L4_TCP_MATCH                        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
+  * @{
+  */
+#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L4SPM
+#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
+#define ETH_L4_SRC_PORT_MATCH_DISABLE           ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
+  * @{
+  */
+#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L4DPM
+#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
+#define ETH_L4_DEST_PORT_MATCH_DISABLE          ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
+  * @{
+  */
+#define ETH_INNERVLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EIVLS_DONOTSTRIP
+#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EIVLS_STRIPIFPASS
+#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EIVLS_STRIPIFFAILS
+#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EIVLS_ALWAYSSTRIP
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
+  * @{
+  */
+#define ETH_VLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EVLS_DONOTSTRIP
+#define ETH_VLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EVLS_STRIPIFPASS
+#define ETH_VLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EVLS_STRIPIFFAILS
+#define ETH_VLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EVLS_ALWAYSSTRIP
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
+  * @{
+  */
+#define ETH_VLANTYPECHECK_DISABLE    ETH_MACVTR_DOVLTC
+#define ETH_VLANTYPECHECK_SVLAN      (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
+#define ETH_VLANTYPECHECK_CVLAN      ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
+  * @{
+  */
+#define ETH_VLANTAGCONTROL_NONE       (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
+#define ETH_VLANTAGCONTROL_DELETE     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
+#define ETH_VLANTAGCONTROL_INSERT     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
+#define ETH_VLANTAGCONTROL_REPLACE    (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
+/**
+  * @}
+  */
+
+/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
+  * @{
+  */
+#define ETH_INNER_TX_VLANTAG    ((uint32_t)0x00000001U)
+#define ETH_OUTER_TX_VLANTAG    ((uint32_t)0x00000000U)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ETHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ETHEx_Exported_Functions_Group1
+  * @{
+  */
+/* MAC ARP Offloading APIs  ***************************************************/
+void              HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
+
+/* MAC L3 L4 Filtering APIs ***************************************************/
+void              HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+
+/* MAC VLAN Processing APIs    ************************************************/
+void              HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
+void              HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+void              HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
+void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
+
+/* Energy Efficient Ethernet APIs *********************************************/
+void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
+void              HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
+uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_ETH_EX_LEGACY_H */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_legacy.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_legacy.h
new file mode 100644
index 0000000000..878036dd81
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/Legacy/stm32h7xx_hal_eth_legacy.h
@@ -0,0 +1,1682 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_eth_legacy.h
+  * @author  MCD Application Team
+  * @brief   Header file of ETH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_ETH_LEGACY_H
+#define STM32H7xx_HAL_ETH_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(ETH)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ETH
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#ifndef ETH_TX_DESC_CNT
+ #define ETH_TX_DESC_CNT         4U
+#endif
+
+#ifndef ETH_RX_DESC_CNT
+ #define ETH_RX_DESC_CNT         4U
+#endif
+
+/*********************** Descriptors struct def section ************************/
+/** @defgroup ETH_Exported_Types ETH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ETH DMA Descriptor structure definition
+  */
+typedef struct
+{
+  __IO uint32_t DESC0;
+  __IO uint32_t DESC1;
+  __IO uint32_t DESC2;
+  __IO uint32_t DESC3;
+  uint32_t BackupAddr0; /* used to store rx buffer 1 address */
+  uint32_t BackupAddr1; /* used to store rx buffer 2 address */
+}ETH_DMADescTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Buffers List structure definition
+  */
+typedef struct __ETH_BufferTypeDef
+{
+  uint8_t *buffer;                /*<! buffer address */
+
+  uint32_t len;                   /*<! buffer length */
+
+  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
+}ETH_BufferTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  DMA Transmit Descriptors Wrapper structure definition
+  */
+typedef struct
+{
+  uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
+
+  uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
+
+  uint32_t* PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
+
+  uint32_t* CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
+
+  uint32_t BuffersInUse;                   /*<! Buffers in Use */
+}ETH_TxDescListTypeDef;
+/**
+  *
+  */
+
+ /**
+  * @brief  Transmit Packet Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Attributes;              /*!< Tx packet HW features capabilities.
+                                         This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
+
+  uint32_t Length;                  /*!< Total packet length   */
+
+  ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
+
+  uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
+                                         This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
+
+  uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
+
+  uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
+
+  uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
+                                        This parameter can be a value from 0x0 to 0x3FFF */
+
+  uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
+                                        This parameter can be a value from 0x0 to 0x3FFFF */
+
+  uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
+                                        This parameter can be a value from 0x5 to 0xF */
+
+  uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
+                                        This parameter can be a value from 0x0 to 0xFFFF*/
+
+  uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
+
+  uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
+                                        This parameter can be a value from 0x0 to 0x3FFFF */
+
+  uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
+                                        This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
+
+}ETH_TxPacketConfig;
+/**
+  *
+  */
+
+/**
+ * @brief  DMA Receive Descriptors Wrapper structure definition
+ */
+typedef struct
+{
+  uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
+
+  uint32_t CurRxDesc;                   /*<! Current Rx descriptor, ready for next reception. */
+
+  uint32_t FirstAppDesc;                /*<! First descriptor of last received packet. */
+
+  uint32_t AppDescNbr;                  /*<! Number of descriptors of last received packet. */
+
+  uint32_t AppContextDesc;              /*<! If 1 a context descriptor is present in last received packet.
+                                             If 0 no context descriptor is present in last received packet. */
+
+  uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
+                                             If 0, DMA will not generate the Rx complete interrupt. */
+}ETH_RxDescListTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  Received Packet Information structure definition
+  */
+typedef struct
+{
+  uint32_t SegmentCnt;      /*<! Number of Rx Descriptors */
+
+  uint32_t VlanTag;         /*<! Vlan Tag value */
+
+  uint32_t InnerVlanTag;    /*<! Inner Vlan Tag value */
+
+  uint32_t Checksum;        /*<! Rx Checksum status.
+                                 This parameter can be a value of @ref ETH_Rx_Checksum_Status */
+
+  uint32_t HeaderType;      /*<! IP header type.
+                                 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
+
+  uint32_t PayloadType;     /*<! Payload type.
+                                 This parameter can be a value of @ref ETH_Rx_Payload_Type */
+
+  uint32_t MacFilterStatus; /*<! MAC filter status.
+                                 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
+
+  uint32_t L3FilterStatus;  /*<! L3 filter status
+                                 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
+
+  uint32_t L4FilterStatus;  /*<! L4 filter status
+                                 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
+
+  uint32_t ErrorCode;       /*<! Rx error code
+                                 This parameter can be a combination of @ref ETH_Rx_Error_Code */
+
+} ETH_RxPacketInfo;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH MAC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t         SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
+                                                     This parameter can be a value of @ref ETH_Source_Addr_Control */
+
+  FunctionalState  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
+
+  uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
+                                                     This parameter can be a value of @ref ETH_Inter_Packet_Gap */
+
+  FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
+
+  FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
+
+  FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
+
+  FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
+
+  FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path
+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
+                                                           When disabled, the MAC can receive up to 16384 bytes. */
+
+  FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path
+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
+                                                           When disabled, the MAC can send up to 16384 bytes. */
+
+  FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
+                                                           When enabled, the MAC allows jumbo packets of 9,018 bytes
+                                                           without reporting a giant packet error */
+
+  uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
+                                                           This parameter can be a value of @ref ETH_Speed */
+
+  uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */
+
+  FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
+
+  FunctionalState  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
+
+  FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
+
+  FunctionalState  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
+
+  FunctionalState  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
+
+  uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
+                                                        This parameter can be a value of @ref ETH_Back_Off_Limit */
+
+  FunctionalState  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
+
+  uint32_t         PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
+                                                           This parameter can be a value of @ref ETH_Preamble_Length */
+
+  FunctionalState  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
+
+  FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
+
+  FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
+
+  uint32_t         GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
+	                                                  greater than the value programmed in this field in units of bytes
+                                                          This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
+
+  FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
+
+  uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
+                                                           This parameter can be a value from 0x0 to 0xFF */
+
+  FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
+
+  uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
+                                                        This parameter can be a value of @ref ETH_Watchdog_Timeout */
+
+   uint32_t        PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
+                                                   This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+
+  FunctionalState  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
+
+  uint32_t         PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
+                                                   This parameter can be a value of @ref ETH_Pause_Low_Threshold */
+
+  FunctionalState  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
+                                                   or the MAC back pressure operation in Half Duplex mode */
+
+  FunctionalState  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
+
+  FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
+                                                  and disables its transmitter for a specified (Pause) time */
+
+  uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
+                                                      This parameter can be a value of @ref ETH_Transmit_Mode */
+
+  uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
+                                                             This parameter can be a value of @ref ETH_Receive_Mode */
+
+  FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
+
+  FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
+
+  FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
+} ETH_MACConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH DMA Configuration Structure definition
+  */
+ typedef struct
+ {
+   uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
+                                                         This parameter can be a value of @ref ETH_DMA_Arbitration */
+
+   FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
+                                                            burst transfers on Read and Write channels  */
+
+   uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
+                                                     This parameter can be a value of @ref ETH_Burst_Mode */
+
+   FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
+                                                   of any initiated burst transfer with INCRx and SINGLE transfers. */
+
+   FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
+
+   uint32_t        TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+                                                     This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+   FunctionalState SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
+                                                      Packet of Transmit data even before obtaining the status for the first one. */
+
+   uint32_t        RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+                                                    This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+
+   FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
+
+   FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
+
+   uint32_t        MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
+                                                  This parameter can be a value from 0x40 to 0x3FFF */
+} ETH_DMAConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Media Interfaces enum definition
+  */
+typedef enum
+{
+  HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
+  HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */
+}ETH_MediaInterfaceTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Init Structure definition
+  */
+typedef struct
+{
+
+  uint8_t                     *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
+  ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
+
+  ETH_DMADescTypeDef          *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
+
+  ETH_DMADescTypeDef          *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
+
+  uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
+
+}ETH_InitTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef uint32_t HAL_ETH_StateTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Handle Structure definition
+  */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+typedef struct __ETH_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  ETH_TypeDef                *Instance;                 /*!< Register base address       */
+
+  ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
+
+  ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
+                                                            addresses and current descriptor index  */
+
+  ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
+                                                            addresses and current descriptor index  */
+
+  HAL_LockTypeDef            Lock;                      /*!< Locking object             */
+
+  __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
+                                                              and also related to Tx operations.
+                                                             This parameter can be a value of @ref HAL_ETH_StateTypeDef */
+
+  __IO HAL_ETH_StateTypeDef  RxState;                   /*!< ETH state information related to Rx operations.
+                                                             This parameter can be a value of @ref HAL_ETH_StateTypeDef */
+
+  __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
+                                                             This parameter can be a value of of @ref ETH_Error_Code */
+
+  __IO uint32_t              DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
+                                                             This parameter can be a combination of @ref ETH_DMA_Status_Flags */
+
+  __IO uint32_t              MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
+                                                             This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
+
+  __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
+                                                             This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
+
+  __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
+                                                             This parameter can be a value of @ref ETHEx_LPI_Event */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+
+  void    (* TxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);   /*!< ETH Tx Complete Callback */
+  void    (* RxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Rx  Complete Callback     */
+  void    (* DMAErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH DMA Error Callback   */
+  void    (* MACErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH MAC Error Callback     */
+  void    (* PMTCallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Power Management Callback            */
+  void    (* EEECallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH EEE Callback   */
+  void    (* WakeUpCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Wake UP Callback   */
+
+  void    (* MspInitCallback)    ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp Init callback              */
+  void    (* MspDeInitCallback)  ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp DeInit callback            */
+
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+} ETH_HandleTypeDef;
+/**
+  *
+  */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ETH Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
+  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
+
+  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
+  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
+  HAL_ETH_DMA_ERROR_CB_ID          = 0x04U,    /*!< ETH DMA Error Callback ID         */
+  HAL_ETH_MAC_ERROR_CB_ID          = 0x05U,    /*!< ETH MAC Error Callback ID         */
+  HAL_ETH_PMT_CB_ID                = 0x06U,     /*!< ETH Power Management Callback ID  */
+  HAL_ETH_EEE_CB_ID                = 0x07U,     /*!< ETH EEE Callback ID               */
+  HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
+
+
+}HAL_ETH_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ETH Callback pointer definition
+  */
+typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @brief  ETH MAC filter structure definition
+  */
+typedef struct{
+  FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
+
+  FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
+
+  FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
+
+  FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
+
+  FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
+
+  FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
+
+  FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
+
+  FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
+
+  FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
+
+  FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
+
+  uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
+                                                 This parameter can be a value of @ref ETH_Control_Packets_Filter */
+}ETH_MACFilterConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Power Down structure definition
+  */
+typedef struct{
+  FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
+
+  FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
+
+  FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
+
+  FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
+
+}ETH_PowerDownConfigTypeDef;
+/**
+  *
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ETH_Exported_Constants ETH Exported Constants
+  * @{
+  */
+
+/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
+  * @{
+  */
+
+/*
+   DMA Tx Normal Descriptor Read Format
+  -----------------------------------------------------------------------------------------------
+  TDES0 |                         Buffer1 or Header Address  [31:0]                              |
+  -----------------------------------------------------------------------------------------------
+  TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |
+  -----------------------------------------------------------------------------------------------
+  TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |
+  -----------------------------------------------------------------------------------------------
+  TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
+  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of TDES0 RF register
+  */
+#define ETH_DMATXNDESCRF_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
+
+/**
+  * @brief  Bit definition of TDES1 RF register
+  */
+#define ETH_DMATXNDESCRF_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
+
+/**
+  * @brief  Bit definition of TDES2 RF register
+  */
+#define ETH_DMATXNDESCRF_IOC          ((uint32_t)0x80000000U)  /*!< Interrupt on Completion */
+#define ETH_DMATXNDESCRF_TTSE         ((uint32_t)0x40000000U)  /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCRF_B2L          ((uint32_t)0x3FFF0000U)  /*!< Buffer 2 Length */
+#define ETH_DMATXNDESCRF_VTIR         ((uint32_t)0x0000C000U)  /*!< VLAN Tag Insertion or Replacement mask */
+#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)  /*!< Do not add a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REMOVE  ((uint32_t)0x00004000U)  /*!< Remove the VLAN tag from the packets before transmission. */
+#define ETH_DMATXNDESCRF_VTIR_INSERT  ((uint32_t)0x00008000U)  /*!< Insert a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)  /*!< Replace the VLAN tag. */
+#define ETH_DMATXNDESCRF_B1L          ((uint32_t)0x00003FFFU)  /*!< Buffer 1 Length */
+#define ETH_DMATXNDESCRF_HL           ((uint32_t)0x000003FFU)  /*!< Header Length */
+
+/**
+  * @brief  Bit definition of TDES3 RF register
+  */
+#define ETH_DMATXNDESCRF_OWN                                 ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCRF_CTXT                                ((uint32_t)0x40000000U)  /*!< Context Type */
+#define ETH_DMATXNDESCRF_FD                                  ((uint32_t)0x20000000U)  /*!< First Descriptor */
+#define ETH_DMATXNDESCRF_LD                                  ((uint32_t)0x10000000U)  /*!< Last Descriptor */
+#define ETH_DMATXNDESCRF_CPC                                 ((uint32_t)0x0C000000U)  /*!< CRC Pad Control mask */
+#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   ((uint32_t)0x00000000U)  /*!< CRC Pad Control: CRC and Pad Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      ((uint32_t)0x04000000U)  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
+#define ETH_DMATXNDESCRF_CPC_DISABLE                         ((uint32_t)0x08000000U)  /*!< CRC Pad Control: Disable CRC Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     ((uint32_t)0x0C000000U)  /*!< CRC Pad Control: CRC Replacement */
+#define ETH_DMATXNDESCRF_SAIC                                ((uint32_t)0x03800000U)  /*!< SA Insertion Control mask*/
+#define ETH_DMATXNDESCRF_SAIC_DISABLE                        ((uint32_t)0x00000000U)  /*!< SA Insertion Control: Do not include the source address */
+#define ETH_DMATXNDESCRF_SAIC_INSERT                         ((uint32_t)0x00800000U)  /*!< SA Insertion Control: Include or insert the source address */
+#define ETH_DMATXNDESCRF_SAIC_REPLACE                        ((uint32_t)0x01000000U)  /*!< SA Insertion Control: Replace the source address */
+#define ETH_DMATXNDESCRF_THL                                 ((uint32_t)0x00780000U)  /*!< TCP Header Length */
+#define ETH_DMATXNDESCRF_TSE                                 ((uint32_t)0x00040000U)  /*!< TCP segmentation enable */
+#define ETH_DMATXNDESCRF_CIC                                 ((uint32_t)0x00030000U)  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXNDESCRF_CIC_DISABLE                         ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is disabled */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    ((uint32_t)0x00010000U)  /*!< Only IP header checksum calculation and insertion are enabled. */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            ((uint32_t)0x00020000U)  /*!< IP header checksum and payload checksum calculation and insertion are
+                                                                                          enabled, but pseudo header checksum is not calculated in hardware */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ((uint32_t)0x00030000U)  /*!< IP Header checksum and payload checksum calculation and insertion are
+                                                                                          enabled, and pseudo header checksum is calculated in hardware. */
+#define ETH_DMATXNDESCRF_TPL                                 ((uint32_t)0x0003FFFFU)  /*!< TCP Payload Length */
+#define ETH_DMATXNDESCRF_FL                                  ((uint32_t)0x00007FFFU)  /*!< Transmit End of Ring */
+
+/*
+   DMA Tx Normal Descriptor Write Back Format
+  -----------------------------------------------------------------------------------------------
+  TDES0 |                         Timestamp Low                                                  |
+  -----------------------------------------------------------------------------------------------
+  TDES1 |                         Timestamp High                                                 |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |                           Reserved[31:0]                                               |
+  -----------------------------------------------------------------------------------------------
+  TDES3 | OWN(31) |                          Status[30:0]                                        |
+  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of TDES0 WBF register
+  */
+#define ETH_DMATXNDESCWBF_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
+
+/**
+  * @brief  Bit definition of TDES1 WBF register
+  */
+#define ETH_DMATXNDESCWBF_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */
+
+/**
+  * @brief  Bit definition of TDES3 WBF register
+  */
+#define ETH_DMATXNDESCWBF_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCWBF_CTXT                    ((uint32_t)0x40000000U)  /*!< Context Type */
+#define ETH_DMATXNDESCWBF_FD                      ((uint32_t)0x20000000U)  /*!< First Descriptor */
+#define ETH_DMATXNDESCWBF_LD                      ((uint32_t)0x10000000U)  /*!< Last Descriptor */
+#define ETH_DMATXNDESCWBF_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Timestamp Status */
+#define ETH_DMATXNDESCWBF_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */
+#define ETH_DMATXNDESCWBF_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCWBF_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
+#define ETH_DMATXNDESCWBF_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */
+#define ETH_DMATXNDESCWBF_FF                      ((uint32_t)0x00002000U)  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
+#define ETH_DMATXNDESCWBF_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */
+#define ETH_DMATXNDESCWBF_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXNDESCWBF_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXNDESCWBF_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXNDESCWBF_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXNDESCWBF_CC                      ((uint32_t)0x000000F0U)  /*!< Collision Count */
+#define ETH_DMATXNDESCWBF_ED                      ((uint32_t)0x00000008U)  /*!< Excessive Deferral */
+#define ETH_DMATXNDESCWBF_UF                      ((uint32_t)0x00000004U)  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXNDESCWBF_DB                      ((uint32_t)0x00000002U)  /*!< Deferred Bit */
+#define ETH_DMATXNDESCWBF_IHE                     ((uint32_t)0x00000004U)  /*!< IP Header Error */
+
+
+/*
+   DMA Tx Context Descriptor
+  -----------------------------------------------------------------------------------------------
+  TDES0 |                               Timestamp Low                                            |
+  -----------------------------------------------------------------------------------------------
+  TDES1 |                               Timestamp High                                           |
+  -----------------------------------------------------------------------------------------------
+  TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
+  -----------------------------------------------------------------------------------------------
+  TDES3 | OWN(31) |                          Status[30:0]                                        |
+  -----------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 0
+  */
+#define ETH_DMATXCDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 1
+  */
+#define ETH_DMATXCDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 2
+  */
+#define ETH_DMATXCDESC_IVT   ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag */
+#define ETH_DMATXCDESC_MSS   ((uint32_t)0x00003FFFU)  /*!< Maximum Segment Size */
+
+/**
+  * @brief  Bit definition of Tx context descriptor register 3
+  */
+#define ETH_DMATXCDESC_OWN                     ((uint32_t)0x80000000U)     /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXCDESC_CTXT                    ((uint32_t)0x40000000U)     /*!< Context Type */
+#define ETH_DMATXCDESC_OSTC                    ((uint32_t)0x08000000U)     /*!< One-Step Timestamp Correction Enable */
+#define ETH_DMATXCDESC_TCMSSV                  ((uint32_t)0x04000000U)     /*!< One-Step Timestamp Correction Input or MSS Valid */
+#define ETH_DMATXCDESC_CDE                     ((uint32_t)0x00800000U)     /*!< Context Descriptor Error */
+#define ETH_DMATXCDESC_IVTIR                   ((uint32_t)0x000C0000U)     /*!< Inner VLAN Tag Insert or Replace Mask */
+#define ETH_DMATXCDESC_IVTIR_DISABLE           ((uint32_t)0x00000000U)     /*!< Do not add the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REMOVE            ((uint32_t)0x00040000U)     /*!< Remove the inner VLAN tag from the packets before transmission. */
+#define ETH_DMATXCDESC_IVTIR_INSERT            ((uint32_t)0x00080000U)     /*!< Insert the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REPLACE           ((uint32_t)0x000C0000U)     /*!< Replace the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVLTV                   ((uint32_t)0x00020000U)     /*!< Inner VLAN Tag Valid */
+#define ETH_DMATXCDESC_VLTV                    ((uint32_t)0x00010000U)     /*!< VLAN Tag Valid */
+#define ETH_DMATXCDESC_VT                      ((uint32_t)0x0000FFFFU)     /*!< VLAN Tag */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
+  * @{
+  */
+
+/*
+  DMA Rx Normal Descriptor read format
+  -----------------------------------------------------------------------------------------------------------
+  RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
+  -----------------------------------------------------------------------------------------------------------
+  RDES1 |                                            Reserved                                               |
+  -----------------------------------------------------------------------------------------------------------
+  RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
+  -----------------------------------------------------------------------------------------------------------
+  RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
+  -----------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 0 read format
+  */
+#define ETH_DMARXNDESCRF_BUF1AP        ((uint32_t)0xFFFFFFFFU)  /*!< Header or Buffer 1 Address Pointer  */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 2 read format
+  */
+#define ETH_DMARXNDESCRF_BUF2AP        ((uint32_t)0xFFFFFFFFU)  /*!< Buffer 2 Address Pointer  */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 3 read format
+  */
+#define ETH_DMARXNDESCRF_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARXNDESCRF_IOC         ((uint32_t)0x40000000U)  /*!< Interrupt Enabled on Completion  */
+#define ETH_DMARXNDESCRF_BUF2V       ((uint32_t)0x02000000U)  /*!< Buffer 2 Address Valid */
+#define ETH_DMARXNDESCRF_BUF1V       ((uint32_t)0x01000000U)  /*!< Buffer 1 Address Valid */
+
+/*
+  DMA Rx Normal Descriptor write back format
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
+	---------------------------------------------------------------------------------------------------------------------
+  RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
+  ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 0 write back format
+  */
+#define ETH_DMARXNDESCWBF_IVT        ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag  */
+#define ETH_DMARXNDESCWBF_OVT        ((uint32_t)0x0000FFFFU)  /*!< Outer VLAN Tag  */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 1 write back format
+  */
+#define ETH_DMARXNDESCWBF_OPC             ((uint32_t)0xFFFF0000U)  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
+#define ETH_DMARXNDESCWBF_TD              ((uint32_t)0x00008000U)  /*!< Timestamp Dropped  */
+#define ETH_DMARXNDESCWBF_TSA             ((uint32_t)0x00004000U)  /*!< Timestamp Available  */
+#define ETH_DMARXNDESCWBF_PV              ((uint32_t)0x00002000U)  /*!< PTP Version  */
+#define ETH_DMARXNDESCWBF_PFT             ((uint32_t)0x00001000U)  /*!< PTP Packet Type  */
+#define ETH_DMARXNDESCWBF_PMT_NO          ((uint32_t)0x00000000U)  /*!< PTP Message Type: No PTP message received  */
+#define ETH_DMARXNDESCWBF_PMT_SYNC        ((uint32_t)0x00000100U)  /*!< PTP Message Type: SYNC (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_FUP         ((uint32_t)0x00000200U)  /*!< PTP Message Type: Follow_Up (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_DREQ        ((uint32_t)0x00000300U)  /*!< PTP Message Type: Delay_Req (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_DRESP       ((uint32_t)0x00000400U)  /*!< PTP Message Type: Delay_Resp (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_PDREQ       ((uint32_t)0x00000500U)  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_PDRESP      ((uint32_t)0x00000600U)  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   ((uint32_t)0x00000700U)  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    ((uint32_t)0x00000800U)  /*!< PTP Message Type: Announce  */
+#define ETH_DMARXNDESCWBF_PMT_MANAG       ((uint32_t)0x00000900U)  /*!< PTP Message Type: Management  */
+#define ETH_DMARXNDESCWBF_PMT_SIGN        ((uint32_t)0x00000A00U)  /*!< PTP Message Type: Signaling  */
+#define ETH_DMARXNDESCWBF_PMT_RESERVED    ((uint32_t)0x00000F00U)  /*!< PTP Message Type: PTP packet with Reserved message type  */
+#define ETH_DMARXNDESCWBF_IPCE            ((uint32_t)0x00000080U)  /*!< IP Payload Error */
+#define ETH_DMARXNDESCWBF_IPCB            ((uint32_t)0x00000040U)  /*!< IP Checksum Bypassed */
+#define ETH_DMARXNDESCWBF_IPV6            ((uint32_t)0x00000020U)  /*!< IPv6 header Present */
+#define ETH_DMARXNDESCWBF_IPV4            ((uint32_t)0x00000010U)  /*!< IPv4 header Present */
+#define ETH_DMARXNDESCWBF_IPHE            ((uint32_t)0x00000008U)  /*!< IP Header Error */
+#define ETH_DMARXNDESCWBF_PT              ((uint32_t)0x00000003U)  /*!< Payload Type mask */
+#define ETH_DMARXNDESCWBF_PT_UNKNOWN      ((uint32_t)0x00000000U)  /*!< Payload Type: Unknown type or IP/AV payload not processed */
+#define ETH_DMARXNDESCWBF_PT_UDP          ((uint32_t)0x00000001U)  /*!< Payload Type: UDP */
+#define ETH_DMARXNDESCWBF_PT_TCP          ((uint32_t)0x00000002U)  /*!< Payload Type: TCP  */
+#define ETH_DMARXNDESCWBF_PT_ICMP         ((uint32_t)0x00000003U)  /*!< Payload Type: ICMP */
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 2 write back format
+  */
+#define ETH_DMARXNDESCWBF_L3L4FM          ((uint32_t)0x20000000U)  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
+#define ETH_DMARXNDESCWBF_L4FM            ((uint32_t)0x10000000U)  /*!< Layer 4 Filter Match                  */
+#define ETH_DMARXNDESCWBF_L3FM            ((uint32_t)0x08000000U)  /*!< Layer 3 Filter Match                  */
+#define ETH_DMARXNDESCWBF_MADRM           ((uint32_t)0x07F80000U)  /*!< MAC Address Match or Hash Value       */
+#define ETH_DMARXNDESCWBF_HF              ((uint32_t)0x00040000U)  /*!< Hash Filter Status                    */
+#define ETH_DMARXNDESCWBF_DAF             ((uint32_t)0x00020000U)  /*!< Destination Address Filter Fail       */
+#define ETH_DMARXNDESCWBF_SAF             ((uint32_t)0x00010000U)  /*!< SA Address Filter Fail                */
+#define ETH_DMARXNDESCWBF_VF              ((uint32_t)0x00008000U)  /*!< VLAN Filter Status                    */
+#define ETH_DMARXNDESCWBF_ARPNR           ((uint32_t)0x00000400U)  /*!< ARP Reply Not Generated               */
+
+
+/**
+  * @brief  Bit definition of Rx normal descriptor register 3 write back format
+  */
+#define ETH_DMARXNDESCWBF_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit */
+#define ETH_DMARXNDESCWBF_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor */
+#define ETH_DMARXNDESCWBF_FD         ((uint32_t)0x20000000U)  /*!< First Descriptor */
+#define ETH_DMARXNDESCWBF_LD         ((uint32_t)0x10000000U)  /*!< Last Descriptor */
+#define ETH_DMARXNDESCWBF_RS2V       ((uint32_t)0x08000000U)  /*!< Receive Status RDES2 Valid */
+#define ETH_DMARXNDESCWBF_RS1V       ((uint32_t)0x04000000U)  /*!< Receive Status RDES1 Valid */
+#define ETH_DMARXNDESCWBF_RS0V       ((uint32_t)0x02000000U)  /*!< Receive Status RDES0 Valid */
+#define ETH_DMARXNDESCWBF_CE         ((uint32_t)0x01000000U)  /*!< CRC Error */
+#define ETH_DMARXNDESCWBF_GP         ((uint32_t)0x00800000U)  /*!< Giant Packet */
+#define ETH_DMARXNDESCWBF_RWT        ((uint32_t)0x00400000U)  /*!< Receive Watchdog Timeout */
+#define ETH_DMARXNDESCWBF_OE         ((uint32_t)0x00200000U)  /*!< Overflow Error */
+#define ETH_DMARXNDESCWBF_RE         ((uint32_t)0x00100000U)  /*!< Receive Error */
+#define ETH_DMARXNDESCWBF_DE         ((uint32_t)0x00080000U)  /*!< Dribble Bit Error */
+#define ETH_DMARXNDESCWBF_LT         ((uint32_t)0x00070000U)  /*!< Length/Type Field */
+#define ETH_DMARXNDESCWBF_LT_LP      ((uint32_t)0x00000000U)  /*!< The packet is a length packet */
+#define ETH_DMARXNDESCWBF_LT_TP      ((uint32_t)0x00010000U)  /*!< The packet is a type packet */
+#define ETH_DMARXNDESCWBF_LT_ARP     ((uint32_t)0x00030000U)  /*!< The packet is a ARP Request packet type */
+#define ETH_DMARXNDESCWBF_LT_VLAN    ((uint32_t)0x00040000U)  /*!< The packet is a type packet with VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_DVLAN   ((uint32_t)0x00050000U)  /*!< The packet is a type packet with Double VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_MAC     ((uint32_t)0x00060000U)  /*!< The packet is a MAC Control packet type */
+#define ETH_DMARXNDESCWBF_LT_OAM     ((uint32_t)0x00070000U)  /*!< The packet is a OAM packet type */
+#define ETH_DMARXNDESCWBF_ES         ((uint32_t)0x00008000U)  /*!< Error Summary */
+#define ETH_DMARXNDESCWBF_PL         ((uint32_t)0x00007FFFU)  /*!< Packet Length */
+
+/*
+  DMA Rx context Descriptor
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES0 |                                     Timestamp Low[31:0]                                                     |
+	---------------------------------------------------------------------------------------------------------------------
+  RDES1 |                                     Timestamp High[31:0]                                                    |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES2 |                                          Reserved                                                           |
+  ---------------------------------------------------------------------------------------------------------------------
+  RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
+  ---------------------------------------------------------------------------------------------------------------------
+*/
+
+/**
+  * @brief  Bit definition of Rx context descriptor register 0
+  */
+#define ETH_DMARXCDESC_RTSL        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp Low  */
+
+/**
+  * @brief  Bit definition of Rx context descriptor register 1
+  */
+#define ETH_DMARXCDESC_RTSH        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp High  */
+
+/**
+  * @brief  Bit definition of Rx context descriptor register 3
+  */
+#define ETH_DMARXCDESC_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit  */
+#define ETH_DMARXCDESC_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Frame_settings ETH frame settings
+  * @{
+  */
+#define ETH_MAX_PACKET_SIZE      ((uint32_t)1528U)    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                  ((uint32_t)4U)    /*!< Ethernet CRC */
+#define ETH_VLAN_TAG             ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_PAYLOAD          ((uint32_t)46U)    /*!< Minimum Ethernet payload size */
+#define ETH_MAX_PAYLOAD          ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD  ((uint32_t)9000U)    /*!< Jumbo frame payload size */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Error_Code ETH Error Code
+  * @{
+  */
+#define HAL_ETH_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
+#define HAL_ETH_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
+#define HAL_ETH_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
+#define HAL_ETH_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
+#define HAL_ETH_ERROR_DMA          ((uint32_t)0x00000008U)   /*!< DMA transfer error  */
+#define HAL_ETH_ERROR_MAC          ((uint32_t)0x00000010U)   /*!< MAC transfer error  */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
+  * @{
+  */
+#define ETH_TX_PACKETS_FEATURES_CSUM          ((uint32_t)0x00000001U)
+#define ETH_TX_PACKETS_FEATURES_SAIC          ((uint32_t)0x00000002U)
+#define ETH_TX_PACKETS_FEATURES_VLANTAG       ((uint32_t)0x00000004U)
+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  ((uint32_t)0x00000008U)
+#define ETH_TX_PACKETS_FEATURES_TSO           ((uint32_t)0x00000010U)
+#define ETH_TX_PACKETS_FEATURES_CRCPAD        ((uint32_t)0x00000020U)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
+  * @{
+  */
+#define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
+#define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
+#define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
+  * @{
+  */
+#define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
+#define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
+#define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
+#define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
+  * @{
+  */
+#define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
+#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
+  * @{
+  */
+#define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
+#define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
+#define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
+#define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
+  * @{
+  */
+#define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
+#define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
+#define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
+#define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
+  * @{
+  */
+#define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
+#define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
+#define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
+  * @{
+  */
+#define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
+#define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
+  * @{
+  */
+#define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
+#define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
+#define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
+#define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
+  * @{
+  */
+#define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
+#define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
+#define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
+#define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
+  * @{
+  */
+#define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
+#define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
+  * @{
+  */
+#define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
+#define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
+  * @{
+  */
+#define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
+#define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
+#define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
+#define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
+#define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
+#define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
+  * @{
+  */
+#define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
+#define ETH_DMAARBITRATION_RX1_TX1   ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
+#define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
+#define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
+#define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1
+#define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1
+#define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
+#define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
+#define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
+#define ETH_DMAARBITRATION_TX1_RX1   ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
+#define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
+#define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
+#define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
+#define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
+#define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
+#define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
+/**
+  * @}
+  */
+
+ /** @defgroup ETH_Burst_Mode ETH Burst Mode
+  * @{
+  */
+#define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
+#define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
+#define ETH_BURSTLENGTH_UNSPECIFIED     ((uint32_t)0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
+  * @{
+  */
+#define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
+#define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
+#define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
+#define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
+#define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
+#define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
+  * @{
+  */
+#define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
+#define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
+#define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
+#define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
+#define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
+#define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+  * @{
+  */
+#define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
+#define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
+#define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
+#define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
+#define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
+#define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
+#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
+#define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
+#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
+#define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
+#define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
+  * @{
+  */
+#define ETH_DMA_RX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
+#define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
+#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
+#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
+#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2
+#define ETH_DMA_TX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
+#define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
+#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
+#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
+#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2
+#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE
+#define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE
+#define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT
+#define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU
+#define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
+  * @{
+  */
+#define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
+#define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
+#define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
+#define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
+#define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
+#define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
+#define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
+#define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
+#define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Receive_Mode ETH Receive Mode
+  * @{
+  */
+#define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
+#define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
+#define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
+#define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
+#define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
+  * @{
+  */
+#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
+#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
+#define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
+#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
+#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
+#define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
+  * @{
+  */
+#define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
+#define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
+#define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
+#define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
+#define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
+#define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
+#define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
+#define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
+#define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
+#define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
+#define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
+#define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
+#define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
+#define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
+  * @{
+  */
+#define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
+#define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
+#define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
+#define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
+#define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
+#define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
+#define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
+#define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Speed  ETH Speed
+  * @{
+  */
+#define ETH_SPEED_10M        ((uint32_t)0x00000000U)
+#define ETH_SPEED_100M       ETH_MACCR_FES
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+  * @{
+  */
+#define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
+#define ETH_HALFDUPLEX_MODE       ((uint32_t)0x00000000U)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
+  * @{
+  */
+#define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
+#define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
+#define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
+#define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Preamble_Length ETH Preamble Length
+  * @{
+  */
+#define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
+#define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
+#define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
+  * @{
+  */
+#define ETH_SOURCEADDRESS_DISABLE           ((uint32_t)0x00000000U)
+#define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
+#define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
+#define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
+#define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1
+/**
+  * @}
+  */
+
+/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
+  * @{
+  */
+#define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
+#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
+#define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
+#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
+/**
+  * @}
+  */
+
+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
+  * @{
+  */
+#define ETH_VLANTAGCOMPARISON_16BIT          ((uint32_t)0x00000000U)
+#define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_addresses ETH MAC addresses
+  * @{
+  */
+#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)
+#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)
+#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)
+#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+  * @{
+  */
+#define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
+#define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
+#define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
+#define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
+#define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
+#define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
+  * @{
+  */
+#define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
+#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
+/**
+  * @}
+  */
+
+/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
+  * @{
+  */
+#define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
+#define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
+#define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
+#define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
+#define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
+#define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
+#define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_StateTypeDef ETH States
+  * @{
+  */
+#define HAL_ETH_STATE_RESET       ((uint32_t)0x00000000U)    /*!< Peripheral not yet Initialized or disabled */
+#define HAL_ETH_STATE_READY       ((uint32_t)0x00000010U)    /*!< Peripheral Communication started           */
+#define HAL_ETH_STATE_BUSY        ((uint32_t)0x00000023U)    /*!< an internal process is ongoing             */
+#define HAL_ETH_STATE_BUSY_TX     ((uint32_t)0x00000021U)    /*!< Transmission process is ongoing            */
+#define HAL_ETH_STATE_BUSY_RX     ((uint32_t)0x00000022U)    /*!< Reception process is ongoing               */
+#define HAL_ETH_STATE_ERROR       ((uint32_t)0x000000E0U)    /*!< Error State                                */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ETH_Exported_Macros ETH Exported Macros
+  * @{
+  */
+
+/** @brief Reset ETH handle state
+  * @param  __HANDLE__: specifies the ETH handle.
+  * @retval None
+  */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0)
+#else
+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
+                                                     } while(0)
+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enables the specified ETHERNET DMA interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  *   enabled @ref ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET DMA interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+  *   disabled. @ref ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+  * @retval The ETH DMA IT Source enabled or disabled
+  */
+#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Gets the ETHERNET DMA IT pending bit.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
+  * @retval The state of ETH DMA IT (SET or RESET)
+  */
+#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the ETHERNET DMA IT pending bit.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
+* @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+  * @retval The state of ETH DMA FLAG (SET or RESET).
+  */
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
+
+/**
+  * @brief  Clears the specified ETHERNET DMA flag.
+* @param  __HANDLE__: ETH Handle
+  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
+  * @retval The state of ETH DMA FLAG (SET or RESET).
+  */
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
+
+/**
+  * @brief  Enables the specified ETHERNET MAC interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled @ref ETH_MAC_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disables the specified ETHERNET MAC interrupts.
+  * @param  __HANDLE__   : ETH Handle
+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+  *   enabled @ref ETH_MAC_Interrupts
+  * @retval None
+  */
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
+  * @param  __HANDLE__: ETH Handle
+  * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
+  * @retval The state of ETH MAC IT (SET or RESET).
+  */
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                   (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
+
+/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
+#define ETH_WAKEUP_EXTI_LINE  ((uint32_t)0x00400000U)  /* !<  86 - 64 = 22 */
+
+/**
+  * @brief Enable the ETH WAKEUP Exti Line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval EXTI ETH WAKEUP Line Status.
+  */
+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))
+
+/**
+  * @brief Clear the ETH WAKEUP Exti flag.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
+
+#if defined(DUAL_CORE)
+/**
+  * @brief Enable the ETH WAKEUP Exti Line by Core2.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval EXTI ETH WAKEUP Line Status.
+  */
+#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))
+
+/**
+  * @brief Clear the ETH WAKEUP Exti flag.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
+  *   @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None.
+  */
+#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
+#endif
+
+/**
+  * @brief  enable rising edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
+                                                                (EXTI->RTSR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief  enable falling edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
+                                                                 (EXTI->FTSR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief  enable falling edge interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
+                                                                        (EXTI->FTSR3 |= (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
+  *  @arg ETH_WAKEUP_EXTI_LINE
+  * @retval None
+  */
+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
+
+/**
+  * @}
+  */
+
+/* Include ETH HAL Extension module */
+#include "stm32h7xx_hal_eth_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup ETH_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de initialization functions  **********************************/
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
+
+uint8_t           HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
+HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
+HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
+HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
+
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
+
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
+
+void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
+void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* MAC & DMA Configuration APIs  **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
+
+/* MAC VLAN Processing APIs    ************************************************/
+void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
+
+/* MAC L2 Packet Filtering APIs  **********************************************/
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
+
+/* MAC Power Down APIs    *****************************************************/
+void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
+void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
+
+/**
+  * @}
+  */
+
+/** @addtogroup ETH_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions  **************************************************/
+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetError(ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ETH */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_ETH_LEGACY_H */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.c
index 099fb4bc95..35eeb7e20b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.c
@@ -5,6 +5,17 @@
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -19,17 +30,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -47,11 +47,11 @@
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /**
- * @brief STM32H7xx HAL Driver version number V1.10.0
+ * @brief STM32H7xx HAL Driver version number
    */
 #define __STM32H7xx_HAL_VERSION_MAIN   (0x01UL) /*!< [31:24] main version */
-#define __STM32H7xx_HAL_VERSION_SUB1   (0x0AUL) /*!< [23:16] sub1 version */
-#define __STM32H7xx_HAL_VERSION_SUB2   (0x00UL) /*!< [15:8]  sub2 version */
+#define __STM32H7xx_HAL_VERSION_SUB1   (0x0BUL) /*!< [23:16] sub1 version */
+#define __STM32H7xx_HAL_VERSION_SUB2   (0x03UL) /*!< [15:8]  sub2 version */
 #define __STM32H7xx_HAL_VERSION_RC     (0x00UL) /*!< [7:0]  release candidate */
 #define __STM32H7xx_HAL_VERSION         ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
                                         |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
@@ -78,11 +78,11 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
-/** @defgroup HAL_Private_Functions  HAL Private Functions
+/** @addtogroup HAL_Exported_Functions
   * @{
   */
 
-/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+/** @addtogroup HAL_Group1
  *  @brief    Initialization and de-initialization functions
  *
 @verbatim
@@ -252,7 +252,7 @@ __weak void HAL_MspDeInit(void)
   * @note In the default implementation, SysTick timer is the source of time base.
   *       It is used to generate interrupts at regular time intervals.
   *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
-  *       The the SysTick interrupt must have higher priority (numerically lower)
+  *       the SysTick interrupt must have higher priority (numerically lower)
   *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
   *       The function is declared as __weak  to be overwritten  in case of other
   *       implementation  in user file.
@@ -292,7 +292,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
   * @}
   */
 
-/** @defgroup HAL_Group2 HAL Control functions
+/** @addtogroup HAL_Group2
  *  @brief    HAL Control functions
  *
 @verbatim
@@ -383,7 +383,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
 
 /**
   * @brief Return tick frequency.
-  * @retval tick period in Hz
+  * @retval Tick frequency.
+  *         Value of @ref HAL_TickFreqTypeDef.
   */
 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
 {
@@ -421,7 +422,7 @@ __weak void HAL_Delay(uint32_t Delay)
   * @brief Suspend Tick increment.
   * @note In the default implementation , SysTick timer is the source of time base. It is
   *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the the SysTick interrupt will be disabled and so Tick increment
+  *       is called, the SysTick interrupt will be disabled and so Tick increment
   *       is suspended.
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
@@ -437,7 +438,7 @@ __weak void HAL_SuspendTick(void)
   * @brief Resume Tick increment.
   * @note In the default implementation , SysTick timer is the source of time base. It is
   *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the the SysTick interrupt will be enabled and so Tick increment
+  *       is called, the SysTick interrupt will be enabled and so Tick increment
   *       is resumed.
   * @note This function is declared as __weak to be overwritten in case of other
   *       implementations in user file.
@@ -887,9 +888,6 @@ void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0)
 
   MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT0, Adc2AltRout0);
 }
-/**
-  * @}
-  */
 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/
 
 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT1)
@@ -905,16 +903,13 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1)
 
   MODIFY_REG(SYSCFG->ADC2ALT, SYSCFG_ADC2ALT_ADC2_ROUT1, Adc2AltRout1);
 }
-/**
-  * @}
-  */
 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
 
 /**
   * @brief  Enable the Debug Module during Domain1/CDomain SLEEP mode
   * @retval None
   */
-void HAL_EnableDBGSleepMode(void)
+void HAL_DBGMCU_EnableDBGSleepMode(void)
 {
   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
 }
@@ -923,7 +918,7 @@ void HAL_EnableDBGSleepMode(void)
   * @brief  Disable the Debug Module during Domain1/CDomain SLEEP mode
   * @retval None
   */
-void HAL_DisableDBGSleepMode(void)
+void HAL_DBGMCU_DisableDBGSleepMode(void)
 {
   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);
 }
@@ -933,7 +928,7 @@ void HAL_DisableDBGSleepMode(void)
   * @brief  Enable the Debug Module during Domain1/CDomain STOP mode
   * @retval None
   */
-void HAL_EnableDBGStopMode(void)
+void HAL_DBGMCU_EnableDBGStopMode(void)
 {
   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
 }
@@ -942,7 +937,7 @@ void HAL_EnableDBGStopMode(void)
   * @brief  Disable the Debug Module during Domain1/CDomain STOP mode
   * @retval None
   */
-void HAL_DisableDBGStopMode(void)
+void HAL_DBGMCU_DisableDBGStopMode(void)
 {
   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);
 }
@@ -951,7 +946,7 @@ void HAL_DisableDBGStopMode(void)
   * @brief  Enable the Debug Module during Domain1/CDomain STANDBY mode
   * @retval None
   */
-void HAL_EnableDBGStandbyMode(void)
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
 {
   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
 }
@@ -960,7 +955,7 @@ void HAL_EnableDBGStandbyMode(void)
   * @brief  Disable the Debug Module during Domain1/CDomain STANDBY mode
   * @retval None
   */
-void HAL_DisableDBGStandbyMode(void)
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
 {
   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
 }
@@ -1314,4 +1309,4 @@ void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , ui
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h
index 95a44bf59c..2e05881326 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h
@@ -7,13 +7,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -53,18 +52,30 @@ typedef enum
   */
 
 /* Exported constants --------------------------------------------------------*/
-
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
 /** @defgroup REV_ID device revision ID
   * @{
   */
 #define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */
+#define REV_ID_Z ((uint32_t)0x1001)  /*!< STM32H7 rev.Z */
+#define REV_ID_A ((uint32_t)0x1000)  /*!< STM32H7 rev.A */
 #define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */
+#if (STM32H7_DEV_ID == 0x450UL)
 #define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */
+#else
+#define REV_ID_X ((uint32_t)0x1007)  /*!< STM32H7 rev.X */
+#endif /* STM32H7_DEV_ID */
 #define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */
 
 /**
   * @}
   */
+  
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
 
 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
   * @{
@@ -231,7 +242,9 @@ typedef enum
   * @}
   */
 
-
+/**
+  * @}
+  */
 
 
 /** @defgroup EXTI_Event_Input_Config  Event Input Config
@@ -697,9 +710,14 @@ typedef enum
 /**
   * @}
   */
-
+/**
+  * @}
+  */
 
 /* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
 #if defined(DUAL_CORE)
 /** @defgroup ART_Exported_Macros ART Exported Macros
   * @{
@@ -836,6 +854,10 @@ typedef enum
   * @}
   */
 
+/** @defgroup DBG_Exported_Macros DBG Exported Macros
+  * @{
+  */
+
 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
   */
 #define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
@@ -1003,6 +1025,12 @@ typedef enum
 #define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
 
 #endif /*DUAL_CORE*/
+/**
+  * @}
+  */
+/**
+  * @}
+  */
 
 /** @defgroup HAL_Private_Macros HAL Private Macros
   * @{
@@ -1027,15 +1055,27 @@ extern HAL_TickFreqTypeDef uwTickFreq;
   */
 
 /* Exported functions --------------------------------------------------------*/
-
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
 /* Initialization and de-initialization functions  ******************************/
+/** @defgroup HAL_Group1 Initialization and de-initialization Functions
+  * @{
+  */
 HAL_StatusTypeDef HAL_Init(void);
 HAL_StatusTypeDef HAL_DeInit(void);
 void HAL_MspInit(void);
 void HAL_MspDeInit(void);
 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
 
+/**
+  * @}
+  */
+
 /* Peripheral Control functions  ************************************************/
+/** @defgroup HAL_Group2 HAL Control functions
+ *
+ */
 void HAL_IncTick(void);
 void HAL_Delay(uint32_t Delay);
 uint32_t HAL_GetTick(void);
@@ -1079,12 +1119,12 @@ void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG
 #if defined(SYSCFG_CCCR_NCC_MMC)
 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
 #endif /* SYSCFG_CCCR_NCC_MMC */
-void HAL_EnableDBGSleepMode(void);
-void HAL_DisableDBGSleepMode(void);
-void HAL_EnableDBGStopMode(void);
-void HAL_DisableDBGStopMode(void);
-void HAL_EnableDBGStandbyMode(void);
-void HAL_DisableDBGStandbyMode(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
 #if defined(DUAL_CORE)
 void HAL_EnableDomain2DBGSleepMode(void);
 void HAL_DisableDomain2DBGSleepMode(void);
@@ -1126,6 +1166,14 @@ void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0);
 void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/
 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -1140,4 +1188,4 @@ void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1);
 
 #endif /* STM32H7xx_HAL_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c
index 7803f9281e..f42169402e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c
@@ -5,20 +5,22 @@
   * @brief   This file provides firmware functions to manage the following
   *          functionalities of the Analog to Digital Converter (ADC)
   *          peripheral:
-  *           + Initialization and de-initialization functions
-  *             ++ Initialization and Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of regular
-  *                group, using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Channels configuration on regular group
-  *             ++ Analog Watchdog configuration
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
   *          Other functions (extended functions) are available in file
   *          "stm32h7xx_hal_adc_ex.c".
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### ADC peripheral features #####
@@ -221,11 +223,11 @@
 
      The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
      allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_ADC_RegisterCallback()
+     Use Functions HAL_ADC_RegisterCallback()
      to register an interrupt callback.
     [..]
 
-     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+     Function HAL_ADC_RegisterCallback() allows to register following callbacks:
        (+) ConvCpltCallback               : ADC conversion complete callback
        (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
        (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
@@ -241,11 +243,11 @@
      and a pointer to the user callback function.
     [..]
 
-     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+     Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
      weak function.
     [..]
 
-     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
      and the Callback ID.
      This function allows to reset following callbacks:
        (+) ConvCpltCallback               : ADC conversion complete callback
@@ -261,27 +263,27 @@
        (+) MspDeInitCallback              : ADC Msp DeInit callback
      [..]
 
-     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+     By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
      all callbacks are set to the corresponding weak functions:
-     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+     examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
      Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+     reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
      these callbacks are null (not registered beforehand).
     [..]
 
-     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+     If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
      [..]
 
-     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+     Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
      Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+     in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     [..]
 
      Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
-     or @ref HAL_ADC_Init() function.
+     using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
+     or HAL_ADC_Init() function.
      [..]
 
      When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
@@ -290,17 +292,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -2529,44 +2520,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
     /* group having no further conversion upcoming (same conditions as        */
     /* regular group interruption disabling above),                           */
     /* and if injected scan sequence is completed.                            */
-    if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
-        ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
-         ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
-          (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+    if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
     {
-      /* If End of Sequence is reached, disable interrupts */
-      if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+      if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+          ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+           (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
       {
-        /* Particular case if injected contexts queue is enabled:             */
-        /* when the last context has been fully processed, JSQR is reset      */
-        /* by the hardware. Even if no injected conversion is planned to come */
-        /* (queue empty, triggers are ignored), it can start again            */
-        /* immediately after setting a new context (JADSTART is still set).   */
-        /* Therefore, state of HAL ADC injected group is kept to busy.        */
-        if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
         {
-          /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
-          /* JADSTART==0 (no conversion on going)                             */
-          if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+          /* Particular case if injected contexts queue is enabled:             */
+          /* when the last context has been fully processed, JSQR is reset      */
+          /* by the hardware. Even if no injected conversion is planned to come */
+          /* (queue empty, triggers are ignored), it can start again            */
+          /* immediately after setting a new context (JADSTART is still set).   */
+          /* Therefore, state of HAL ADC injected group is kept to busy.        */
+          if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
           {
-            /* Disable ADC end of sequence conversion interrupt  */
-            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
-
-            /* Set ADC state */
-            CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
-
-            if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+            /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
+            /* JADSTART==0 (no conversion on going)                             */
+            if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
             {
-              SET_BIT(hadc->State, HAL_ADC_STATE_READY);
-            }
-          }
-          else
-          {
-            /* Update ADC state machine to error */
-            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+              /* Disable ADC end of sequence conversion interrupt  */
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
 
-            /* Set ADC error code to ADC peripheral internal error */
-            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+              /* Set ADC state */
+              CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+              if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+              {
+                SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+              }
+            }
+            else
+            {
+              /* Update ADC state machine to error */
+              SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+              /* Set ADC error code to ADC peripheral internal error */
+              SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+            }
           }
         }
       }
@@ -2895,17 +2888,19 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
   /*  - Channel rank                                                          */
   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
   {
-
-#if defined(ADC_VER_V5_V90)
-    if (hadc->Instance != ADC3)
+    if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
     {
-      /* ADC channels preselection */
-      hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
-    }
+#if defined(ADC_VER_V5_V90)
+      if (hadc->Instance != ADC3)
+      {
+        /* ADC channels preselection */
+        hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+      }
 #else
-    /* ADC channels preselection */
-    hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
+      /* ADC channels preselection */
+      hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
 #endif /* ADC_VER_V5_V90 */
+    }
 
     /* Set ADC group regular sequence: channel on the selected scan sequence rank */
     LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
@@ -4059,4 +4054,3 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h
index 155aaa7c7c..5eb79db68e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -131,8 +130,8 @@ typedef struct
                                        Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
                                                        Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
                                                        Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
-													   and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, 
-													   use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
+                                                       and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, 
+                                                       use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
 
   FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
                                        after the first ADC conversion start trigger occurred (software start or external trigger).
@@ -257,8 +256,8 @@ typedef struct
 
   uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.
                                         Offset value must be a positive number.
-                                        Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
-                                        0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
+                                        Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used).
+                                        This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024).
                                         Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
                                               without continuous mode or external trigger that could launch a conversion). */
 
@@ -756,14 +755,14 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
   * @{
   */
-#define ADC3_AWD_FILTERING_NONE          (0x00000000UL)                                                   /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_2SAMPLES      ((ADC3_TR1_AWDFILT_0))                                           /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_3SAMPLES      ((ADC3_TR1_AWDFILT_1))                                           /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_4SAMPLES      ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0))                      /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_5SAMPLES      ((ADC3_TR1_AWDFILT_2))                                           /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_6SAMPLES      ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0))                      /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_7SAMPLES      ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1))                      /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
-#define ADC3_AWD_FILTERING_8SAMPLES      ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_NONE          (0x00000000UL)                                                   /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_2SAMPLES      ((ADC3_TR1_AWDFILT_0))                                           /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_3SAMPLES      ((ADC3_TR1_AWDFILT_1))                                           /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_4SAMPLES      ((ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0))                      /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_5SAMPLES      ((ADC3_TR1_AWDFILT_2))                                           /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_6SAMPLES      ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_0))                      /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_7SAMPLES      ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1))                      /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
+#define ADC3_AWD_FILTERING_8SAMPLES      ((ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)) /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. Applicable for ADC3 on devices STM32H72xx and STM32H73xx */
 /**
   * @}
   */
@@ -911,7 +910,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
 #define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
 #define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
-
+#define ADC_FLAG_LDORDY        ADC_ISR_LDORDY   /*!< ADC LDO output voltage ready bit */
 /**
   * @}
   */
@@ -1373,7 +1372,8 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
   *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
   *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag
+  *            @arg @ref ADC_FLAG_LDORDY  ADC LDO output voltage ready bit.
   * @retval State of flag (TRUE or FALSE).
   */
 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
@@ -2032,4 +2032,3 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc);
 
 #endif /* STM32H7xx_HAL_ADC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c
index 8e44bf1e6e..749473f773 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c
@@ -5,20 +5,21 @@
   * @brief   This file provides firmware functions to manage the following
   *          functionalities of the Analog to Digital Converter (ADC)
   *          peripheral:
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of ADC group injected,
-  *                using 2 possible modes: polling, interruption.
-  *             ++ Calibration
-  *               +++ ADC automatic self-calibration
-  *               +++ Calibration factors get or set
-  *             ++ Multimode feature when available
-  *           + Control functions
-  *             ++ Channels configuration on ADC group injected
-  *           + State functions
-  *             ++ ADC group injected contexts queue management
+  *           + Peripheral Control functions
   *          Other functions (generic functions) are available in file
   *          "stm32h7xx_hal_adc.c".
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   [..]
   (@) Sections "ADC peripheral features" and "How to use this driver" are
@@ -26,17 +27,6 @@
   [..]
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -265,7 +255,9 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc,
   * @param SingleDiff This parameter can be only:
   *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
   *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
-  * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+  * @param CalibrationFactor Calibration factor On devices STM32H72xx and STM32H73xx this parameter is coded on 11 bits
+  *                                             maximum for ADC1/2 and on 7 bits for ADC3.
+  *                                             On devices STM32H74xx and STM32H75xx this parameter is coded on 11 bits.
   * @retval HAL state
   */
 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
@@ -277,7 +269,19 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32
   /* Check the parameters */
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+#if defined(ADC_VER_V5_V90)
+  if (hadc->Instance == ADC3)
+  {
+    assert_param(IS_ADC_CALFACT_ADC3(CalibrationFactor));
+  }
+  else
+  {
+    assert_param(IS_ADC_CALFACT(CalibrationFactor));
+  }
+#else
   assert_param(IS_ADC_CALFACT(CalibrationFactor));
+#endif
 
   /* Process locked */
   __HAL_LOCK(hadc);
@@ -1001,8 +1005,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
   *         Interruptions enabled in this function:
   *          overrun, DMA half transfer, DMA transfer complete.
   *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of ADC slave using its own DMA channel (typical case being both ADC instances using DMA channel
+  *         of ADC master with data concatenated): multimode must be configured without data packing and
+  *         this function must be called first with handle of ADC slave, then with handle of ADC master.
   * @note   State field of Slave ADC handle is not updated in this configuration:
-  *          user should not rely on it for information related to Slave regular
+  *         user should not rely on it for information related to Slave regular
   *         conversions.
   * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
   * @param pData Destination Buffer address.
@@ -1029,28 +1036,38 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
     /* Process locked */
     __HAL_LOCK(hadc);
 
-    tmphadcSlave.State = HAL_ADC_STATE_RESET;
-    tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
-    /* Set a temporary handle of the ADC slave associated to the ADC master   */
-    ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
-
-    if (tmphadcSlave.Instance == NULL)
+    /* Case of ADC slave using its own DMA channel: check whether handle selected
+       corresponds to ADC master or slave instance */
+    if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
     {
-      /* Set ADC state */
-      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hadc);
-
-      return HAL_ERROR;
+      /* Case of ADC slave selected: enable ADC instance */
+      tmp_hal_status = ADC_Enable(hadc);
     }
-
-    /* Enable the ADC peripherals: master and slave (in case if not already   */
-    /* enabled previously)                                                    */
-    tmp_hal_status = ADC_Enable(hadc);
-    if (tmp_hal_status == HAL_OK)
+    else
     {
-      tmp_hal_status = ADC_Enable(&tmphadcSlave);
+      tmphadcSlave.State = HAL_ADC_STATE_RESET;
+      tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
+      /* Set a temporary handle of the ADC slave associated to the ADC master   */
+      ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
+
+      if (tmphadcSlave.Instance == NULL)
+      {
+        /* Set ADC state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+
+        return HAL_ERROR;
+      }
+
+      /* Enable the ADC peripherals: master and slave (in case if not already   */
+      /* enabled previously)                                                    */
+      tmp_hal_status = ADC_Enable(hadc);
+      if (tmp_hal_status == HAL_OK)
+      {
+        tmp_hal_status = ADC_Enable(&tmphadcSlave);
+      }
     }
 
     /* Start multimode conversion of ADCs pair */
@@ -1073,9 +1090,6 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
       /* Set the DMA error callback */
       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
 
-      /* Pointer to the common control register  */
-      tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
-
       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
       /* start (in case of SW start):                                           */
 
@@ -1091,15 +1105,29 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t
       /* Enable ADC overrun interrupt */
       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
 
-      /* Start the DMA channel */
-      tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+      /* Case of ADC slave using its own DMA channel: check whether handle selected
+         corresponds to ADC master or slave instance */
+      if (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) != hadc->Instance)
+      {
+        /* Case of ADC slave selected: Start the DMA channel. */
+        /* Note: Data transfer will start upon next call of this function using handle of ADC master */
+        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+      }
+      else
+      {
+        /* Pointer to the common control register  */
+        tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
 
-      /* Enable conversion of regular group.                                    */
-      /* If software start has been selected, conversion starts immediately.    */
-      /* If external trigger has been selected, conversion will start at next   */
-      /* trigger event.                                                         */
-      /* Start ADC group regular conversion */
-      LL_ADC_REG_StartConversion(hadc->Instance);
+        /* Start the DMA channel */
+        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+        /* Enable conversion of regular group.                                    */
+        /* If software start has been selected, conversion starts immediately.    */
+        /* If external trigger has been selected, conversion will start at next   */
+        /* trigger event.                                                         */
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
     }
     else
     {
@@ -2025,16 +2053,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
   /*    mode is disabled.                                                     */
   if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
   {
-#if defined(ADC_VER_V5_V90)
-    if (hadc->Instance != ADC3)
+    if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel)))
     {
-      /* ADC channels preselection */
-      hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
-    }
+#if defined(ADC_VER_V5_V90)
+      if (hadc->Instance != ADC3)
+      {
+        /* ADC channels preselection */
+        hadc->Instance->PCSEL_RES0 |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
+      }
 #else
-    /* ADC channels preselection */
-    hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
+      /* ADC channels preselection */
+      hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
 #endif /* ADC_VER_V5_V90 */
+    }
 
     /* If auto-injected mode is disabled: no constraint                       */
     if (sConfigInjected->AutoInjectedConv == DISABLE)
@@ -2102,7 +2133,18 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
 
     if (sConfigInjected->InjecOversamplingMode == ENABLE)
     {
+#if defined(ADC_VER_V5_V90)
+      if (hadc->Instance == ADC3)
+      {
+        assert_param(IS_ADC_OVERSAMPLING_RATIO_ADC3(sConfigInjected->InjecOversampling.Ratio));
+      }
+      else
+      {
+        assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+      }
+#else
       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
+#endif
       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
 
       /*  JOVSE must be reset in case of triggered regular mode  */
@@ -2113,14 +2155,39 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
       /*  - Right bit shift                                                     */
 
       /* Enable OverSampling mode */
+#if defined(ADC_VER_V5_V90)
+      if (hadc->Instance != ADC3)
+      {
+        MODIFY_REG(hadc->Instance->CFGR2,
+                   ADC_CFGR2_JOVSE |
+                   ADC_CFGR2_OVSR  |
+                   ADC_CFGR2_OVSS,
+                   ADC_CFGR2_JOVSE                                  |
+                  ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+                   sConfigInjected->InjecOversampling.RightBitShift
+                  );
+      }
+      else
+      {
+        MODIFY_REG(hadc->Instance->CFGR2,
+                   ADC_CFGR2_JOVSE |
+                   ADC3_CFGR2_OVSR  |
+                   ADC_CFGR2_OVSS,
+                   ADC_CFGR2_JOVSE                                  |
+                  (sConfigInjected->InjecOversampling.Ratio)        |
+                   sConfigInjected->InjecOversampling.RightBitShift
+                  );
+      }
+#else
       MODIFY_REG(hadc->Instance->CFGR2,
-                 ADC_CFGR2_JOVSE |
-                 ADC_CFGR2_OVSR  |
-                 ADC_CFGR2_OVSS,
-                 ADC_CFGR2_JOVSE                                  |
-                ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
-                 sConfigInjected->InjecOversampling.RightBitShift
-                );
+           ADC_CFGR2_JOVSE |
+           ADC_CFGR2_OVSR  |
+           ADC_CFGR2_OVSS,
+           ADC_CFGR2_JOVSE                                  |
+          ((sConfigInjected->InjecOversampling.Ratio - 1UL) << ADC_CFGR2_OVSR_Pos) |
+           sConfigInjected->InjecOversampling.RightBitShift
+          );
+#endif
     }
     else
     {
@@ -2145,7 +2212,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
     {
       tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
     }
-    
+
     if (sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
     {
       /* Set ADC selected offset number */
@@ -2590,4 +2657,3 @@ HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h
index ae185074db..aaf6d751fa 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -113,8 +112,8 @@ typedef struct
 
   uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.
                                                Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
-                                               between Min_Data = 0x000 and Max_Data = 0xFFF,  0x3FF, 0xFF or 0x3F respectively.
+                                               Maximum value depends on ADC resolution and oversampling ratio (in case of oversampling used).
+                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFFC00 (corresponding to resolution 16 bit and oversampling ratio 1024).
                                                Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
                                                without continuous mode or external trigger that could launch a conversion). */
 
@@ -138,7 +137,7 @@ typedef struct
   FunctionalState InjectedOffsetSignedSaturation;      /*!< Specifies whether the Signed saturation feature is used or not.
                                                This parameter is applied only for 16-bit or 8-bit resolution.
                                                This parameter can be set to ENABLE or DISABLE. */
-  
+
   uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
                                                To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
                                                This parameter must be a number between Min_Data = 1 and Max_Data = 4.
@@ -250,8 +249,10 @@ typedef struct
 #define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
 #define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#if defined(HRTIM1)
 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)      /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)      /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
+#endif /* HRTIM1 */
 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */
@@ -917,12 +918,20 @@ typedef struct
 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
 
 /**
-  * @brief Calibration factor size verification (7 bits maximum).
+  * @brief Calibration factor size verification (11 bits maximum).
   * @param __CALIBRATION_FACTOR__ Calibration factor value.
   * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
   */
-#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FFU))
 
+#if defined(ADC_VER_V5_V90)
+/**
+  * @brief Calibration factor size verification (7 bits maximum on ADC3).
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+  */
+#define IS_ADC_CALFACT_ADC3(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+#endif
 
 /**
   * @brief Verify the ADC channel setting.
@@ -1044,6 +1053,7 @@ typedef struct
   * @param __INJTRIG__ programmed ADC injected conversions external trigger.
   * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
   */
+#if defined (HRTIM1)
 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
@@ -1060,9 +1070,36 @@ typedef struct
                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
                                           ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT)  || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT)  || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT)  || \
                                                                                           \
                                            ((__INJTRIG__) == ADC_SOFTWARE_START)                   )
-
+#else
+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT)  || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT)  || \
+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT)  || \
+                                                                                          \
+                                           ((__INJTRIG__) == ADC_SOFTWARE_START)                   )
+#endif /* HRTIM */
 /**
   * @brief Verify the ADC edge trigger setting for injected group.
   * @param __EDGE__ programmed ADC edge trigger setting.
@@ -1349,4 +1386,3 @@ HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *h
 #endif /* STM32H7xx_HAL_ADC_EX_H */
 
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c
index d732a36d6a..8a2dd6ddce 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c
@@ -11,6 +11,17 @@
   *           + Peripheral Control function
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -47,10 +58,10 @@
 
   The compilation define  USE_HAL_CEC_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
-  Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
+  Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback()
   to register an interrupt callback.
 
-  Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks:
+  Function HAL_CEC_RegisterCallback() allows to register following callbacks:
     (+) TxCpltCallback     : Tx Transfer completed callback.
     (+) ErrorCallback      : callback for error detection.
     (+) MspInitCallback    : CEC MspInit.
@@ -59,11 +70,11 @@
   and a pointer to the user callback function.
 
   For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks
-  @ref HAL_CEC_RegisterRxCpltCallback().
+  HAL_CEC_RegisterRxCpltCallback().
 
-  Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default
+  Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default
   weak function.
-  @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
   and the Callback ID.
   This function allows to reset following callbacks:
     (+) TxCpltCallback     : Tx Transfer completed callback.
@@ -72,15 +83,15 @@
     (+) MspDeInitCallback  : CEC MspDeInit.
 
   For callback HAL_CEC_RxCpltCallback use dedicated unregister callback :
-  @ref HAL_CEC_UnRegisterRxCpltCallback().
+  HAL_CEC_UnRegisterRxCpltCallback().
 
-  By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
+  By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET
   all callbacks are set to the corresponding weak functions :
-  examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback().
+  examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback().
   Exception done for MspInit and MspDeInit functions that are
-  reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when
+  reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when
   these callbacks are null (not registered beforehand).
-  if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit()
+  if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit()
   keep and use the user MspInit/MspDeInit functions (registered beforehand)
 
   Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only.
@@ -88,25 +99,14 @@
   in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state,
   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit()
-  or @ref HAL_CEC_Init() function.
+  using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit()
+  or HAL_CEC_Init() function.
 
   When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or
   not defined, the callback registration feature is not available and all callbacks
   are set to the corresponding weak functions.
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -233,7 +233,8 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
 
   /* Write to CEC Control Register */
   hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \
-                         hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen | \
+                         hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \
+                         hcec->Init.BroadcastMsgNoErrorBitGen | \
                          hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \
                          hcec->Init.ListenMode;
 
@@ -412,10 +413,10 @@ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
   * @param  hcec CEC handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
-  *          @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
-  *          @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+  *          @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+  *          @arg HAL_CEC_ERROR_CB_ID Error callback ID
+  *          @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
@@ -497,14 +498,14 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call
 
 /**
   * @brief  Unregister an CEC Callback
-  *         CEC callabck is redirected to the weak predefined callback
+  *         CEC callback is redirected to the weak predefined callback
   * @param hcec uart handle
   * @param CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
-  *          @arg @ref HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
-  *          @arg @ref HAL_CEC_ERROR_CB_ID Error callback ID
-  *          @arg @ref HAL_CEC_MSPINIT_CB_ID MspInit callback ID
-  *          @arg @ref HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
+  *          @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID
+  *          @arg HAL_CEC_ERROR_CB_ID Error callback ID
+  *          @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID
   * @retval status
   */
 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID)
@@ -694,9 +695,9 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
-                                      uint8_t *pData, uint32_t Size)
+                                      const uint8_t *pData, uint32_t Size)
 {
-  /* if the IP isn't already busy and if there is no previous transmission
+  /* if the peripheral isn't already busy and if there is no previous transmission
      already pending due to arbitration lost */
   if (hcec->gState == HAL_CEC_STATE_READY)
   {
@@ -749,7 +750,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
   * @param hcec CEC handle
   * @retval Frame size
   */
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
+uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec)
 {
   return hcec->RxXferSize;
 }
@@ -775,13 +776,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 {
 
   /* save interrupts register for further error or interrupts handling purposes */
-  uint32_t reg;
-  reg = hcec->Instance->ISR;
+  uint32_t itflag;
+  itflag = hcec->Instance->ISR;
 
 
   /* ----------------------------Arbitration Lost Management----------------------------------*/
   /* CEC TX arbitration error interrupt occurred --------------------------------------*/
-  if ((reg & CEC_FLAG_ARBLST) != 0U)
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST))
   {
     hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
@@ -789,7 +790,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 
   /* ----------------------------Rx Management----------------------------------*/
   /* CEC RX byte received interrupt  ---------------------------------------------------*/
-  if ((reg & CEC_FLAG_RXBR) != 0U)
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR))
   {
     /* reception is starting */
     hcec->RxState = HAL_CEC_STATE_BUSY_RX;
@@ -801,7 +802,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
   }
 
   /* CEC RX end received interrupt  ---------------------------------------------------*/
-  if ((reg & CEC_FLAG_RXEND) != 0U)
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND))
   {
     /* clear IT */
     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
@@ -820,7 +821,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 
   /* ----------------------------Tx Management----------------------------------*/
   /* CEC TX byte request interrupt ------------------------------------------------*/
-  if ((reg & CEC_FLAG_TXBR) != 0U)
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR))
   {
     --hcec->TxXferCount;
     if (hcec->TxXferCount == 0U)
@@ -829,14 +830,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
       __HAL_CEC_LAST_BYTE_TX_SET(hcec);
     }
     /* In all cases transmit the byte */
-    hcec->Instance->TXDR = *hcec->pTxBuffPtr;
+    hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr;
     hcec->pTxBuffPtr++;
     /* clear Tx-Byte request flag */
     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR);
   }
 
   /* CEC TX end interrupt ------------------------------------------------*/
-  if ((reg & CEC_FLAG_TXEND) != 0U)
+  if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND))
   {
     __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
 
@@ -854,21 +855,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
   }
 
   /* ----------------------------Rx/Tx Error Management----------------------------------*/
-  if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR |
-              CEC_ISR_TXACKE)) != 0U)
+  if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR |
+                 CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)
   {
-    hcec->ErrorCode = reg;
+    hcec->ErrorCode = itflag;
     __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE |
                          HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE);
 
 
-    if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
+    if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U)
     {
       hcec->Init.RxBuffer -= hcec->RxXferSize;
       hcec->RxXferSize = 0U;
       hcec->RxState = HAL_CEC_STATE_READY;
     }
-    else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
+    else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U))
     {
       /* Set the CEC state ready to be able to start again the process */
       hcec->gState = HAL_CEC_STATE_READY;
@@ -957,9 +958,10 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
   *              the configuration information for the specified CEC module.
   * @retval HAL state
   */
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
+HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec)
 {
-  uint32_t temp1, temp2;
+  uint32_t temp1;
+  uint32_t temp2;
   temp1 = hcec->gState;
   temp2 = hcec->RxState;
 
@@ -972,7 +974,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
   *              the configuration information for the specified CEC.
   * @retval CEC Error Code
   */
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
+uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec)
 {
   return hcec->ErrorCode;
 }
@@ -993,5 +995,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h
index e4ff48d33e..15e187ca2d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -49,70 +48,80 @@ extern "C" {
 typedef struct
 {
   uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.
-                                              It can be one of @ref CEC_Signal_Free_Time
+                                              It can be one of CEC_Signal_Free_Time
                                               and belongs to the set {0,...,7} where
                                               0x0 is the default configuration
                                               else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
 
   uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
-                                              it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
-                                              or CEC_EXTENDED_TOLERANCE */
+                                              it can be a value of CEC_Tolerance :
+                                              it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */
 
-  uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
+  uint32_t BRERxStop;                    /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising
+                                              Error stops the reception.
                                               CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
                                               CEC_RX_STOP_ON_BRE:    reception is stopped. */
 
-  uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
+  uint32_t BREErrorBitGen;               /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an
+                                              Error-Bit is generated on the
                                               CEC line upon Bit Rising Error detection.
                                               CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
                                               CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */
 
-  uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
+  uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an
+                                              Error-Bit is generated on the
                                               CEC line upon Long Bit Period Error detection.
                                               CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.
                                               CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */
 
-  uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
+  uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an
+                                              Error-Bit generation on the CEC line
                                               upon an error detected on a broadcast message.
 
-                                              It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
+                                              It supersedes BREGEN and LBPEGEN bits for a broadcast message error
+                                              handling. It can take two values:
 
                                               1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
-                                                 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
-                                                    and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
+                                                 a) BRE detection: error-bit generation on the CEC line if
+                                                    BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
                                                  b) LBPE detection: error-bit generation on the CEC line
                                                     if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
 
                                               2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
-                                                 no error-bit generation in case neither a) nor b) are satisfied. Additionally,
-                                                 there is no error-bit generation in case of Short Bit Period Error detection in
-                                                 a broadcast message while LSTN bit is set. */
+                                                 no error-bit generation in case neither a) nor b) are satisfied.
+                                                 Additionally, there is no error-bit generation in case of Short Bit
+                                                 Period Error detection in a broadcast message while LSTN bit is set. */
 
-  uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
+  uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts.
                                               CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.
-                                              CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */
+                                              CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end
+                                              of message transmission/reception. */
 
-  uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
+  uint32_t ListenMode;                   /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode.
+                                              It can take two values:
 
-                                              CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
-                                                own address (OAR). Messages addressed to different destination are ignored.
+                                              CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed
+                                                to its own address (OAR). Messages addressed to different destination
+                                                are ignored.
                                                 Broadcast messages are always received.
 
-                                              CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
-                                                address (OAR) with positive acknowledge. Messages addressed to different destination
-                                                are received, but without interfering with the CEC bus: no acknowledge sent.  */
+                                              CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its
+                                                own address (OAR) with positive acknowledge. Messages addressed to
+                                                different destination are received, but without interfering with the
+                                                CEC bus: no acknowledge sent.  */
 
-  uint16_t  OwnAddress;                 /*!< Own addresses configuration
-                                             This parameter can be a value of @ref CEC_OWN_ADDRESS */
+  uint16_t  OwnAddress;                  /*!< Own addresses configuration
+                                              This parameter can be a value of CEC_OWN_ADDRESS */
 
-  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */
+  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointer */
 
 
 } CEC_InitTypeDef;
 
 /**
   * @brief HAL CEC State definition
-  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
+  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState
+           (see CEC_State_Definition).
   *        - gState contains CEC state information related to global Handle management
   *          and also information related to Tx operations.
   *          gState value coding follow below described bitmap :
@@ -121,14 +130,14 @@ typedef struct
   *          b6  Error information
   *             0  : No Error
   *             1  : Error
-  *          b5     IP initialization status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized. HAL CEC Init function already called)
+  *          b5     CEC peripheral initialization status
+  *             0  : Reset (peripheral not initialized)
+  *             1  : Init done (peripheral initialized. HAL CEC Init function already called)
   *          b4-b3  (not used)
   *             xx : Should be set to 00
   *          b2     Intrinsic process state
   *             0  : Ready
-  *             1  : Busy (IP busy with some configuration or internal operations)
+  *             1  : Busy (peripheral busy with some configuration or internal operations)
   *          b1     (not used)
   *             x  : Should be set to 0
   *          b0     Tx state
@@ -138,9 +147,9 @@ typedef struct
   *          RxState value coding follow below described bitmap :
   *          b7-b6  (not used)
   *             xx : Should be set to 00
-  *          b5     IP initialization status
-  *             0  : Reset (IP not initialized)
-  *             1  : Init done (IP initialized)
+  *          b5     CEC peripheral initialization status
+  *             0  : Reset (peripheral not initialized)
+  *             1  : Init done (peripheral initialized)
   *          b4-b2  (not used)
   *            xxx : Should be set to 000
   *          b1     Rx state
@@ -160,37 +169,37 @@ typedef struct __CEC_HandleTypeDef
 typedef struct
 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
 {
-  CEC_TypeDef             *Instance;      /*!< CEC registers base address */
+  CEC_TypeDef             *Instance;      /*!< CEC registers base address                                 */
 
-  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */
+  CEC_InitTypeDef         Init;           /*!< CEC communication parameters                               */
 
-  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */
+  const uint8_t           *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer                          */
 
-  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */
+  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter                                    */
 
-  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */
+  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only              */
 
-  HAL_LockTypeDef         Lock;           /*!< Locking object */
+  HAL_LockTypeDef         Lock;           /*!< Locking object                                             */
 
   HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management
                                                and also related to Tx operations.
-                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+                                               This parameter can be a value of HAL_CEC_StateTypeDef      */
 
   HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.
-                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */
+                                               This parameter can be a value of HAL_CEC_StateTypeDef      */
 
   uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register
-                                               in case error is reported */
+                                               in case error is reported                                  */
 
 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
   void (* TxCpltCallback)(struct __CEC_HandleTypeDef
-                          *hcec);                                /*!< CEC Tx Transfer completed callback */
+                          *hcec);                                /*!< CEC Tx Transfer completed callback  */
   void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
-                          uint32_t RxFrameSize);          /*!< CEC Rx Transfer completed callback */
-  void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec);                                 /*!< CEC error callback */
+                          uint32_t RxFrameSize);                 /*!< CEC Rx Transfer completed callback  */
+  void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec);      /*!< CEC error callback                  */
 
-  void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec);               /*!< CEC Msp Init callback              */
-  void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec);             /*!< CEC Msp DeInit callback            */
+  void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec);    /*!< CEC Msp Init callback               */
+  void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec);  /*!< CEC Msp DeInit callback             */
 
 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
 } CEC_HandleTypeDef;
@@ -203,7 +212,7 @@ typedef enum
 {
   HAL_CEC_TX_CPLT_CB_ID      = 0x00U,    /*!< CEC Tx Transfer completed callback ID  */
   HAL_CEC_RX_CPLT_CB_ID      = 0x01U,    /*!< CEC Rx Transfer completed callback ID  */
-  HAL_CEC_ERROR_CB_ID        = 0x02U,    /*!< CEC error callback ID                 */
+  HAL_CEC_ERROR_CB_ID        = 0x02U,    /*!< CEC error callback ID                  */
   HAL_CEC_MSPINIT_CB_ID      = 0x03U,    /*!< CEC Msp Init callback ID               */
   HAL_CEC_MSPDEINIT_CB_ID    = 0x04U     /*!< CEC Msp DeInit callback ID             */
 } HAL_CEC_CallbackIDTypeDef;
@@ -213,7 +222,8 @@ typedef enum
   */
 typedef  void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec);  /*!< pointer to an CEC callback function */
 typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
-                                        uint32_t RxFrameSize);  /*!< pointer to an Rx Transfer completed callback function */
+                                        uint32_t RxFrameSize);  /*!< pointer to an Rx Transfer completed
+                                                                     callback function */
 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
 /**
   * @}
@@ -359,16 +369,16 @@ typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
 /** @defgroup CEC_OWN_ADDRESS   CEC Own Address
   * @{
   */
-#define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */
-#define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */
-#define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */
-#define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */
-#define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */
-#define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */
-#define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */
-#define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */
-#define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */
-#define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */
+#define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value        */
+#define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0  */
+#define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1  */
+#define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2  */
+#define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3  */
+#define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4  */
+#define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5  */
+#define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6  */
+#define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7  */
+#define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9  */
 #define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */
 #define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */
 #define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */
@@ -422,8 +432,8 @@ typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
 /** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
   * @{
   */
-#define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
-                                        CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
+#define CEC_ISR_ALL_ERROR       ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
+                                 CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
 /**
   * @}
   */
@@ -431,7 +441,7 @@ typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
 /** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
   * @{
   */
-#define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
+#define CEC_IER_RX_ALL_ERR      ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
 /**
   * @}
   */
@@ -439,7 +449,7 @@ typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
 /** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
   * @{
   */
-#define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
+#define CEC_IER_TX_ALL_ERR      ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
 /**
   * @}
   */
@@ -623,7 +633,8 @@ typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
   * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
   * @retval none
   */
-#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, \
+                                                            (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
 
 /**
   * @}
@@ -661,8 +672,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
   */
 /* I/O operation functions  ***************************************************/
 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
-                                      uint8_t *pData, uint32_t Size);
-uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
+                                      const uint8_t *pData, uint32_t Size);
+uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec);
 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
@@ -676,8 +687,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
   * @{
   */
 /* Peripheral State functions  ************************************************/
-HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
-uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
+HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec);
+uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec);
 /**
   * @}
   */
@@ -732,8 +743,9 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
 #define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
                                                  ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
 
-#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
-                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \
+  (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
+   ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
 
 #define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
                                           ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
@@ -790,5 +802,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
 #endif
 
 #endif /* STM32H7xxHAL_CEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c
index 59a2590ce8..e73ebb6e61 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c
@@ -6,10 +6,19 @@
   *          This file provides firmware functions to manage the following 
   *          functionalities of the COMP peripheral:
   *           + Initialization and de-initialization functions
-  *           + Start/Stop operation functions in polling mode
-  *           + Start/Stop operation functions in interrupt mode
   *           + Peripheral control functions
-  *           + Peripheral state functions      
+  *           + Peripheral state functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ================================================================================
                    ##### COMP Peripheral features #####
@@ -98,11 +107,11 @@
 
      The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
      allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_COMP_RegisterCallback()
+     Use Functions HAL_COMP_RegisterCallback()
      to register an interrupt callback.
     [..]
 
-     Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
+     Function HAL_COMP_RegisterCallback() allows to register following callbacks:
        (+) TriggerCallback       : callback for COMP trigger.
        (+) MspInitCallback       : callback for Msp Init.
        (+) MspDeInitCallback     : callback for Msp DeInit.
@@ -110,11 +119,11 @@
      and a pointer to the user callback function.
     [..]
 
-     Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
+     Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
      weak function.
     [..]
 
-     @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
      and the Callback ID.
      This function allows to reset following callbacks:
        (+) TriggerCallback       : callback for COMP trigger.
@@ -122,27 +131,27 @@
        (+) MspDeInitCallback     : callback for Msp DeInit.
      [..]
 
-     By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
+     By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
      all callbacks are set to the corresponding weak functions:
-     example @ref HAL_COMP_TriggerCallback().
+     example HAL_COMP_TriggerCallback().
      Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
+     reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
      these callbacks are null (not registered beforehand).
     [..]
 
-     If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
+     If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
      [..]
 
-     Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
+     Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
      Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
+     in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     [..]
 
      Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
-     or @ref HAL_COMP_Init() function.
+     using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
+     or HAL_COMP_Init() function.
      [..]
 
      When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
@@ -179,17 +188,6 @@
   (1) GPIO must be set to alternate function for comparator
   (2) Comparators output to timers is set in timers instances.
 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
   ******************************************************************************
   */
 
@@ -1247,4 +1245,3 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.h
index 1db50aa22e..ba42ed117a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -951,4 +950,4 @@ uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
 
 #endif /* STM32H7xx_HAL_COMP_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c
index 37f70e7ef6..7eea29cb6c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c
@@ -11,7 +11,18 @@
   *           + IRQ handler management
   *           + Peripheral State functions
   *
-  *  @verbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
   ================================================================================
             ##### How to use this driver #####
   ================================================================================
@@ -79,9 +90,9 @@
 
   The compilation define  USE_HAL_CORDIC_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
-  Use Function @ref HAL_CORDIC_RegisterCallback() to register an interrupt callback.
+  Use Function HAL_CORDIC_RegisterCallback() to register an interrupt callback.
 
-  Function @ref HAL_CORDIC_RegisterCallback() allows to register following callbacks:
+  Function HAL_CORDIC_RegisterCallback() allows to register following callbacks:
     (+) ErrorCallback             : Error Callback.
     (+) CalculateCpltCallback     : Calculate complete Callback.
     (+) MspInitCallback           : CORDIC MspInit.
@@ -89,9 +100,9 @@
   This function takes as parameters the HAL peripheral handle, the Callback ID
   and a pointer to the user callback function.
 
-  Use function @ref HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
+  Use function HAL_CORDIC_UnRegisterCallback() to reset a callback to the default
   weak function.
-  @ref HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  HAL_CORDIC_UnRegisterCallback takes as parameters the HAL peripheral handle,
   and the Callback ID.
   This function allows to reset following callbacks:
     (+) ErrorCallback             : Error Callback.
@@ -101,11 +112,11 @@
 
   By default, after the HAL_CORDIC_Init() and when the state is HAL_CORDIC_STATE_RESET,
   all callbacks are set to the corresponding weak functions:
-  examples @ref HAL_CORDIC_ErrorCallback(), @ref HAL_CORDIC_CalculateCpltCallback().
+  examples HAL_CORDIC_ErrorCallback(), HAL_CORDIC_CalculateCpltCallback().
   Exception done for MspInit and MspDeInit functions that are
-  reset to the legacy weak function in the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit() only when
+  reset to the legacy weak function in the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit() only when
   these callbacks are null (not registered beforehand).
-  if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ @ref HAL_CORDIC_DeInit()
+  if not, MspInit or MspDeInit are not null, the HAL_CORDIC_Init()/ HAL_CORDIC_DeInit()
   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
   Callbacks can be registered/unregistered in HAL_CORDIC_STATE_READY state only.
@@ -113,7 +124,7 @@
   in HAL_CORDIC_STATE_READY or HAL_CORDIC_STATE_RESET state,
   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_CORDIC_RegisterCallback() before calling @ref HAL_CORDIC_DeInit()
+  using HAL_CORDIC_RegisterCallback() before calling HAL_CORDIC_DeInit()
   or HAL_CORDIC_Init() function.
 
   When The compilation define USE_HAL_CORDIC_REGISTER_CALLBACKS is set to 0 or
@@ -121,18 +132,6 @@
   are set to the corresponding weak functions.
 
   @endverbatim
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
   ******************************************************************************
   */
 
@@ -160,8 +159,8 @@
 /** @defgroup CORDIC_Private_Functions CORDIC Private Functions
   * @{
   */
-static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff);
-static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
+static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff);
+static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff);
 static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma);
 static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma);
 static void CORDIC_DMAError(DMA_HandleTypeDef *hdma);
@@ -556,7 +555,7 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H
   *         contains the CORDIC configuration information.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -603,12 +602,12 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con
   * @param  Timeout Specify Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                        uint32_t NbCalc, uint32_t Timeout)
 {
   uint32_t tickstart;
   uint32_t index;
-  int32_t *p_tmp_in_buff = pInBuff;
+  const int32_t *p_tmp_in_buff = pInBuff;
   int32_t *p_tmp_out_buff = pOutBuff;
 
   /* Check parameters setting */
@@ -697,12 +696,12 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p
   * @param  Timeout Specify Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                          uint32_t NbCalc, uint32_t Timeout)
 {
   uint32_t tickstart;
   uint32_t index;
-  int32_t *p_tmp_in_buff = pInBuff;
+  const int32_t *p_tmp_in_buff = pInBuff;
   int32_t *p_tmp_out_buff = pOutBuff;
 
   /* Check parameters setting */
@@ -790,10 +789,10 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t
   * @param  NbCalc Number of CORDIC calculation to process.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                           uint32_t NbCalc)
 {
-  int32_t *tmp_pInBuff = pInBuff;
+  const int32_t *tmp_pInBuff = pInBuff;
 
   /* Check parameters setting */
   if ((pInBuff == NULL) || (pOutBuff == NULL) || (NbCalc == 0U))
@@ -882,13 +881,11 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t
   *         DMA transfer to and from the Peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                            uint32_t NbCalc, uint32_t DMADirection)
 {
   uint32_t sizeinbuff;
   uint32_t sizeoutbuff;
-  uint32_t inputaddr;
-  uint32_t outputaddr;
 
   /* Check the parameters */
   assert_param(IS_CORDIC_DMA_DIRECTION(DMADirection));
@@ -961,10 +958,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
         sizeoutbuff = NbCalc;
       }
 
-      outputaddr = (uint32_t)pOutBuff;
-
       /* Enable the DMA stream managing CORDIC output data read */
-      if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, outputaddr, sizeoutbuff) != HAL_OK)
+      if (HAL_DMA_Start_IT(hcordic->hdmaOut, (uint32_t)&hcordic->Instance->RDATA, (uint32_t) pOutBuff, sizeoutbuff)
+          != HAL_OK)
       {
         /* Update the error code */
         hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
@@ -996,10 +992,9 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_
         sizeinbuff = NbCalc;
       }
 
-      inputaddr  = (uint32_t)pInBuff;
-
       /* Enable the DMA stream managing CORDIC input data write */
-      if (HAL_DMA_Start_IT(hcordic->hdmaIn, inputaddr, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff) != HAL_OK)
+      if (HAL_DMA_Start_IT(hcordic->hdmaIn, (uint32_t) pInBuff, (uint32_t)&hcordic->Instance->WDATA, sizeinbuff)
+          != HAL_OK)
       {
         /* Update the error code */
         hcordic->ErrorCode |= HAL_CORDIC_ERROR_DMA;
@@ -1138,7 +1133,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
         /*Call registered callback*/
         hcordic->CalculateCpltCallback(hcordic);
 #else
-        /*Call legacy weak (surcharged) callback*/
+        /*Call legacy weak callback*/
         HAL_CORDIC_CalculateCpltCallback(hcordic);
 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
       }
@@ -1170,7 +1165,7 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic)
   *         the configuration information for CORDIC module
   * @retval HAL state
   */
-HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
+HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic)
 {
   /* Return CORDIC handle state */
   return hcordic->State;
@@ -1183,7 +1178,7 @@ HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic)
   * @note   The returned error is a bit-map combination of possible errors
   * @retval Error bit-map
   */
-uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
+uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic)
 {
   /* Return CORDIC error code */
   return hcordic->ErrorCode;
@@ -1208,7 +1203,7 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic)
   * @param  ppInBuff Pointer to pointer to input buffer.
   * @retval none
   */
-static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppInBuff)
+static void CORDIC_WriteInDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, const int32_t **ppInBuff)
 {
   /* First write of input data in the Write Data register */
   WRITE_REG(hcordic->Instance->WDATA, (uint32_t) **ppInBuff);
@@ -1234,7 +1229,7 @@ static void CORDIC_WriteInDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_
   * @param  ppOutBuff Pointer to pointer to output buffer.
   * @retval none
   */
-static void CORDIC_ReadOutDataIncrementPtr(CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
+static void CORDIC_ReadOutDataIncrementPtr(const CORDIC_HandleTypeDef *hcordic, int32_t **ppOutBuff)
 {
   /* First read of output data from the Read Data register */
   **ppOutBuff = (int32_t)READ_REG(hcordic->Instance->RDATA);
@@ -1279,7 +1274,7 @@ static void CORDIC_DMAInCplt(DMA_HandleTypeDef *hdma)
     /*Call registered callback*/
     hcordic->CalculateCpltCallback(hcordic);
 #else
-    /*Call legacy weak (surcharged) callback*/
+    /*Call legacy weak callback*/
     HAL_CORDIC_CalculateCpltCallback(hcordic);
 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
   }
@@ -1308,7 +1303,7 @@ static void CORDIC_DMAOutCplt(DMA_HandleTypeDef *hdma)
   /*Call registered callback*/
   hcordic->CalculateCpltCallback(hcordic);
 #else
-  /*Call legacy weak (surcharged) callback*/
+  /*Call legacy weak callback*/
   HAL_CORDIC_CalculateCpltCallback(hcordic);
 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
 }
@@ -1333,7 +1328,7 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
   /*Call registered callback*/
   hcordic->ErrorCallback(hcordic);
 #else
-  /*Call legacy weak (surcharged) callback*/
+  /*Call legacy weak callback*/
   HAL_CORDIC_ErrorCallback(hcordic);
 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
 }
@@ -1352,5 +1347,3 @@ static void CORDIC_DMAError(DMA_HandleTypeDef *hdma)
 
 #endif /* HAL_CORDIC_MODULE_ENABLED */
 #endif /* CORDIC */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h
index 04e2d79b52..0aa08c4316 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h
@@ -7,13 +7,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -65,7 +64,7 @@ typedef struct
 {
   CORDIC_TypeDef                *Instance;   /*!< Register base address */
 
-  int32_t                       *pInBuff;    /*!< Pointer to CORDIC input data buffer */
+  const int32_t                 *pInBuff;    /*!< Pointer to CORDIC input data buffer */
 
   int32_t                       *pOutBuff;   /*!< Pointer to CORDIC output data buffer */
 
@@ -547,14 +546,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H
   */
 #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
-HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, const CORDIC_ConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                        uint32_t NbCalc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                          uint32_t NbCalc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                           uint32_t NbCalc);
-HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
+HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, const int32_t *pInBuff, int32_t *pOutBuff,
                                            uint32_t NbCalc, uint32_t DMADirection);
 /**
   * @}
@@ -583,8 +582,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
   * @{
   */
 /* Peripheral State functions *************************************************/
-HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic);
-uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
+HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(const CORDIC_HandleTypeDef *hcordic);
+uint32_t HAL_CORDIC_GetError(const CORDIC_HandleTypeDef *hcordic);
 /**
   * @}
   */
@@ -608,5 +607,3 @@ uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
 #endif
 
 #endif /* STM32H7xx_HAL_CORDIC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.c
index e45e7936f3..e272cfc2db 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.c
@@ -68,13 +68,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -289,10 +288,43 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
   __DSB();
   __ISB();
 }
+
+/**
+  * @brief  Enables the MPU Region.
+  * @retval None
+  */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU->RNR = RegionNumber;
+
+  /* Enable the Region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Disables the MPU Region.
+  * @retval None
+  */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+  /* Set the Region number */
+  MPU->RNR = RegionNumber;
+
+  /* Disable the Region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
 /**
   * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                  the initialization and configuration information.
+  * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
   * @retval None
   */
 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
@@ -300,38 +332,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
   /* Check the parameters */
   assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
   assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+  assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+  assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+  assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+  assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+  assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+  assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+  assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+  assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
 
   /* Set the Region number */
   MPU->RNR = MPU_Init->Number;
 
-  if ((MPU_Init->Enable) != 0UL)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+  /* Disable the Region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 
-    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00;
-    MPU->RASR = 0x00;
-  }
+  /* Apply configuration */
+  MPU->RBAR = MPU_Init->BaseAddress;
+  MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+              ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+              ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+              ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+              ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+              ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+              ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+              ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+              ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
 }
 #endif /* __MPU_PRESENT */
 
@@ -530,4 +556,3 @@ uint32_t HAL_GetCurrentCPUID(void)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.h
index 17b111ce1b..134fc483f4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cortex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -308,6 +307,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
 #if (__MPU_PRESENT == 1)
 void HAL_MPU_Enable(uint32_t MPU_Control);
 void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
 #endif /* __MPU_PRESENT */
 uint32_t HAL_NVIC_GetPriorityGrouping(void);
@@ -458,4 +459,3 @@ uint32_t HAL_GetCurrentCPUID(void);
 #endif /* STM32H7xx_HAL_CORTEX_H */
 
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.c
index e0860ac1df..6690bc82e0 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.c
@@ -9,6 +9,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                      ##### How to use this driver #####
@@ -29,17 +40,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -62,8 +62,8 @@
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /** @defgroup CRC_Private_Functions CRC Private Functions
- * @{
- */
+  * @{
+  */
 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
 /**
@@ -77,8 +77,8 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   */
 
 /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions.
- *
+  *  @brief    Initialization and Configuration functions.
+  *
 @verbatim
  ===============================================================================
             ##### Initialization and de-initialization functions #####
@@ -200,7 +200,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
   __HAL_CRC_DR_RESET(hcrc);
 
   /* Reset IDR register content */
-  CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+  CLEAR_REG(hcrc->Instance->IDR);
 
   /* DeInit the low level hardware */
   HAL_CRC_MspDeInit(hcrc);
@@ -250,8 +250,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
   */
 
 /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
- *  @brief    management functions.
- *
+  *  @brief    management functions.
+  *
 @verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
@@ -385,8 +385,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
   */
 
 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
- *  @brief    Peripheral State functions.
- *
+  *  @brief    Peripheral State functions.
+  *
 @verbatim
  ===============================================================================
                       ##### Peripheral State functions #####
@@ -403,7 +403,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
   * @param  hcrc CRC handle
   * @retval HAL state
   */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc)
 {
   /* Return CRC handle state */
   return hcrc->State;
@@ -418,8 +418,8 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
   */
 
 /** @addtogroup CRC_Private_Functions
- * @{
- */
+  * @{
+  */
 
 /**
   * @brief  Enter 8-bit input data to the CRC calculator.
@@ -514,5 +514,3 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.h
index e1ebe4c708..cd0c2b795e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -60,19 +59,22 @@ typedef struct
 {
   uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
                                             If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
-                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
+                                            X^4 + X^2+ X +1.
                                             In that case, there is no need to set GeneratingPolynomial field.
-                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
+                                            CRCLength fields must be set. */
 
   uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
                                            If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
-                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.
-                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
+                                           otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
 
   uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
-                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
-                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
-                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal,
+                                           representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
+                                           is written 0x65. No need to specify it if DefaultPolynomialUse is set to
+                                            DEFAULT_POLYNOMIAL_ENABLE.   */
 
   uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
                                            Value can be either one of
@@ -87,14 +89,18 @@ typedef struct
   uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
                                            Can be either one of the following values
                                            @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
-                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
-                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
-                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
+                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D
+                                           becomes 0x58D43CB2
+                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion,
+                                           0x1A2B3C4D becomes 0xD458B23C
+                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D
+                                           becomes 0xB23CD458 */
 
   uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
                                             Can be either
                                             @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
-                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted
+                                             into 0x22CC4488 */
 } CRC_InitTypeDef;
 
 /**
@@ -112,12 +118,16 @@ typedef struct
 
   uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
                                             Can be either
-                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
-                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
-                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes
+                                            (8-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of
+                                            half-words (16-bit data)
+                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words
+                                            (32-bit data)
 
-                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
-                                           must occur if InputBufferFormat is not one of the three values listed above  */
+                                          Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
+                                          error must occur if InputBufferFormat is not one of the three values listed
+                                          above  */
 } CRC_HandleTypeDef;
 /**
   * @}
@@ -199,15 +209,6 @@ typedef struct
   * @}
   */
 
-/** @defgroup CRC_Aliases CRC API aliases
-  * @{
-  */
-#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
-#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-/**
-  * @}
-  */
-
 /**
   * @}
   */
@@ -317,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
 /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
   * @{
   */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
+HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc);
 /**
   * @}
   */
@@ -339,5 +340,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
 #endif
 
 #endif /* STM32H7xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c
index 97e70c1491..b4ba3de352 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c
@@ -6,6 +6,17 @@
   *          This file provides firmware functions to manage the extended
   *          functionalities of the CRC peripheral.
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
 ================================================================================
             ##### How to use this driver #####
@@ -16,17 +27,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -94,44 +94,53 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
   /* Check the parameters */
   assert_param(IS_CRC_POL_LENGTH(PolyLength));
 
-  /* check polynomial definition vs polynomial size:
-   * polynomial length must be aligned with polynomial
-   * definition. HAL_ERROR is reported if Pol degree is
-   * larger than that indicated by PolyLength.
-   * Look for MSB position: msb will contain the degree of
-   *  the second to the largest polynomial member. E.g., for
-   *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
-  while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+  /* Ensure that the generating polynomial is odd */
+  if ((Pol & (uint32_t)(0x1U)) ==  0U)
   {
+    status =  HAL_ERROR;
   }
-
-  switch (PolyLength)
+  else
   {
-    case CRC_POLYLENGTH_7B:
-      if (msb >= HAL_CRC_LENGTH_7B)
-      {
-        status =   HAL_ERROR;
-      }
-      break;
-    case CRC_POLYLENGTH_8B:
-      if (msb >= HAL_CRC_LENGTH_8B)
-      {
-        status =   HAL_ERROR;
-      }
-      break;
-    case CRC_POLYLENGTH_16B:
-      if (msb >= HAL_CRC_LENGTH_16B)
-      {
-        status =   HAL_ERROR;
-      }
-      break;
+    /* check polynomial definition vs polynomial size:
+     * polynomial length must be aligned with polynomial
+     * definition. HAL_ERROR is reported if Pol degree is
+     * larger than that indicated by PolyLength.
+     * Look for MSB position: msb will contain the degree of
+     *  the second to the largest polynomial member. E.g., for
+     *  X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+    while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+    {
+    }
 
-    case CRC_POLYLENGTH_32B:
-      /* no polynomial definition vs. polynomial length issue possible */
-      break;
-    default:
-      status =  HAL_ERROR;
-      break;
+    switch (PolyLength)
+    {
+
+      case CRC_POLYLENGTH_7B:
+        if (msb >= HAL_CRC_LENGTH_7B)
+        {
+          status =   HAL_ERROR;
+        }
+        break;
+      case CRC_POLYLENGTH_8B:
+        if (msb >= HAL_CRC_LENGTH_8B)
+        {
+          status =   HAL_ERROR;
+        }
+        break;
+      case CRC_POLYLENGTH_16B:
+        if (msb >= HAL_CRC_LENGTH_16B)
+        {
+          status =   HAL_ERROR;
+        }
+        break;
+
+      case CRC_POLYLENGTH_32B:
+        /* no polynomial definition vs. polynomial length issue possible */
+        break;
+      default:
+        status =  HAL_ERROR;
+        break;
+    }
   }
   if (status == HAL_OK)
   {
@@ -221,5 +230,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.h
index 0ca334fbf5..bc7022618d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -149,5 +148,3 @@ HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_
 #endif
 
 #endif /* STM32H7xx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c
index baf248d36a..61d732e4be 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c
@@ -13,6 +13,17 @@
   *           + CRYP IRQ handler management
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -38,7 +49,8 @@
                  priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
 
       (#)Initialize the CRYP according to the specified parameters :
-         (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
+         (##) The data type: bit swap(1-bit data), byte swap(8-bit data), half word swap(16-bit data)
+            or no swap(32-bit data).
          (##) The key size: 128, 192 or 256.
          (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
          (##) The initialization vector (counter). It is not used in ECB mode.
@@ -65,13 +77,13 @@
          new parametres, finally user can  start encryption/decryption.
 
        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
-       
+
        (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
           without having to configure again the Key or the Initialization Vector between each API call,
           the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
           Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
           or HAL_CRYP_Decrypt_DMA().
-          
+
     [..]
       The cryptographic processor supports following standards:
       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
@@ -104,7 +116,7 @@
           encryption + data XORing. It works in a similar way for ciphertext (C).
          (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
           HAL_CRYPEx_AESGCM_GenerateAuthTAG API used in this phase to generate 4 words which correspond
-          to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits. 
+          to the Tag. user should consider only part of this 4 words, if Tag length is less than 128 bits.
       (#)  structure of message construction in GCM is defined as below  :
          (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
          (##) The authenticated header A (also knows as Additional Authentication Data AAD)
@@ -251,20 +263,6 @@
                 95  ...64    CRYP_IV1L[31:0]     B0[95:64]
                 63 ... 32    CRYP_IV0R[31:0]     B0[63:32]
                 31 ... 0     CRYP_IV0L[31:0]     B0[31:0], where flag bits set to 0
-
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -289,9 +287,9 @@
 /** @addtogroup CRYP_Private_Defines
   * @{
   */
-#define CRYP_TIMEOUT_KEYPREPARATION      82U         /*The latency of key preparation operation is 82 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /*  The latency of  GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /*  The latency of  GCM/CCM header phase is 290 clock cycles.*/
+#define CRYP_TIMEOUT_KEYPREPARATION      82U         /*!<  The latency of key preparation operation is 82 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE     299U        /*!<  The latency of  GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMHEADERPHASE   290U        /*!<  The latency of  GCM/CCM header phase is 290 clock cycles.*/
 
 #define  CRYP_PHASE_READY                0x00000001U /*!< CRYP peripheral is ready for initialization. */
 #define  CRYP_PHASE_PROCESS              0x00000002U /*!< CRYP peripheral is in processing phase */
@@ -333,7 +331,7 @@
 /* Private struct -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CRYP_Private_Functions_prototypes
+/** @addtogroup CRYP_Private_Functions_Prototypes
   * @{
   */
 
@@ -456,7 +454,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
   }
 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
 
-  /* Set the key size(This bit field is "don't care" in the DES or TDES modes) data type and Algorithm */
+  /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
   MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
              hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
 #if !defined (CRYP_VER_2_2)
@@ -468,7 +466,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
 
   /* Reset peripheral Key and IV configuration flag */
   hcryp->KeyIVConfig = 0U;
-  
+
   /* Change the CRYP state */
   hcryp->State = HAL_CRYP_STATE_READY;
 
@@ -557,17 +555,19 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
     __HAL_LOCK(hcryp);
 
     /* Set  CRYP parameters  */
-    hcryp->Init.DataType     = pConf->DataType;
-    hcryp->Init.pKey         = pConf->pKey;
-    hcryp->Init.Algorithm    = pConf->Algorithm;
-    hcryp->Init.KeySize      = pConf->KeySize;
-    hcryp->Init.pInitVect    = pConf->pInitVect;
-    hcryp->Init.Header       = pConf->Header;
-    hcryp->Init.HeaderSize   = pConf->HeaderSize;
-    hcryp->Init.B0           = pConf->B0;
-    hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
+    hcryp->Init.DataType        = pConf->DataType;
+    hcryp->Init.pKey            = pConf->pKey;
+    hcryp->Init.Algorithm       = pConf->Algorithm;
+    hcryp->Init.KeySize         = pConf->KeySize;
+    hcryp->Init.pInitVect       = pConf->pInitVect;
+    hcryp->Init.Header          = pConf->Header;
+    hcryp->Init.HeaderSize      = pConf->HeaderSize;
+    hcryp->Init.B0              = pConf->B0;
+    hcryp->Init.DataWidthUnit   = pConf->DataWidthUnit;
+    hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
+    hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
 
-    /* Set the key size(This bit field is "don't care" in the DES or TDES modes) data type, AlgoMode and operating mode*/
+    /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
     MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
                hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
 
@@ -629,7 +629,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD
     pConf->Header          = hcryp->Init.Header ;
     pConf->HeaderSize      = hcryp->Init.HeaderSize;
     pConf->B0              = hcryp->Init.B0;
-    pConf->DataWidthUnit    = hcryp->Init.DataWidthUnit;
+    pConf->DataWidthUnit   = hcryp->Init.DataWidthUnit;
+    pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
+    pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hcryp);
@@ -780,7 +782,7 @@ HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_
 
 /**
   * @brief  Unregister an CRYP Callback
-  *         CRYP callabck is redirected to the weak predefined callback
+  *         CRYP callback is redirected to the weak predefined callback
   * @param hcryp cryp handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -976,7 +978,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
         /* Set the phase */
         hcryp->Phase = CRYP_PHASE_PROCESS;
 
-        /* Statrt DES/TDES encryption process */
+        /* Start DES/TDES encryption process */
         status = CRYP_TDES_Process(hcryp, Timeout);
         break;
 
@@ -1239,7 +1241,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
 
         /* Enable CRYP to start DES/TDES process*/
         __HAL_CRYP_ENABLE(hcryp);
-        
+
         status = HAL_OK;
         break;
 
@@ -1473,7 +1475,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
         hcryp->Phase = CRYP_PHASE_PROCESS;
 
         /* Start DMA process transfer for DES/TDES */
-        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
+                          (uint32_t)(hcryp->pCrypOutBuffPtr));
 
         break;
 
@@ -1506,10 +1509,10 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
           /* Set the Initialization Vector*/
           if (hcryp->Init.Algorithm != CRYP_AES_ECB)
           {
-          hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-          hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
-          hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
-          hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+            hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+            hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+            hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+            hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
           }
         } /* if (DoKeyIVConfig == 1U) */
 
@@ -1517,7 +1520,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
         hcryp->Phase = CRYP_PHASE_PROCESS;
 
         /* Start DMA process transfer for AES */
-        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
+                          (uint32_t)(hcryp->pCrypOutBuffPtr));
         break;
 
       case CRYP_AES_GCM:
@@ -1625,7 +1629,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
         hcryp->Phase = CRYP_PHASE_PROCESS;
 
         /* Start DMA process transfer for DES/TDES */
-        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+        CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
+                          (uint32_t)(hcryp->pCrypOutBuffPtr));
         break;
 
       case CRYP_AES_ECB:
@@ -1700,11 +1705,13 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
 
   if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
   {
-    if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
+    if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) ||
+        (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
     {
       CRYP_TDES_IT(hcryp); /* DES or TDES*/
     }
-    else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) || (hcryp->Init.Algorithm == CRYP_AES_CTR))
+    else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) ||
+             (hcryp->Init.Algorithm == CRYP_AES_CTR))
     {
       CRYP_AES_IT(hcryp); /*AES*/
     }
@@ -1800,6 +1807,9 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
 /**
   * @}
   */
+/**
+  * @}
+  */
 
 /* Private functions ---------------------------------------------------------*/
 /** @addtogroup CRYP_Private_Functions
@@ -1866,7 +1876,8 @@ static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t T
 
     if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
     {
-      /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
+      /* Read the output block from the Output FIFO and put them in temporary Buffer
+       then get CrypOutBuff from temporary buffer  */
       temp = hcryp->Instance->DOUT;
       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
       hcryp->CrypOutCount++;
@@ -1902,19 +1913,19 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
   {
     if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
     {
-      if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
+      if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
       {
         /* Write input block in the IN FIFO */
         hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
         hcryp->CrypInCount++;
         hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
         hcryp->CrypInCount++;
-        
+
         if (hcryp->CrypInCount == (hcryp->Size / 4U))
         {
           /* Disable interruption */
           __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-          
+
           /* Call the input data transfer complete callback */
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
           /*Call registered Input complete callback*/
@@ -1929,9 +1940,10 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
 
     if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
     {
-      if(__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
+      if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
       {
-        /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer  */
+        /* Read the output block from the Output FIFO and put them in temporary Buffer
+         then get CrypOutBuff from temporary buffer  */
         temp = hcryp->Instance->DOUT;
         *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
         hcryp->CrypOutCount++;
@@ -1942,16 +1954,16 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
         {
           /* Disable interruption */
           __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-          
+
           /* Disable CRYP */
           __HAL_CRYP_DISABLE(hcryp);
-          
+
           /* Process unlocked */
           __HAL_UNLOCK(hcryp);
-          
+
           /* Change the CRYP state */
           hcryp->State = HAL_CRYP_STATE_READY;
-          
+
           /* Call output transfer complete callback */
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
           /*Call registered Output complete callback*/
@@ -1960,7 +1972,7 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
           /*Call legacy weak Output complete callback*/
           HAL_CRYP_OutCpltCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-          
+
         }
       }
     }
@@ -2146,52 +2158,52 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
 
   if (DoKeyIVConfig == 1U)
   {
-  /*  Key preparation for ECB/CBC */
-  if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
-  {
-    /* change ALGOMODE to key preparation for decryption*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
-
-    /*  Set the Key*/
-    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-
-    /* Wait for BUSY flag to be raised */
-    if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+    /*  Key preparation for ECB/CBC */
+    if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
     {
-      /* Disable the CRYP peripheral clock */
-      __HAL_CRYP_DISABLE(hcryp);
+      /* change ALGOMODE to key preparation for decryption*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
 
-      /* Change state */
-      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-      hcryp->State = HAL_CRYP_STATE_READY;
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-      /* Process unlocked */
-      __HAL_UNLOCK(hcryp);
-      return HAL_ERROR;
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Wait for BUSY flag to be raised */
+      if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
+
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+      /* Turn back to ALGOMODE of the configuration */
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+    }
+    else  /*Algorithm CTR */
+    {
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
     }
-    /* Turn back to ALGOMODE of the configuration */
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
-  }
-  else  /*Algorithm CTR */
-  {
-    /*  Set the Key*/
-    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-  }
 
-  /* Set IV */
-  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
-  {
-    /* Set the Initialization Vector*/
-    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
-  }
-} /* if (DoKeyIVConfig == 1U) */
-    
+    /* Set IV */
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+      hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
 
@@ -2227,7 +2239,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
 {
   __IO uint32_t count = 0U;
-   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
   if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
   {
@@ -2248,55 +2260,56 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
 
   if (DoKeyIVConfig == 1U)
   {
-  /*  Key preparation for ECB/CBC */
-  if (hcryp->Init.Algorithm != CRYP_AES_CTR)
-  {
-    /* change ALGOMODE to key preparation for decryption*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
-
-    /*  Set the Key*/
-    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-
-    /* Wait for BUSY flag to be raised */
-    count = CRYP_TIMEOUT_KEYPREPARATION;
-    do
+    /*  Key preparation for ECB/CBC */
+    if (hcryp->Init.Algorithm != CRYP_AES_CTR)
     {
-      count-- ;
-      if (count == 0U)
+      /* change ALGOMODE to key preparation for decryption*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Wait for BUSY flag to be raised */
+      count = CRYP_TIMEOUT_KEYPREPARATION;
+      do
       {
-        /* Change state */
-        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-        hcryp->State = HAL_CRYP_STATE_READY;
+        count-- ;
+        if (count == 0U)
+        {
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
 
-        /* Process unlocked */
-        __HAL_UNLOCK(hcryp);
-        return HAL_ERROR;
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
       }
-    } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+      while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
 
-    /* Turn back to ALGOMODE of the configuration */
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
-  }
-  else  /*Algorithm CTR */
-  {
-    /*  Set the Key*/
-    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-  }
+      /* Turn back to ALGOMODE of the configuration */
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+    }
+    else  /*Algorithm CTR */
+    {
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    }
+
+    /* Set IV */
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+      hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    }
+  } /* if (DoKeyIVConfig == 1U) */
 
-  /* Set IV */
-  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
-  {
-    /* Set the Initialization Vector*/
-    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
-  }
-} /* if (DoKeyIVConfig == 1U) */
-    
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
   if (hcryp->Size != 0U)
@@ -2348,56 +2361,57 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
 
   if (DoKeyIVConfig == 1U)
   {
-  /*  Key preparation for ECB/CBC */
-  if (hcryp->Init.Algorithm != CRYP_AES_CTR)
-  {
-    /* change ALGOMODE to key preparation for decryption*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
-
-    /*  Set the Key*/
-    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE(hcryp);
-
-    /* Wait for BUSY flag to be raised */
-    count = CRYP_TIMEOUT_KEYPREPARATION;
-    do
+    /*  Key preparation for ECB/CBC */
+    if (hcryp->Init.Algorithm != CRYP_AES_CTR)
     {
-      count-- ;
-      if (count == 0U)
+      /* change ALGOMODE to key preparation for decryption*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
+
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+      /* Enable CRYP */
+      __HAL_CRYP_ENABLE(hcryp);
+
+      /* Wait for BUSY flag to be raised */
+      count = CRYP_TIMEOUT_KEYPREPARATION;
+      do
       {
-        /* Disable the CRYP peripheral clock */
-        __HAL_CRYP_DISABLE(hcryp);
+        count-- ;
+        if (count == 0U)
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
 
-        /* Change state */
-        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-        hcryp->State = HAL_CRYP_STATE_READY;
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
 
-        /* Process unlocked */
-        __HAL_UNLOCK(hcryp);
-        return HAL_ERROR;
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
       }
-    } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+      while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
 
-    /* Turn back to ALGOMODE of the configuration */
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
-  }
-  else  /*Algorithm CTR */
-  {
-    /*  Set the Key*/
-    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-  }
+      /* Turn back to ALGOMODE of the configuration */
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
+    }
+    else  /*Algorithm CTR */
+    {
+      /*  Set the Key*/
+      CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    }
 
-  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
-  {
-    /* Set the Initialization Vector*/
-    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
-  }
-} /* if (DoKeyIVConfig == 1U) */
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+      hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+      hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+      hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    }
+  } /* if (DoKeyIVConfig == 1U) */
 
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -2405,7 +2419,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
   if (hcryp->Size != 0U)
   {
     /* Set the input and output addresses and start DMA transfer */
-    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
+                      (uint32_t)(hcryp->pCrypOutBuffPtr));
   }
   else
   {
@@ -2455,28 +2470,28 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
   uint32_t npblb;
   uint32_t lastwordsize;
   uint32_t temp;  /* Temporary CrypOutBuff */
-  uint32_t temp_cr_algodir;  
+  uint32_t temp_cr_algodir;
   CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
 
   /* Disable the DMA transfer for output FIFO */
   hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
-  
+
   /* Last block transfer in case of GCM or CCM with Size not %16*/
   if (((hcryp->Size) % 16U) != 0U)
   {
     /* set CrypInCount and CrypOutCount to exact number of word already computed via DMA  */
     hcryp->CrypInCount = (hcryp->Size / 16U) * 4U ;
     hcryp->CrypOutCount = hcryp->CrypInCount;
-    
+
     /* Compute the number of padding bytes in last block of payload */
     npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
-    
+
 #if !defined (CRYP_VER_2_2)
     if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
     {
-    /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
+      /* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
       temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
       if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
           ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
@@ -2491,7 +2506,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
         __HAL_CRYP_ENABLE(hcryp);
       }
     }
-    
+
     /* Number of valid words (lastwordsize) in last block */
     if ((npblb % 4U) == 0U)
     {
@@ -2537,12 +2552,14 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
         HAL_CRYP_ErrorCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
       }
-    } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
+    }
+    while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
 
     /*Read the output block from the output FIFO */
     for (count = 0U; count < 4U; count++)
     {
-      /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+      /* Read the output block from the output FIFO and put them in temporary buffer
+         then get CrypOutBuff from temporary buffer */
       temp = hcryp->Instance->DOUT;
 
       *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
@@ -2714,13 +2731,14 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 
   if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
   {
-    /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
+    /* Read the output block from the Output FIFO and put them in temporary buffer
+       then get CrypOutBuff from temporary buffer  */
     for (i = 0U; i < 4U; i++)
     {
       temp[i] = hcryp->Instance->DOUT;
     }
     i = 0U;
-    while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+    while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
     {
       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
       hcryp->CrypOutCount++;
@@ -2781,13 +2799,14 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
 
     if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
     {
-      /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
+      /* Read the output block from the output FIFO and put them in temporary buffer
+         then get CrypOutBuff from temporary buffer  */
       for (i = 0U; i < 4U; i++)
       {
         temp[i] = hcryp->Instance->DOUT;
       }
       i = 0U;
-      while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+      while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
       {
         *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
         hcryp->CrypOutCount++;
@@ -2890,6 +2909,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
   uint32_t temp[4];  /* Temporary CrypOutBuff */
   uint32_t index ;
   uint32_t lastwordsize ;
+  uint32_t nolastpaddingbytes;
+  uint8_t *pval;
   uint16_t outcount;  /* Temporary CrypOutCount Value */
   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
@@ -2918,80 +2939,80 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
 
   if (DoKeyIVConfig == 1U)
   {
-  /*  Reset CrypHeaderCount */
-  hcryp->CrypHeaderCount = 0U;
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
 
-  /****************************** Init phase **********************************/
+    /****************************** Init phase **********************************/
 
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
 
-  /* Set the key */
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-  /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
-  hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-  hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-  hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-  hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
 
-  /* Get tick */
-  tickstart = HAL_GetTick();
+    /* Get tick */
+    tickstart = HAL_GetTick();
 
-  /*Wait for the CRYPEN bit to be cleared*/
-  while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
+    /*Wait for the CRYPEN bit to be cleared*/
+    while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
     {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
       {
-        /* Disable the CRYP peripheral clock */
-        __HAL_CRYP_DISABLE(hcryp);
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
 
-        /* Change state */
-        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-        hcryp->State = HAL_CRYP_STATE_READY;
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
 
-        /* Process unlocked */
-        __HAL_UNLOCK(hcryp);
-        return HAL_ERROR;
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
       }
     }
-  }
 
-  /************************ Header phase *************************************/
+    /************************ Header phase *************************************/
 
-  if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
+    if (CRYP_GCMCCM_SetHeaderPhase(hcryp,  Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
 
-  /*************************Payload phase ************************************/
+    /*************************Payload phase ************************************/
 
-  /* Set the phase */
-  hcryp->Phase = CRYP_PHASE_PROCESS;
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
 
-  /* Disable the CRYP peripheral */
-  __HAL_CRYP_DISABLE(hcryp);
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
 
 #if !defined (CRYP_VER_2_2)
-  if (hcryp->Version >= REV_ID_B)
+    if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-  {
-    /* Set to 0 the number of non-valid bytes using NPBLB register*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
-  }
+    {
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
+    }
 
-  /* Select payload phase once the header phase is performed */
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+    /* Select payload phase once the header phase is performed */
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
+  } /* if (DoKeyIVConfig == 1U) */
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
-} /* if (DoKeyIVConfig == 1U) */
-  
   if ((hcryp->Size % 16U) != 0U)
   {
     /* recalculate  wordsize */
@@ -3103,12 +3124,52 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
       {
         for (index = 0U; index < 4U; index++)
         {
-          /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+          /* Read the output block from the output FIFO and put them in temporary buffer
+          then get CrypOutBuff from temporary buffer */
           temp[index] = hcryp->Instance->DOUT;
         }
-        for (index=0; index<lastwordsize; index++)
+
+        for (index = 0U; index < lastwordsize; index++)
         {
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
+          pval = (uint8_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount));
+
+          if (index == (lastwordsize - 1U))
+          {
+            nolastpaddingbytes = npblb % 4U;
+
+            switch (nolastpaddingbytes)
+            {
+              case 1:
+                *(pval) = (uint8_t)(temp[index]);
+                pval++;
+                *(pval) = (uint8_t)(temp[index] >> 8U);
+                pval++;
+                *(pval) = (uint8_t)(temp[index] >> 16U);
+                break;
+              case 2:
+                *(pval) = (uint8_t)(temp[index]);
+                pval++;
+                *(pval) = (uint8_t)(temp[index] >> 8U);
+                break;
+              case 3:
+                *(pval) = (uint8_t)(temp[index]);
+                break;
+              default:
+                *(pval) = (uint8_t)(temp[index]);
+                pval++;
+                *(pval) = (uint8_t)(temp[index] >> 8U);
+                pval++;
+                *(pval) = (uint8_t)(temp[index] >> 16U);
+                pval++;
+                *(pval) = (uint8_t)(temp[index] >> 24U);
+                break;
+            }
+          }
+          else
+          {
+            *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
+          }
+
           hcryp->CrypOutCount++;
         }
       }
@@ -3164,49 +3225,50 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
   /* Configure Key, IV and process message (header and payload) */
   if (DoKeyIVConfig == 1U)
   {
-  /*  Reset CrypHeaderCount */
-  hcryp->CrypHeaderCount = 0U;
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
 
-  /******************************* Init phase *********************************/
+    /******************************* Init phase *********************************/
 
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
 
-  /* Set the key */
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-  /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
-  hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-  hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-  hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-  hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
 
-  /*Wait for the CRYPEN bit to be cleared*/
-  count = CRYP_TIMEOUT_GCMCCMINITPHASE;
-  do
-  {
-    count-- ;
-    if (count == 0U)
+    /*Wait for the CRYPEN bit to be cleared*/
+    count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+    do
     {
-      /* Disable the CRYP peripheral clock */
-      __HAL_CRYP_DISABLE(hcryp);
+      count-- ;
+      if (count == 0U)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
 
-      /* Change state */
-      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-      hcryp->State = HAL_CRYP_STATE_READY;
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
 
-      /* Process unlocked */
-      __HAL_UNLOCK(hcryp);
-      return HAL_ERROR;
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
     }
-  } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+    while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
 
-  /***************************** Header phase *********************************/
+    /***************************** Header phase *********************************/
 
-  /* Select header phase */
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+    /* Select header phase */
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
   } /* end of if (DoKeyIVConfig == 1U) */
   /* Enable interrupts */
   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
@@ -3260,73 +3322,74 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
 
   if (DoKeyIVConfig == 1U)
   {
- /*  Reset CrypHeaderCount */
-  hcryp->CrypHeaderCount = 0U;
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
 
-  /*************************** Init phase ************************************/
+    /*************************** Init phase ************************************/
 
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
 
-  /* Set the key */
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-  /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
-  hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-  hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-  hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-  hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
+    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
+    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
+    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
 
-  /*Wait for the CRYPEN bit to be cleared*/
-  count = CRYP_TIMEOUT_GCMCCMINITPHASE;
-  do
-  {
-    count-- ;
-    if (count == 0U)
+    /*Wait for the CRYPEN bit to be cleared*/
+    count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+    do
     {
-      /* Disable the CRYP peripheral clock */
-      __HAL_CRYP_DISABLE(hcryp);
+      count-- ;
+      if (count == 0U)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
 
-      /* Change state */
-      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-      hcryp->State = HAL_CRYP_STATE_READY;
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
 
-      /* Process unlocked */
-      __HAL_UNLOCK(hcryp);
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+    while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+    /************************ Header phase *************************************/
+
+    if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+    {
       return HAL_ERROR;
     }
-  } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
 
-  /************************ Header phase *************************************/
+    /************************ Payload phase ************************************/
 
-  if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
 
-  /************************ Payload phase ************************************/
-
-  /* Set the phase */
-  hcryp->Phase = CRYP_PHASE_PROCESS;
-
-  /* Disable the CRYP peripheral */
-  __HAL_CRYP_DISABLE(hcryp);
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
 
 #if !defined (CRYP_VER_2_2)
-  if (hcryp->Version >= REV_ID_B)
+    if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-  {
-    /* Set to 0 the number of non-valid bytes using NPBLB register*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
-  }
+    {
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
+    }
 
-  /* Select payload phase once the header phase is performed */
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+    /* Select payload phase once the header phase is performed */
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+
+  } /* if (DoKeyIVConfig == 1U) */
 
-} /* if (DoKeyIVConfig == 1U) */
-    
   if (hcryp->Size == 0U)
   {
     /* Process unLocked */
@@ -3338,13 +3401,15 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
   else if (hcryp->Size >= 16U)
   {
     /* for STM32H7 below rev.B : Size should be %4  otherwise Tag will  be incorrectly generated for GCM Encryption:
-    Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise TAG is incorrectly generated */
+    Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise
+    TAG is incorrectly generated */
 
     /*DMA transfer must not include the last block in case of Size is not %16 */
     wordsize = wordsize - (wordsize % 4U);
 
     /*DMA transfer */
-    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize,
+                      (uint32_t)(hcryp->pCrypOutBuffPtr));
   }
   else /* length of input data is < 16 */
   {
@@ -3413,15 +3478,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
         HAL_CRYP_ErrorCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
       }
-    } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
+    }
+    while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
 
     /*Read the output block from the output FIFO */
     for (index = 0U; index < 4U; index++)
     {
-      /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+      /* Read the output block from the output FIFO and put them in temporary buffer
+      then get CrypOutBuff from temporary buffer */
       temp[index] = hcryp->Instance->DOUT;
     }
-    for (index=0; index<lastwordsize; index++)
+    for (index = 0; index < lastwordsize; index++)
     {
       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
       hcryp->CrypOutCount++;
@@ -3482,130 +3549,130 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
 
   if (DoKeyIVConfig == 1U)
   {
-  /*  Reset CrypHeaderCount */
-  hcryp->CrypHeaderCount = 0U;
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
 
-  /********************** Init phase ******************************************/
+    /********************** Init phase ******************************************/
 
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
 
-  /* Set the key */
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-  /* Set the initialization vector (IV) with CTR1 information */
-  hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
-  hcryp->Instance->IV0RR = hcryp->Init.B0[1];
-  hcryp->Instance->IV1LR = hcryp->Init.B0[2];
-  hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
+    /* Set the initialization vector (IV) with CTR1 information */
+    hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+    hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+    hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+    hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
 
 #if defined (CRYP_VER_2_2)
-  {
-    /* for STM32H7 rev.B and above Write  B0 packet into CRYP_DR*/
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
-  }
-#else
-  if (hcryp->Version >= REV_ID_B)
-  {
-    /* for STM32H7 rev.B and above Write  B0 packet into CRYP_DR*/
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
-  }
-  else /* data has to be swapped according to the DATATYPE */
-  {
-    if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
-    {
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
-    }
-    else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
-    {
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
-    }
-    else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
-    {
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
-    }
-    else
     {
+      /* for STM32H7 rev.B and above Write  B0 packet into CRYP_DR*/
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
     }
-  }
-#endif
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /*Wait for the CRYPEN bit to be cleared*/
-  while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
+#else
+    if (hcryp->Version >= REV_ID_B)
     {
-      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      /* for STM32H7 rev.B and above Write  B0 packet into CRYP_DR*/
+      hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+      hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+      hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+      hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+    }
+    else /* data has to be swapped according to the DATATYPE */
+    {
+      if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
       {
-        /* Disable the CRYP peripheral clock */
-        __HAL_CRYP_DISABLE(hcryp);
-
-        /* Change state */
-        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-        hcryp->State = HAL_CRYP_STATE_READY;
-
-        /* Process unlocked */
-        __HAL_UNLOCK(hcryp);
-        return HAL_ERROR;
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
+      }
+      else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
+      {
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+      }
+      else if (hcryp->Init.DataType == CRYP_BIT_SWAP)
+      {
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+      }
+      else
+      {
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
       }
     }
-  }
+#endif /* CRYP_VER_2_2 */
+    /* Get tick */
+    tickstart = HAL_GetTick();
 
-  /************************* Header phase *************************************/
-  /* Header block(B1) : associated data length expressed in bytes concatenated
-  with Associated Data (A)*/
+    /*Wait for the CRYPEN bit to be cleared*/
+    while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
+    {
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          /* Disable the CRYP peripheral clock */
+          __HAL_CRYP_DISABLE(hcryp);
 
-  if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-  /********************** Payload phase ***************************************/
+          /* Change state */
+          hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+          hcryp->State = HAL_CRYP_STATE_READY;
 
-  /* Set the phase */
-  hcryp->Phase = CRYP_PHASE_PROCESS;
+          /* Process unlocked */
+          __HAL_UNLOCK(hcryp);
+          return HAL_ERROR;
+        }
+      }
+    }
 
-  /* Disable the CRYP peripheral */
-  __HAL_CRYP_DISABLE(hcryp);
+    /************************* Header phase *************************************/
+    /* Header block(B1) : associated data length expressed in bytes concatenated
+    with Associated Data (A)*/
+
+    if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+    /********************** Payload phase ***************************************/
+
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
+
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
 #if !defined (CRYP_VER_2_2)
-  if (hcryp->Version >= REV_ID_B)
+    if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-  {
-    /* Set to 0 the number of non-valid bytes using NPBLB register*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
-  }
+    {
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
+    }
 
-  /* Select payload phase once the header phase is performed */
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+    /* Select payload phase once the header phase is performed */
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
+
+  } /* if (DoKeyIVConfig == 1U) */
 
-} /* if (DoKeyIVConfig == 1U) */
-   
   if ((hcryp->Size % 16U) != 0U)
   {
     /* recalculate  wordsize */
@@ -3716,22 +3783,23 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
       {
         for (index = 0U; index < 4U; index++)
         {
-          /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+          /* Read the output block from the output FIFO and put them in temporary buffer
+          then get CrypOutBuff from temporary buffer */
           temp[index] = hcryp->Instance->DOUT;
         }
-        for (index=0; index<lastwordsize; index++)
+        for (index = 0; index < lastwordsize; index++)
         {
           *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
           hcryp->CrypOutCount++;
-        } 
+        }
       }
     }
 #if !defined (CRYP_VER_2_2)
     else /* No NPBLB, Workaround to be used */
     {
-      /* CRYP Workaround :  CRYP1 generates correct TAG  during CCM decryption only when ciphertext blocks size is multiple of
-      128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
-      is selected, then the TAG message will be wrong.*/
+      /* CRYP Workaround :  CRYP1 generates correct TAG  during CCM decryption only when ciphertext
+      blocks size is multiple of 128 bits. If lthe size of the last block of payload is inferior to 128 bits,
+      when CCM decryption is selected, then the TAG message will be wrong.*/
       CRYP_Workaround(hcryp, Timeout);
     }
 #endif /*End of not defined CRYP_VER_2_2*/
@@ -3778,92 +3846,93 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
   /* Configure Key, IV and process message (header and payload) */
   if (DoKeyIVConfig == 1U)
   {
-  /*  Reset CrypHeaderCount */
-  hcryp->CrypHeaderCount = 0U;
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
 
-  /************ Init phase ************/
+    /************ Init phase ************/
 
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
 
-  /* Set the key */
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-  /* Set the initialization vector (IV) with CTR1 information */
-  hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
-  hcryp->Instance->IV0RR = hcryp->Init.B0[1];
-  hcryp->Instance->IV1LR = hcryp->Init.B0[2];
-  hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
+    /* Set the initialization vector (IV) with CTR1 information */
+    hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+    hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+    hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+    hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
 
-  /*Write the B0 packet into CRYP_DR*/
+    /*Write the B0 packet into CRYP_DR*/
 #if !defined (CRYP_VER_2_2)
-  if (hcryp->Version >= REV_ID_B)
+    if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-  {
-    /* for STM32H7 rev.B and above data has not to be swapped */
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
-  }
-#if !defined (CRYP_VER_2_2)
-  else /* data has to be swapped according to the DATATYPE */
-  {
-    if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
-    {
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
-    }
-    else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
-    {
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
-    }
-    else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
-    {
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
-    }
-    else
     {
+      /* for STM32H7 rev.B and above data has not to be swapped */
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
     }
-  }
-#endif /*End of not defined CRYP_VER_2_2*/
-  /*Wait for the CRYPEN bit to be cleared*/
-  count = CRYP_TIMEOUT_GCMCCMINITPHASE;
-  do
-  {
-    count-- ;
-    if (count == 0U)
+#if !defined (CRYP_VER_2_2)
+    else /* data has to be swapped according to the DATATYPE */
     {
-      /* Disable the CRYP peripheral clock */
-      __HAL_CRYP_DISABLE(hcryp);
-
-      /* Change state */
-      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-      hcryp->State = HAL_CRYP_STATE_READY;
-
-      /* Process unlocked */
-      __HAL_UNLOCK(hcryp);
-      return HAL_ERROR;
+      if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
+      {
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
+      }
+      else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
+      {
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+      }
+      else if (hcryp->Init.DataType == CRYP_BIT_SWAP)
+      {
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+      }
+      else
+      {
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+      }
     }
-  } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+#endif /*End of not defined CRYP_VER_2_2*/
+    /*Wait for the CRYPEN bit to be cleared*/
+    count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+    do
+    {
+      count-- ;
+      if (count == 0U)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
 
-  /* Select header phase */
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-} /* end of if (DoKeyIVConfig == 1U) */
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+    while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+    /* Select header phase */
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
+  } /* end of if (DoKeyIVConfig == 1U) */
   /* Enable interrupts */
   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
 
@@ -3914,113 +3983,114 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
 
   if (DoKeyIVConfig == 1U)
   {
-  /*  Reset CrypHeaderCount */
-  hcryp->CrypHeaderCount = 0U;
+    /*  Reset CrypHeaderCount */
+    hcryp->CrypHeaderCount = 0U;
 
-  /************************** Init phase **************************************/
+    /************************** Init phase **************************************/
 
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
 
-  /* Set the key */
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+    /* Set the key */
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
 
-  /* Set the initialization vector (IV) with CTR1 information */
-  hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
-  hcryp->Instance->IV0RR = hcryp->Init.B0[1];
-  hcryp->Instance->IV1LR = hcryp->Init.B0[2];
-  hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
+    /* Set the initialization vector (IV) with CTR1 information */
+    hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
+    hcryp->Instance->IV0RR = hcryp->Init.B0[1];
+    hcryp->Instance->IV1LR = hcryp->Init.B0[2];
+    hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) |  CRYP_CCM_CTR1_2;
 
-  /* Enable the CRYP peripheral */
-  __HAL_CRYP_ENABLE(hcryp);
+    /* Enable the CRYP peripheral */
+    __HAL_CRYP_ENABLE(hcryp);
 
-  /*Write the B0 packet into CRYP_DR*/
+    /*Write the B0 packet into CRYP_DR*/
 #if !defined (CRYP_VER_2_2)
-  if (hcryp->Version >= REV_ID_B)
+    if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-  {
-    /* for STM32H7 rev.B and above data has not to be swapped */
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
-    hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
-  }
-#if !defined (CRYP_VER_2_2)
-  else /* data has to be swapped according to the DATATYPE */
-  {
-    if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
-    {
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
-      hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
-    }
-    else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
-    {
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
-      hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
-    }
-    else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
-    {
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
-      hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
-    }
-    else
     {
+      /* for STM32H7 rev.B and above data has not to be swapped */
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
       hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
     }
-  }
-#endif /*End of not defined CRYP_VER_2_2*/
-  /*Wait for the CRYPEN bit to be cleared*/
-  count = CRYP_TIMEOUT_GCMCCMINITPHASE;
-  do
-  {
-    count-- ;
-    if (count == 0U)
+#if !defined (CRYP_VER_2_2)
+    else /* data has to be swapped according to the DATATYPE */
     {
-      /* Disable the CRYP peripheral clock */
-      __HAL_CRYP_DISABLE(hcryp);
+      if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
+      {
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
+        hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
+      }
+      else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
+      {
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
+        hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
+      }
+      else if (hcryp->Init.DataType == CRYP_BIT_SWAP)
+      {
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
+        hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
+      }
+      else
+      {
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
+        hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
+      }
+    }
+#endif /*End of not defined CRYP_VER_2_2*/
+    /*Wait for the CRYPEN bit to be cleared*/
+    count = CRYP_TIMEOUT_GCMCCMINITPHASE;
+    do
+    {
+      count-- ;
+      if (count == 0U)
+      {
+        /* Disable the CRYP peripheral clock */
+        __HAL_CRYP_DISABLE(hcryp);
 
-      /* Change state */
-      hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
-      hcryp->State = HAL_CRYP_STATE_READY;
+        /* Change state */
+        hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
+        hcryp->State = HAL_CRYP_STATE_READY;
 
-      /* Process unlocked */
-      __HAL_UNLOCK(hcryp);
+        /* Process unlocked */
+        __HAL_UNLOCK(hcryp);
+        return HAL_ERROR;
+      }
+    }
+    while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
+
+    /********************* Header phase *****************************************/
+
+    if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
+    {
       return HAL_ERROR;
     }
-  } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
 
-  /********************* Header phase *****************************************/
+    /******************** Payload phase *****************************************/
 
-  if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
+    /* Set the phase */
+    hcryp->Phase = CRYP_PHASE_PROCESS;
 
-  /******************** Payload phase *****************************************/
-
-  /* Set the phase */
-  hcryp->Phase = CRYP_PHASE_PROCESS;
-
-  /* Disable the CRYP peripheral */
-  __HAL_CRYP_DISABLE(hcryp);
+    /* Disable the CRYP peripheral */
+    __HAL_CRYP_DISABLE(hcryp);
 #if !defined (CRYP_VER_2_2)
-  if (hcryp->Version >= REV_ID_B)
+    if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-  {
-    /* Set to 0 the number of non-valid bytes using NPBLB register*/
-    MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
-  }
+    {
+      /* Set to 0 the number of non-valid bytes using NPBLB register*/
+      MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
+    }
 
-  /* Select payload phase once the header phase is performed */
-  CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+    /* Select payload phase once the header phase is performed */
+    CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
   } /* if (DoKeyIVConfig == 1U) */
 
   if (hcryp->Size == 0U)
@@ -4033,12 +4103,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
   }
   else if (hcryp->Size >= 16U)
   {
-    /* for STM32H7 below rev.B ::  Size should be %4  otherwise Tag will  be incorrectly generated for CCM Decryption, Workaround is implemented in polling mode*/
+    /* for STM32H7 below rev.B ::  Size should be %4  otherwise Tag will  be incorrectly generated for CCM Decryption,
+    Workaround is implemented in polling mode*/
     /*DMA transfer must not include the last block in case of Size is not %16 */
     wordsize = wordsize - (wordsize % 4U);
 
     /*DMA transfer */
-    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr));
+    CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t) wordsize,
+                      (uint32_t)(hcryp->pCrypOutBuffPtr));
   }
   else /* length of input data is  < 16U */
   {
@@ -4107,15 +4179,17 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
         HAL_CRYP_ErrorCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
       }
-    } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
+    }
+    while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE));
 
     /*Read the output block from the output FIFO */
     for (index = 0U; index < 4U; index++)
     {
-      /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+      /* Read the output block from the output FIFO and put them in temporary buffer
+      then get CrypOutBuff from temporary buffer */
       temp[index] = hcryp->Instance->DOUT;
     }
-    for (index=0; index<lastwordsize; index++)
+    for (index = 0; index < lastwordsize; index++)
     {
       *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
       hcryp->CrypOutCount++;
@@ -4166,11 +4240,11 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
     /* Change the CRYP state */
     hcryp->State = HAL_CRYP_STATE_READY;
   }
-  
+
   else if ((((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) &&
            (negative == 0U))
   {
-    if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
+    if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
     {
       /* Write the input block in the IN FIFO */
       hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
@@ -4194,18 +4268,19 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
         HAL_CRYP_InCpltCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
       }
-      
-      if (hcryp->CrypOutCount < (hcryp->Size / 4U))     
+
+      if (hcryp->CrypOutCount < (hcryp->Size / 4U))
       {
         if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
         {
-          /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
+          /* Read the output block from the Output FIFO and put them in temporary buffer
+          then get CrypOutBuff from temporary buffer  */
           for (i = 0U; i < 4U; i++)
           {
             temp[i] = hcryp->Instance->DOUT;
           }
           i = 0U;
-          while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+          while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
           {
             *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
             hcryp->CrypOutCount++;
@@ -4218,20 +4293,20 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
 
             /* Change the CRYP state */
             hcryp->State = HAL_CRYP_STATE_READY;
-            
+
             /* Disable CRYP */
             __HAL_CRYP_DISABLE(hcryp);
-            
+
             /* Process unlocked */
             __HAL_UNLOCK(hcryp);
-            
+
             /* Call output transfer complete callback */
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-        /*Call registered Output complete callback*/
-        hcryp->OutCpltCallback(hcryp);
+            /*Call registered Output complete callback*/
+            hcryp->OutCpltCallback(hcryp);
 #else
-        /*Call legacy weak Output complete callback*/
-        HAL_CRYP_OutCpltCallback(hcryp);
+            /*Call legacy weak Output complete callback*/
+            HAL_CRYP_OutCpltCallback(hcryp);
 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
           }
         }
@@ -4240,59 +4315,59 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
   }
   else if ((hcryp->Size % 16U) != 0U)
   {
-	/* Set padding only in case of input fifo interrupt */
-	if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
- {
-    /* Compute the number of padding bytes in last block of payload */
-    npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
-    
+    /* Set padding only in case of input fifo interrupt */
+    if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM) != 0x0U)
+    {
+      /* Compute the number of padding bytes in last block of payload */
+      npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
+
 #if !defined (CRYP_VER_2_2)
-    if (hcryp->Version >= REV_ID_B)
+      if (hcryp->Version >= REV_ID_B)
 #endif /*End of not defined CRYP_VER_2_2*/
-    {
-      /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
-      temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
-
-      if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
-          ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
       {
-        /* Disable the CRYP */
-        __HAL_CRYP_DISABLE(hcryp);
+        /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
+        temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
 
-        /* Specify the number of non-valid bytes using NPBLB register*/
-        MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
+        if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
+            ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
+        {
+          /* Disable the CRYP */
+          __HAL_CRYP_DISABLE(hcryp);
 
-        /* Enable CRYP to start the final phase */
-        __HAL_CRYP_ENABLE(hcryp);
+          /* Specify the number of non-valid bytes using NPBLB register*/
+          MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
+
+          /* Enable CRYP to start the final phase */
+          __HAL_CRYP_ENABLE(hcryp);
+        }
       }
-    }
 
-    /* Number of valid words (lastwordsize) in last block */
-    if ((npblb % 4U) == 0U)
-    {
-      lastwordsize = (16U - npblb) / 4U;
-    }
-    else
-    {
-      lastwordsize = ((16U - npblb) / 4U) + 1U;
-    }
+      /* Number of valid words (lastwordsize) in last block */
+      if ((npblb % 4U) == 0U)
+      {
+        lastwordsize = (16U - npblb) / 4U;
+      }
+      else
+      {
+        lastwordsize = ((16U - npblb) / 4U) + 1U;
+      }
 
-    /* Write the last input block in the IN FIFO */
-    for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
-    {
-      hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
-      hcryp->CrypInCount++;
-    }
-    /* Pad the data with zeros to have a complete block */
-    while (loopcounter < 4U)
-    {
-      hcryp->Instance->DIN  = 0U;
-      loopcounter++;
-    }
+      /* Write the last input block in the IN FIFO */
+      for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
+      {
+        hcryp->Instance->DIN  = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
+        hcryp->CrypInCount++;
+      }
+      /* Pad the data with zeros to have a complete block */
+      while (loopcounter < 4U)
+      {
+        hcryp->Instance->DIN  = 0U;
+        loopcounter++;
+      }
 
-    /* Disable the input FIFO Interrupt */
-    __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-	}
+      /* Disable the input FIFO Interrupt */
+      __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
+    }
 
     /*Read the output block from the output FIFO */
     if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
@@ -4301,16 +4376,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
       {
         temp[i] = hcryp->Instance->DOUT;
       }
-      if (( (hcryp->Size)/4U)==0U)
+      if (((hcryp->Size) / 4U) == 0U)
       {
-        for (i = 0U; (uint16_t)i<((hcryp->Size)%4U); i++)
+        for (i = 0U; (uint16_t)i < ((hcryp->Size) % 4U); i++)
         {
           *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
           hcryp->CrypOutCount++;
-        }     
+        }
       }
       i = 0U;
-      while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+      while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
       {
         *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
         hcryp->CrypOutCount++;
@@ -4386,7 +4461,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
     {
       /*  No padding */
       for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
-      
+
       {
         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
         hcryp->CrypHeaderCount++ ;
@@ -4460,17 +4535,17 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u
       }
       else
       {
-         /* Enter last bytes, padded with zeroes */
-         tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
-         tmp &= mask[size_in_bytes % 4U];
-         hcryp->Instance->DIN = tmp;
-         loopcounter++;
-         /* Pad the data with zeros to have a complete block */
-         while (loopcounter < 4U)
-         {
-           hcryp->Instance->DIN = 0x0U;
-           loopcounter++;
-         }
+        /* Enter last bytes, padded with zeroes */
+        tmp =  *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+        tmp &= mask[size_in_bytes % 4U];
+        hcryp->Instance->DIN = tmp;
+        loopcounter++;
+        /* Pad the data with zeros to have a complete block */
+        while (loopcounter < 4U)
+        {
+          hcryp->Instance->DIN = 0x0U;
+          loopcounter++;
+        }
       }
       /* Wait for CCF IFEM to be raised */
       if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
@@ -4558,13 +4633,15 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
             __HAL_UNLOCK(hcryp);
             return HAL_ERROR;
           }
-        } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+        }
+        while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
       }
     }
     else
     {
       /*Write header block in the IN FIFO without last block */
-      for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+      for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
+           loopcounter += 4U)
       {
         hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
         hcryp->CrypHeaderCount++ ;
@@ -4593,7 +4670,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
             __HAL_UNLOCK(hcryp);
             return HAL_ERROR;
           }
-        } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+        }
+        while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
       }
       /*  Last block optionally pad the data with zeros*/
       for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
@@ -4623,7 +4701,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
           __HAL_UNLOCK(hcryp);
           return HAL_ERROR;
         }
-      } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
+      }
+      while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
     }
     /* Wait until the complete message has been processed */
     count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
@@ -4641,7 +4720,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry
         __HAL_UNLOCK(hcryp);
         return HAL_ERROR;
       }
-    } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
+    }
+    while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
   }
 
   /* Return function status */
@@ -4760,7 +4840,7 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
       __HAL_CRYP_DISABLE(hcryp);
 
       /*Update CRYP_IV1R register and ALGOMODE*/
-      hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R)-1U);
+      hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
 
       /* Enable CRYP to start the final phase */
@@ -4823,67 +4903,67 @@ static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
       /* configured  final phase  */
       MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
 
-      if ( (hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
+      if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_NO_SWAP)
       {
-        if ((npblb %4U)==1U)
+        if ((npblb % 4U) == 1U)
         {
-          intermediate_data[lastwordsize-1U] &= 0xFFFFFF00U;
+          intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
         }
-        if ((npblb %4U)==2U)
+        if ((npblb % 4U) == 2U)
         {
-          intermediate_data[lastwordsize-1U] &= 0xFFFF0000U;
+          intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
         }
-        if ((npblb %4U)==3U)
+        if ((npblb % 4U) == 3U)
         {
-          intermediate_data[lastwordsize-1U] &= 0xFF000000U;
+          intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
         }
       }
-      else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
+      else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_BYTE_SWAP)
       {
-        if ((npblb %4U)==1U)
+        if ((npblb % 4U) == 1U)
         {
-          intermediate_data[lastwordsize-1U] &= __REV(0xFFFFFF00U);
+          intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
         }
-        if ((npblb %4U)==2U)
+        if ((npblb % 4U) == 2U)
         {
-          intermediate_data[lastwordsize-1U] &= __REV(0xFFFF0000U);
+          intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
         }
-        if ((npblb %4U)==3U)
+        if ((npblb % 4U) == 3U)
         {
-          intermediate_data[lastwordsize-1U] &= __REV(0xFF000000U);
+          intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
         }
       }
-      else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
+      else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_HALFWORD_SWAP)
       {
-        if ((npblb %4U)==1U)
+        if ((npblb % 4U) == 1U)
         {
-          intermediate_data[lastwordsize-1U] &= __ROR((0xFFFFFF00U), 16);
+          intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
         }
-        if ((npblb %4U)==2U)
+        if ((npblb % 4U) == 2U)
         {
-          intermediate_data[lastwordsize-1U] &= __ROR((0xFFFF0000U), 16);
+          intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
         }
-        if ((npblb %4U)==3U)
+        if ((npblb % 4U) == 3U)
         {
-          intermediate_data[lastwordsize-1U] &= __ROR((0xFF000000U), 16);
+          intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
         }
       }
-      else /*CRYP_DATATYPE_1B*/
+      else /*CRYP_BIT_SWAP*/
       {
-        if ((npblb %4U)==1U)
+        if ((npblb % 4U) == 1U)
         {
-          intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFFFF00U);
+          intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
         }
-        if ((npblb %4U)==2U)
+        if ((npblb % 4U) == 2U)
         {
-          intermediate_data[lastwordsize-1U] &= __RBIT(0xFFFF0000U);
+          intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
         }
-        if ((npblb %4U)==3U)
+        if ((npblb % 4U) == 3U)
         {
-          intermediate_data[lastwordsize-1U] &= __RBIT(0xFF000000U);
+          intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
         }
       }
-      
+
       for (index = 0U; index < lastwordsize ; index ++)
       {
         /*Write the intermediate_data in the IN FIFO */
@@ -5160,10 +5240,6 @@ static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef  *hcryp, u
 
 
 
-/**
-  * @}
-  */
-
 /**
   * @}
   */
@@ -5179,4 +5255,3 @@ static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(const CRYP_HandleTypeDef  *hcryp, u
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h
index 619c86285b..a6802ed6ba 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -48,8 +47,8 @@ extern "C" {
 
 typedef struct
 {
-  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                                        This parameter can be a value of @ref CRYP_Data_Type */
+  uint32_t DataType;                   /*!< no swap(32-bit data), halfword swap(16-bit data), byte swap(8-bit data)
+                                        or bit swap(1-bit data).this parameter can be a value of @ref CRYP_Data_Type */
   uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
                                             This parameter can be a value of @ref CRYP_Key_Size */
   uint32_t *pKey;                      /*!< The key used for encryption/decryption */
@@ -61,9 +60,9 @@ typedef struct
   uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
                                         GCM : also known as Additional Authentication Data
                                         CCM : named B1 composed of the associated data length and Associated Data. */
-  uint32_t HeaderSize;                /*!< The size of header buffer */
-  uint32_t *B0;                       /*!< B0 is first authentication block used only  in AES CCM mode */
-  uint32_t DataWidthUnit;             /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+  uint32_t HeaderSize;                 /*!< The size of header buffer */
+  uint32_t *B0;                        /*!< B0 is first authentication block used only  in AES CCM mode */
+  uint32_t DataWidthUnit;              /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
   uint32_t HeaderWidthUnit;            /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
   uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to configure Key and Initialization
                                            Vector only once and to skip configuration for consecutive processing.
@@ -211,7 +210,7 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   */
 
 #define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is word */
+#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< Size unit is byte, but all input will be loaded in HW CRYPT IP by block of 4 words */
 
 /**
   * @}
@@ -222,7 +221,7 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   */
 
 #define CRYP_HEADERWIDTHUNIT_WORD   0x00000000U  /*!< By default, header size unit is word */
-#define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< By default, header size unit is byte */
+#define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< Size unit is byte, but all input will be loaded in HW CRYPT IP by block of 4 words */
 
 /**
   * @}
@@ -262,10 +261,10 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   * @{
   */
 
-#define CRYP_DATATYPE_32B         0x00000000U
-#define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE
+#define CRYP_NO_SWAP         0x00000000U
+#define CRYP_HALFWORD_SWAP   CRYP_CR_DATATYPE_0
+#define CRYP_BYTE_SWAP       CRYP_CR_DATATYPE_1
+#define CRYP_BIT_SWAP        CRYP_CR_DATATYPE
 
 /**
   * @}
@@ -359,8 +358,11 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   */
 #define CRYP_FLAG_MASK  0x0000001FU
 
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
-                                                   ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__)\
+  ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) &\
+                                              ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
+   ((((__HANDLE__)->Instance->RISR) &\
+     ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
 
 /** @brief  Check whether the specified CRYP interrupt is set or not.
   * @param  __HANDLE__: specifies the CRYP handle.
@@ -371,7 +373,8 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   * @retval The state of __INTERRUPT__ (TRUE or FALSE).
   */
 
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR &\
+                                                       (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Enable the CRYP interrupt.
@@ -488,10 +491,10 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
                                  ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \
                                  ((KEYSIZE) == CRYP_KEYSIZE_256B))
 
-#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B)   || \
-                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
-                                   ((DATATYPE) == CRYP_DATATYPE_8B) || \
-                                   ((DATATYPE) == CRYP_DATATYPE_1B))
+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_NO_SWAP)   || \
+                                   ((DATATYPE) == CRYP_HALFWORD_SWAP) || \
+                                   ((DATATYPE) == CRYP_BYTE_SWAP) || \
+                                   ((DATATYPE) == CRYP_BIT_SWAP))
 
 #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
                              ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
@@ -565,4 +568,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
 
 #endif /* STM32H7xx_HAL_CRYP_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c
index d42c72d9dc..ddce86e43b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c
@@ -7,6 +7,17 @@
   *          functionalities of CRYP extension peripheral:
   *           + Extended AES processing functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -16,18 +27,6 @@
     Encryption/Decryption to get the authentication messages.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -103,9 +102,9 @@
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
   * @param  AuthTag: Pointer to the authentication buffer
-  *         the AuthTag generated here is 128bits length, if the TAG length is 
+  *         the AuthTag generated here is 128bits length, if the TAG length is
   *         less than 128bits, user should consider only the valid part of AuthTag
-  *         buffer which correspond exactly to TAG length.  
+  *         buffer which correspond exactly to TAG length.
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
@@ -116,7 +115,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
   uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
   uint32_t tagaddr = (uint32_t)AuthTag;
 
-   /* Correct header length if Init.HeaderSize is actually in bytes */
+  /* Correct header length if Init.HeaderSize is actually in bytes */
   if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
   {
     headerlength /= 4U;
@@ -179,28 +178,28 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
 #if !defined (CRYP_VER_2_2)
     else/* data has to be swapped according to the DATATYPE */
     {
-      if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+      if (hcryp->Init.DataType == CRYP_BIT_SWAP)
       {
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength));
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength));
       }
-      else if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
+      else if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
       {
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = __REV((uint32_t)(headerlength));
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = __REV((uint32_t)(inputlength));
       }
-      else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+      else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
       {
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U);
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U);
       }
-      else if (hcryp->Init.DataType == CRYP_DATATYPE_32B)
+      else if (hcryp->Init.DataType == CRYP_NO_SWAP)
       {
         hcryp->Instance->DIN = 0U;
         hcryp->Instance->DIN = (uint32_t)(headerlength);
@@ -269,9 +268,9 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
   * @param  AuthTag: Pointer to the authentication buffer
-  *         the AuthTag generated here is 128bits length, if the TAG length is 
+  *         the AuthTag generated here is 128bits length, if the TAG length is
   *         less than 128bits, user should consider only the valid part of AuthTag
-  *         buffer which correspond exactly to TAG length.  
+  *         buffer which correspond exactly to TAG length.
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
@@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
 #if !defined (CRYP_VER_2_2)
     else /* data has to be swapped according to the DATATYPE */
     {
-      if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
+      if (hcryp->Init.DataType == CRYP_BYTE_SWAP)
       {
         hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
         ctr0addr += 4U;
@@ -354,7 +353,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
         ctr0addr += 4U;
         hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
       }
-      else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
+      else if (hcryp->Init.DataType == CRYP_HALFWORD_SWAP)
       {
         hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
         ctr0addr += 4U;
@@ -364,7 +363,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
         ctr0addr += 4U;
         hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U);
       }
-      else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
+      else if (hcryp->Init.DataType == CRYP_BIT_SWAP)
       {
         hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr));
         ctr0addr += 4U;
@@ -455,4 +454,3 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.h
index 117598a78a..8820e0b7aa 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -120,4 +119,3 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
 
 #endif /* STM32H7xx_HAL_CRYP_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c
index db5ab8c7da..a5e6225186 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c
@@ -11,6 +11,17 @@
   *           + Peripheral State and Errors functions
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                       ##### DAC Peripheral features #####
@@ -48,6 +59,7 @@
           (DAC_TRIGGER_HR1_TRGO1, DAC_TRIGGER_HR1_TRGO2)
 
       (#) Software using DAC_TRIGGER_SOFTWARE
+
       *** DAC Buffer mode feature ***
       ===============================
       [..]
@@ -60,15 +72,6 @@
       (@) Refer to the device datasheet for more details about output
           impedance value with and without output buffer.
 
-      *** DAC connect feature ***
-      ===============================
-      [..]
-      Each DAC channel can be connected internally.
-      To connect, use
-      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
-      or
-      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH;
-
       *** GPIO configurations guidelines ***
       =====================
       [..]
@@ -219,7 +222,7 @@
       The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
       allows the user to configure dynamically the driver callbacks.
 
-    Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback,
+    Use Functions HAL_DAC_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
@@ -234,8 +237,8 @@
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
-    Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
+    Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
       (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
       (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
       (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
@@ -249,12 +252,12 @@
       (+) All Callbacks
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-      By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init
-      and @ref  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit
+      reset to the legacy weak (overridden) functions in the HAL_DAC_Init
+      and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
       Callbacks can be registered/unregistered in READY state only.
@@ -262,12 +265,12 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit
-      or @ref HAL_DAC_Init function.
+      using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
+      or HAL_DAC_Init function.
 
       When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak (overridden) callbacks are used.
 
      *** DAC HAL driver macros list ***
      =============================================
@@ -283,17 +286,6 @@
       (@) You can refer to the DAC HAL driver header file for more useful macros
 
 @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
   ******************************************************************************
   */
 
@@ -357,7 +349,7 @@
   */
 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
 {
-  /* Check DAC handle */
+  /* Check the DAC peripheral handle */
   if (hdac == NULL)
   {
     return HAL_ERROR;
@@ -418,7 +410,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
   */
 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
 {
-  /* Check DAC handle */
+  /* Check the DAC peripheral handle */
   if (hdac == NULL)
   {
     return HAL_ERROR;
@@ -521,6 +513,12 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
   */
 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
 
@@ -542,6 +540,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
       SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
     }
   }
+
   else
   {
     /* Check if software trigger enabled */
@@ -552,6 +551,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
     }
   }
 
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
 
@@ -574,6 +574,12 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
 
@@ -595,7 +601,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData The destination peripheral Buffer address.
+  * @param  pData The source Buffer address.
   * @param  Length The length of data to be transferred from memory to DAC peripheral
   * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
@@ -604,11 +610,17 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
                                     uint32_t Alignment)
 {
   HAL_StatusTypeDef status;
-  uint32_t tmpreg = 0U;
+  uint32_t tmpreg;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
 
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
@@ -645,14 +657,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
         /* Get DHR12L1 address */
         tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
         break;
-      case DAC_ALIGN_8B_R:
+      default: /* case DAC_ALIGN_8B_R */
         /* Get DHR8R1 address */
         tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
         break;
-      default:
-        break;
     }
   }
+
   else
   {
     /* Set the DMA transfer complete callback for channel2 */
@@ -678,16 +689,13 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
         /* Get DHR12L2 address */
         tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
         break;
-      case DAC_ALIGN_8B_R:
+      default: /* case DAC_ALIGN_8B_R */
         /* Get DHR8R2 address */
         tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
         break;
-      default:
-        break;
     }
   }
 
-  /* Enable the DMA Stream */
   if (Channel == DAC_CHANNEL_1)
   {
     /* Enable the DAC DMA underrun interrupt */
@@ -696,6 +704,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
     /* Enable the DMA Stream */
     status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
   }
+
   else
   {
     /* Enable the DAC DMA underrun interrupt */
@@ -705,6 +714,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
     status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
   }
 
+
   /* Process Unlocked */
   __HAL_UNLOCK(hdac);
 
@@ -734,6 +744,12 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u
   */
 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
 
@@ -754,6 +770,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
     /* Disable the DAC DMA underrun interrupt */
     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
   }
+
   else /* Channel2 is used for */
   {
     /* Disable the DMA Stream */
@@ -763,6 +780,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
     __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
   }
 
+
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
 
@@ -780,22 +798,25 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
   */
 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
 {
-  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
+  uint32_t itsource = hdac->Instance->CR;
+  uint32_t itflag   = hdac->Instance->SR;
+
+  if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
   {
     /* Check underrun flag of DAC channel 1 */
-    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
+    if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
     {
       /* Change DAC state to error state */
       hdac->State = HAL_DAC_STATE_ERROR;
 
-      /* Set DAC error code to chanel1 DMA underrun error */
+      /* Set DAC error code to channel1 DMA underrun error */
       SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
 
       /* Clear the underrun flag */
       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
 
       /* Disable the selected DAC channel1 DMA request */
-      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+      __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
 
       /* Error callback */
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -806,10 +827,11 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
     }
   }
 
-  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
+
+  if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
   {
     /* Check underrun flag of DAC channel 2 */
-    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
+    if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
     {
       /* Change DAC state to error state */
       hdac->State = HAL_DAC_STATE_ERROR;
@@ -821,7 +843,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
       __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
 
       /* Disable the selected DAC channel2 DMA request */
-      CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+      __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
 
       /* Error callback */
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -831,6 +853,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
     }
   }
+
 }
 
 /**
@@ -851,7 +874,13 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
   */
 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
 {
-  __IO uint32_t tmp = 0;
+  __IO uint32_t tmp = 0UL;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
 
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
@@ -863,11 +892,13 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui
   {
     tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
   }
+
   else
   {
     tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
   }
 
+
   /* Set the DAC channel selected data holding register */
   *(__IO uint32_t *) tmp = Data;
 
@@ -968,20 +999,28 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
   * @retval The selected DAC channel data output value.
   */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
+  uint32_t result;
+
+  /* Check the DAC peripheral handle */
+  assert_param(hdac != NULL);
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
 
-  /* Returns the DAC channel data output register value */
   if (Channel == DAC_CHANNEL_1)
   {
-    return hdac->Instance->DOR1;
+    result = hdac->Instance->DOR1;
   }
+
   else
   {
-    return hdac->Instance->DOR2;
+    result = hdac->Instance->DOR2;
   }
+
+  /* Returns the DAC channel data output register value */
+  return result;
 }
 
 /**
@@ -995,13 +1034,21 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
   *            @arg DAC_CHANNEL_2: DAC Channel2 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+                                        const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpreg1;
   uint32_t tmpreg2;
   uint32_t tickstart;
   uint32_t connectOnChip;
 
+  /* Check the DAC peripheral handle and channel configuration struct */
+  if ((hdac == NULL) || (sConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the DAC parameters */
   assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
   assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
@@ -1040,18 +1087,22 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
         /* Check for the Timeout */
         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
         {
-          /* Update error code */
-          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+          /* New check to avoid false timeout detection in case of preemption */
+          if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+          {
+            /* Update error code */
+            SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
 
-          /* Change the DMA state */
-          hdac->State = HAL_DAC_STATE_TIMEOUT;
+            /* Change the DMA state */
+            hdac->State = HAL_DAC_STATE_TIMEOUT;
 
-          return HAL_TIMEOUT;
+            return HAL_TIMEOUT;
+          }
         }
       }
-      HAL_Delay(1);
       hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
     }
+
     else /* Channel 2 */
     {
       /* SHSR2 can be written when BWST2 is cleared */
@@ -1060,19 +1111,23 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
         /* Check for the Timeout */
         if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
         {
-          /* Update error code */
-          SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+          /* New check to avoid false timeout detection in case of preemption */
+          if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+          {
+            /* Update error code */
+            SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
 
-          /* Change the DMA state */
-          hdac->State = HAL_DAC_STATE_TIMEOUT;
+            /* Change the DMA state */
+            hdac->State = HAL_DAC_STATE_TIMEOUT;
 
-          return HAL_TIMEOUT;
+            return HAL_TIMEOUT;
+          }
         }
       }
-      HAL_Delay(1U);
       hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
     }
 
+
     /* HoldTime */
     MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
                (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
@@ -1103,6 +1158,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
   /* Clear DAC_MCR_MODEx bits */
   tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
   /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
+
+
   if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
   {
     connectOnChip = 0x00000000UL;
@@ -1143,7 +1200,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
   /* Write to DAC CR */
   hdac->Instance->CR = tmpreg1;
   /* Disable wave generation */
-  hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
+  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
 
   /* Change DAC state */
   hdac->State = HAL_DAC_STATE_READY;
@@ -1152,7 +1209,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
   __HAL_UNLOCK(hdac);
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1181,7 +1238,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
   *         the configuration information for the specified DAC.
   * @retval HAL state
   */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
 {
   /* Return DAC handle state */
   return hdac->State;
@@ -1194,7 +1251,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac)
   *         the configuration information for the specified DAC.
   * @retval DAC Error Code
   */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
 {
   return hdac->ErrorCode;
 }
@@ -1217,7 +1274,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User DAC Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @note   The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
+  *         callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
   * @param  hdac DAC handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -1241,6 +1300,12 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
 {
   HAL_StatusTypeDef status = HAL_OK;
 
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   if (pCallback == NULL)
   {
     /* Update the error code */
@@ -1248,9 +1313,6 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hdac);
-
   if (hdac->State == HAL_DAC_STATE_READY)
   {
     switch (CallbackID)
@@ -1267,6 +1329,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
       case HAL_DAC_CH1_UNDERRUN_CB_ID :
         hdac->DMAUnderrunCallbackCh1 = pCallback;
         break;
+
       case HAL_DAC_CH2_COMPLETE_CB_ID :
         hdac->ConvCpltCallbackCh2 = pCallback;
         break;
@@ -1279,6 +1342,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
       case HAL_DAC_CH2_UNDERRUN_CB_ID :
         hdac->DMAUnderrunCallbackCh2 = pCallback;
         break;
+
       case HAL_DAC_MSPINIT_CB_ID :
         hdac->MspInitCallback = pCallback;
         break;
@@ -1319,14 +1383,14 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
   return status;
 }
 
 /**
   * @brief  Unregister a User DAC Callback
-  *         DAC Callback is redirected to the weak (surcharged) predefined callback
+  *         DAC Callback is redirected to the weak (overridden) predefined callback
+  * @note   The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
+  *         callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
   * @param  hdac DAC handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -1347,8 +1411,11 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hdac);
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
 
   if (hdac->State == HAL_DAC_STATE_READY)
   {
@@ -1366,6 +1433,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
       case HAL_DAC_CH1_UNDERRUN_CB_ID :
         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
         break;
+
       case HAL_DAC_CH2_COMPLETE_CB_ID :
         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
         break;
@@ -1378,6 +1446,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
       case HAL_DAC_CH2_UNDERRUN_CB_ID :
         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
         break;
+
       case HAL_DAC_MSPINIT_CB_ID :
         hdac->MspInitCallback = HAL_DAC_MspInit;
         break;
@@ -1389,10 +1458,12 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
         hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
         hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
         hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
         hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
         hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
         hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
         hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
         hdac->MspInitCallback = HAL_DAC_MspInit;
         hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
         break;
@@ -1430,8 +1501,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
   return status;
 }
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -1517,9 +1586,6 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
 #endif /* DAC1 || DAC2 */
 
 #endif /* HAL_DAC_MODULE_ENABLED */
-
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h
index fb2ff1bbae..65e5fd938c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -83,11 +82,13 @@ typedef struct
   void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
   void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
   void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+
   void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
   void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
   void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
   void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
 
+
   void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
   void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
@@ -126,7 +127,7 @@ typedef struct
   uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
                                                This parameter can be a value of @ref DAC_output_buffer */
 
-  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
                                               This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
 
   uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
@@ -136,9 +137,7 @@ typedef struct
   uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
                                                i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
                                                This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
-
 } DAC_ChannelConfTypeDef;
 
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
@@ -151,10 +150,12 @@ typedef enum
   HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
   HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
   HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
+
   HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
   HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
   HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
   HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
+
   HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
   HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
   HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
@@ -208,19 +209,19 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 #if defined(HRTIM1)
 #define DAC_TRIGGER_HR1_TRGO1           (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_HR1_TRGO2           (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
-#endif
+#endif /* HRTIM12 */
 #define DAC_TRIGGER_LPTIM1_OUT          (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_LPTIM2_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
 #if defined(TIM23)
 #define DAC_TRIGGER_T23_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
-#endif
+#endif /* TIM23 */
 #if defined(TIM24)
 #define DAC_TRIGGER_T24_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
-#endif
+#endif /* TIM24 */
 #if defined(DAC2)
 #define DAC_TRIGGER_LPTIM3_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
-#endif
+#endif /* DAC2 */
 
 /**
   * @}
@@ -240,7 +241,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @{
   */
 #define DAC_CHANNEL_1                      0x00000000U
+
 #define DAC_CHANNEL_2                      0x00000010U
+
 /**
   * @}
   */
@@ -260,8 +263,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @{
   */
 #define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
+
 #define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
 
+
 /**
   * @}
   */
@@ -270,8 +275,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @{
   */
 #define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
+
 #define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
 
+
 /**
   * @}
   */
@@ -351,12 +358,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   */
 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
 
+
 /** @brief  Set DHR12R2 alignment.
   * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
 
+
 /** @brief  Set DHR12RD alignment.
   * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
@@ -469,7 +478,7 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
 /* IO operation functions *****************************************************/
 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
                                     uint32_t Alignment);
 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
@@ -495,8 +504,9 @@ HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+                                        const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
 /**
   * @}
   */
@@ -505,8 +515,8 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf
   * @{
   */
 /* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
 
 /**
   * @}
@@ -541,7 +551,4 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
 #endif
 
 
-#endif /*STM32H7xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
+#endif /* STM32H7xx_HAL_DAC_H */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c
index 50dd895d5b..b85533fc67 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c
@@ -7,6 +7,17 @@
   *          functionalities of the DAC peripheral.
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                       ##### How to use this driver #####
@@ -14,6 +25,7 @@
     [..]
      *** Dual mode IO operation ***
      ==============================
+     [..]
       (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
           for dual mode operation.
           If software trigger is selected, using HAL_DACEx_DualStart() will start
@@ -32,9 +44,9 @@
           Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
           HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
           Channel 1 and Channel 2.
-
      *** Signal generation operation ***
      ===================================
+     [..]
       (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
       (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
 
@@ -45,17 +57,6 @@
           at least one time after reset).
 
  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
   ******************************************************************************
   */
 
@@ -78,6 +79,16 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+
+/* Delay for DAC minimum trimming time.                                       */
+/* Note: minimum time needed between two calibration steps                    */
+/*       The delay below is specified under conditions:                       */
+/*        - DAC channel output buffer enabled                                 */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* electrical characteristics, parameter "tTRIM").                            */
+/* Unit: us                                                                   */
+#define DAC_DELAY_TRIM_US          (50UL)     /*!< Delay for DAC minimum trimming time */
+
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -106,6 +117,7 @@
   * @{
   */
 
+
 /**
   * @brief  Enables DAC and starts conversion of both channels.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -116,6 +128,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
 {
   uint32_t tmp_swtrig = 0UL;
 
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
 
   /* Process locked */
   __HAL_LOCK(hdac);
@@ -157,6 +175,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
   */
 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
 {
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
 
   /* Disable the Peripheral */
   __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
@@ -186,12 +210,18 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
-                                          uint32_t Alignment)
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+                                          const uint32_t *pData, uint32_t Length, uint32_t Alignment)
 {
   HAL_StatusTypeDef status;
   uint32_t tmpreg = 0UL;
 
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_ALIGN(Alignment));
@@ -299,6 +329,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
 {
   HAL_StatusTypeDef status;
 
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
 
   /* Disable the selected DAC channel DMA request */
   CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
@@ -343,6 +379,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
   return status;
 }
 
+
 /**
   * @brief  Enable or disable the selected DAC channel wave generation.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -369,6 +406,12 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann
   */
 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
 {
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -419,6 +462,12 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32
   */
 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
 {
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
@@ -443,6 +492,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
   return HAL_OK;
 }
 
+
 /**
   * @brief  Set the specified data holding register value for dual DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -463,6 +513,12 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Align
   uint32_t data;
   uint32_t tmp;
 
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the parameters */
   assert_param(IS_DAC_ALIGN(Alignment));
   assert_param(IS_DAC_DATA(Data1));
@@ -552,6 +608,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
    */
 }
 
+
 /**
   * @brief  Run the self calibration of one DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
@@ -569,9 +626,9 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  __IO uint32_t tmp;
   uint32_t trimmingvalue;
   uint32_t delta;
+  __IO uint32_t wait_loop_index;
 
   /* store/restore channel configuration structure purpose */
   uint32_t oldmodeconfiguration;
@@ -581,7 +638,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
 
   /* Check the DAC handle allocation */
   /* Check if DAC running */
-  if (hdac == NULL)
+  if ((hdac == NULL) || (sConfig == NULL))
   {
     status = HAL_ERROR;
   }
@@ -603,20 +660,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
     /* Set mode in MCR  for calibration */
     MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
 
-    /* Set DAC Channel1 DHR register to the middle value */
-    tmp = (uint32_t)hdac->Instance;
-
-    if (Channel == DAC_CHANNEL_1)
-    {
-      tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
-    }
-    else
-    {
-      tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
-    }
-
-    *(__IO uint32_t *) tmp = 0x0800UL;
-
     /* Enable the selected DAC channel calibration */
     /* i.e. set DAC_CR_CENx bit */
     SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
@@ -630,9 +673,15 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
       /* Set candidate trimming */
       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
 
-      /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
-      /* i.e. minimum time needed between two calibration steps */
-      HAL_Delay(1);
+      /* Wait minimum time needed between two calibration steps (OTRIM) */
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+      /*       32 bits register capacity and handle low frequency. */
+      wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+      while (wait_loop_index != 0UL)
+      {
+        wait_loop_index--;
+      }
 
       if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
       {
@@ -652,14 +701,24 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo
     /* Set candidate trimming */
     MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
 
-    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
-    /* i.e. minimum time needed between two calibration steps */
-    HAL_Delay(1U);
+    /* Wait minimum time needed between two calibration steps (OTRIM) */
+    /* Wait loop initialization and execution */
+    /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+    /*       32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
 
     if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
     {
-      /* Trimming is actually one value more */
-      trimmingvalue++;
+      /* Check trimming value below maximum */
+      if (trimmingvalue < 0x1FU)
+      {
+        /* Trimming is actually one value more */
+        trimmingvalue++;
+      }
       /* Set right trimming */
       MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
     }
@@ -702,8 +761,8 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
   assert_param(IS_DAC_CHANNEL(Channel));
   assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
 
-  /* Check the DAC handle allocation */
-  if (hdac == NULL)
+  /* Check the DAC handle and channel configuration struct allocation */
+  if ((hdac == NULL) || (sConfig == NULL))
   {
     status = HAL_ERROR;
   }
@@ -735,7 +794,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel
   * @retval Trimming value : range: 0->31
   *
  */
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
 {
   /* Check the parameter */
   assert_param(IS_DAC_CHANNEL(Channel));
@@ -762,13 +821,14 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
   * @{
   */
 
+
 /**
   * @brief  Return the last data output value of the selected DAC channel.
   * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval The selected DAC channel data output value.
   */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
 {
   uint32_t tmp = 0UL;
 
@@ -780,10 +840,10 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
   return tmp;
 }
 
+
 /**
   * @}
   */
-
 /**
   * @}
   */
@@ -794,6 +854,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
   * @{
   */
 
+
 /**
   * @brief  DMA conversion complete callback.
   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
@@ -852,6 +913,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
   hdac->State = HAL_DAC_STATE_READY;
 }
 
+
 /**
   * @}
   */
@@ -867,5 +929,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.h
index d1dbf4a721..43060eed71 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -82,6 +81,7 @@ extern "C" {
   * @}
   */
 
+
 /**
   * @}
   */
@@ -141,7 +141,7 @@ extern "C" {
                                  ((TRIGGER) == DAC_TRIGGER_T23_TRGO)   || \
                                  ((TRIGGER) == DAC_TRIGGER_T24_TRGO)   || \
                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-#endif
+#endif /* HRTIM1 */
 
 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
 
@@ -206,11 +206,11 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t
 
 HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
 HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
-                                          uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+                                          const uint32_t *pData, uint32_t Length, uint32_t Alignment);
 HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
 
 void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
 void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
@@ -230,7 +230,7 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
 HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
 HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
                                             uint32_t NewTrimmingValue);
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
 
 /**
   * @}
@@ -268,6 +268,4 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 }
 #endif
 
-#endif /*STM32H7xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32H7xx_HAL_DAC_EX_H */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c
index f9079cf41d..e1549e2473 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State and Error functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -105,18 +116,6 @@
        (@) You can refer to the DCMI HAL driver header file for more useful macros
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -135,8 +134,13 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+/** @addtogroup DCMI_Private_Defines
+  * @{
+  */
 #define HAL_TIMEOUT_DCMI_STOP    ((uint32_t)1000) /* Set timeout to 1s  */
-
+/**
+  * @}
+  */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -1023,7 +1027,7 @@ HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_
 
 /**
   * @brief  Unregister a DCMI Callback
-  *         DCMI callabck is redirected to the weak predefined callback
+  *         DCMI callback is redirected to the weak predefined callback
   * @param  hdcmi DCMI handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -1107,6 +1111,10 @@ HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCM
 }
 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
 
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -1211,9 +1219,6 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
   * @}
   */
 
-/**
-  * @}
-  */
 #endif /* DCMI */
 #endif /* HAL_DCMI_MODULE_ENABLED */
 /**
@@ -1224,4 +1229,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.h
index 244fc27265..a21afc09d5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -581,6 +580,13 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
   */
 
 /* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup DCMI_Private_Defines DCMI Private Defines
+  * @{
+  */
+/**
+  * @}
+  */
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup DCMI_Private_Constants DCMI Private Constants
@@ -668,4 +674,3 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 
 #endif /* STM32H7xx_HAL_DCMI_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h
index f7e3c1345c..188e31cefb 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h
@@ -7,13 +7,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -67,7 +66,9 @@ typedef enum
                               (__DMA_HANDLE__).Parent = (__HANDLE__);             \
                           } while(0)
 
-#define UNUSED(x) ((void)(x))
+#if !defined(UNUSED)
+#define UNUSED(x) ((void)(x))    /* To avoid gcc/g++ warnings */
+#endif /* UNUSED */
 
 /** @brief Reset the Handle's State field.
   * @param __HANDLE__: specifies the Peripheral Handle.
@@ -218,4 +219,4 @@ typedef enum
 
 #endif /* STM32H7xx_HAL_DEF */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.c
index e73cd8011c..46069d52cd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.c
@@ -16,6 +16,17 @@
   *           + Clock absence detector feature
   *           + Break generation on analog watchdog or short-circuit event
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -251,17 +262,6 @@
 
     @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -819,7 +819,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm
   * @param  Timeout Timeout value in milliseconds.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
                                                uint32_t Timeout)
 {
   uint32_t tickstart;
@@ -1109,7 +1109,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_
   * @param  Timeout Timeout value in milliseconds.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
                                               uint32_t Timeout)
 {
   uint32_t tickstart;
@@ -1342,7 +1342,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd
   * @param  hdfsdm_channel DFSDM channel handle.
   * @retval Channel analog watchdog value.
   */
-int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
 {
   return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
 }
@@ -1401,7 +1401,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf
   * @param  hdfsdm_channel DFSDM channel handle.
   * @retval DFSDM channel state.
   */
-HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
 {
   /* Return DFSDM channel handle state */
   return hdfsdm_channel->State;
@@ -2393,7 +2393,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd
   * @param  Channel Corresponding channel of regular conversion.
   * @retval Regular conversion value
   */
-int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
                                         uint32_t                   *Channel)
 {
   uint32_t reg;
@@ -2810,7 +2810,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h
   * @param  Channel Corresponding channel of injected conversion.
   * @retval Injected conversion value
   */
-int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
                                          uint32_t                   *Channel)
 {
   uint32_t reg;
@@ -2841,7 +2841,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef   *hdfsdm_filter,
-                                              DFSDM_Filter_AwdParamTypeDef *awdParam)
+                                              const DFSDM_Filter_AwdParamTypeDef *awdParam)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -2998,7 +2998,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
   * @retval Extreme detector maximum value
   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
   */
-int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
                                        uint32_t                   *Channel)
 {
   uint32_t reg;
@@ -3029,7 +3029,7 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
   * @retval Extreme detector minimum value
   *         This value is between Min_Data = -8388608 and Max_Data = 8388607.
   */
-int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
+int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
                                        uint32_t                   *Channel)
 {
   uint32_t reg;
@@ -3059,7 +3059,7 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
   * @retval Conversion time value
   * @note   To get time in second, this value has to be divided by DFSDM clock frequency.
   */
-uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
 {
   uint32_t reg;
   uint32_t value;
@@ -3413,7 +3413,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil
   * @param  hdfsdm_filter DFSDM filter handle.
   * @retval DFSDM filter state.
   */
-HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
 {
   /* Return DFSDM filter handle state */
   return hdfsdm_filter->State;
@@ -3424,7 +3424,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe
   * @param  hdfsdm_filter DFSDM filter handle.
   * @retval DFSDM filter error code.
   */
-uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
+uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
 {
   return hdfsdm_filter->ErrorCode;
 }
@@ -3795,4 +3795,3 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h
index 189efd0c9e..b4fd219a0f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -401,12 +400,12 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
 #define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)                           /*!< For all DFSDM filters */
 #if (STM32H7_DEV_ID == 0x480UL)
 #define DFSDM_FILTER_EXT_TRIG_COMP1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
-                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)       
+                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
 #define DFSDM_FILTER_EXT_TRIG_COMP2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
                                               DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
 #elif (STM32H7_DEV_ID == 0x483UL)
 #define DFSDM_FILTER_EXT_TRIG_TIM23_TRGO     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | \
-                                              DFSDM_FLTCR1_JEXTSEL_0) 
+                                              DFSDM_FLTCR1_JEXTSEL_0)
 #define DFSDM_FILTER_EXT_TRIG_TIM24_TRGO     (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2 )
 #endif /* STM32H7_DEV_ID == 0x480UL */
 /**
@@ -600,11 +599,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs
 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 
-int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+int16_t           HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
 
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
-HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
 
 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
@@ -616,7 +615,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
   * @{
   */
 /* Channel state function *****************************************************/
-HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 /**
   * @}
   */
@@ -677,16 +676,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
-                                              DFSDM_Filter_AwdParamTypeDef *awdParam);
+                                              const DFSDM_Filter_AwdParamTypeDef *awdParam);
 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 
-int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
-int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
-int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
-int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
-uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+int32_t  HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 
 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 
@@ -707,8 +706,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
   * @{
   */
 /* Filter state functions *****************************************************/
-HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
-uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
+uint32_t                      HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 /**
   * @}
   */
@@ -870,4 +869,3 @@ uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
 
 #endif /* STM32H7xx_HAL_DFSDM_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.c
index de2f6c6cc2..286fd3ef89 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.c
@@ -10,13 +10,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -95,7 +94,7 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeD
   * @param  PulsesValue Value of pulses to be skipped.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
+HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -132,4 +131,3 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.h
index f9cd61cc1d..8a872602c4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -52,7 +51,7 @@ extern "C" {
   */
 
 HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);
-HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
+HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
 
 /**
   * @}
@@ -90,4 +89,3 @@ HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeD
 
 #endif /* STM32H7xx_HAL_DFSDM_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c
index 934400ce42..dada223e62 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c
@@ -8,6 +8,17 @@
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral State and errors functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -78,18 +89,6 @@
       (@) You can refer to the DMA HAL driver header file for more useful macros.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -107,6 +106,9 @@
 #ifdef HAL_DMA_MODULE_ENABLED
 
 /* Private types -------------------------------------------------------------*/
+/** @addtogroup DMA_Private_Types
+  * @{
+  */
 typedef struct
 {
   __IO uint32_t ISR;   /*!< DMA interrupt status register */
@@ -119,6 +121,9 @@ typedef struct
   __IO uint32_t ISR;   /*!< BDMA interrupt status register */
   __IO uint32_t IFCR;  /*!< BDMA interrupt flag clear register */
 } BDMA_Base_Registers;
+/**
+  * @}
+  */
 
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -244,12 +249,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
       assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
     }
 
-    /* Allocate lock resource */
-    __HAL_UNLOCK(hdma);
-
     /* Change DMA peripheral state */
     hdma->State = HAL_DMA_STATE_BUSY;
 
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
     /* Disable the peripheral */
     __HAL_DMA_DISABLE(hdma);
 
@@ -358,12 +363,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
       assert_param(IS_BDMA_REQUEST(hdma->Init.Request));
     }
 
-    /* Allocate lock resource */
-    __HAL_UNLOCK(hdma);
-
     /* Change DMA peripheral state */
     hdma->State = HAL_DMA_STATE_BUSY;
 
+    /* Allocate lock resource */
+    __HAL_UNLOCK(hdma);
+
     /* Get the CR register value */
     registerValue = ((BDMA_Channel_TypeDef *)hdma->Instance)->CCR;
 
@@ -652,12 +657,12 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
   }
   else
   {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);
-
     /* Set the error code to busy */
     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
 
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
     /* Return error status */
     status = HAL_ERROR;
   }
@@ -748,12 +753,12 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
   }
   else
   {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);
-
     /* Set the error code to busy */
     hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
 
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+
     /* Return error status */
     status = HAL_ERROR;
   }
@@ -835,12 +840,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
         /* Update error code */
         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
         /* Change the DMA state */
         hdma->State = HAL_DMA_STATE_ERROR;
 
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
         return HAL_ERROR;
       }
     }
@@ -873,11 +878,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
       }
     }
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-
     /* Change the DMA state */
     hdma->State = HAL_DMA_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
   }
 
   return HAL_OK;
@@ -945,12 +950,12 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
         }
       }
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
       /* Change the DMA state */
       hdma->State = HAL_DMA_STATE_READY;
 
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
       /* Call User Abort callback */
       if(hdma->XferAbortCallback != NULL)
       {
@@ -1173,10 +1178,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
       (*ifcr_reg) = (BDMA_FLAG_TC0 << (hdma->StreamIndex & 0x1FU));
     }
 
+    hdma->State = HAL_DMA_STATE_READY;
+
     /* Process Unlocked */
     __HAL_UNLOCK(hdma);
-
-    hdma->State = HAL_DMA_STATE_READY;
   }
   else /*CompleteLevel = HAL_DMA_HALF_TRANSFER*/
   {
@@ -1324,12 +1329,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
           /* Clear all interrupt flags at correct offset within the register */
           regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hdma);
-
           /* Change the DMA state */
           hdma->State = HAL_DMA_STATE_READY;
 
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+
           if(hdma->XferAbortCallback != NULL)
           {
             hdma->XferAbortCallback(hdma);
@@ -1366,11 +1371,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
             /* Disable the transfer complete interrupt */
             ((DMA_Stream_TypeDef   *)hdma->Instance)->CR  &= ~(DMA_IT_TC);
 
-            /* Process Unlocked */
-            __HAL_UNLOCK(hdma);
-
             /* Change the DMA state */
             hdma->State = HAL_DMA_STATE_READY;
+
+            /* Process Unlocked */
+            __HAL_UNLOCK(hdma);
           }
 
           if(hdma->XferCpltCallback != NULL)
@@ -1401,9 +1406,6 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
         }
         while((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U);
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
         if((((DMA_Stream_TypeDef   *)hdma->Instance)->CR & DMA_SxCR_EN) != 0U)
         {
           /* Change the DMA state to error if DMA disable fails */
@@ -1414,6 +1416,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
           /* Change the DMA state to Ready if DMA disable success */
           hdma->State = HAL_DMA_STATE_READY;
         }
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
       }
 
       if(hdma->XferErrorCallback != NULL)
@@ -1509,11 +1514,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
           /* Disable the transfer complete and error interrupt, if the DMA mode is not CIRCULAR */
           __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hdma);
-
           /* Change the DMA state */
           hdma->State = HAL_DMA_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
         }
 
         if(hdma->XferCpltCallback != NULL)
@@ -1537,12 +1542,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
       /* Update error code */
       hdma->ErrorCode = HAL_DMA_ERROR_TE;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
       /* Change the DMA state */
       hdma->State = HAL_DMA_STATE_READY;
 
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
       if (hdma->XferErrorCallback != NULL)
       {
         /* Transfer error callback */
@@ -1613,6 +1618,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
       break;
 
     default:
+      status =  HAL_ERROR;
       break;
     }
   }
@@ -2054,4 +2060,3 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h
index 7da4420851..82f6f215e5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -1229,6 +1228,14 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
   * @}
   */
 
+/* Private types -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Types DMA Private Types
+  * @{
+  */
+/**
+  * @}
+  */
+
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup DMA_Private_Macros DMA Private Macros
   * @brief    DMA private macros
@@ -1324,4 +1331,3 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 
 #endif /* STM32H7xx_HAL_DMA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c
index dcc18836fd..520841c9f3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State and Errors functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -107,7 +118,7 @@
           and a pointer to the user callback function.
 
       (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
-          weak (surcharged) function.
+          weak (overridden) function.
           @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
           and the Callback ID.
           This function allows to reset following callbacks:
@@ -119,16 +130,16 @@
             (+) MspDeInitCallback  : DMA2D MspDeInit.
 
       (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
-          all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+          all callbacks are reset to the corresponding legacy weak (overridden) functions:
           examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
           Exception done for MspInit and MspDeInit callbacks that are respectively
-          reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
+          reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init
           and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
           If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
           Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
-          as weak (surcharged) functions. They must be defined by the user to be resorted to.
+          as weak (overridden) functions. They must be defined by the user to be resorted to.
 
           Callbacks can be registered/unregistered in READY state only.
           Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
@@ -140,24 +151,13 @@
 
           When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
           not defined, the callback registering feature is not available
-          and weak (surcharged) callbacks are used.
+          and weak (overridden) callbacks are used.
 
      [..]
       (@) You can refer to the DMA2D HAL driver header file for more useful macros
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -431,7 +431,7 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User DMA2D Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used instead of the weak (overridden) predefined callback
   * @param hdma2d DMA2D handle
   * @param CallbackID ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -530,7 +530,7 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM
 
 /**
   * @brief  Unregister a DMA2D Callback
-  *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
+  *         DMA2D Callback is redirected to the weak (overridden) predefined callback
   * @param hdma2d DMA2D handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -571,11 +571,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
         break;
 
       case HAL_DMA2D_MSPINIT_CB_ID :
-        hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
         break;
 
       case HAL_DMA2D_MSPDEINIT_CB_ID :
-        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
         break;
 
       default :
@@ -591,11 +591,11 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_
     switch (CallbackID)
     {
       case HAL_DMA2D_MSPINIT_CB_ID :
-        hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
+        hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (overridden) Msp Init */
         break;
 
       case HAL_DMA2D_MSPDEINIT_CB_ID :
-        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
+        hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (overridden) Msp DeInit */
         break;
 
       default :
@@ -2183,5 +2183,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_
   */
 #endif /* DMA2D */
 #endif /* HAL_DMA2D_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h
index d5acb3f5fa..00f205bc0c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -342,15 +341,6 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe
   * @}
   */
 
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
-  * @{
-  */
-#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 
-                                                                        for compatibility with legacy code */
-/**
-  * @}
-  */
-
 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
 /**
   * @brief  HAL DMA2D common Callback ID enumeration definition
@@ -723,6 +713,3 @@ uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
 #endif
 
 #endif /* STM32H7xx_HAL_DMA2D_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c
index c5f2ef7d9d..a134b4eb62 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.c
@@ -37,13 +37,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -290,18 +289,7 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_
     {
       /* Enable Common interrupts*/
       MODIFY_REG(((DMA_Stream_TypeDef   *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
-
-      /* Mbed CE mod: Only enable the FIFO Error interrupt if the FIFO is actually enabled.
-       * If it's not enabled, then this interrupt can trigger spuriously from memory bus
-       * stalls that the DMA engine encounters, and this creates random DMA failures.
-       * Reference forum thread here:
-       * https://community.st.com/t5/stm32-mcus-products/spi-dma-fifo-error-issue-feifx/td-p/537074
-       * also: https://community.st.com/t5/stm32-mcus-touch-gfx-and-gui/spi-dma-error-is-occurred-when-the-other-dma-memory-to-memory-is/td-p/191590
-       */
-      if(((DMA_Stream_TypeDef *)hdma->Instance)->FCR & DMA_SxFCR_DMDIS)
-      {
-        ((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
-      }
+      ((DMA_Stream_TypeDef   *)hdma->Instance)->FCR |= DMA_IT_FE;
 
       if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
       {
@@ -722,4 +710,3 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.h
index 481a20442a..cde57552a7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -309,4 +308,3 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
 
 #endif /* STM32H7xx_HAL_DMA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c
index 073c2a6e4c..b2ae620626 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c
@@ -9,6 +9,17 @@
   *           + IO operation functions
   *           + Peripheral Control functions
   *           + Peripheral State and Errors functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -119,7 +130,7 @@
     all callbacks are set to the corresponding weak functions:
     examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback().
     Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_DSI_Init()
+    reset to the legacy weak (overridden) functions in the HAL_DSI_Init()
     and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand).
     If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -140,17 +151,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -200,12 +200,14 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32
                                    uint32_t Data1);
 
 static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
-                                     uint32_t ChannelID,
-                                     uint32_t Mode,
-                                     uint32_t Param1,
-                                     uint32_t Param2);
-
+                                        uint32_t ChannelID,
+                                        uint32_t Mode,
+                                        uint32_t Param1,
+                                        uint32_t Param2);
 /* Private functions ---------------------------------------------------------*/
+/** @defgroup DSI_Private_Functions DSI Private Functions
+  * @{
+  */
 /**
   * @brief  Generic DSI packet header configuration
   * @param  DSIx  Pointer to DSI register base
@@ -255,10 +257,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
   tickstart = HAL_GetTick();
 
   /* Wait for Command FIFO Empty */
-  while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
+  while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
   {
     /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
     {
       return HAL_TIMEOUT;
     }
@@ -271,6 +273,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
   return HAL_OK;
 }
 
+/**
+  * @}
+  */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup DSI_Exported_Functions
   * @{
@@ -365,11 +371,17 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
 
   /* Set the PLL division factors */
   hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
-  hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U));
+  hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \
+                            ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \
+                            ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos));
 
   /* Enable the DSI PLL */
   __HAL_DSI_PLL_ENABLE(hdsi);
 
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
   /* Get tick */
   tickstart = HAL_GetTick();
 
@@ -383,24 +395,53 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
     }
   }
 
+  __HAL_DSI_ENABLE(hdsi);
+
+  /************************ Set the DSI clock parameters ************************/
+  /* Set the TX escape clock division factor */
+  hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+  hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+
   /*************************** Set the PHY parameters ***************************/
-
   /* D-PHY clock and digital enable*/
-  hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+  hdsi->Instance->PCTLR |= DSI_PCTLR_DEN;
+
+  hdsi->Instance->PCTLR |= DSI_PCTLR_CKE;
 
-  /* Clock lane configuration */
-  hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
-  hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
 
   /* Configure the number of active data lanes */
   hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
   hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
 
-  /************************ Set the DSI clock parameters ************************/
+  /* Get tick */
+  tickstart = HAL_GetTick();
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC))
+    {
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
 
-  /* Set the TX escape clock division factor */
-  hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
-  hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  else
+  {
+    while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \
+                                                                                    DSI_PSR_PSS1 | DSI_PSR_PSSC))
+    {
+      if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
 
   /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
   /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 )          */
@@ -419,7 +460,13 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI
   hdsi->Instance->IER[1U] = 0U;
   hdsi->ErrorMsk = 0U;
 
-  /* Initialise the error code */
+  __HAL_DSI_DISABLE(hdsi);
+
+  /* Clock lane configuration */
+  hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+  hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
+  /* Initialize the error code */
   hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
 
   /* Initialize the DSI state*/
@@ -473,7 +520,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
   HAL_DSI_MspDeInit(hdsi);
 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
 
-  /* Initialise the error code */
+  /* Initialize the error code */
   hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
 
   /* Initialize the DSI state*/
@@ -698,7 +745,7 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call
 
 /**
   * @brief  Unregister a DSI Callback
-  *         DSI callabck is redirected to the weak predefined callback
+  *         DSI callback is redirected to the weak predefined callback
   * @param hdsi dsi handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -733,11 +780,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca
         break;
 
       case HAL_DSI_MSPINIT_CB_ID :
-        hdsi->MspInitCallback = HAL_DSI_MspInit;                     /* Legcay weak MspInit Callback     */
+        hdsi->MspInitCallback = HAL_DSI_MspInit;                     /* Legacy weak MspInit Callback     */
         break;
 
       case HAL_DSI_MSPDEINIT_CB_ID :
-        hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;                 /* Legcay weak MspDeInit Callback   */
+        hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;                 /* Legacy weak MspDeInit Callback   */
         break;
 
       default :
@@ -753,11 +800,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca
     switch (CallbackID)
     {
       case HAL_DSI_MSPINIT_CB_ID :
-        hdsi->MspInitCallback = HAL_DSI_MspInit;                  /* Legcay weak MspInit Callback   */
+        hdsi->MspInitCallback = HAL_DSI_MspInit;                  /* Legacy weak MspInit Callback   */
         break;
 
       case HAL_DSI_MSPDEINIT_CB_ID :
-        hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;              /* Legcay weak MspDeInit Callback */
+        hdsi->MspDeInitCallback = HAL_DSI_MspDeInit;              /* Legacy weak MspDeInit Callback */
         break;
 
       default :
@@ -808,7 +855,8 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca
   */
 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
 {
-  uint32_t ErrorStatus0, ErrorStatus1;
+  uint32_t ErrorStatus0;
+  uint32_t ErrorStatus1;
 
   /* Tearing Effect Interrupt management ***************************************/
   if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U)
@@ -1365,7 +1413,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT
      High-Speed transmission.
      To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
      to Low-Power and from Low-Power to High-Speed.
-     This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
+     This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration
+     Register (DSI_CLTCR).
      But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
 
      Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
@@ -1587,7 +1636,7 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
   /* Process locked */
   __HAL_LOCK(hdsi);
 
-   status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
+  status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2);
 
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
@@ -1614,12 +1663,14 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
                                     uint32_t Mode,
                                     uint32_t NbParams,
                                     uint32_t Param1,
-                                    uint8_t *ParametersTable)
+                                    const uint8_t *ParametersTable)
 {
-  uint32_t uicounter, nbBytes, count;
+  uint32_t uicounter;
+  uint32_t nbBytes;
+  uint32_t count;
   uint32_t tickstart;
   uint32_t fifoword;
-  uint8_t *pparams = ParametersTable;
+  const uint8_t *pparams = ParametersTable;
 
   /* Process locked */
   __HAL_LOCK(hdsi);
@@ -1721,7 +1772,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
   {
     /* set max return packet size */
     if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU),
-                           (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
+                       (((datasize) >> 8U) & 0xFFU)) != HAL_OK)
     {
       /* Process Unlocked */
       __HAL_UNLOCK(hdsi);
@@ -1782,6 +1833,21 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
 
       return HAL_TIMEOUT;
     }
+
+    /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is   */
+    /* issued to the panel and the read data is not captured by the DSI Host */
+    /* which returns Packet Size Error.                                      */
+    /* Need to ensure that the Read command has finished before checking PSE */
+    if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U)
+    {
+      if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE)
+      {
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdsi);
+
+        return HAL_ERROR;
+      }
+    }
   }
 
   /* Process unlocked */
@@ -1804,6 +1870,95 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
   /* Process locked */
   __HAL_LOCK(hdsi);
 
+  /* Verify the initial status of the DSI Host */
+
+  /* Verify that the clock lane and the digital section of the D-PHY are enabled */
+  if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that the D-PHY PLL and the reference bias are enabled */
+  if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+  else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Verify that there are no ULPS exit or request on data lanes */
+  if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that there are no Transmission trigger */
+  if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
+  /* Verify that D-PHY PLL is locked */
+  tickstart = HAL_GetTick();
+
+  while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U))
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Verify that all active lanes are in Stop state */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
   /* ULPS Request on Data Lanes */
   hdsi->Instance->PUCR |= DSI_PUCR_URDL;
 
@@ -1867,6 +2022,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
   /* Process locked */
   __HAL_LOCK(hdsi);
 
+  /* Verify that all active lanes are in ULPM */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    if ((hdsi->Instance->PSR &  DSI_PSR_UAN0) != 0U)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_ERROR;
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0  | DSI_PSR_UAN1)) != 0U)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
+  /* Turn on the DSI PLL */
+  __HAL_DSI_PLL_ENABLE(hdsi);
+
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for the lock of the PLL */
+  while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
   /* Exit ULPS on Data Lanes */
   hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
 
@@ -1916,6 +2123,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
   /* De-assert the ULPM requests and the ULPM exit bits */
   hdsi->Instance->PUCR = 0U;
 
+  /* Verify that D-PHY PLL is enabled */
+  if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that all active lanes are in Stop state */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0  |  DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that D-PHY PLL is locked */
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for the lock of the PLL */
+  while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
 
@@ -1936,6 +2198,96 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
   /* Process locked */
   __HAL_LOCK(hdsi);
 
+  /* Verify the initial status of the DSI Host */
+
+  /* Verify that the clock lane and the digital section of the D-PHY are enabled */
+  if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN))
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that the D-PHY PLL and the reference bias are enabled */
+  if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+  else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Verify that there are no ULPS exit or request on both data and clock lanes */
+  if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that there are no Transmission trigger */
+  if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
+  /* Verify that D-PHY PLL is locked */
+  tickstart = HAL_GetTick();
+
+  while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U))
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Verify that all active lanes are in Stop state */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \
+                                DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
   /* Clock lane configuration: no more HS request */
   hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
 
@@ -1948,7 +2300,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
   /* Get tick */
   tickstart = HAL_GetTick();
 
-  /* Wait until all active lanes exit ULPM */
+  /* Wait until all active lanes enter ULPM */
   if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
   {
     while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U)
@@ -2008,9 +2360,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
   /* Process locked */
   __HAL_LOCK(hdsi);
 
+  /* Verify that all active lanes are in ULPM */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \
+                                DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_ERROR;
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \
+                                DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+
+    return HAL_ERROR;
+  }
+
   /* Turn on the DSI PLL */
   __HAL_DSI_PLL_ENABLE(hdsi);
 
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
   /* Get tick */
   tickstart = HAL_GetTick();
 
@@ -2077,12 +2464,68 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
   /* De-assert the ULPM requests and the ULPM exit bits */
   hdsi->Instance->PUCR = 0U;
 
-  /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
+  /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */
   __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PHY);
 
   /* Restore clock lane configuration to HS */
   hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
 
+  /* Verify that D-PHY PLL is enabled */
+  if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN)
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that all active lanes are in Stop state */
+  if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
+  {
+    if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \
+                                DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1))
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdsi);
+    return HAL_ERROR;
+  }
+
+  /* Verify that D-PHY PLL is locked */
+  /* Requires min of 400us delay before reading the PLLLS flag */
+  /* 1ms delay is inserted that is the minimum HAL delay granularity */
+  HAL_Delay(1);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for the lock of the PLL */
+  while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE)
+    {
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdsi);
+
+      return HAL_TIMEOUT;
+    }
+  }
+
   /* Process unlocked */
   __HAL_UNLOCK(hdsi);
 
@@ -2691,7 +3134,7 @@ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, Fun
   *               the configuration information for the DSI.
   * @retval HAL state
   */
-HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
+HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi)
 {
   return hdsi->State;
 }
@@ -2702,7 +3145,7 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
   *               the configuration information for the DSI.
   * @retval DSI Error Code
   */
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi)
 {
   /* Get the error code */
   return hdsi->ErrorCode;
@@ -2727,5 +3170,3 @@ uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h
index 06d9ae5938..2aaaeb37dd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -40,6 +39,9 @@ extern "C" {
   */
 
 /* Exported types ------------------------------------------------------------*/
+/** @defgroup DSI_Exported_Types DSI Exported Types
+  * @{
+  */
 /**
   * @brief  DSI Init Structure definition
   */
@@ -61,14 +63,14 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t PLLNDIV;                      /*!< PLL Loop Division Factor
-                                              This parameter must be a value between 10 and 125   */
+  uint32_t PLLNDIV;                 /*!< PLL Loop Division Factor
+                                         This parameter must be a value between 10 and 125                    */
 
-  uint32_t PLLIDF;                       /*!< PLL Input Division Factor
-                                              This parameter can be any value of @ref DSI_PLL_IDF */
+  uint32_t PLLIDF;                  /*!< PLL Input Division Factor
+                                         This parameter can be any value of @ref DSI_PLL_IDF                  */
 
-  uint32_t PLLODF;                       /*!< PLL Output Division Factor
-                                              This parameter can be any value of @ref DSI_PLL_ODF */
+  uint32_t PLLODF;                  /*!< PLL Output Division Factor
+                                         This parameter can be any value of @ref DSI_PLL_ODF                  */
 
 } DSI_PLLInitTypeDef;
 
@@ -346,6 +348,9 @@ typedef enum
 typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to an DSI callback function */
 
 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup DSI_Exported_Constants DSI Exported Constants
@@ -700,8 +705,8 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
 #define DSI_FLOW_CONTROL_BTA       DSI_PCR_BTAE
 #define DSI_FLOW_CONTROL_EOTP_RX   DSI_PCR_ETRXE
 #define DSI_FLOW_CONTROL_EOTP_TX   DSI_PCR_ETTXE
-#define DSI_FLOW_CONTROL_ALL       (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \
-                                    DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \
+#define DSI_FLOW_CONTROL_ALL       (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX  | \
+                                    DSI_FLOW_CONTROL_BTA    | DSI_FLOW_CONTROL_EOTP_RX | \
                                     DSI_FLOW_CONTROL_EOTP_TX)
 /**
   * @}
@@ -841,18 +846,18 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @{
   */
 #define HAL_DSI_ERROR_NONE              0U
-#define HAL_DSI_ERROR_ACK               0x00000001U /*!< acknowledge errors          */
-#define HAL_DSI_ERROR_PHY               0x00000002U /*!< PHY related errors          */
-#define HAL_DSI_ERROR_TX                0x00000004U /*!< transmission error          */
-#define HAL_DSI_ERROR_RX                0x00000008U /*!< reception error             */
-#define HAL_DSI_ERROR_ECC               0x00000010U /*!< ECC errors                  */
-#define HAL_DSI_ERROR_CRC               0x00000020U /*!< CRC error                   */
-#define HAL_DSI_ERROR_PSE               0x00000040U /*!< Packet Size error           */
-#define HAL_DSI_ERROR_EOT               0x00000080U /*!< End Of Transmission error   */
-#define HAL_DSI_ERROR_OVF               0x00000100U /*!< FIFO overflow error         */
-#define HAL_DSI_ERROR_GEN               0x00000200U /*!< Generic FIFO related errors */
+#define HAL_DSI_ERROR_ACK               0x00000001U /*!< Acknowledge errors             */
+#define HAL_DSI_ERROR_PHY               0x00000002U /*!< PHY related errors             */
+#define HAL_DSI_ERROR_TX                0x00000004U /*!< Transmission error             */
+#define HAL_DSI_ERROR_RX                0x00000008U /*!< Reception error                */
+#define HAL_DSI_ERROR_ECC               0x00000010U /*!< ECC errors                     */
+#define HAL_DSI_ERROR_CRC               0x00000020U /*!< CRC error                      */
+#define HAL_DSI_ERROR_PSE               0x00000040U /*!< Packet Size error              */
+#define HAL_DSI_ERROR_EOT               0x00000080U /*!< End Of Transmission error      */
+#define HAL_DSI_ERROR_OVF               0x00000100U /*!< FIFO overflow error            */
+#define HAL_DSI_ERROR_GEN               0x00000200U /*!< Generic FIFO related errors    */
 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
-#define HAL_DSI_ERROR_INVALID_CALLBACK  0x00000400U /*!< DSI Invalid Callback error  */
+#define HAL_DSI_ERROR_INVALID_CALLBACK  0x00000400U /*!< DSI Invalid Callback error      */
 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
 /**
   * @}
@@ -912,6 +917,7 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @}
   */
 
+
 /**
   * @}
   */
@@ -955,11 +961,11 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @retval None.
   */
 #define __HAL_DSI_DISABLE(__HANDLE__) do { \
-                                          __IO uint32_t tmpreg = 0x00U; \
-                                          CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
-                                          /* Delay after an DSI Host disabling */ \
-                                          tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
-                                          UNUSED(tmpreg); \
+                                           __IO uint32_t tmpreg = 0x00U; \
+                                           CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+                                           /* Delay after an DSI Host disabling */ \
+                                           tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+                                           UNUSED(tmpreg); \
                                          } while(0U)
 
 /**
@@ -968,11 +974,11 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @retval None.
   */
 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
-                                                 __IO uint32_t tmpreg = 0x00U; \
-                                                 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
-                                                 /* Delay after an DSI warpper enabling */ \
-                                                 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
-                                                 UNUSED(tmpreg); \
+                                                  __IO uint32_t tmpreg = 0x00U; \
+                                                  SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                  /* Delay after an DSI wrapper enabling */ \
+                                                  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                  UNUSED(tmpreg); \
                                                 } while(0U)
 
 /**
@@ -981,11 +987,11 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @retval None.
   */
 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
-                                                  __IO uint32_t tmpreg = 0x00U; \
-                                                  CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
-                                                  /* Delay after an DSI warpper disabling*/ \
-                                                  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
-                                                  UNUSED(tmpreg); \
+                                                   __IO uint32_t tmpreg = 0x00U; \
+                                                   CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                   /* Delay after an DSI wrapper disabling*/ \
+                                                   tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+                                                   UNUSED(tmpreg); \
                                                  } while(0U)
 
 /**
@@ -994,11 +1000,11 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @retval None.
   */
 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
-                                             __IO uint32_t tmpreg = 0x00U; \
-                                             SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
-                                             /* Delay after an DSI PLL enabling */ \
-                                             tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
-                                             UNUSED(tmpreg); \
+                                              __IO uint32_t tmpreg = 0x00U; \
+                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                              /* Delay after an DSI PLL enabling */ \
+                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                              UNUSED(tmpreg); \
                                             } while(0U)
 
 /**
@@ -1007,11 +1013,11 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @retval None.
   */
 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
-                                              __IO uint32_t tmpreg = 0x00U; \
-                                              CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
-                                              /* Delay after an DSI PLL disabling */ \
-                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
-                                              UNUSED(tmpreg); \
+                                               __IO uint32_t tmpreg = 0x00U; \
+                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                               /* Delay after an DSI PLL disabling */ \
+                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+                                               UNUSED(tmpreg); \
                                              } while(0U)
 
 /**
@@ -1033,11 +1039,11 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
   * @retval None.
   */
 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
-                                              __IO uint32_t tmpreg = 0x00U; \
-                                              CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
-                                              /* Delay after an DSI regulator disabling */ \
-                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
-                                              UNUSED(tmpreg); \
+                                               __IO uint32_t tmpreg = 0x00U; \
+                                               CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+                                               /* Delay after an DSI regulator disabling */ \
+                                               tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+                                               UNUSED(tmpreg); \
                                              } while(0U)
 
 /**
@@ -1121,23 +1127,41 @@ typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to
 /** @defgroup DSI_Exported_Functions DSI Exported Functions
   * @{
   */
+/** @defgroup DSI_Group1 Initialization and Configuration functions
+  *  @brief   Initialization and Configuration functions
+  * @{
+  */
 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);
 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
-
-void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
-void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
-
+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)
 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,
                                            pDSI_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
 
+/** @defgroup DSI_Group2 IO operation functions
+  *  @brief    IO operation functions
+  * @{
+  */
+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);
 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);
@@ -1160,7 +1184,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
                                     uint32_t Mode,
                                     uint32_t NbParams,
                                     uint32_t Param1,
-                                    uint8_t *ParametersTable);
+                                    const uint8_t *ParametersTable);
 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
                                uint32_t ChannelNbr,
                                uint8_t *Array,
@@ -1190,40 +1214,28 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional
 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
 
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
-HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
-HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
+/**
+  * @}
+  */
+
+/** @defgroup DSI_Group4 Peripheral State and Errors functions
+  *  @brief    Peripheral State and Errors functions
+  * @{
+  */
+uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi);
+HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi);
+
+/**
+  * @}
+  */
+
 /**
   * @}
   */
 
 /* Private types -------------------------------------------------------------*/
-/** @defgroup DSI_Private_Types DSI Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
 /* Private defines -----------------------------------------------------------*/
-/** @defgroup DSI_Private_Defines DSI Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */
-
 /* Private variables ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Variables DSI Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup DSI_Private_Constants DSI Private Constants
   * @{
@@ -1249,45 +1261,73 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
                                                      ((ODF) == DSI_PLL_OUT_DIV2) || \
                                                      ((ODF) == DSI_PLL_OUT_DIV4) || \
                                                      ((ODF) == DSI_PLL_OUT_DIV8))
-#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
-#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\
+                                                     || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE)\
+                                                     || ((NumberOfLanes) == DSI_TWO_DATA_LANES))
 #define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
 #define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5U)
-#define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
-#define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
-#define IS_DSI_VSYNC_POLARITY(VSYNC)                (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
-#define IS_DSI_HSYNC_POLARITY(HSYNC)                (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
+#define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\
+                                                     || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
+#define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\
+                                                     || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
+#define IS_DSI_VSYNC_POLARITY(Vsync)                (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\
+                                                     || ((Vsync) == DSI_VSYNC_ACTIVE_LOW))
+#define IS_DSI_HSYNC_POLARITY(Hsync)                (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\
+                                                     || ((Hsync) == DSI_HSYNC_ACTIVE_LOW))
 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \
                                                      ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \
                                                      ((VideoModeType) == DSI_VID_MODE_BURST))
-#define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
+#define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL)\
+                                                     || ((ColorMode) == DSI_COLOR_MODE_EIGHT))
 #define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))
-#define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
+#define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE)\
+                                                     || ((LPCommand) == DSI_LP_COMMAND_ENABLE))
 #define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))
 #define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))
-#define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))
+#define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE)\
+                                                     || ((LPVActive) == DSI_LP_VACT_ENABLE))
 #define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))
 #define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))
-#define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
-#define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
+#define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\
+                                                     || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
+#define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\
+                                                     || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
 #define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))
-#define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))
-#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))
-#define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))
-#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
-#define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
-#define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
-#define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
-#define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
-#define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
-#define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
-#define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))
-#define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
-#define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
-#define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
-#define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))
-#define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
+#define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE)\
+                                                     || ((TEPolarity) == DSI_TE_FALLING_EDGE))
+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE)\
+                                                     || ((AutomaticRefresh) == DSI_AR_ENABLE))
+#define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING)\
+                                                     || ((VSPolarity) == DSI_VSYNC_RISING))
+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\
+                                                     || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\
+                                                     || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
+#define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\
+                                                     || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
+#define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\
+                                                     || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
+#define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\
+                                                     || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
+#define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\
+                                                     || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
+#define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\
+                                                     || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
+#define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\
+                                                     || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
+#define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE)\
+                                                     || ((LP_GLW) == DSI_LP_GLW_ENABLE))
+#define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\
+                                                     || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
+#define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\
+                                                     || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
+#define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\
+                                                     || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
+#define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE)\
+                                                     || ((LP_DLW) == DSI_LP_DLW_ENABLE))
+#define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\
+                                                     || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \
                                                      ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \
                                                      ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \
@@ -1299,10 +1339,14 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \
                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \
                                                      ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
-#define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))
+#define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || \
+                                                     ((CommDelay) == DSI_SLEW_RATE_LPTX) || \
+                                                     ((CommDelay) == DSI_HS_DELAY))
 #define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))
-#define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
-#define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
+#define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS)\
+                                                     || ((CustomLane) == DSI_INVERT_HS_SIGNAL))
+#define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || \
+                                                     ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))
 #define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \
                                                      ((Timing) == DSI_TLPX_CLK    ) || \
                                                      ((Timing) == DSI_THS_EXIT    ) || \
@@ -1317,24 +1361,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
   * @}
   */
 
-/* Private functions prototypes ----------------------------------------------*/
-/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DSI_Private_Functions DSI Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
 /**
   * @}
   */
@@ -1349,5 +1375,3 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
 #endif
 
 #endif /* STM32H7xx_HAL_DSI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c
index e2774d19be..9f122a49bd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.c
@@ -11,6 +11,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
 ================================================================================
           ##### DTS Peripheral features #####
@@ -27,17 +38,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -76,6 +76,12 @@
  */
 #define TS_TIMEOUT_MS     (5UL)
 
+/* @brief DTS factory temperatures
+ * @note  Unit: degree Celsius
+ */
+#define DTS_FACTORY_TEMPERATURE1 (30UL)
+#define DTS_FACTORY_TEMPERATURE2 (130UL)
+
 /**
   * @}
   */
@@ -83,9 +89,6 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
-static void DTS_ResetCallback(DTS_HandleTypeDef *hdts);
-#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
 /* Exported functions --------------------------------------------------------*/
 
 /** @defgroup DTS_Exported_Functions DTS Exported Functions
@@ -131,8 +134,13 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts)
   if (hdts->State == HAL_DTS_STATE_RESET)
   {
 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
-    /* Reset interrupt callbacks to legacy weak callbacks */
-    DTS_ResetCallback(hdts);
+    /* Reset the DTS callback to the legacy weak callbacks */
+    hdts->EndCallback       = HAL_DTS_EndCallback;        /* End measure Callback                 */
+    hdts->LowCallback       = HAL_DTS_LowCallback;        /* low threshold Callback               */
+    hdts->HighCallback      = HAL_DTS_HighCallback;       /* high threshold Callback              */
+    hdts->AsyncEndCallback  = HAL_DTS_AsyncEndCallback;   /* Asynchronous end of measure Callback */
+    hdts->AsyncLowCallback  = HAL_DTS_AsyncLowCallback;   /* Asynchronous low threshold Callback  */
+    hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback;  /* Asynchronous high threshold Callback */
 
     if (hdts->MspInitCallback == NULL)
     {
@@ -277,6 +285,180 @@ __weak void HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts)
   */
 }
 
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a user DTS callback to be used instead of the weak predefined callback.
+  * @param  hdts DTS handle.
+  * @param  CallbackID ID of the callback to be registered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID.
+  *           @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID.
+  *           @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID.
+  *           @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID.
+  *           @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID.
+  *           @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID.
+  *           @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @param  pCallback pointer to the callback function.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef        *hdts,
+                                           HAL_DTS_CallbackIDTypeDef CallbackID,
+                                           pDTS_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check parameters */
+  if (pCallback == NULL)
+  {
+    /* Update status */
+    status = HAL_ERROR;
+  }
+  else
+  {
+    if (hdts->State == HAL_DTS_STATE_READY)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DTS_MEAS_COMPLETE_CB_ID :
+          hdts->EndCallback = pCallback;
+          break;
+        case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID :
+          hdts->AsyncEndCallback = pCallback;
+          break;
+        case HAL_DTS_LOW_THRESHOLD_CB_ID :
+          hdts->LowCallback = pCallback;
+          break;
+        case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID :
+          hdts->AsyncLowCallback = pCallback;
+          break;
+        case HAL_DTS_HIGH_THRESHOLD_CB_ID :
+          hdts->HighCallback = pCallback;
+          break;
+        case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID :
+          hdts->AsyncHighCallback = pCallback;
+          break;
+        case HAL_DTS_MSPINIT_CB_ID :
+          hdts->MspInitCallback = pCallback;
+          break;
+        case HAL_DTS_MSPDEINIT_CB_ID :
+          hdts->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* Update status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else if (hdts->State == HAL_DTS_STATE_RESET)
+    {
+      switch (CallbackID)
+      {
+        case HAL_DTS_MSPINIT_CB_ID :
+          hdts->MspInitCallback = pCallback;
+          break;
+        case HAL_DTS_MSPDEINIT_CB_ID :
+          hdts->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* Update status */
+          status = HAL_ERROR;
+          break;
+      }
+    }
+    else
+    {
+      /* Update status */
+      status = HAL_ERROR;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Unregister a user DTS callback.
+  *         DTS callback is redirected to the weak predefined callback.
+  * @param  hdts DTS handle.
+  * @param  CallbackID ID of the callback to be unregistered.
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_DTS_MEAS_COMPLETE_CB_ID measure complete callback ID.
+  *           @arg @ref HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID asynchronous measure complete callback ID.
+  *           @arg @ref HAL_DTS_LOW_THRESHOLD_CB_ID low threshold detection callback ID.
+  *           @arg @ref HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID asynchronous low threshold detection callback ID.
+  *           @arg @ref HAL_DTS_HIGH_THRESHOLD_CB_ID high threshold detection callback ID.
+  *           @arg @ref HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID asynchronous high threshold detection callback ID.
+  *           @arg @ref HAL_DTS_MSPINIT_CB_ID MSP init callback ID.
+  *           @arg @ref HAL_DTS_MSPDEINIT_CB_ID MSP de-init callback ID.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef        *hdts,
+                                             HAL_DTS_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hdts->State == HAL_DTS_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DTS_MEAS_COMPLETE_CB_ID :
+        hdts->EndCallback = HAL_DTS_EndCallback;
+        break;
+      case HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID :
+        hdts->AsyncEndCallback = HAL_DTS_AsyncEndCallback;
+        break;
+      case HAL_DTS_LOW_THRESHOLD_CB_ID :
+        hdts->LowCallback = HAL_DTS_LowCallback;
+        break;
+      case HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID :
+        hdts->AsyncLowCallback = HAL_DTS_AsyncLowCallback;
+        break;
+      case HAL_DTS_HIGH_THRESHOLD_CB_ID :
+        hdts->HighCallback = HAL_DTS_HighCallback;
+        break;
+      case HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID :
+        hdts->AsyncHighCallback = HAL_DTS_AsyncHighCallback;
+        break;
+      case HAL_DTS_MSPINIT_CB_ID :
+        hdts->MspInitCallback = HAL_DTS_MspInit;
+        break;
+      case HAL_DTS_MSPDEINIT_CB_ID :
+        hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
+        break;
+      default :
+        /* Update status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdts->State == HAL_DTS_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DTS_MSPINIT_CB_ID :
+        hdts->MspInitCallback = HAL_DTS_MspInit;
+        break;
+      case HAL_DTS_MSPDEINIT_CB_ID :
+        hdts->MspDeInitCallback = HAL_DTS_MspDeInit;
+        break;
+      default :
+        /* Update status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update status */
+    status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return status;
+}
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -538,11 +720,11 @@ HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Tempe
 
     if (t0_temp == 0UL)
     {
-      t0_temp = 30UL; /* 30 deg C */
+      t0_temp = DTS_FACTORY_TEMPERATURE1; /* 30 deg C */
     }
     else if (t0_temp == 1UL)
     {
-      t0_temp = 110UL; /* 110 deg C */
+      t0_temp = DTS_FACTORY_TEMPERATURE2; /* 130 deg C */
     }
     else
     {
@@ -785,33 +967,6 @@ HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts)
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DTS_Private_Functions DTS Private Functions
-  * @{
-  */
-#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Reset interrupt callbacks to the legacy weak callbacks.
-  * @param  hdts pointer to a DTS_HandleTypeDef structure that contains
-  *                the configuration information for DTS module.
-  * @retval None
-  */
-static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
-{
-  /* Reset the DTS callback to the legacy weak callbacks */
-  hdts->DTS_EndCallback       = HAL_DTS_EndCallback;        /* End measure Callback                 */
-  hdts->DTS_LowCallback       = HAL_DTS_LowCallback;        /* low threshold Callback               */
-  hdts->DTS_HighCallback      = HAL_DTS_HighCallback;       /* high threshold Callback              */
-  hdts->DTS_AsyncEndCallback  = HAL_DTS_AsyncEndCallback;   /* Asynchronous end of measure Callback */
-  hdts->DTS_AsyncLowCallback  = HAL_DTS_AsyncLowCallback;   /* Asynchronous low threshold Callback  */
-  hdts->DTS_AsyncHighCallback = HAL_DTS_AsyncHighCallback;  /* Asynchronous high threshold Callback */
-}
-#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
 /**
   * @}
   */
@@ -824,4 +979,3 @@ static void DTS_ResetCallback(DTS_HandleTypeDef *hdts)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.h
index 63815fb478..f9bff1703e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dts.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -25,14 +24,15 @@
 extern "C" {
 #endif
 
-#if defined(DTS)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
+
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
-
+#if defined(DTS)
 /** @addtogroup DTS
   * @{
   */
@@ -96,15 +96,37 @@ typedef struct
 #if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
   void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< DTS Base Msp Init Callback                   */
   void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts);       /*!< DTS Base Msp DeInit Callback                 */
-  void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< End measure Callback                         */
-  void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< low threshold Callback                       */
-  void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts);        /*!< high threshold Callback                      */
-  void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous end of measure Callback         */
-  void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous low threshold Callback          */
-  void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous high threshold Callback         */
+  void (* EndCallback)(struct __DTS_HandleTypeDef *hdts);             /*!< End measure Callback                         */
+  void (* LowCallback)(struct __DTS_HandleTypeDef *hdts);             /*!< low threshold Callback                       */
+  void (* HighCallback)(struct __DTS_HandleTypeDef *hdts);            /*!< high threshold Callback                      */
+  void (* AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts);        /*!< Asynchronous end of measure Callback         */
+  void (* AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts);        /*!< Asynchronous low threshold Callback          */
+  void (* AsyncHighCallback)(struct __DTS_HandleTypeDef *hdts);       /*!< Asynchronous high threshold Callback         */
 #endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
 } DTS_HandleTypeDef;
 
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  DTS callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DTS_MEAS_COMPLETE_CB_ID        = 0x00U, /*!< Measure complete callback ID */
+  HAL_DTS_ASYNC_MEAS_COMPLETE_CB_ID  = 0x01U, /*!< Asynchronous measure complete callback ID */
+  HAL_DTS_LOW_THRESHOLD_CB_ID        = 0x02U, /*!< Low threshold detection callback ID */
+  HAL_DTS_ASYNC_LOW_THRESHOLD_CB_ID  = 0x03U, /*!< Asynchronous low threshold detection callback ID */
+  HAL_DTS_HIGH_THRESHOLD_CB_ID       = 0x04U, /*!< High threshold detection callback ID */
+  HAL_DTS_ASYNC_HIGH_THRESHOLD_CB_ID = 0x05U, /*!< Asynchronous high threshold detection callback ID */
+  HAL_DTS_MSPINIT_CB_ID              = 0x06U, /*!< MSP init callback ID */
+  HAL_DTS_MSPDEINIT_CB_ID            = 0x07U  /*!< MSP de-init callback ID */
+} HAL_DTS_CallbackIDTypeDef;
+
+/**
+  * @brief  DTS callback pointers definition
+  */
+typedef void (*pDTS_CallbackTypeDef)(DTS_HandleTypeDef *hdts);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -213,7 +235,15 @@ typedef struct
   * @param  __HANDLE__ DTS handle.
   * @retval None
   */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__) do{                                             \
+                                                      (__HANDLE__)->State = HAL_DTS_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback = NULL;      \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \
+                                                    } while(0)
+#else /* USE_HAL_DTS_REGISTER_CALLBACKS */
 #define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__)    ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
 
 /**
   * @brief  Enable the specified DTS sensor
@@ -372,6 +402,13 @@ HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
 HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
 void              HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
 void              HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_DTS_RegisterCallback(DTS_HandleTypeDef        *hdts,
+                                           HAL_DTS_CallbackIDTypeDef CallbackID,
+                                           pDTS_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_DTS_UnRegisterCallback(DTS_HandleTypeDef        *hdts,
+                                             HAL_DTS_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
 /**
   * @}
   */
@@ -397,6 +434,9 @@ void              HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
 /**
   * @}
   */
+/**
+  * @}
+  */
 
 /* Private types -------------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -436,7 +476,7 @@ void              HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
 
 #define IS_DTS_THRESHOLD(__THRESHOLD__)  ((__THRESHOLD__) <= 0xFFFFUL)
 
-#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL)))
+#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) ((__NUMBER__) <= 127UL)
 
 #define IS_DTS_SAMPLINGTIME(__CYCLE__)  (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE)  || \
                                              ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE)    || \
@@ -480,4 +520,3 @@ void              HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
 
 #endif /* __STM32H7xx_HAL_DTS_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c
index decff79455..77cbabe31b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State and Errors functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
@@ -39,18 +50,14 @@
           (##) HAL_ETH_Start():
                This API starts the MAC and DMA transmission and reception process,
                without enabling end of transfer interrupts, in this mode user
-               has to poll for data availability by calling HAL_ETH_IsRxDataAvailable()
+               has to poll for data reception by calling HAL_ETH_ReadData()
           (##) HAL_ETH_Start_IT():
                This API starts the MAC and DMA transmission and reception process,
                end of transfer interrupts are enabled in this mode,
                HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received
 
-      (#) When data is received (HAL_ETH_IsRxDataAvailable() returns 1 or Rx interrupt
-          occurred), user can call the following APIs to get received data:
-          (##) HAL_ETH_GetRxDataBuffer(): Get buffer address of received frame
-          (##) HAL_ETH_GetRxDataLength(): Get received frame length
-          (##) HAL_ETH_GetRxDataInfo(): Get received frame additional info,
-               please refer to ETH_RxPacketInfo typedef structure
+      (#) When data is received user can call the following API to get received data:
+          (##) HAL_ETH_ReadData(): Read a received packet
 
       (#) For transmission path, two APIs are available:
          (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode
@@ -69,20 +76,32 @@
           (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef
           (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef
 
-      -@- The PTP protocol offload APIs are not supported in this driver.
+      (#) Configure the Ethernet PTP after ETH peripheral initialization
+          (##) Define HAL_ETH_USE_PTP to use PTP APIs.
+          (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef
+          (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef
+          (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers
+          (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers
+          (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers
+          (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission
+          (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp
+          (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp
+
+      -@- The ARP offload feature is not supported in this driver.
+
+      -@- The PTP offload feature is not supported in this driver.
 
   *** Callback registration ***
   =============================================
 
   The compilation define  USE_HAL_ETH_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
-  Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback.
+  Use Function HAL_ETH_RegisterCallback() to register an interrupt callback.
 
-  Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks:
+  Function HAL_ETH_RegisterCallback() allows to register following callbacks:
     (+) TxCpltCallback   : Tx Complete Callback.
     (+) RxCpltCallback   : Rx Complete Callback.
-    (+) DMAErrorCallback : DMA Error Callback.
-    (+) MACErrorCallback : MAC Error Callback.
+    (+) ErrorCallback    : Error Callback.
     (+) PMTCallback      : Power Management Callback
     (+) EEECallback      : EEE Callback.
     (+) WakeUpCallback   : Wake UP Callback
@@ -92,28 +111,51 @@
   This function takes as parameters the HAL peripheral handle, the Callback ID
   and a pointer to the user callback function.
 
-  Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default
+  For specific callbacks RxAllocateCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterRxAllocateCallback().
+
+  For specific callbacks RxLinkCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterRxLinkCallback().
+
+  For specific callbacks TxFreeCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterTxFreeCallback().
+
+  For specific callbacks TxPtpCallback use dedicated register callbacks:
+  respectively HAL_ETH_RegisterTxPtpCallback().
+
+  Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default
   weak function.
-  @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle,
   and the Callback ID.
   This function allows to reset following callbacks:
     (+) TxCpltCallback   : Tx Complete Callback.
     (+) RxCpltCallback   : Rx Complete Callback.
-    (+) DMAErrorCallback : DMA Error Callback.
-    (+) MACErrorCallback : MAC Error Callback.
+    (+) ErrorCallback    : Error Callback.
     (+) PMTCallback      : Power Management Callback
     (+) EEECallback      : EEE Callback.
     (+) WakeUpCallback   : Wake UP Callback
     (+) MspInitCallback  : MspInit Callback.
     (+) MspDeInitCallback: MspDeInit Callback.
 
+  For specific callbacks RxAllocateCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterRxAllocateCallback().
+
+  For specific callbacks RxLinkCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterRxLinkCallback().
+
+  For specific callbacks TxFreeCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterTxFreeCallback().
+
+  For specific callbacks TxPtpCallback use dedicated unregister callbacks:
+  respectively HAL_ETH_UnRegisterTxPtpCallback().
+
   By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET
   all callbacks are set to the corresponding weak functions:
-  examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback().
+  examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback().
   Exception done for MspInit and MspDeInit functions that are
-  reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when
+  reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when
   these callbacks are null (not registered beforehand).
-  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit
+  if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit
   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
   Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only.
@@ -121,7 +163,7 @@
   in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state,
   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit
+  using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit
   or HAL_ETH_Init function.
 
   When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or
@@ -130,17 +172,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -163,33 +194,34 @@
 /** @addtogroup ETH_Private_Constants ETH Private Constants
   * @{
   */
-#define ETH_MACCR_MASK       ((uint32_t)0xFFFB7F7CU)
-#define ETH_MACECR_MASK      ((uint32_t)0x3F077FFFU)
-#define ETH_MACPFR_MASK      ((uint32_t)0x800007FFU)
-#define ETH_MACWTR_MASK      ((uint32_t)0x0000010FU)
-#define ETH_MACTFCR_MASK     ((uint32_t)0xFFFF00F2U)
-#define ETH_MACRFCR_MASK     ((uint32_t)0x00000003U)
-#define ETH_MTLTQOMR_MASK    ((uint32_t)0x00000072U)
-#define ETH_MTLRQOMR_MASK    ((uint32_t)0x0000007BU)
+#define ETH_MACCR_MASK                0xFFFB7F7CU
+#define ETH_MACECR_MASK               0x3F077FFFU
+#define ETH_MACPFR_MASK               0x800007FFU
+#define ETH_MACWTR_MASK               0x0000010FU
+#define ETH_MACTFCR_MASK              0xFFFF00F2U
+#define ETH_MACRFCR_MASK              0x00000003U
+#define ETH_MTLTQOMR_MASK             0x00000072U
+#define ETH_MTLRQOMR_MASK             0x0000007BU
 
-#define ETH_DMAMR_MASK       ((uint32_t)0x00007802U)
-#define ETH_DMASBMR_MASK     ((uint32_t)0x0000D001U)
-#define ETH_DMACCR_MASK      ((uint32_t)0x00013FFFU)
-#define ETH_DMACTCR_MASK     ((uint32_t)0x003F1010U)
-#define ETH_DMACRCR_MASK     ((uint32_t)0x803F0000U)
-#define ETH_MACPCSR_MASK     (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
-                              ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
-                              ETH_MACPCSR_RWKPFE)
+#define ETH_DMAMR_MASK                0x00007802U
+#define ETH_DMASBMR_MASK              0x0000D001U
+#define ETH_DMACCR_MASK               0x00013FFFU
+#define ETH_DMACTCR_MASK              0x003F1010U
+#define ETH_DMACRCR_MASK              0x803F0000U
+#define ETH_MACPCSR_MASK              (ETH_MACPCSR_PWRDWN | ETH_MACPCSR_RWKPKTEN | \
+                                       ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | \
+                                       ETH_MACPCSR_RWKPFE)
 
 /* Timeout values */
-#define ETH_SWRESET_TIMEOUT                 ((uint32_t)500U)
-#define ETH_MDIO_BUS_TIMEOUT                ((uint32_t)1000U)
-
 #define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t)(ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \
                                                   ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\
                                                   ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE))
 
-#define ETH_MAC_US_TICK               ((uint32_t)1000000U)
+#define ETH_MACTSCR_MASK              0x0087FF2FU
+
+#define ETH_MACSTSUR_VALUE            0xFFFFFFFFU
+#define ETH_MACSTNUR_VALUE            0xBB9ACA00U
+#define ETH_SEGMENT_SIZE_DEFAULT      0x218U
 /**
   * @}
   */
@@ -200,17 +232,17 @@
   */
 /* Helper macros for TX descriptor handling */
 #define INCR_TX_DESC_INDEX(inx, offset) do {\
-	(inx) += (offset);\
-          if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
-            (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
-} while (0)
+                                             (inx) += (offset);\
+                                             if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\
+                                             (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\
+                                           } while (0)
 
 /* Helper macros for RX descriptor handling */
 #define INCR_RX_DESC_INDEX(inx, offset) do {\
-	(inx) += (offset);\
-          if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
-            (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
-} while (0)
+                                             (inx) += (offset);\
+                                             if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\
+                                             (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\
+                                           } while (0)
 /**
   * @}
   */
@@ -218,13 +250,14 @@
 /** @defgroup ETH_Private_Functions   ETH Private Functions
   * @{
   */
-static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth);
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf);
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf);
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf);
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf);
 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth);
 static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth);
 static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth);
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode);
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
+                                           uint32_t ItMode);
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth);
 
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
@@ -259,9 +292,6 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth);
         (++) Tx DMA Descriptors Tab
         (++) Length of Rx Buffers
 
-      (+) Call the function HAL_ETH_DescAssignMemory() to assign data buffers
-          for each Rx DMA Descriptor
-
       (+) Call the function HAL_ETH_DeInit() to restore the default configuration
           of the selected ETH peripheral.
 
@@ -279,44 +309,35 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
 {
   uint32_t tickstart;
 
-  if(heth == NULL)
+  if (heth == NULL)
   {
     return HAL_ERROR;
   }
+  if (heth->gState == HAL_ETH_STATE_RESET)
+  {
+    heth->gState = HAL_ETH_STATE_BUSY;
 
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 
-  if(heth->gState == HAL_ETH_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    heth->Lock = HAL_UNLOCKED;
-
     ETH_InitCallbacksToDefault(heth);
 
-    if(heth->MspInitCallback == NULL)
+    if (heth->MspInitCallback == NULL)
     {
       heth->MspInitCallback = HAL_ETH_MspInit;
     }
 
     /* Init the low level hardware */
     heth->MspInitCallback(heth);
-  }
-
 #else
-
-  /* Check the ETH peripheral state */
-  if(heth->gState == HAL_ETH_STATE_RESET)
-  {
     /* Init the low level hardware : GPIO, CLOCK, NVIC. */
     HAL_ETH_MspInit(heth);
-  }
-#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
 
-  heth->gState = HAL_ETH_STATE_BUSY;
+#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
+  }
 
   __HAL_RCC_SYSCFG_CLK_ENABLE();
 
-  if(heth->Init.MediaInterface == HAL_ETH_MII_MODE)
+  if (heth->Init.MediaInterface == HAL_ETH_MII_MODE)
   {
     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_MII);
   }
@@ -325,6 +346,9 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
     HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII);
   }
 
+  /* Dummy read to sync with ETH */
+  (void)SYSCFG->PMCR;
+
   /* Ethernet Software reset */
   /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
   /* After reset all the registers holds their respective reset values */
@@ -336,7 +360,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
   /* Wait for software reset */
   while (READ_BIT(heth->Instance->DMAMR, ETH_DMAMR_SWR) > 0U)
   {
-    if(((HAL_GetTick() - tickstart ) > ETH_SWRESET_TIMEOUT))
+    if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT))
     {
       /* Set Error Code */
       heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT;
@@ -348,7 +372,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
   }
 
   /*------------------ MDIO CSR Clock Range Configuration --------------------*/
-  ETH_MAC_MDIO_ClkConfig(heth);
+  HAL_ETH_SetMDIOClockRange(heth);
 
   /*------------------ MAC LPI 1US Tic Counter Configuration --------------------*/
   WRITE_REG(heth->Instance->MAC1USTCR, (((uint32_t)HAL_RCC_GetHCLKFreq() / ETH_MAC_US_TICK) - 1U));
@@ -387,9 +411,16 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
   heth->Instance->MACA0LR = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) |
                              ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]);
 
+  /* Disable Rx MMC Interrupts */
+  SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RXLPITRCIM | ETH_MMCRIMR_RXLPIUSCIM | \
+          ETH_MMCRIMR_RXUCGPIM | ETH_MMCRIMR_RXALGNERPIM | ETH_MMCRIMR_RXCRCERPIM);
+
+  /* Disable Tx MMC Interrupts */
+  SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TXLPITRCIM | ETH_MMCTIMR_TXLPIUSCIM | \
+          ETH_MMCTIMR_TXGPKTIM | ETH_MMCTIMR_TXMCOLGPIM | ETH_MMCTIMR_TXSCOLGPIM);
+
   heth->ErrorCode = HAL_ETH_ERROR_NONE;
   heth->gState = HAL_ETH_STATE_READY;
-  heth->RxState = HAL_ETH_STATE_READY;
 
   return HAL_OK;
 }
@@ -407,7 +438,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
 
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 
-  if(heth->MspDeInitCallback == NULL)
+  if (heth->MspDeInitCallback == NULL)
   {
     heth->MspDeInitCallback = HAL_ETH_MspDeInit;
   }
@@ -421,7 +452,7 @@ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
 #endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */
 
   /* Set ETH HAL state to Disabled */
-  heth->gState= HAL_ETH_STATE_RESET;
+  heth->gState = HAL_ETH_STATE_RESET;
 
   /* Return function status */
   return HAL_OK;
@@ -466,8 +497,7 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
   *        This parameter can be one of the following values:
   *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
   *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
-  *          @arg @ref HAL_ETH_MAC_ERROR_CB_ID   MAC Error Callback ID
+  *          @arg @ref HAL_ETH_ERROR_CB_ID       Error Callback ID
   *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
   *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
   *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
@@ -476,86 +506,80 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
   * @param pCallback pointer to the Callback function
   * @retval status
   */
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+                                           pETH_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(pCallback == NULL)
+  if (pCallback == NULL)
   {
     /* Update the error code */
     heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(heth);
 
-  if(heth->gState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_READY)
   {
     switch (CallbackID)
     {
-    case HAL_ETH_TX_COMPLETE_CB_ID :
-      heth->TxCpltCallback = pCallback;
-      break;
+      case HAL_ETH_TX_COMPLETE_CB_ID :
+        heth->TxCpltCallback = pCallback;
+        break;
 
-    case HAL_ETH_RX_COMPLETE_CB_ID :
-      heth->RxCpltCallback = pCallback;
-      break;
+      case HAL_ETH_RX_COMPLETE_CB_ID :
+        heth->RxCpltCallback = pCallback;
+        break;
 
-    case HAL_ETH_DMA_ERROR_CB_ID :
-      heth->DMAErrorCallback = pCallback;
-      break;
+      case HAL_ETH_ERROR_CB_ID :
+        heth->ErrorCallback = pCallback;
+        break;
 
-    case HAL_ETH_MAC_ERROR_CB_ID :
-      heth->MACErrorCallback = pCallback;
-      break;
+      case HAL_ETH_PMT_CB_ID :
+        heth->PMTCallback = pCallback;
+        break;
 
-    case HAL_ETH_PMT_CB_ID :
-      heth->PMTCallback = pCallback;
-      break;
+      case HAL_ETH_EEE_CB_ID :
+        heth->EEECallback = pCallback;
+        break;
 
-    case HAL_ETH_EEE_CB_ID :
-      heth->EEECallback = pCallback;
-      break;
+      case HAL_ETH_WAKEUP_CB_ID :
+        heth->WakeUpCallback = pCallback;
+        break;
 
-    case HAL_ETH_WAKEUP_CB_ID :
-      heth->WakeUpCallback = pCallback;
-      break;
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = pCallback;
+        break;
 
-    case HAL_ETH_MSPINIT_CB_ID :
-      heth->MspInitCallback = pCallback;
-      break;
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = pCallback;
+        break;
 
-   case HAL_ETH_MSPDEINIT_CB_ID :
-      heth->MspDeInitCallback = pCallback;
-      break;
-
-    default :
-      /* Update the error code */
-      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-      /* Return error status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
     }
   }
-  else if(heth->gState == HAL_ETH_STATE_RESET)
+  else if (heth->gState == HAL_ETH_STATE_RESET)
   {
     switch (CallbackID)
     {
-    case HAL_ETH_MSPINIT_CB_ID :
-      heth->MspInitCallback = pCallback;
-      break;
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = pCallback;
+        break;
 
-   case HAL_ETH_MSPDEINIT_CB_ID :
-      heth->MspDeInitCallback = pCallback;
-      break;
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = pCallback;
+        break;
 
-    default :
-      /* Update the error code */
-      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-     /* Return error status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else
@@ -566,22 +590,18 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(heth);
-
   return status;
 }
 
 /**
   * @brief  Unregister an ETH Callback
-  *         ETH callabck is redirected to the weak predefined callback
+  *         ETH callback is redirected to the weak predefined callback
   * @param heth eth handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
   *          @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID
   *          @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *          @arg @ref HAL_ETH_DMA_ERROR_CB_ID   DMA Error Callback ID
-  *          @arg @ref HAL_ETH_MAC_ERROR_CB_ID   MAC Error Callback ID
+  *          @arg @ref HAL_ETH_ERROR_CB_ID       Error Callback ID
   *          @arg @ref HAL_ETH_PMT_CB_ID         Power Management Callback ID
   *          @arg @ref HAL_ETH_EEE_CB_ID         EEE Callback ID
   *          @arg @ref HAL_ETH_WAKEUP_CB_ID      Wake UP Callback ID
@@ -593,75 +613,68 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(heth);
-
-  if(heth->gState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_READY)
   {
     switch (CallbackID)
     {
-    case HAL_ETH_TX_COMPLETE_CB_ID :
-      heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
-      break;
+      case HAL_ETH_TX_COMPLETE_CB_ID :
+        heth->TxCpltCallback = HAL_ETH_TxCpltCallback;
+        break;
 
-    case HAL_ETH_RX_COMPLETE_CB_ID :
-      heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
-      break;
+      case HAL_ETH_RX_COMPLETE_CB_ID :
+        heth->RxCpltCallback = HAL_ETH_RxCpltCallback;
+        break;
 
-    case HAL_ETH_DMA_ERROR_CB_ID :
-      heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;
-      break;
+      case HAL_ETH_ERROR_CB_ID :
+        heth->ErrorCallback = HAL_ETH_ErrorCallback;
+        break;
 
-    case HAL_ETH_MAC_ERROR_CB_ID :
-      heth->MACErrorCallback = HAL_ETH_MACErrorCallback;
-      break;
+      case HAL_ETH_PMT_CB_ID :
+        heth->PMTCallback = HAL_ETH_PMTCallback;
+        break;
 
-    case HAL_ETH_PMT_CB_ID :
-      heth->PMTCallback = HAL_ETH_PMTCallback;
-      break;
+      case HAL_ETH_EEE_CB_ID :
+        heth->EEECallback = HAL_ETH_EEECallback;
+        break;
 
-    case HAL_ETH_EEE_CB_ID :
-      heth->EEECallback = HAL_ETH_EEECallback;
-      break;
+      case HAL_ETH_WAKEUP_CB_ID :
+        heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
+        break;
 
-    case HAL_ETH_WAKEUP_CB_ID :
-      heth->WakeUpCallback = HAL_ETH_WakeUpCallback;
-      break;
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = HAL_ETH_MspInit;
+        break;
 
-    case HAL_ETH_MSPINIT_CB_ID :
-      heth->MspInitCallback = HAL_ETH_MspInit;
-      break;
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+        break;
 
-   case HAL_ETH_MSPDEINIT_CB_ID :
-      heth->MspDeInitCallback = HAL_ETH_MspDeInit;
-      break;
-
-    default :
-      /* Update the error code */
-      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-     /* Return error status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
     }
   }
-  else if(heth->gState == HAL_ETH_STATE_RESET)
+  else if (heth->gState == HAL_ETH_STATE_RESET)
   {
     switch (CallbackID)
     {
-    case HAL_ETH_MSPINIT_CB_ID :
-      heth->MspInitCallback = HAL_ETH_MspInit;
-      break;
+      case HAL_ETH_MSPINIT_CB_ID :
+        heth->MspInitCallback = HAL_ETH_MspInit;
+        break;
 
-   case HAL_ETH_MSPDEINIT_CB_ID :
-      heth->MspDeInitCallback = HAL_ETH_MspDeInit;
-      break;
+      case HAL_ETH_MSPDEINIT_CB_ID :
+        heth->MspDeInitCallback = HAL_ETH_MspDeInit;
+        break;
 
-    default :
-      /* Update the error code */
-      heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
-     /* Return error status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK;
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else
@@ -672,57 +685,10 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(heth);
-
   return status;
 }
 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
-/**
-  * @brief  Assign memory buffers to a DMA Rx descriptor
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  Index : index of the DMA Rx descriptor
-  *                  this parameter can be a value from 0x0 to (ETH_RX_DESC_CNT -1)
-  * @param  pBuffer1: address of buffer 1
-  * @param  pBuffer2: address of buffer 2 if available
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1, uint8_t *pBuffer2)
-{
-  ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[Index];
-
-  if((pBuffer1 == NULL) || (Index >= (uint32_t)ETH_RX_DESC_CNT))
-  {
-    /* Set Error Code */
-    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
-    /* Return Error */
-    return HAL_ERROR;
-  }
-
-  /* write buffer address to RDES0 */
-  WRITE_REG(dmarxdesc->DESC0, (uint32_t)pBuffer1);
-  /* store buffer address */
-  WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)pBuffer1);
-  /* set buffer address valid bit to RDES3 */
-  SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
-  if(pBuffer2 != NULL)
-  {
-    /* write buffer 2 address to RDES1 */
-    WRITE_REG(dmarxdesc->DESC2, (uint32_t)pBuffer2);
-     /* store buffer 2 address */
-    WRITE_REG(dmarxdesc->BackupAddr1, (uint32_t)pBuffer2);
-    /* set buffer 2 address valid bit to RDES3 */
-    SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
-  }
-  /* set OWN bit to RDES3 */
-  SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
-
-  return HAL_OK;
-}
-
 /**
   * @}
   */
@@ -750,10 +716,16 @@ HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Ind
   */
 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
 {
-  if(heth->gState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_READY)
   {
     heth->gState = HAL_ETH_STATE_BUSY;
 
+    /* Set number of descriptors to build */
+    heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
+
+    /* Build all descriptors */
+    ETH_UpdateDescriptor(heth);
+
     /* Enable the MAC transmission */
     SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
@@ -772,8 +744,7 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
     /* Clear Tx and Rx process stopped flags */
     heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
 
-    heth->gState = HAL_ETH_STATE_READY;
-    heth->RxState = HAL_ETH_STATE_BUSY_RX;
+    heth->gState = HAL_ETH_STATE_STARTED;
 
     return HAL_OK;
   }
@@ -791,32 +762,18 @@ HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
   */
 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
 {
-  uint32_t descindex;
-
-  ETH_DMADescTypeDef *dmarxdesc;
-
-  if(heth->gState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_READY)
   {
     heth->gState = HAL_ETH_STATE_BUSY;
 
-    /* Set IOC bit to all Rx descriptors */
-    for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
-    {
-      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
-      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
-    }
-
     /* save IT mode to ETH Handle */
     heth->RxDescList.ItMode = 1U;
 
-    /* Enable the MAC transmission */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+    /* Set number of descriptors to build */
+    heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT;
 
-    /* Enable the MAC reception */
-    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
-
-    /* Set the Flush Transmit FIFO bit */
-    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+    /* Build all descriptors */
+    ETH_UpdateDescriptor(heth);
 
     /* Enable the DMA transmission */
     SET_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -827,17 +784,24 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
     /* Clear Tx and Rx process stopped flags */
     heth->Instance->DMACSR |= (ETH_DMACSR_TPS | ETH_DMACSR_RPS);
 
+    /* Set the Flush Transmit FIFO bit */
+    SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
+
+    /* Enable the MAC transmission */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
+
+    /* Enable the MAC reception */
+    SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
+
     /* Enable ETH DMA interrupts:
     - Tx complete interrupt
     - Rx complete interrupt
     - Fatal bus interrupt
     */
     __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
-                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
-
-    heth->gState = HAL_ETH_STATE_READY;
-    heth->RxState = HAL_ETH_STATE_BUSY_RX;
+                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
 
+    heth->gState = HAL_ETH_STATE_STARTED;
     return HAL_OK;
   }
   else
@@ -854,9 +818,9 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth)
   */
 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
 {
-  if(heth->gState != HAL_ETH_STATE_RESET)
+  if (heth->gState == HAL_ETH_STATE_STARTED)
   {
-     /* Set the ETH peripheral state to BUSY */
+    /* Set the ETH peripheral state to BUSY */
     heth->gState = HAL_ETH_STATE_BUSY;
 
     /* Disable the DMA transmission */
@@ -866,7 +830,7 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
     CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
 
     /* Disable the MAC reception */
-    CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
 
     /* Set the Flush Transmit FIFO bit */
     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
@@ -875,7 +839,6 @@ HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
     CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
     heth->gState = HAL_ETH_STATE_READY;
-    heth->RxState = HAL_ETH_STATE_READY;
 
     /* Return function status */
     return HAL_OK;
@@ -897,7 +860,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
   ETH_DMADescTypeDef *dmarxdesc;
   uint32_t descindex;
 
-  if(heth->gState != HAL_ETH_STATE_RESET)
+  if (heth->gState == HAL_ETH_STATE_STARTED)
   {
     /* Set the ETH peripheral state to BUSY */
     heth->gState = HAL_ETH_STATE_BUSY;
@@ -908,7 +871,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
     - Fatal bus interrupt
     */
     __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMACIER_NIE | ETH_DMACIER_RIE | ETH_DMACIER_TIE  |
-                                   ETH_DMACIER_FBEE | ETH_DMACIER_AIE));
+                                    ETH_DMACIER_FBEE | ETH_DMACIER_AIE | ETH_DMACIER_RBUE));
 
     /* Disable the DMA transmission */
     CLEAR_BIT(heth->Instance->DMACTCR, ETH_DMACTCR_ST);
@@ -917,7 +880,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
     CLEAR_BIT(heth->Instance->DMACRCR, ETH_DMACRCR_SR);
 
     /* Disable the MAC reception */
-    CLEAR_BIT( heth->Instance->MACCR, ETH_MACCR_RE);
+    CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE);
 
     /* Set the Flush Transmit FIFO bit */
     SET_BIT(heth->Instance->MTLTQOMR, ETH_MTLTQOMR_FTQ);
@@ -926,7 +889,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
     CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE);
 
     /* Clear IOC bit to all Rx descriptors */
-    for(descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
+    for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++)
     {
       dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex];
       CLEAR_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
@@ -935,7 +898,6 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
     heth->RxDescList.ItMode = 0U;
 
     heth->gState = HAL_ETH_STATE_READY;
-    heth->RxState = HAL_ETH_STATE_READY;
 
     /* Return function status */
     return HAL_OK;
@@ -954,18 +916,18 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth)
   * @param  Timeout: timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout)
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout)
 {
   uint32_t tickstart;
-  const ETH_DMADescTypeDef *dmatxdesc;
+  ETH_DMADescTypeDef *dmatxdesc;
 
-  if(pTxConfig == NULL)
+  if (pTxConfig == NULL)
   {
     heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
     return HAL_ERROR;
   }
 
-  if(heth->gState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_STARTED)
   {
     /* Config DMA Tx descriptor by Tx Packet info */
     if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE)
@@ -975,6 +937,9 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
       return HAL_ERROR;
     }
 
+    /* Ensure completion of descriptor preparation before transmission start */
+    __DSB();
+
     dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc];
 
     /* Incr current tx desc index */
@@ -987,25 +952,24 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
     tickstart = HAL_GetTick();
 
     /* Wait for data to be transmitted or timeout occurred */
-    while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
+    while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET)
     {
-      if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
+      if ((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET)
       {
         heth->ErrorCode |= HAL_ETH_ERROR_DMA;
         heth->DMAErrorCode = heth->Instance->DMACSR;
-        /* Set ETH HAL State to Ready */
-        heth->gState = HAL_ETH_STATE_ERROR;
         /* Return function status */
         return HAL_ERROR;
       }
 
       /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY)
       {
-        if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
         {
           heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT;
-          heth->gState = HAL_ETH_STATE_ERROR;
+          /* Clear TX descriptor so that we can proceed */
+          dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD);
           return HAL_ERROR;
         }
       }
@@ -1027,16 +991,19 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *
   * @param  pTxConfig: Hold the configuration of packet to be transmitted
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig)
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig)
 {
-  if(pTxConfig == NULL)
+  if (pTxConfig == NULL)
   {
     heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
     return HAL_ERROR;
   }
 
-  if(heth->gState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_STARTED)
   {
+    /* Save the packet pointer to release.  */
+    heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData;
+
     /* Config DMA Tx descriptor by Tx Packet info */
     if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE)
     {
@@ -1044,6 +1011,9 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi
       return HAL_ERROR;
     }
 
+    /* Ensure completion of descriptor preparation before transmission start */
+    __DSB();
+
     /* Incr current tx desc index */
     INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U);
 
@@ -1061,410 +1031,823 @@ HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfi
 }
 
 /**
-  * @brief  Checks for received Packets.
+  * @brief  Read a received packet.
   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @retval  1: A Packet is received
-  *          0: no Packet received
+  * @param  pAppBuff: Pointer to an application buffer to receive the packet.
+  * @retval HAL status
   */
-uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth)
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff)
 {
-  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
-  uint32_t descidx = dmarxdesclist->CurRxDesc;
-  ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-  uint32_t descscancnt = 0;
-  uint32_t appdesccnt = 0, firstappdescidx = 0;
+  uint32_t descidx;
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t desccnt = 0U;
+  uint32_t desccntmax;
+  uint32_t bufflength;
+  uint8_t rxdataready = 0U;
 
-  if(dmarxdesclist->AppDescNbr != 0U)
+  if (pAppBuff == NULL)
   {
-    /* data already received by not yet processed*/
-    return 0;
+    heth->ErrorCode |= HAL_ETH_ERROR_PARAM;
+    return HAL_ERROR;
   }
 
+  if (heth->gState != HAL_ETH_STATE_STARTED)
+  {
+    return HAL_ERROR;
+  }
+
+  descidx = heth->RxDescList.RxDescIdx;
+  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+  desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt;
+
   /* Check if descriptor is not owned by DMA */
-  while((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (descscancnt < (uint32_t)ETH_RX_DESC_CNT))
+  while ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_OWN) == (uint32_t)RESET) && (desccnt < desccntmax)
+         && (rxdataready == 0U))
   {
-    descscancnt++;
-
-    /* Check if last descriptor */
-    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
+    if (READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
     {
-      /* Increment the number of descriptors to be passed to the application */
-      appdesccnt += 1U;
-
-      if(appdesccnt == 1U)
+      /* Get timestamp high */
+      heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1;
+      /* Get timestamp low */
+      heth->RxDescList.TimeStamp.TimeStampLow  = dmarxdesc->DESC0;
+    }
+    if ((READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL))
+    {
+      /* Check if first descriptor */
+      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
       {
-        WRITE_REG(firstappdescidx, descidx);
+        heth->RxDescList.RxDescCnt = 0;
+        heth->RxDescList.RxDataLength = 0;
       }
 
-      /* Increment current rx descriptor index */
-      INCR_RX_DESC_INDEX(descidx, 1U);
+      /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
+      bufflength = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength;
 
-      /* Check for Context descriptor */
-      /* Get current descriptor address */
-      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
-      if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_OWN)  == (uint32_t)RESET)
+      /* Check if last descriptor */
+      if (READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LD) != (uint32_t)RESET)
       {
-        if(READ_BIT(dmarxdesc->DESC3,  ETH_DMARXNDESCWBF_CTXT)  != (uint32_t)RESET)
-        {
-          /* Increment the number of descriptors to be passed to the application */
-          dmarxdesclist->AppContextDesc = 1;
-          /* Increment current rx descriptor index */
-          INCR_RX_DESC_INDEX(descidx, 1U);
-        }
-      }
-      /* Fill information to Rx descriptors list */
-      dmarxdesclist->CurRxDesc = descidx;
-      dmarxdesclist->FirstAppDesc = firstappdescidx;
-      dmarxdesclist->AppDescNbr = appdesccnt;
+        /* Save Last descriptor index */
+        heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3;
 
-      /* Return function status */
-      return 1;
-    }
-    /* Check if first descriptor */
-    else if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_FD) != (uint32_t)RESET)
-    {
-      WRITE_REG(firstappdescidx, descidx);
-      /* Increment the number of descriptors to be passed to the application */
-      appdesccnt = 1U;
-
-      /* Increment current rx descriptor index */
-      INCR_RX_DESC_INDEX(descidx, 1U);
-      /* Get current descriptor address */
-      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-    }
-    /* It should be an intermediate descriptor */
-    else
-    {
-      /* Increment the number of descriptors to be passed to the application */
-      appdesccnt += 1U;
-
-      /* Increment current rx descriptor index */
-      INCR_RX_DESC_INDEX(descidx, 1U);
-      /* Get current descriptor address */
-      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-    }
-  }
-
-  /* Build Descriptors if an incomplete Packet is received */
-  if(appdesccnt > 0U)
-  {
-    dmarxdesclist->CurRxDesc = descidx;
-    dmarxdesclist->FirstAppDesc = firstappdescidx;
-    descidx = firstappdescidx;
-    dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
-    for(descscancnt = 0; descscancnt < appdesccnt; descscancnt++)
-    {
-      WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
-      WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
-      if (READ_REG(dmarxdesc->BackupAddr1) != ((uint32_t)RESET))
-      {
-        WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
-        SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
+        /* Packet ready */
+        rxdataready = 1;
       }
 
-      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
+      /* Link data */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Link callback*/
+      heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+                           (uint8_t *)dmarxdesc->BackupAddr0, bufflength);
+#else
+      /* Link callback */
+      HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd,
+                             (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      heth->RxDescList.RxDescCnt++;
+      heth->RxDescList.RxDataLength += bufflength;
 
-      if(dmarxdesclist->ItMode != ((uint32_t)RESET))
-      {
-        SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
-      }
-      if(descscancnt < (appdesccnt - 1U))
-      {
-        /* Increment rx descriptor index */
-        INCR_RX_DESC_INDEX(descidx, 1U);
-        /* Get descriptor address */
-        dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-      }
+      /* Clear buffer pointer */
+      dmarxdesc->BackupAddr0 = 0;
     }
 
-    /* Set the Tail pointer address to the last rx descriptor hold by the app */
-    WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
-  }
-
-  /* Fill information to Rx descriptors list: No received Packet */
-  dmarxdesclist->AppDescNbr = 0U;
-
-  return 0;
-}
-
-/**
-  * @brief  This function gets the buffer address of last received Packet.
-  * @note   Please insure to allocate the RxBuffer structure before calling this function
-  *         how to use example:
-  *           HAL_ETH_GetRxDataLength(heth, &Length);
-  *           BuffersNbr = (Length / heth->Init.RxBuffLen) + 1;
-  *           RxBuffer = (ETH_BufferTypeDef *)malloc(BuffersNbr * sizeof(ETH_BufferTypeDef));
-  *           HAL_ETH_GetRxDataBuffer(heth, RxBuffer);
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  RxBuffer: Pointer to a ETH_BufferTypeDef structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer)
-{
-  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
-  uint32_t descidx = dmarxdesclist->FirstAppDesc;
-  uint32_t index, accumulatedlen = 0, lastdesclen;
-  __IO const ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-  ETH_BufferTypeDef *rxbuff = RxBuffer;
-
-  if(rxbuff == NULL)
-  {
-    heth->ErrorCode = HAL_ETH_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-
-  if(dmarxdesclist->AppDescNbr == 0U)
-  {
-    if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
-    {
-      /* No data to be transferred to the application */
-      return HAL_ERROR;
-    }
-    else
-    {
-      descidx = dmarxdesclist->FirstAppDesc;
-      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-    }
-  }
-
-  /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */
-  for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++)
-  {
-    /* Get Address and length of the first buffer address */
-    rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
-    rxbuff->len =  heth->Init.RxBuffLen;
-
-    /* Check if the second buffer address of this descriptor is valid */
-    if(dmarxdesc->BackupAddr1 != 0U)
-    {
-      /* Point to next buffer */
-      rxbuff = rxbuff->next;
-      /* Get Address and length of the second buffer address */
-      rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
-      rxbuff->len =  heth->Init.RxBuffLen;
-    }
-    else
-    {
-      /* Nothing to do here */
-    }
-
-    /* get total length until this descriptor */
-    accumulatedlen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
-
-    /* Increment to next descriptor */
+    /* Increment current rx descriptor index */
     INCR_RX_DESC_INDEX(descidx, 1U);
-    dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
-    /* Point to next buffer */
-    rxbuff = rxbuff->next;
+    /* Get current descriptor address */
+    dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+    desccnt++;
   }
 
-  /* last descriptor data length */
-  lastdesclen = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL) - accumulatedlen;
-
-  /* Get Address of the first buffer address */
-  rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr0;
-
-  /* data is in only one buffer */
-  if(lastdesclen <= heth->Init.RxBuffLen)
+  heth->RxDescList.RxBuildDescCnt += desccnt;
+  if ((heth->RxDescList.RxBuildDescCnt) != 0U)
   {
-    rxbuff->len = lastdesclen;
-  }
-  /* data is in two buffers */
-  else if(dmarxdesc->BackupAddr1 != 0U)
-  {
-    /* Get the Length of the first buffer address */
-    rxbuff->len = heth->Init.RxBuffLen;
-    /* Point to next buffer */
-    rxbuff = rxbuff->next;
-    /* Get the Address the Length of the second buffer address */
-    rxbuff->buffer = (uint8_t *) dmarxdesc->BackupAddr1;
-    rxbuff->len =  lastdesclen - (heth->Init.RxBuffLen);
-  }
-  else /* Buffer 2 not valid*/
-  {
-    return HAL_ERROR;
+    /* Update Descriptors */
+    ETH_UpdateDescriptor(heth);
   }
 
-  return HAL_OK;
+  heth->RxDescList.RxDescIdx = descidx;
+
+  if (rxdataready == 1U)
+  {
+    /* Return received packet */
+    *pAppBuff = heth->RxDescList.pRxStart;
+    /* Reset first element */
+    heth->RxDescList.pRxStart = NULL;
+
+    return HAL_OK;
+  }
+
+  /* Packet not ready */
+  return HAL_ERROR;
 }
 
 /**
-  * @brief  This function gets the length of last received Packet.
+  * @brief  This function gives back Rx Desc of the last received Packet
+  *         to the DMA, so ETH DMA will be able to use these descriptors
+  *         to receive next Packets.
   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
-  * @param  Length: parameter to hold Rx packet length
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length)
-{
-  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
-  uint32_t descidx = dmarxdesclist->FirstAppDesc;
-  __IO const ETH_DMADescTypeDef *dmarxdesc;
-
-  if(dmarxdesclist->AppDescNbr == 0U)
-  {
-    if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
-    {
-      /* No data to be transferred to the application */
-      return HAL_ERROR;
-    }
-  }
-
-  /* Get index of last descriptor */
-  INCR_RX_DESC_INDEX(descidx, (dmarxdesclist->AppDescNbr - 1U));
-  /* Point to last descriptor */
-  dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
-  *Length = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_PL);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the Rx data info (Packet type, VLAN tag, Filters status, ...)
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @param  RxPacketInfo: parameter to hold info of received buffer
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo)
+static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth)
 {
-  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
-  uint32_t descidx = dmarxdesclist->FirstAppDesc;
-  __IO const ETH_DMADescTypeDef *dmarxdesc;
+  uint32_t descidx;
+  uint32_t tailidx;
+  uint32_t desccount;
+  ETH_DMADescTypeDef *dmarxdesc;
+  uint8_t *buff = NULL;
+  uint8_t allocStatus = 1U;
 
-  if(dmarxdesclist->AppDescNbr == 0U)
+  descidx = heth->RxDescList.RxBuildDescIdx;
+  dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+  desccount = heth->RxDescList.RxBuildDescCnt;
+
+  while ((desccount > 0U) && (allocStatus != 0U))
   {
-    if(HAL_ETH_IsRxDataAvailable(heth) == 0U)
+    /* Check if a buffer's attached the descriptor */
+    if (READ_REG(dmarxdesc->BackupAddr0) == 0U)
     {
-      /* No data to be transferred to the application */
-      return HAL_ERROR;
-    }
-  }
-
-  /* Get index of last descriptor */
-  INCR_RX_DESC_INDEX(descidx, ((dmarxdesclist->AppDescNbr) - 1U));
-  /* Point to last descriptor */
-  dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
-
-  if((dmarxdesc->DESC3 & ETH_DMARXNDESCWBF_ES) != (uint32_t)RESET)
-  {
-    RxPacketInfo->ErrorCode = READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_ERRORS_MASK);
-  }
-  else
-  {
-    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS0V) != 0U)
-    {
-
-      if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_LT) == ETH_DMARXNDESCWBF_LT_DVLAN)
+      /* Get a new buffer. */
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+      /*Call registered Allocate callback*/
+      heth->rxAllocateCallback(&buff);
+#else
+      /* Allocate callback */
+      HAL_ETH_RxAllocateCallback(&buff);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      if (buff == NULL)
       {
-        RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
-        RxPacketInfo->InnerVlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_IVT) >> 16;
+        allocStatus = 0U;
       }
       else
       {
-        RxPacketInfo->VlanTag = READ_BIT(dmarxdesc->DESC0, ETH_DMARXNDESCWBF_OVT);
+        WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff);
+        WRITE_REG(dmarxdesc->DESC0, (uint32_t)buff);
       }
     }
 
-    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS1V) != 0U)
+    if (allocStatus != 0U)
     {
-      /* Get Payload type */
-      RxPacketInfo->PayloadType =READ_BIT( dmarxdesc->DESC1, ETH_DMARXNDESCWBF_PT);
-      /* Get Header type */
-      RxPacketInfo->HeaderType = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPV4 | ETH_DMARXNDESCWBF_IPV6));
-      /* Get Checksum status */
-      RxPacketInfo->Checksum = READ_BIT(dmarxdesc->DESC1, (ETH_DMARXNDESCWBF_IPCE | ETH_DMARXNDESCWBF_IPCB | ETH_DMARXNDESCWBF_IPHE));
-    }
 
-    if(READ_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCWBF_RS2V) != 0U)
-    {
-      RxPacketInfo->MacFilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_HF | ETH_DMARXNDESCWBF_DAF | ETH_DMARXNDESCWBF_SAF | ETH_DMARXNDESCWBF_VF));
-      RxPacketInfo->L3FilterStatus = READ_BIT(dmarxdesc->DESC2,  (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM));
-      RxPacketInfo->L4FilterStatus = READ_BIT(dmarxdesc->DESC2, (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM));
+      if (heth->RxDescList.ItMode != 0U)
+      {
+        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC);
+      }
+      else
+      {
+        WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V);
+      }
+
+      /* Increment current rx descriptor index */
+      INCR_RX_DESC_INDEX(descidx, 1U);
+      /* Get current descriptor address */
+      dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx];
+      desccount--;
     }
   }
 
-  /* Get the segment count */
-  WRITE_REG(RxPacketInfo->SegmentCnt, dmarxdesclist->AppDescNbr);
+  if (heth->RxDescList.RxBuildDescCnt != desccount)
+  {
+    /* Set the tail pointer index */
+    tailidx = (ETH_RX_DESC_CNT + descidx - 1U) % ETH_RX_DESC_CNT;
+
+    /* DMB instruction to avoid race condition */
+    __DMB();
+
+    /* Set the Tail pointer address */
+    WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (tailidx))));
+
+    heth->RxDescList.RxBuildDescIdx = descidx;
+    heth->RxDescList.RxBuildDescCnt = desccount;
+  }
+}
+
+/**
+  * @brief  Register the Rx alloc callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  rxAllocateCallback: pointer to function to alloc buffer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback)
+{
+  if (rxAllocateCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+
+  /* Set function to allocate buffer */
+  heth->rxAllocateCallback = rxAllocateCallback;
 
   return HAL_OK;
 }
 
 /**
-* @brief  This function gives back Rx Desc of the last received Packet
-*         to the DMA, so ETH DMA will be able to use these descriptors
-*         to receive next Packets.
-*         It should be called after processing the received Packet.
-* @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-*         the configuration information for ETHERNET module
-* @retval HAL status.
-*/
-HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
+  * @brief  Unregister the Rx alloc callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth)
 {
-  ETH_RxDescListTypeDef *dmarxdesclist = &heth->RxDescList;
-  uint32_t descindex = dmarxdesclist->FirstAppDesc;
-  __IO ETH_DMADescTypeDef *dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
-  uint32_t totalappdescnbr = dmarxdesclist->AppDescNbr;
-  uint32_t descscan;
-
-  if(dmarxdesclist->AppDescNbr == 0U)
-  {
-    /* No Rx descriptors to build */
-    return HAL_ERROR;
-  }
-
-  if(dmarxdesclist->AppContextDesc != 0U)
-  {
-    /* A context descriptor is available */
-    totalappdescnbr += 1U;
-  }
-
-  for(descscan =0; descscan < totalappdescnbr; descscan++)
-  {
-    WRITE_REG(dmarxdesc->DESC0, dmarxdesc->BackupAddr0);
-    WRITE_REG(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF1V);
-
-    if (READ_REG(dmarxdesc->BackupAddr1) != 0U)
-    {
-      WRITE_REG(dmarxdesc->DESC2, dmarxdesc->BackupAddr1);
-      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_BUF2V);
-    }
-
-    SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_OWN);
-
-    if(dmarxdesclist->ItMode != 0U)
-    {
-      SET_BIT(dmarxdesc->DESC3, ETH_DMARXNDESCRF_IOC);
-    }
-
-    if(descscan < (totalappdescnbr - 1U))
-    {
-      /* Increment rx descriptor index */
-      INCR_RX_DESC_INDEX(descindex, 1U);
-      /* Get descriptor address */
-      dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descindex];
-    }
-  }
-
-  /* Set the Tail pointer address to the last rx descriptor hold by the app */
-  WRITE_REG(heth->Instance->DMACRDTPR, (uint32_t)dmarxdesc);
-
-  /* reset the Application desc number */
-  WRITE_REG(dmarxdesclist->AppDescNbr, 0);
-
-  /*  reset the application context descriptor */
-  WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+  /* Set function to allocate buffer */
+  heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback;
 
   return HAL_OK;
 }
 
+/**
+  * @brief  Rx Allocate callback.
+  * @param  buff: pointer to allocated buffer
+  * @retval None
+  */
+__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(buff);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxAllocateCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Rx Link callback.
+  * @param  pStart: pointer to packet start
+  * @param  pEnd: pointer to packet end
+  * @param  buff: pointer to received data
+  * @param  Length: received data length
+  * @retval None
+  */
+__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(pStart);
+  UNUSED(pEnd);
+  UNUSED(buff);
+  UNUSED(Length);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_RxLinkCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Set the Rx link data function.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  rxLinkCallback: pointer to function to link data
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback)
+{
+  if (rxLinkCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+
+  /* Set function to link data */
+  heth->rxLinkCallback = rxLinkCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Rx link callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->rxLinkCallback = HAL_ETH_RxLinkCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the error state of the last received packet.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  pErrorCode: pointer to uint32_t to hold the error code
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode)
+{
+  /* Get error bits. */
+  *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXNDESCWBF_ERRORS_MASK);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the Tx free function.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  txFreeCallback: pointer to function to release the packet
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback)
+{
+  if (txFreeCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+
+  /* Set function to free transmmitted packet */
+  heth->txFreeCallback = txFreeCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Tx free callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->txFreeCallback = HAL_ETH_TxFreeCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Tx Free callback.
+  * @param  buff: pointer to buffer to free
+  * @retval None
+  */
+__weak void HAL_ETH_TxFreeCallback(uint32_t *buff)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(buff);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxFreeCallback could be implemented in the user file
+  */
+}
+
+/**
+  * @brief  Release transmitted Tx packets.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth)
+{
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+  uint32_t numOfBuf =  dmatxdesclist->BuffersInUse;
+  uint32_t idx =       dmatxdesclist->releaseIndex;
+  uint8_t pktTxStatus = 1U;
+  uint8_t pktInUse;
+#ifdef HAL_ETH_USE_PTP
+  ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp;
+#endif /* HAL_ETH_USE_PTP */
+
+  /* Loop through buffers in use.  */
+  while ((numOfBuf != 0U) && (pktTxStatus != 0U))
+  {
+    pktInUse = 1U;
+    numOfBuf--;
+    /* If no packet, just examine the next packet.  */
+    if (dmatxdesclist->PacketAddress[idx] == NULL)
+    {
+      /* No packet in use, skip to next.  */
+      INCR_TX_DESC_INDEX(idx, 1U);
+      pktInUse = 0U;
+    }
+
+    if (pktInUse != 0U)
+    {
+      /* Determine if the packet has been transmitted.  */
+      if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U)
+      {
+#ifdef HAL_ETH_USE_PTP
+
+        /* Disable Ptp transmission */
+        CLEAR_BIT(heth->Init.TxDesc[idx].DESC3, (0x40000000U));
+
+        if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD)
+            && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS))
+        {
+          /* Get timestamp low */
+          timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0;
+          /* Get timestamp high */
+          timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1;
+        }
+        else
+        {
+          timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX;
+        }
+#endif /* HAL_ETH_USE_PTP */
+
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+        /*Call registered callbacks*/
+#ifdef HAL_ETH_USE_PTP
+        /* Handle Ptp  */
+        if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
+        {
+          heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+        }
+#endif  /* HAL_ETH_USE_PTP */
+        /* Release the packet.  */
+        heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]);
+#else
+        /* Call callbacks */
+#ifdef HAL_ETH_USE_PTP
+        /* Handle Ptp  */
+        if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX)
+        {
+          HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp);
+        }
+#endif  /* HAL_ETH_USE_PTP */
+        /* Release the packet.  */
+        HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+        /* Clear the entry in the in-use array.  */
+        dmatxdesclist->PacketAddress[idx] = NULL;
+
+        /* Update the transmit relesae index and number of buffers in use.  */
+        INCR_TX_DESC_INDEX(idx, 1U);
+        dmatxdesclist->BuffersInUse = numOfBuf;
+        dmatxdesclist->releaseIndex = idx;
+      }
+      else
+      {
+        /* Get out of the loop!  */
+        pktTxStatus = 0U;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  Set the Ethernet PTP configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
+  *         the configuration information for PTP
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
+{
+  uint32_t tmpTSCR;
+  ETH_TimeTypeDef time;
+
+  if (ptpconfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  tmpTSCR = ptpconfig->Timestamp |
+            ((uint32_t)ptpconfig->TimestampUpdate << ETH_MACTSCR_TSUPDT_Pos) |
+            ((uint32_t)ptpconfig->TimestampAll << ETH_MACTSCR_TSENALL_Pos) |
+            ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_MACTSCR_TSCTRLSSR_Pos) |
+            ((uint32_t)ptpconfig->TimestampV2 << ETH_MACTSCR_TSVER2ENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampEthernet << ETH_MACTSCR_TSIPENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampIPv6 << ETH_MACTSCR_TSIPV6ENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampIPv4 << ETH_MACTSCR_TSIPV4ENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampEvent << ETH_MACTSCR_TSEVNTENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampMaster << ETH_MACTSCR_TSMSTRENA_Pos) |
+            ((uint32_t)ptpconfig->TimestampSnapshots << ETH_MACTSCR_SNAPTYPSEL_Pos) |
+            ((uint32_t)ptpconfig->TimestampFilter << ETH_MACTSCR_TSENMACADDR_Pos) |
+            ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_MACTSCR_CSC_Pos) |
+            ((uint32_t)ptpconfig->TimestampStatusMode << ETH_MACTSCR_TXTSSTSM_Pos);
+
+  /* Write to MACTSCR */
+  MODIFY_REG(heth->Instance->MACTSCR, ETH_MACTSCR_MASK, tmpTSCR);
+
+  /* Enable Timestamp */
+  SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
+  WRITE_REG(heth->Instance->MACSSIR, ptpconfig->TimestampSubsecondInc);
+  WRITE_REG(heth->Instance->MACTSAR, ptpconfig->TimestampAddend);
+
+  /* Enable Timestamp */
+  if (ptpconfig->TimestampAddendUpdate == ENABLE)
+  {
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSADDREG);
+    while ((heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG) != 0)
+    {
+
+    }
+  }
+
+  /* Ptp Init */
+  SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSINIT);
+
+  /* Set PTP Configuration done */
+  heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED;
+
+  /* Set Seconds */
+  time.Seconds = heth->Instance->MACSTSR;
+  /* Set NanoSeconds */
+  time.NanoSeconds = heth->Instance->MACSTNR;
+
+  HAL_ETH_PTP_SetTime(heth, &time);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the Ethernet PTP configuration.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains
+  *         the configuration information for PTP
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig)
+{
+  if (ptpconfig == NULL)
+  {
+    return HAL_ERROR;
+  }
+  ptpconfig->Timestamp = READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSENA);
+  ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->MACTSCR,
+                                          ETH_MACTSCR_TSCFUPDT) >> ETH_MACTSCR_TSUPDT_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->MACTSCR,
+                                       ETH_MACTSCR_TSENALL) >> ETH_MACTSCR_TSENALL_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->MACTSCR,
+                                                ETH_MACTSCR_TSCTRLSSR) >> ETH_MACTSCR_TSCTRLSSR_Pos) > 0U)
+                                     ? ENABLE : DISABLE;
+  ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->MACTSCR,
+                                      ETH_MACTSCR_TSVER2ENA) >> ETH_MACTSCR_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->MACTSCR,
+                                            ETH_MACTSCR_TSIPENA) >> ETH_MACTSCR_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->MACTSCR,
+                                        ETH_MACTSCR_TSIPV6ENA) >> ETH_MACTSCR_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->MACTSCR,
+                                        ETH_MACTSCR_TSIPV4ENA) >> ETH_MACTSCR_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->MACTSCR,
+                                         ETH_MACTSCR_TSEVNTENA) >> ETH_MACTSCR_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->MACTSCR,
+                                          ETH_MACTSCR_TSMSTRENA) >> ETH_MACTSCR_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampSnapshots = ((READ_BIT(heth->Instance->MACTSCR,
+                                             ETH_MACTSCR_SNAPTYPSEL) >> ETH_MACTSCR_SNAPTYPSEL_Pos) > 0U)
+                                  ? ENABLE : DISABLE;
+  ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->MACTSCR,
+                                          ETH_MACTSCR_TSENMACADDR) >> ETH_MACTSCR_TSENMACADDR_Pos) > 0U)
+                               ? ENABLE : DISABLE;
+  ptpconfig->TimestampChecksumCorrection = ((READ_BIT(heth->Instance->MACTSCR,
+                                                      ETH_MACTSCR_CSC) >> ETH_MACTSCR_CSC_Pos) > 0U) ? ENABLE : DISABLE;
+  ptpconfig->TimestampStatusMode = ((READ_BIT(heth->Instance->MACTSCR,
+                                              ETH_MACTSCR_TXTSSTSM) >> ETH_MACTSCR_TXTSSTSM_Pos) > 0U)
+                                   ? ENABLE : DISABLE;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Seconds and Nanoseconds for the Ethernet PTP registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  time: pointer to a ETH_TimeTypeDef structure that contains
+  *         time to set
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Set Seconds */
+    heth->Instance->MACSTSUR = time->Seconds;
+
+    /* Set NanoSeconds */
+    heth->Instance->MACSTNUR = time->NanoSeconds;
+
+    /* the system time is updated */
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get Seconds and Nanoseconds for the Ethernet PTP registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  time: pointer to a ETH_TimeTypeDef structure that contains
+  *         time to get
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Get Seconds */
+    time->Seconds = heth->Instance->MACSTSR;
+    /* Get NanoSeconds */
+    time->NanoSeconds = heth->Instance->MACSTNR;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Update time for the Ethernet PTP registers.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains
+  *         the time update information
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+                                            ETH_TimeTypeDef *timeoffset)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    if (ptpoffsettype ==  HAL_ETH_PTP_NEGATIVE_UPDATE)
+    {
+      /* Set Seconds update */
+      heth->Instance->MACSTSUR = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U;
+
+      if (READ_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSCTRLSSR) == ETH_MACTSCR_TSCTRLSSR)
+      {
+        /* Set nanoSeconds update */
+        heth->Instance->MACSTNUR = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds;
+      }
+      else
+      {
+        /* Set nanoSeconds update */
+        heth->Instance->MACSTNUR = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U;
+      }
+    }
+    else
+    {
+      /* Set Seconds update */
+      heth->Instance->MACSTSUR = timeoffset->Seconds;
+      /* Set nanoSeconds update */
+      heth->Instance->MACSTNUR = timeoffset->NanoSeconds;
+    }
+
+    SET_BIT(heth->Instance->MACTSCR, ETH_MACTSCR_TSUPDT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Insert Timestamp in transmission.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth)
+{
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+  uint32_t descidx = dmatxdesclist->CurTxDesc;
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
+
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Enable Time Stamp transmission */
+    SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_TTSE);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get transmission timestamp.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
+  *         transmission timestamp
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
+{
+  ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
+  uint32_t idx =       dmatxdesclist->releaseIndex;
+  ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx];
+
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Get timestamp low */
+    timestamp->TimeStampLow = dmatxdesc->DESC0;
+    /* Get timestamp high */
+    timestamp->TimeStampHigh = dmatxdesc->DESC1;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Get receive timestamp.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains
+  *         receive timestamp
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp)
+{
+  if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED)
+  {
+    /* Get timestamp low */
+    timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow;
+    /* Get timestamp high */
+    timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Register the Tx Ptp callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @param  txPtpCallback: Function to handle Ptp transmission
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback)
+{
+  if (txPtpCallback == NULL)
+  {
+    /* No buffer to save */
+    return HAL_ERROR;
+  }
+  /* Set Function to handle Tx Ptp */
+  heth->txPtpCallback = txPtpCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Unregister the Tx Ptp callback.
+  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
+  *         the configuration information for ETHERNET module
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth)
+{
+  /* Set function to allocate buffer */
+  heth->txPtpCallback = HAL_ETH_TxPtpCallback;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Tx Ptp callback.
+  * @param  buff: pointer to application buffer
+  * @param  timestamp: pointer to ETH_TimeStampTypeDef structure that contains
+  *         transmission timestamp
+  * @retval None
+  */
+__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(buff);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+  the HAL_ETH_TxPtpCallback could be implemented in the user file
+  */
+}
+#endif  /* HAL_ETH_USE_PTP */
 
 /**
   * @brief  This function handles ETH interrupt request.
@@ -1474,105 +1857,102 @@ HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth)
   */
 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
 {
+  uint32_t mac_flag = READ_REG(heth->Instance->MACISR);
+  uint32_t dma_flag = READ_REG(heth->Instance->DMACSR);
+  uint32_t dma_itsource = READ_REG(heth->Instance->DMACIER);
+  uint32_t exti_d1_flag = READ_REG(EXTI_D1->PR3);
+#if defined(DUAL_CORE)
+  uint32_t exti_d2_flag = READ_REG(EXTI_D2->PR3);
+#endif /* DUAL_CORE */
+
   /* Packet received */
-  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_RI))
+  if (((dma_flag & ETH_DMACSR_RI) != 0U) && ((dma_itsource & ETH_DMACIER_RIE) != 0U))
   {
-    if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
-    {
+    /* Clear the Eth DMA Rx IT pending bits */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
 
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /*Call registered Receive complete callback*/
-      heth->RxCpltCallback(heth);
+    /*Call registered Receive complete callback*/
+    heth->RxCpltCallback(heth);
 #else
-      /* Receive complete callback */
-      HAL_ETH_RxCpltCallback(heth);
+    /* Receive complete callback */
+    HAL_ETH_RxCpltCallback(heth);
 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
-      /* Clear the Eth DMA Rx IT pending bits */
-      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
-    }
   }
 
   /* Packet transmitted */
-  if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_TI))
+  if (((dma_flag & ETH_DMACSR_TI) != 0U) && ((dma_itsource & ETH_DMACIER_TIE) != 0U))
   {
-    if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_TIE))
-    {
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-        /*Call registered Transmit complete callback*/
-        heth->TxCpltCallback(heth);
-#else
-      /* Transfer complete callback */
-      HAL_ETH_TxCpltCallback(heth);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+    /* Clear the Eth DMA Tx IT pending bits */
+    __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
 
-      /* Clear the Eth DMA Tx IT pending bits */
-      __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_TI | ETH_DMACSR_NIS);
-    }
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /*Call registered Transmit complete callback*/
+    heth->TxCpltCallback(heth);
+#else
+    /* Transfer complete callback */
+    HAL_ETH_TxCpltCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
   }
 
-
   /* ETH DMA Error */
-  if(__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_AIS))
+  if (((dma_flag & ETH_DMACSR_AIS) != 0U) && ((dma_itsource & ETH_DMACIER_AIE) != 0U))
   {
-    if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_AIE))
+    heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+    /* if fatal bus error occurred */
+    if ((dma_flag & ETH_DMACSR_FBE) != 0U)
     {
-      heth->ErrorCode |= HAL_ETH_ERROR_DMA;
+      /* Get DMA error code  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
 
-      /* if fatal bus error occurred */
-      if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE))
-      {
-        /* Get DMA error code  */
-        heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_FBE | ETH_DMACSR_TPS | ETH_DMACSR_RPS));
-
-        /* Disable all interrupts */
-        __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
-
-        /* Set HAL state to ERROR */
-        heth->gState = HAL_ETH_STATE_ERROR;
-      }
-      else
-      {
-        /* Get DMA error status  */
-       heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
-                                                       ETH_DMACSR_RBU | ETH_DMACSR_AIS));
-
-        /* Clear the interrupt summary flag */
-        __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
-                                    ETH_DMACSR_RBU | ETH_DMACSR_AIS));
-      }
-#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /* Call registered DMA Error callback*/
-      heth->DMAErrorCallback(heth);
-#else
-      /* Ethernet DMA Error callback */
-      HAL_ETH_DMAErrorCallback(heth);
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+      /* Disable all interrupts */
+      __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMACIER_NIE | ETH_DMACIER_AIE);
 
+      /* Set HAL state to ERROR */
+      heth->gState = HAL_ETH_STATE_ERROR;
     }
+    else
+    {
+      /* Get DMA error status  */
+      heth->DMAErrorCode = READ_BIT(heth->Instance->DMACSR, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+                                                             ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+
+      /* Clear the interrupt summary flag */
+      __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMACSR_CDE | ETH_DMACSR_ETI | ETH_DMACSR_RWT |
+                                    ETH_DMACSR_RBU | ETH_DMACSR_AIS));
+    }
+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
+#else
+    /* Ethernet DMA Error callback */
+    HAL_ETH_ErrorCallback(heth);
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
   }
 
   /* ETH MAC Error IT */
-  if(__HAL_ETH_MAC_GET_IT(heth, (ETH_MACIER_RXSTSIE | ETH_MACIER_TXSTSIE)))
+  if (((mac_flag & ETH_MACIER_RXSTSIE) == ETH_MACIER_RXSTSIE) || \
+      ((mac_flag & ETH_MACIER_TXSTSIE) == ETH_MACIER_TXSTSIE))
   {
+    heth->ErrorCode |= HAL_ETH_ERROR_MAC;
+
     /* Get MAC Rx Tx status and clear Status register pending bit */
     heth->MACErrorCode = READ_REG(heth->Instance->MACRXTXSR);
 
     heth->gState = HAL_ETH_STATE_ERROR;
 
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-    /* Call registered MAC Error callback*/
-    heth->DMAErrorCallback(heth);
+    /* Call registered Error callback*/
+    heth->ErrorCallback(heth);
 #else
-    /* Ethernet MAC Error callback */
-    HAL_ETH_MACErrorCallback(heth);
+    /* Ethernet Error callback */
+    HAL_ETH_ErrorCallback(heth);
 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
-
     heth->MACErrorCode = (uint32_t)(0x0U);
   }
 
   /* ETH PMT IT */
-  if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT))
+  if ((mac_flag & ETH_MAC_PMT_IT) != 0U)
   {
     /* Get MAC Wake-up source and clear the status register pending bit */
     heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPCSR, (ETH_MACPCSR_RWKPRCVD | ETH_MACPCSR_MGKPRCVD));
@@ -1589,10 +1969,10 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
   }
 
   /* ETH EEE IT */
-  if(__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_LPI_IT))
+  if ((mac_flag & ETH_MAC_LPI_IT) != 0U)
   {
     /* Get MAC LPI interrupt source and clear the status register pending bit */
-    heth->MACLPIEvent = READ_BIT(heth->Instance->MACPCSR, 0x0000000FU);
+    heth->MACLPIEvent = READ_BIT(heth->Instance->MACLCSR, 0x0000000FU);
 
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
     /* Call registered EEE callback*/
@@ -1609,7 +1989,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
   if (HAL_GetCurrentCPUID() == CM7_CPUID)
   {
     /* check ETH WAKEUP exti flag */
-    if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+    if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
     {
       /* Clear ETH WAKEUP Exti pending bit */
       __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -1619,13 +1999,13 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
 #else
       /* ETH WAKEUP callback */
       HAL_ETH_WakeUpCallback(heth);
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
     }
   }
   else
   {
     /* check ETH WAKEUP exti flag */
-    if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+    if ((exti_d2_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
     {
       /* Clear ETH WAKEUP Exti pending bit */
       __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@@ -1635,24 +2015,24 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
 #else
       /* ETH WAKEUP callback */
       HAL_ETH_WakeUpCallback(heth);
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
     }
   }
-#else
+#else /* DUAL_CORE not defined */
   /* check ETH WAKEUP exti flag */
-  if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
+  if ((exti_d1_flag & ETH_WAKEUP_EXTI_LINE) != 0U)
   {
     /* Clear ETH WAKEUP Exti pending bit */
     __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-      /* Call registered WakeUp callback*/
-      heth->WakeUpCallback(heth);
+    /* Call registered WakeUp callback*/
+    heth->WakeUpCallback(heth);
 #else
-      /* ETH WAKEUP callback */
-      HAL_ETH_WakeUpCallback(heth);
-#endif
+    /* ETH WAKEUP callback */
+    HAL_ETH_WakeUpCallback(heth);
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
   }
-#endif
+#endif /* DUAL_CORE */
 }
 
 /**
@@ -1686,32 +2066,17 @@ __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
 }
 
 /**
-  * @brief  Ethernet DMA transfer error callbacks
+  * @brief  Ethernet transfer error callbacks
   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval None
   */
-__weak void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth)
+__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(heth);
   /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_DMAErrorCallback could be implemented in the user file
-  */
-}
-
-/**
-* @brief  Ethernet MAC transfer error callbacks
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-__weak void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(heth);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-  the HAL_ETH_MACErrorCallback could be implemented in the user file
+  the HAL_ETH_ErrorCallback could be implemented in the user file
   */
 }
 
@@ -1769,12 +2134,14 @@ __weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth)
   * @param pRegValue: parameter to hold read value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue)
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                          uint32_t *pRegValue)
 {
-  uint32_t tmpreg, tickstart;
+  uint32_t tickstart;
+  uint32_t tmpreg;
 
   /* Check for the Busy flag */
-  if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
   {
     return HAL_ERROR;
   }
@@ -1788,7 +2155,7 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
      - Set the read mode
      - Set the MII Busy bit */
 
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
   MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
   MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_RD);
   SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
@@ -1799,9 +2166,9 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
   tickstart = HAL_GetTick();
 
   /* Wait for the Busy flag */
-  while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
   {
-    if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
     {
       return HAL_ERROR;
     }
@@ -1813,7 +2180,6 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
   return HAL_OK;
 }
 
-
 /**
   * @brief  Writes to a PHY register.
   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
@@ -1823,12 +2189,14 @@ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYA
   * @param  RegValue: the value to write
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue)
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                           uint32_t RegValue)
 {
-  uint32_t tmpreg, tickstart;
+  uint32_t tickstart;
+  uint32_t tmpreg;
 
   /* Check for the Busy flag */
-  if(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != 0U)
+  if (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) != (uint32_t)RESET)
   {
     return HAL_ERROR;
   }
@@ -1842,12 +2210,11 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
      - Set the write mode
      - Set the MII Busy bit */
 
-  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr <<21));
+  MODIFY_REG(tmpreg, ETH_MACMDIOAR_PA, (PHYAddr << 21));
   MODIFY_REG(tmpreg, ETH_MACMDIOAR_RDA, (PHYReg << 16));
   MODIFY_REG(tmpreg, ETH_MACMDIOAR_MOC, ETH_MACMDIOAR_MOC_WR);
   SET_BIT(tmpreg, ETH_MACMDIOAR_MB);
 
-
   /* Give the value to the MII data register */
   WRITE_REG(ETH->MACMDIODR, (uint16_t)RegValue);
 
@@ -1857,9 +2224,9 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
   tickstart = HAL_GetTick();
 
   /* Wait for the Busy flag */
-  while(READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
+  while (READ_BIT(heth->Instance->MACMDIOAR, ETH_MACMDIOAR_MB) > 0U)
   {
-    if(((HAL_GetTick() - tickstart ) > ETH_MDIO_BUS_TIMEOUT))
+    if (((HAL_GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT))
     {
       return HAL_ERROR;
     }
@@ -1894,7 +2261,7 @@ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHY
   *         the configuration of the MAC.
   * @retval HAL Status
   */
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf)
 {
   if (macconf == NULL)
   {
@@ -1903,22 +2270,25 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
 
   /* Get MAC parameters */
   macconf->PreambleLength = READ_BIT(heth->Instance->MACCR, ETH_MACCR_PRELEN);
-  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC)>> 4) > 0U) ? ENABLE : DISABLE;
+  macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE;
   macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL);
   macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DR) >> 8) == 0U) ? ENABLE : DISABLE;
-  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U) ? ENABLE : DISABLE;
+  macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DCRS) >> 9) > 0U)
+                                        ? ENABLE : DISABLE;
   macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DO) >> 10) == 0U) ? ENABLE : DISABLE;
-  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
+  macconf->CarrierSenseBeforeTransmit = ((READ_BIT(heth->Instance->MACCR,
+                                                   ETH_MACCR_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE;
   macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE;
   macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM);
   macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES);
   macconf->JumboPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JE) >> 16) > 0U) ? ENABLE : DISABLE;
-  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >>17) == 0U) ? ENABLE : DISABLE;
-  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >>19) == 0U) ? ENABLE : DISABLE;
+  macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 17) == 0U) ? ENABLE : DISABLE;
+  macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 19) == 0U) ? ENABLE : DISABLE;
   macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ACS) >> 20) > 0U) ? ENABLE : DISABLE;
   macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CST) >> 21) > 0U) ? ENABLE : DISABLE;
   macconf->Support2KPacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_S2KP) >> 22) > 0U) ? ENABLE : DISABLE;
-  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
+  macconf->GiantPacketSizeLimitControl = ((READ_BIT(heth->Instance->MACCR,
+                                                    ETH_MACCR_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE;
   macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPG);
   macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPC) >> 27) > 0U) ? ENABLE : DISABLE;
   macconf->SourceAddrControl = READ_BIT(heth->Instance->MACCR, ETH_MACCR_SARC);
@@ -1926,11 +2296,12 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
   macconf->GiantPacketSizeLimit = READ_BIT(heth->Instance->MACECR, ETH_MACECR_GPSL);
   macconf->CRCCheckingRxPackets = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_DCRCC) >> 16) == 0U) ? ENABLE : DISABLE;
   macconf->SlowProtocolDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_SPEN) >> 17) > 0U) ? ENABLE : DISABLE;
-  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
-  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE;
+  macconf->UnicastSlowProtocolPacketDetect = ((READ_BIT(heth->Instance->MACECR,
+                                                        ETH_MACECR_USP) >> 18) > 0U) ? ENABLE : DISABLE;
+  macconf->ExtendedInterPacketGap = ((READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPGEN) >> 24) > 0U)
+                                    ? ENABLE : DISABLE;
   macconf->ExtendedInterPacketGapVal = READ_BIT(heth->Instance->MACECR, ETH_MACECR_EIPG) >> 25;
 
-
   macconf->ProgrammableWatchdog = ((READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_PWE) >> 8) > 0U) ? ENABLE : DISABLE;
   macconf->WatchdogTimeout = READ_BIT(heth->Instance->MACWTR, ETH_MACWTR_WTO);
 
@@ -1938,17 +2309,18 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
   macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE;
   macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PLT);
   macconf->PauseTime = (READ_BIT(heth->Instance->MACTFCR, ETH_MACTFCR_PT) >> 16);
-
-
   macconf->ReceiveFlowControl = (READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_RFE) > 0U) ? ENABLE : DISABLE;
-  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U) ? ENABLE : DISABLE;
+  macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACRFCR, ETH_MACRFCR_UP) >> 1) > 0U)
+                                      ? ENABLE : DISABLE;
 
   macconf->TransmitQueueMode = READ_BIT(heth->Instance->MTLTQOMR, (ETH_MTLTQOMR_TTC | ETH_MTLTQOMR_TSF));
 
   macconf->ReceiveQueueMode = READ_BIT(heth->Instance->MTLRQOMR, (ETH_MTLRQOMR_RTC | ETH_MTLRQOMR_RSF));
-  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
+  macconf->ForwardRxUndersizedGoodPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+                                                      ETH_MTLRQOMR_FUP) >> 3) > 0U) ? ENABLE : DISABLE;
   macconf->ForwardRxErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_FEP) >> 4) > 0U) ? ENABLE : DISABLE;
-  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
+  macconf->DropTCPIPChecksumErrorPacket = ((READ_BIT(heth->Instance->MTLRQOMR,
+                                                     ETH_MTLRQOMR_DISTCPEF) >> 6) == 0U) ? ENABLE : DISABLE;
 
   return HAL_OK;
 }
@@ -1961,7 +2333,7 @@ HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTyp
   *         the configuration of the ETH DMA.
   * @retval HAL Status
   */
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf)
 {
   if (dmaconf == NULL)
   {
@@ -1970,11 +2342,11 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
 
   dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_AAL) >> 12) > 0U) ? ENABLE : DISABLE;
   dmaconf->BurstMode = READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_FB | ETH_DMASBMR_MB);
-  dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB)>> 15) > 0U) ? ENABLE : DISABLE;
+  dmaconf->RebuildINCRxBurst = ((READ_BIT(heth->Instance->DMASBMR, ETH_DMASBMR_RB) >> 15) > 0U) ? ENABLE : DISABLE;
 
-  dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR |ETH_DMAMR_PR | ETH_DMAMR_DA));
+  dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMAMR, (ETH_DMAMR_TXPR | ETH_DMAMR_PR | ETH_DMAMR_DA));
 
-  dmaconf->PBLx8Mode =  ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL)>> 16) > 0U) ? ENABLE : DISABLE;
+  dmaconf->PBLx8Mode = ((READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_8PBL) >> 16) > 0U) ? ENABLE : DISABLE;
   dmaconf->MaximumSegmentSize = READ_BIT(heth->Instance->DMACCR, ETH_DMACCR_MSS);
 
   dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMACRCR,  ETH_DMACRCR_RPF) >> 31) > 0U) ? ENABLE : DISABLE;
@@ -1997,12 +2369,12 @@ HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTyp
   */
 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
 {
-  if(macconf == NULL)
+  if (macconf == NULL)
   {
     return HAL_ERROR;
   }
 
-  if(heth->RxState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_READY)
   {
     ETH_SetMACConfig(heth, macconf);
 
@@ -2024,12 +2396,12 @@ HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTy
   */
 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
 {
-  if(dmaconf == NULL)
+  if (dmaconf == NULL)
   {
     return HAL_ERROR;
   }
 
-  if(heth->RxState == HAL_ETH_STATE_READY)
+  if (heth->gState == HAL_ETH_STATE_READY)
   {
     ETH_SetDMAConfig(heth, dmaconf);
 
@@ -2049,43 +2421,49 @@ HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTy
   */
 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
 {
-  uint32_t tmpreg, hclk;
+  uint32_t hclk;
+  uint32_t tmpreg;
 
   /* Get the ETHERNET MACMDIOAR value */
   tmpreg = (heth->Instance)->MACMDIOAR;
 
-	/* Clear CSR Clock Range bits */
+  /* Clear CSR Clock Range bits */
   tmpreg &= ~ETH_MACMDIOAR_CR;
 
-	/* Get hclk frequency value */
+  /* Get hclk frequency value */
   hclk = HAL_RCC_GetHCLKFreq();
 
-	/* Set CR bits depending on hclk value */
-  if((hclk >= 20000000U)&&(hclk < 35000000U))
+  /* Set CR bits depending on hclk value */
+  if (hclk < 35000000U)
   {
-    /* CSR Clock Range between 20-35 MHz */
+    /* CSR Clock Range between 0-35 MHz */
     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
   }
-  else if((hclk >= 35000000U)&&(hclk < 60000000U))
+  else if (hclk < 60000000U)
   {
     /* CSR Clock Range between 35-60 MHz */
     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
   }
-  else if((hclk >= 60000000U)&&(hclk < 100000000U))
+  else if (hclk < 100000000U)
   {
     /* CSR Clock Range between 60-100 MHz */
     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
   }
-  else if((hclk >= 100000000U)&&(hclk < 150000000U))
+  else if (hclk < 150000000U)
   {
     /* CSR Clock Range between 100-150 MHz */
     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
   }
-  else /* (hclk >= 150000000)&&(hclk <= 200000000) */
+  else if (hclk < 250000000U)
   {
-    /* CSR Clock Range between 150-200 MHz */
+    /* CSR Clock Range between 150-250 MHz */
     tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
   }
+  else /* (hclk >= 250000000U) */
+  {
+    /* CSR Clock >= 250 MHz */
+    tmpreg |= (uint32_t)(ETH_MACMDIOAR_CR_DIV124);
+  }
 
   /* Configure the CSR Clock Range */
   (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
@@ -2099,26 +2477,26 @@ void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth)
   *         the configuration of the ETH MAC filters.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig)
 {
   uint32_t filterconfig;
 
-  if(pFilterConfig == NULL)
+  if (pFilterConfig == NULL)
   {
     return HAL_ERROR;
   }
 
   filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode |
                   ((uint32_t)pFilterConfig->HashUnicast << 1) |
-                    ((uint32_t)pFilterConfig->HashMulticast << 2)  |
-                      ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
-                        ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
-                          ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
-                            ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
-                              ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
-                                ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
-                                  ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
-                                    pFilterConfig->ControlPacketsFilter);
+                  ((uint32_t)pFilterConfig->HashMulticast << 2)  |
+                  ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) |
+                  ((uint32_t)pFilterConfig->PassAllMulticast << 4) |
+                  ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) |
+                  ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) |
+                  ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) |
+                  ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) |
+                  ((uint32_t)pFilterConfig->ReceiveAllMode << 31) |
+                  pFilterConfig->ControlPacketsFilter);
 
   MODIFY_REG(heth->Instance->MACPFR, ETH_MACPFR_MASK, filterconfig);
 
@@ -2133,9 +2511,9 @@ HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
   *         the configuration of the ETH MAC filters.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig)
 {
-  if(pFilterConfig == NULL)
+  if (pFilterConfig == NULL)
   {
     return HAL_ERROR;
   }
@@ -2143,13 +2521,16 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
   pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PR)) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HUC) >> 1) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HMC) >> 2) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
+                                                       ETH_MACPFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PM) >> 4) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_DBF) >> 5) == 0U) ? ENABLE : DISABLE;
   pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_PCF);
-  pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACPFR,
+                                                      ETH_MACPFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE;
   pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE;
-  pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U) ? ENABLE : DISABLE;
+  pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_HPF) >> 10) > 0U)
+                                       ? ENABLE : DISABLE;
   pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACPFR, ETH_MACPFR_RA) >> 31) > 0U) ? ENABLE : DISABLE;
 
   return HAL_OK;
@@ -2167,19 +2548,21 @@ HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFil
   * @param  pMACAddr: Pointer to MAC address buffer data (6 bytes)
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr)
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
+                                                const uint8_t *pMACAddr)
 {
-  uint32_t macaddrhr, macaddrlr;
+  uint32_t macaddrlr;
+  uint32_t macaddrhr;
 
-  if(pMACAddr == NULL)
+  if (pMACAddr == NULL)
   {
     return HAL_ERROR;
   }
 
   /* Get mac addr high reg offset */
-  macaddrhr = ((uint32_t)&(heth->Instance->MACA0HR) + AddrNbr);
+  macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr);
   /* Get mac addr low reg offset */
-  macaddrlr = ((uint32_t)&(heth->Instance->MACA0LR) + AddrNbr);
+  macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr);
 
   /* Set MAC addr bits 32 to 47 */
   (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]);
@@ -2187,7 +2570,7 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_
   (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) |
                                    ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]);
 
-   /* Enable address and set source address bit */
+  /* Enable address and set source address bit */
   (*(__IO uint32_t *)macaddrhr) |= (ETH_MACAHR_SA | ETH_MACAHR_AE);
 
   return HAL_OK;
@@ -2203,7 +2586,7 @@ HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_
   */
 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable)
 {
-  if(pHashTable == NULL)
+  if (pHashTable == NULL)
   {
     return HAL_ERROR;
   }
@@ -2225,14 +2608,14 @@ HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashT
   */
 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier)
 {
-  if(ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
+  if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT)
   {
-    MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL , VLANIdentifier);
+    MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL, VLANIdentifier);
     CLEAR_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
   }
   else
   {
-    MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID , VLANIdentifier);
+    MODIFY_REG(heth->Instance->MACVTR, ETH_MACVTR_VL_VID, VLANIdentifier);
     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_ETV);
   }
 }
@@ -2245,15 +2628,15 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit
   *         that contains the Power Down configuration
   * @retval None.
   */
-void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig)
+void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig)
 {
   uint32_t powerdownconfig;
 
   powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) |
                      ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) |
-                       ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
-                         ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
-                           ETH_MACPCSR_PWRDWN);
+                     ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) |
+                     ((uint32_t)pPowerDownConfig->WakeUpForward << 10) |
+                     ETH_MACPCSR_PWRDWN);
 
   /* Enable PMT interrupt */
   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_PMTIE);
@@ -2270,9 +2653,10 @@ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigType
 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth)
 {
   /* clear wake up sources */
-  CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST | ETH_MACPCSR_RWKPFE);
+  CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKPKTEN | ETH_MACPCSR_MGKPKTEN | ETH_MACPCSR_GLBLUCAST |
+            ETH_MACPCSR_RWKPFE);
 
-  if(READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != 0U)
+  if (READ_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN) != (uint32_t)RESET)
   {
     /* Exit power down mode */
     CLEAR_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_PWRDWN);
@@ -2294,7 +2678,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
 {
   uint32_t regindex;
 
-  if(pFilter == NULL)
+  if (pFilter == NULL)
   {
     return HAL_ERROR;
   }
@@ -2303,7 +2687,7 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
   SET_BIT(heth->Instance->MACPCSR, ETH_MACPCSR_RWKFILTRST);
 
   /* Wake up packet filter config */
-  for(regindex = 0; regindex < Count; regindex++)
+  for (regindex = 0; regindex < Count; regindex++)
   {
     /* Write filter regs */
     WRITE_REG(heth->Instance->MACRWKPFR, pFilter[regindex]);
@@ -2339,15 +2723,9 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
   *         the configuration information for ETHERNET module
   * @retval HAL state
   */
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
+HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth)
 {
-  HAL_ETH_StateTypeDef ret;
-  HAL_ETH_StateTypeDef gstate = heth->gState;
-  HAL_ETH_StateTypeDef rxstate =heth->RxState;
-
-  ret = gstate;
-  ret |= rxstate;
-  return ret;
+  return heth->gState;
 }
 
 /**
@@ -2356,7 +2734,7 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
   *         the configuration information for ETHERNET module
   * @retval ETH Error Code
   */
-uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth)
 {
   return heth->ErrorCode;
 }
@@ -2367,7 +2745,7 @@ uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth)
   *         the configuration information for ETHERNET module
   * @retval ETH DMA Error Code
   */
-uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth)
 {
   return heth->DMAErrorCode;
 }
@@ -2378,7 +2756,7 @@ uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth)
   *         the configuration information for ETHERNET module
   * @retval ETH MAC Error Code
   */
-uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth)
 {
   return heth->MACErrorCode;
 }
@@ -2389,7 +2767,7 @@ uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth)
   *         the configuration information for ETHERNET module
   * @retval ETH MAC WakeUp event source
   */
-uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth)
 {
   return heth->MACWakeUpEvent;
 }
@@ -2406,42 +2784,42 @@ uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth)
   * @{
   */
 
-static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *macconf)
+static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf)
 {
   uint32_t macregval;
 
   /*------------------------ MACCR Configuration --------------------*/
-  macregval =(macconf->InterPacketGapVal |
-              macconf->SourceAddrControl |
-                ((uint32_t)macconf->ChecksumOffload<< 27) |
-                  ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
-                    ((uint32_t)macconf->Support2KPacket  << 22) |
-                      ((uint32_t)macconf->CRCStripTypePacket << 21) |
-                        ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
-                          ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
-                            ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
-                              ((uint32_t)macconf->JumboPacket << 16) |
-                                macconf->Speed |
-                                  macconf->DuplexMode |
-                                    ((uint32_t)macconf->LoopbackMode << 12) |
-                                      ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11)|
-                                        ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10)|
-                                          ((uint32_t)macconf->CarrierSenseDuringTransmit << 9)|
-                                            ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8)|
-                                              macconf->BackOffLimit |
-                                                ((uint32_t)macconf->DeferralCheck << 4)|
-                                                  macconf->PreambleLength);
+  macregval = (macconf->InterPacketGapVal |
+               macconf->SourceAddrControl |
+               ((uint32_t)macconf->ChecksumOffload << 27) |
+               ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) |
+               ((uint32_t)macconf->Support2KPacket  << 22) |
+               ((uint32_t)macconf->CRCStripTypePacket << 21) |
+               ((uint32_t)macconf->AutomaticPadCRCStrip << 20) |
+               ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) |
+               ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) |
+               ((uint32_t)macconf->JumboPacket << 16) |
+               macconf->Speed |
+               macconf->DuplexMode |
+               ((uint32_t)macconf->LoopbackMode << 12) |
+               ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) |
+               ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) |
+               ((uint32_t)macconf->CarrierSenseDuringTransmit << 9) |
+               ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) |
+               macconf->BackOffLimit |
+               ((uint32_t)macconf->DeferralCheck << 4) |
+               macconf->PreambleLength);
 
   /* Write to MACCR */
   MODIFY_REG(heth->Instance->MACCR, ETH_MACCR_MASK, macregval);
 
   /*------------------------ MACECR Configuration --------------------*/
-  macregval = ((macconf->ExtendedInterPacketGapVal << 25)|
-               ((uint32_t)macconf->ExtendedInterPacketGap << 24)|
-                 ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18)|
-                   ((uint32_t)macconf->SlowProtocolDetect << 17)|
-                     ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U)<< 16) |
-                       macconf->GiantPacketSizeLimit);
+  macregval = ((macconf->ExtendedInterPacketGapVal << 25) |
+               ((uint32_t)macconf->ExtendedInterPacketGap << 24) |
+               ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) |
+               ((uint32_t)macconf->SlowProtocolDetect << 17) |
+               ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) |
+               macconf->GiantPacketSizeLimit);
 
   /* Write to MACECR */
   MODIFY_REG(heth->Instance->MACECR, ETH_MACECR_MASK, macregval);
@@ -2456,8 +2834,8 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *mac
   /*------------------------ MACTFCR Configuration --------------------*/
   macregval = (((uint32_t)macconf->TransmitFlowControl << 1) |
                macconf->PauseLowThreshold |
-                 ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U)<< 7) |
-                   (macconf->PauseTime << 16));
+               ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) |
+               (macconf->PauseTime << 16));
 
   /* Write to MACTFCR */
   MODIFY_REG(heth->Instance->MACTFCR, ETH_MACTFCR_MASK, macregval);
@@ -2476,14 +2854,14 @@ static void ETH_SetMACConfig(ETH_HandleTypeDef *heth,  ETH_MACConfigTypeDef *mac
   /*------------------------ MTLRQOMR Configuration --------------------*/
   macregval = (macconf->ReceiveQueueMode |
                ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) |
-                 ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
-                   ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
+               ((uint32_t)macconf->ForwardRxErrorPacket << 4) |
+               ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3));
 
   /* Write to MTLRQOMR */
   MODIFY_REG(heth->Instance->MTLRQOMR, ETH_MTLRQOMR_MASK, macregval);
 }
 
-static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dmaconf)
+static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf)
 {
   uint32_t dmaregval;
 
@@ -2493,20 +2871,19 @@ static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth,  ETH_DMAConfigTypeDef *dma
   /*------------------------ DMASBMR Configuration --------------------*/
   dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) |
                dmaconf->BurstMode |
-                 ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
+               ((uint32_t)dmaconf->RebuildINCRxBurst << 15));
 
   MODIFY_REG(heth->Instance->DMASBMR, ETH_DMASBMR_MASK, dmaregval);
 
   /*------------------------ DMACCR Configuration --------------------*/
   dmaregval = (((uint32_t)dmaconf->PBLx8Mode << 16) |
                dmaconf->MaximumSegmentSize);
-
   MODIFY_REG(heth->Instance->DMACCR, ETH_DMACCR_MASK, dmaregval);
 
   /*------------------------ DMACTCR Configuration --------------------*/
   dmaregval = (dmaconf->TxDMABurstLength |
-               ((uint32_t)dmaconf->SecondPacketOperate << 4)|
-                 ((uint32_t)dmaconf->TCPSegmentation << 12));
+               ((uint32_t)dmaconf->SecondPacketOperate << 4) |
+               ((uint32_t)dmaconf->TCPSegmentation << 12));
 
   MODIFY_REG(heth->Instance->DMACTCR, ETH_DMACTCR_MASK, dmaregval);
 
@@ -2542,17 +2919,17 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
   macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE;
   macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE;
   macDefaultConf.ExtendedInterPacketGap = DISABLE;
-  macDefaultConf.ExtendedInterPacketGapVal = 0x0;
+  macDefaultConf.ExtendedInterPacketGapVal = 0x0U;
   macDefaultConf.ForwardRxErrorPacket = DISABLE;
   macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE;
-  macDefaultConf.GiantPacketSizeLimit = 0x618;
+  macDefaultConf.GiantPacketSizeLimit = 0x618U;
   macDefaultConf.GiantPacketSizeLimitControl = DISABLE;
   macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT;
   macDefaultConf.Jabber = ENABLE;
   macDefaultConf.JumboPacket = DISABLE;
   macDefaultConf.LoopbackMode = DISABLE;
   macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4;
-  macDefaultConf.PauseTime = 0x0;
+  macDefaultConf.PauseTime = 0x0U;
   macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7;
   macDefaultConf.ProgrammableWatchdog = DISABLE;
   macDefaultConf.ReceiveFlowControl = DISABLE;
@@ -2585,63 +2962,12 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth)
   dmaDefaultConf.SecondPacketOperate = DISABLE;
   dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
   dmaDefaultConf.TCPSegmentation = DISABLE;
-  dmaDefaultConf.MaximumSegmentSize = 536;
+  dmaDefaultConf.MaximumSegmentSize = ETH_SEGMENT_SIZE_DEFAULT;
 
   /* DMA default configuration */
   ETH_SetDMAConfig(heth, &dmaDefaultConf);
 }
 
-/**
-  * @brief  Configures the Clock range of SMI interface.
-  *         called by HAL_ETH_Init() API.
-  * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
-  *         the configuration information for ETHERNET module
-  * @retval None
-  */
-static void ETH_MAC_MDIO_ClkConfig(ETH_HandleTypeDef *heth)
-{
-  uint32_t tmpreg, hclk;
-
-  /* Get the ETHERNET MACMDIOAR value */
-  tmpreg = (heth->Instance)->MACMDIOAR;
-
-  /* Clear CSR Clock Range bits */
-  tmpreg &= ~ETH_MACMDIOAR_CR;
-
-  /* Get hclk frequency value */
-  hclk = HAL_RCC_GetHCLKFreq();
-
-  /* Set CR bits depending on hclk value */
-  if((hclk >= 20000000U)&&(hclk < 35000000U))
-  {
-    /* CSR Clock Range between 20-35 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV16;
-  }
-  else if((hclk >= 35000000U)&&(hclk < 60000000U))
-  {
-    /* CSR Clock Range between 35-60 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV26;
-  }
-  else if((hclk >= 60000000U)&&(hclk < 100000000U))
-  {
-    /* CSR Clock Range between 60-100 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV42;
-  }
-  else if((hclk >= 100000000U)&&(hclk < 150000000U))
-  {
-    /* CSR Clock Range between 100-150 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV62;
-  }
-  else /* (hclk >= 150000000)&&(hclk <= 200000000) */
-  {
-    /* CSR Clock Range between 150-200 MHz */
-    tmpreg |= (uint32_t)ETH_MACMDIOAR_CR_DIV102;
-  }
-
-  /* Configure the CSR Clock Range */
-  (heth->Instance)->MACMDIOAR = (uint32_t)tmpreg;
-}
-
 /**
   * @brief  Initializes the DMA Tx descriptors.
   *         called by HAL_ETH_Init() API.
@@ -2655,22 +2981,23 @@ static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth)
   uint32_t i;
 
   /* Fill each DMATxDesc descriptor with the right values */
-  for(i=0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
+  for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++)
   {
     dmatxdesc = heth->Init.TxDesc + i;
 
-    WRITE_REG(dmatxdesc->DESC0, 0x0);
-    WRITE_REG(dmatxdesc->DESC1, 0x0);
-    WRITE_REG(dmatxdesc->DESC2, 0x0);
-    WRITE_REG(dmatxdesc->DESC3, 0x0);
+    WRITE_REG(dmatxdesc->DESC0, 0x0U);
+    WRITE_REG(dmatxdesc->DESC1, 0x0U);
+    WRITE_REG(dmatxdesc->DESC2, 0x0U);
+    WRITE_REG(dmatxdesc->DESC3, 0x0U);
 
     WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc);
+
   }
 
   heth->TxDescList.CurTxDesc = 0;
 
   /* Set Transmit Descriptor Ring Length */
-  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT -1));
+  WRITE_REG(heth->Instance->DMACTDRLR, (ETH_TX_DESC_CNT - 1U));
 
   /* Set Transmit Descriptor List Address */
   WRITE_REG(heth->Instance->DMACTDLAR, (uint32_t) heth->Init.TxDesc);
@@ -2691,35 +3018,36 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
   ETH_DMADescTypeDef *dmarxdesc;
   uint32_t i;
 
-  for(i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
+  for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++)
   {
     dmarxdesc =  heth->Init.RxDesc + i;
 
-    WRITE_REG(dmarxdesc->DESC0, 0x0);
-    WRITE_REG(dmarxdesc->DESC1, 0x0);
-    WRITE_REG(dmarxdesc->DESC2, 0x0);
-    WRITE_REG(dmarxdesc->DESC3, 0x0);
-    WRITE_REG(dmarxdesc->BackupAddr0, 0x0);
-    WRITE_REG(dmarxdesc->BackupAddr1, 0x0);
+    WRITE_REG(dmarxdesc->DESC0, 0x0U);
+    WRITE_REG(dmarxdesc->DESC1, 0x0U);
+    WRITE_REG(dmarxdesc->DESC2, 0x0U);
+    WRITE_REG(dmarxdesc->DESC3, 0x0U);
+    WRITE_REG(dmarxdesc->BackupAddr0, 0x0U);
+    WRITE_REG(dmarxdesc->BackupAddr1, 0x0U);
 
     /* Set Rx descritors addresses */
     WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc);
+
   }
 
-  WRITE_REG(heth->RxDescList.CurRxDesc, 0);
-  WRITE_REG(heth->RxDescList.FirstAppDesc, 0);
-  WRITE_REG(heth->RxDescList.AppDescNbr, 0);
-  WRITE_REG(heth->RxDescList.ItMode, 0);
-  WRITE_REG(heth->RxDescList.AppContextDesc, 0);
+  WRITE_REG(heth->RxDescList.RxDescIdx, 0U);
+  WRITE_REG(heth->RxDescList.RxDescCnt, 0U);
+  WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U);
+  WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U);
+  WRITE_REG(heth->RxDescList.ItMode, 0U);
 
   /* Set Receive Descriptor Ring Length */
-  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1)));
+  WRITE_REG(heth->Instance->DMACRDRLR, ((uint32_t)(ETH_RX_DESC_CNT - 1U)));
 
   /* Set Receive Descriptor List Address */
   WRITE_REG(heth->Instance->DMACRDLAR, (uint32_t) heth->Init.RxDesc);
 
   /* Set Receive Descriptor Tail pointer Address */
-  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1))));
+  WRITE_REG(heth->Instance->DMACRDTPR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U))));
 }
 
 /**
@@ -2731,19 +3059,23 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth)
   * @param  ItMode: Enable or disable Tx EOT interrept
   * @retval Status
   */
-static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode)
+static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig,
+                                           uint32_t ItMode)
 {
   ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList;
   uint32_t descidx = dmatxdesclist->CurTxDesc;
   uint32_t firstdescidx = dmatxdesclist->CurTxDesc;
-  uint32_t descnbr = 0, idx;
+  uint32_t idx;
+  uint32_t descnbr = 0;
   ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
 
   ETH_BufferTypeDef  *txbuffer = pTxConfig->TxBuffer;
   uint32_t           bd_count = 0;
+  uint32_t primask_bit;
 
   /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-  if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+  if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+      || (dmatxdesclist->PacketAddress[descidx] != NULL))
   {
     return HAL_ETH_ERROR_BUSY;
   }
@@ -2752,7 +3084,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
   /*****************    Context descriptor configuration (Optional) **********/
   /***************************************************************************/
   /* If VLAN tag is enabled for this packet */
-  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
   {
     /* Set vlan tag value */
     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXCDESC_VT, pTxConfig->VlanTag);
@@ -2762,7 +3094,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
     SET_BIT(heth->Instance->MACVIR, ETH_MACVIR_VLTI);
 
     /* if inner VLAN is enabled */
-    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != 0U)
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_INNERVLANTAG) != (uint32_t)RESET)
     {
       /* Set inner vlan tag value */
       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_IVT, (pTxConfig->InnerVlanTag << 16));
@@ -2780,7 +3112,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
   }
 
   /* if tcp segmentation is enabled for this packet */
-  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
   {
     /* Set MSS value */
     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXCDESC_MSS, pTxConfig->MaxSegmentSize);
@@ -2788,10 +3120,13 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_TCMSSV);
   }
 
-  if((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)|| (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U))
+  if ((READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
+      || (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET))
   {
     /* Set as context descriptor */
     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_CTXT);
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
     /* Set own bit */
     SET_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
     /* Increment current tx descriptor index */
@@ -2802,9 +3137,11 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
     descnbr += 1U;
 
     /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-    if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
+    if (READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN)
     {
       dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx];
+      /* Ensure rest of descriptor is written to RAM before the OWN bit */
+      __DMB();
       /* Clear own bit */
       CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXCDESC_OWN);
 
@@ -2823,7 +3160,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
   /* Set header or buffer 1 Length */
   MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len);
 
-  if(txbuffer->next != NULL)
+  if (txbuffer->next != NULL)
   {
     txbuffer = txbuffer->next;
     /* Set buffer 2 address */
@@ -2833,12 +3170,12 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
   }
   else
   {
-    WRITE_REG(dmatxdesc->DESC1, 0x0);
+    WRITE_REG(dmatxdesc->DESC1, 0x0U);
     /* Set buffer 2 Length */
     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
   }
 
-  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
   {
     /* Set TCP Header length */
     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19));
@@ -2851,18 +3188,18 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
   {
     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
 
-    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
     {
       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
     }
 
-    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U)
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET)
     {
       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl);
     }
   }
 
-  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U)
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)RESET)
   {
     /* Set Vlan Tag control */
     MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl);
@@ -2872,11 +3209,13 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
   /* Mark it as NORMAL descriptor */
   CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
+  /* Ensure rest of descriptor is written to RAM before the OWN bit */
+  __DMB();
   /* set OWN bit of FIRST descriptor */
   SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
 
   /* If source address insertion/replacement is enabled for this packet */
-  if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != 0U)
+  if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_SAIC) != (uint32_t)RESET)
   {
     MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl);
   }
@@ -2895,14 +3234,18 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
     CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
 
     /* Current Tx Descriptor Owned by DMA: cannot be used by the application  */
-    if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL))
+    if ((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
+        || (dmatxdesclist->PacketAddress[descidx] != NULL))
     {
       descidx = firstdescidx;
       dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
 
       /* clear previous desc own bit */
-      for(idx = 0; idx < descnbr; idx ++)
+      for (idx = 0; idx < descnbr; idx ++)
       {
+        /* Ensure rest of descriptor is written to RAM before the OWN bit */
+        __DMB();
+
         CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
 
         /* Increment current tx descriptor index */
@@ -2935,12 +3278,12 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
     }
     else
     {
-      WRITE_REG(dmatxdesc->DESC1, 0x0);
+      WRITE_REG(dmatxdesc->DESC1, 0x0U);
       /* Set buffer 2 Length */
       MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U);
     }
 
-    if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U)
+    if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET)
     {
       /* Set TCP payload length */
       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen);
@@ -2952,7 +3295,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
       /* Set the packet length */
       MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length);
 
-      if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U)
+      if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET)
       {
         /* Checksum Insertion Control */
         MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl);
@@ -2960,13 +3303,16 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
     }
 
     bd_count += 1U;
+
+    /* Ensure rest of descriptor is written to RAM before the OWN bit */
+    __DMB();
     /* Set Own bit */
     SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN);
     /* Mark it as NORMAL descriptor */
     CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT);
   }
 
-  if(ItMode != ((uint32_t)RESET))
+  if (ItMode != ((uint32_t)RESET))
   {
     /* Set Interrupt on completion bit */
     SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC);
@@ -2984,14 +3330,14 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
 
   dmatxdesclist->CurTxDesc = descidx;
 
-  /* disable the interrupt */
-  __disable_irq();
+  /* Enter critical section */
+  primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1);
 
   dmatxdesclist->BuffersInUse += bd_count + 1U;
 
-  /* Enable interrupts back */
-  __enable_irq();
-
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
 
   /* Return function status */
   return HAL_ETH_ERROR_NONE;
@@ -3003,11 +3349,16 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
   /* Init the ETH Callback settings */
   heth->TxCpltCallback   = HAL_ETH_TxCpltCallback;    /* Legacy weak TxCpltCallback   */
   heth->RxCpltCallback   = HAL_ETH_RxCpltCallback;    /* Legacy weak RxCpltCallback   */
-  heth->DMAErrorCallback = HAL_ETH_DMAErrorCallback;  /* Legacy weak DMAErrorCallback */
-  heth->MACErrorCallback = HAL_ETH_MACErrorCallback;  /* Legacy weak MACErrorCallback */
+  heth->ErrorCallback    = HAL_ETH_ErrorCallback;     /* Legacy weak ErrorCallback */
   heth->PMTCallback      = HAL_ETH_PMTCallback;       /* Legacy weak PMTCallback      */
   heth->EEECallback      = HAL_ETH_EEECallback;       /* Legacy weak EEECallback      */
   heth->WakeUpCallback   = HAL_ETH_WakeUpCallback;    /* Legacy weak WakeUpCallback   */
+  heth->rxLinkCallback   = HAL_ETH_RxLinkCallback;    /* Legacy weak RxLinkCallback   */
+  heth->txFreeCallback   = HAL_ETH_TxFreeCallback;    /* Legacy weak TxFreeCallback   */
+#ifdef HAL_ETH_USE_PTP
+  heth->txPtpCallback    = HAL_ETH_TxPtpCallback;     /* Legacy weak TxPtpCallback   */
+#endif /* HAL_ETH_USE_PTP */
+  heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */
 }
 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
@@ -3026,5 +3377,3 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h
index 354ce3f5f8..0cc5eb2d42 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h
@@ -6,26 +6,24 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef STM32H7xx_HAL_ETH_H
 #define STM32H7xx_HAL_ETH_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
@@ -37,23 +35,35 @@
 
 /** @addtogroup ETH
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 #ifndef ETH_TX_DESC_CNT
- #define ETH_TX_DESC_CNT         4U
-#endif
-	 
+#define ETH_TX_DESC_CNT         4U
+#endif /* ETH_TX_DESC_CNT */
+
 #ifndef ETH_RX_DESC_CNT
- #define ETH_RX_DESC_CNT         4U
-#endif
+#define ETH_RX_DESC_CNT         4U
+#endif /* ETH_RX_DESC_CNT */
+
+#ifndef ETH_SWRESET_TIMEOUT
+#define ETH_SWRESET_TIMEOUT     500U
+#endif /* ETH_SWRESET_TIMEOUT */
+
+#ifndef ETH_MDIO_BUS_TIMEOUT
+#define ETH_MDIO_BUS_TIMEOUT    1000U
+#endif /* ETH_MDIO_BUS_TIMEOUT */
+
+#ifndef ETH_MAC_US_TICK
+#define ETH_MAC_US_TICK         1000000U
+#endif /* ETH_MAC_US_TICK */
 
 /*********************** Descriptors struct def section ************************/
 /** @defgroup ETH_Exported_Types ETH Exported Types
   * @{
   */
 
-/** 
+/**
   * @brief  ETH DMA Descriptor structure definition
   */
 typedef struct
@@ -64,180 +74,182 @@ typedef struct
   __IO uint32_t DESC3;
   uint32_t BackupAddr0; /* used to store rx buffer 1 address */
   uint32_t BackupAddr1; /* used to store rx buffer 2 address */
-}ETH_DMADescTypeDef;
-/** 
-  * 
+} ETH_DMADescTypeDef;
+/**
+  *
   */
 
-/** 
+/**
   * @brief  ETH Buffers List structure definition
   */
 typedef struct __ETH_BufferTypeDef
 {
   uint8_t *buffer;                /*<! buffer address */
-  
+
   uint32_t len;                   /*<! buffer length */
-  
-  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */	
-}ETH_BufferTypeDef;
-/** 
-  * 
+
+  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
+} ETH_BufferTypeDef;
+/**
+  *
   */
-  
-/** 
+
+/**
   * @brief  DMA Transmit Descriptors Wrapper structure definition
   */
 typedef struct
 {
   uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
-  
+
   uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
 
-  uint32_t* PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
+  uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
 
-  uint32_t* CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
+  uint32_t *CurrentPacketAddress;           /*<! Current transmit NX_PACKET addresses */
 
   uint32_t BuffersInUse;                   /*<! Buffers in Use */
-}ETH_TxDescListTypeDef;
-/** 
-  * 
+
+  uint32_t releaseIndex;                  /*<! Release index */
+} ETH_TxDescListTypeDef;
+/**
+  *
   */
 
- /** 
+/**
   * @brief  Transmit Packet Configuration structure definition
   */
 typedef struct
 {
-  uint32_t Attributes;              /*!< Tx packet HW features capabilities. 
+  uint32_t Attributes;              /*!< Tx packet HW features capabilities.
                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
-  
+
   uint32_t Length;                  /*!< Total packet length   */
-  
+
   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
-  
+
   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
-  
-  uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control. 
+
+  uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
-  
-  uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control. 
+
+  uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
-  
-  uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 
+
+  uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
                                         This parameter can be a value from 0x0 to 0x3FFF */
-  
-  uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.     
+
+  uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
                                         This parameter can be a value from 0x0 to 0x3FFFF */
-  
+
   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
                                         This parameter can be a value from 0x5 to 0xF */
 
-  uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled. 
+  uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
                                         This parameter can be a value from 0x0 to 0xFFFF*/
-  
-  uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 
+
+  uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
-  
+
   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
                                         This parameter can be a value from 0x0 to 0x3FFFF */
-  
-  uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 
+
+  uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
-  
-}ETH_TxPacketConfig;
-/** 
-  * 
+
+  void *pData;                     /*!< Specifies Application packet pointer to save   */
+
+} ETH_TxPacketConfigTypeDef;
+/**
+  *
   */
 
-/** 
- * @brief  DMA Receive Descriptors Wrapper structure definition
- */
+/**
+  * @brief  ETH Timestamp structure definition
+  */
+typedef struct
+{
+  uint32_t TimeStampLow;
+  uint32_t TimeStampHigh;
+
+} ETH_TimeStampTypeDef;
+/**
+  *
+  */
+
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  ETH Timeupdate structure definition
+  */
+typedef struct
+{
+  uint32_t Seconds;
+  uint32_t NanoSeconds;
+} ETH_TimeTypeDef;
+/**
+  *
+  */
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  DMA Receive Descriptors Wrapper structure definition
+  */
 typedef struct
 {
   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
-  
-  uint32_t CurRxDesc;                   /*<! Current Rx descriptor, ready for next reception. */
-  
-  uint32_t FirstAppDesc;                /*<! First descriptor of last received packet. */
-  
-  uint32_t AppDescNbr;                  /*<! Number of descriptors of last received packet. */
- 
-  uint32_t AppContextDesc;              /*<! If 1 a context descriptor is present in last received packet.
-                                             If 0 no context descriptor is present in last received packet. */
-  
+
   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
-                                             If 0, DMA will not generate the Rx complete interrupt. */ 
-}ETH_RxDescListTypeDef;
-/** 
-  * 
+                                             If 0, DMA will not generate the Rx complete interrupt. */
+
+  uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */
+
+  uint32_t RxDescCnt;                 /*<! Number of descriptors . */
+
+  uint32_t RxDataLength;              /*<! Received Data Length. */
+
+  uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */
+
+  uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */
+
+  uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */
+
+  ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */
+
+  void *pRxStart;                     /*<! Pointer to the first buff. */
+
+  void *pRxEnd;                       /*<! Pointer to the last buff. */
+
+} ETH_RxDescListTypeDef;
+/**
+  *
   */
 
-/** 
-  * @brief  Received Packet Information structure definition
-  */ 
-typedef struct  
-{  
-  uint32_t SegmentCnt;      /*<! Number of Rx Descriptors */
-  
-  uint32_t VlanTag;         /*<! Vlan Tag value */
-  
-  uint32_t InnerVlanTag;    /*<! Inner Vlan Tag value */
-  
-  uint32_t Checksum;        /*<! Rx Checksum status. 
-                                 This parameter can be a value of @ref ETH_Rx_Checksum_Status */
-  
-  uint32_t HeaderType;      /*<! IP header type. 
-                                 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
-  
-  uint32_t PayloadType;     /*<! Payload type. 
-                                 This parameter can be a value of @ref ETH_Rx_Payload_Type */
-  
-  uint32_t MacFilterStatus; /*<! MAC filter status.  
-                                 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
-  
-  uint32_t L3FilterStatus;  /*<! L3 filter status
-                                 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
-  
-  uint32_t L4FilterStatus;  /*<! L4 filter status  
-                                 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
-  
-  uint32_t ErrorCode;       /*<! Rx error code  
-                                 This parameter can be a combination of @ref ETH_Rx_Error_Code */
-
-} ETH_RxPacketInfo;
-/** 
-  * 
-  */
-
-/** 
-  * @brief  ETH MAC Configuration Structure definition  
+/**
+  * @brief  ETH MAC Configuration Structure definition
   */
 typedef struct
 {
-  uint32_t         SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.                                                           
-                                                     This parameter can be a value of @ref ETH_Source_Addr_Control */                  
+  uint32_t
+  SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
+                                                     This parameter can be a value of @ref ETH_Source_Addr_Control */
 
-  FunctionalState  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */    
+  FunctionalState
+  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
 
   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
-                                                     This parameter can be a value of @ref ETH_Inter_Packet_Gap */   
+                                                     This parameter can be a value of @ref ETH_Inter_Packet_Gap */
 
-  FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */  
+  FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
 
-  FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 
+  FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
 
-  FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/ 
+  FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
 
-  FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/ 
-																													 
-  FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path
-                                                           When enabled, the MAC allows no more then 2048 bytes to be received.
-                                                           When disabled, the MAC can receive up to 16384 bytes. */  
+  FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
 
-  FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path
-                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.
-                                                           When disabled, the MAC can send up to 16384 bytes. */
+  FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path.*/
+
+  FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path.*/
 
   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
@@ -251,217 +263,331 @@ typedef struct
 
   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
 
-  FunctionalState  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
+  FunctionalState
+  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
 
-  FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */  
+  FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
 
-  FunctionalState  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
+  FunctionalState
+  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
 
-  FunctionalState  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
+  FunctionalState
+  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
 
   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
 
-  FunctionalState  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
+  FunctionalState
+  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
 
-  uint32_t         PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
-                                                           This parameter can be a value of @ref ETH_Preamble_Length */ 
-                                                           
-  FunctionalState  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */   
+  uint32_t
+  PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
+                                                           This parameter can be a value of @ref ETH_Preamble_Length */
 
-  FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */   
+  FunctionalState
+  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
 
-  FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */   
+  FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
+
+  FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
+
+  uint32_t
+  GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
+                                                    greater than the value programmed in this field in units of bytes
+                                                    This parameter must be a number between
+                                                    Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
+
+  FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
 
-  uint32_t         GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 
-	                                                  greater than the value programmed in this field in units of bytes 
-                                                          This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/                                                          
- 
-  FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */ 
-  
   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
-                                                           This parameter can be a value from 0x0 to 0xFF */ 
-  
+                                                           This parameter can be a value from 0x0 to 0xFF */
+
   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
-	
+
   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
-                                                        This parameter can be a value of @ref ETH_Watchdog_Timeout */                                                            
+                                                        This parameter can be a value of @ref ETH_Watchdog_Timeout */
 
-   uint32_t        PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 
-                                                   This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+  uint32_t
+  PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
+                                                   This parameter must be a number between
+                                                   Min_Data = 0x0 and Max_Data = 0xFFFF.*/
 
-  FunctionalState  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/  
+  FunctionalState
+  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
 
-  uint32_t         PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
+  uint32_t
+  PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
 
-  FunctionalState  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
+  FunctionalState
+  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
                                                    or the MAC back pressure operation in Half Duplex mode */
 
-  FunctionalState  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
-  
-  FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet  
+  FunctionalState
+  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
+
+  FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
                                                   and disables its transmitter for a specified (Pause) time */
-																													                                                        	 
+
   uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.
-                                                      This parameter can be a value of @ref ETH_Transmit_Mode */ 
+                                                      This parameter can be a value of @ref ETH_Transmit_Mode */
 
   uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.
                                                              This parameter can be a value of @ref ETH_Receive_Mode */
 
-  FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 
+  FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
 
-  FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */ 
+  FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */
 
-  FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/ 
+  FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/
 } ETH_MACConfigTypeDef;
-/** 
-  * 
+/**
+  *
   */
 
-/** 
-  * @brief  ETH DMA Configuration Structure definition  
+/**
+  * @brief  ETH DMA Configuration Structure definition
   */
- typedef struct
- {
-   uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
+typedef struct
+{
+  uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx
                                                          This parameter can be a value of @ref ETH_DMA_Arbitration */
-      
-   FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned 
+
+  FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned
                                                             burst transfers on Read and Write channels  */
-      
-   uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
+
+  uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.
                                                      This parameter can be a value of @ref ETH_Burst_Mode */
-      
-   FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats 
+  FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats
                                                    of any initiated burst transfer with INCRx and SINGLE transfers. */
-      
-   FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
-      
-   uint32_t        TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
-                                                     This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */	
-      
-   FunctionalState SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
-                                                      Packet of Transmit data even before obtaining the status for the first one. */	
-      
-   uint32_t        RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
+
+  FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */
+
+  uint32_t
+  TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
+                                                     This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
+
+  FunctionalState
+  SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
+                                                      Packet of Transmit data even before
+                                                      obtaining the status for the first one. */
+
+  uint32_t
+  RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
-      
-   FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
-      
-   FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
-      
-   uint32_t        MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
-                                                  This parameter can be a value from 0x40 to 0x3FFF */    
+
+  FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */
+
+  FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */
+
+  uint32_t
+  MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet
+                                                  This parameter can be a value from 0x40 to 0x3FFF */
+
 } ETH_DMAConfigTypeDef;
-/** 
-  * 
+/**
+  *
   */
 
-/** 
-  * @brief  HAL ETH Media Interfaces enum definition  
-  */ 
+/**
+  * @brief  HAL ETH Media Interfaces enum definition
+  */
 typedef enum
 {
   HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
   HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */
-}ETH_MediaInterfaceTypeDef;
-/** 
-  * 
+} ETH_MediaInterfaceTypeDef;
+/**
+  *
   */
 
-/** 
-  * @brief  ETH Init Structure definition  
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  HAL ETH PTP Update type enum definition
+  */
+typedef enum
+{
+  HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,   /*!<  PTP positive time update       */
+  HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U   /*!<  PTP negative time update       */
+} ETH_PtpUpdateTypeDef;
+/**
+  *
+  */
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  ETH Init Structure definition
   */
 typedef struct
 {
-   
-  uint8_t                     *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-  	
+  uint8_t
+  *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
+
   ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */
 
-  ETH_DMADescTypeDef          *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
-  
-  ETH_DMADescTypeDef          *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
-  
+  ETH_DMADescTypeDef
+  *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */
+
+  ETH_DMADescTypeDef
+  *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */
+
   uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */
 
-}ETH_InitTypeDef;
-/** 
-  * 
+} ETH_InitTypeDef;
+/**
+  *
   */
 
-/** 
-  * @brief  HAL State structures definition  
-  */ 
+#ifdef HAL_ETH_USE_PTP
+/**
+  * @brief  ETH PTP Init Structure definition
+  */
+typedef struct
+{
+  uint32_t                    Timestamp;                    /*!< Enable Timestamp */
+  uint32_t                    TimestampUpdateMode;          /*!< Fine or Coarse Timestamp Update */
+  uint32_t                    TimestampInitialize;          /*!< Initialize Timestamp */
+  uint32_t                    TimestampUpdate;              /*!< Timestamp Update */
+  uint32_t                    TimestampAddendUpdate;        /*!< Timestamp Addend Update */
+  uint32_t                    TimestampAll;                 /*!< Enable Timestamp for All Packets */
+  uint32_t                    TimestampRolloverMode;        /*!< Timestamp Digital or Binary Rollover Control */
+  uint32_t                    TimestampV2;                  /*!< Enable PTP Packet Processing for Version 2 Format */
+  uint32_t                    TimestampEthernet;            /*!< Enable Processing of PTP over Ethernet Packets */
+  uint32_t                    TimestampIPv6;                /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
+  uint32_t                    TimestampIPv4;                /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
+  uint32_t                    TimestampEvent;               /*!< Enable Timestamp Snapshot for Event Messages */
+  uint32_t                    TimestampMaster;              /*!< Enable Timestamp Snapshot for Event Messages */
+  uint32_t                    TimestampSnapshots;           /*!< Select PTP packets for Taking Snapshots */
+  uint32_t                    TimestampFilter;              /*!< Enable MAC Address for PTP Packet Filtering */
+  uint32_t
+  TimestampChecksumCorrection;  /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
+  uint32_t                    TimestampStatusMode;          /*!< Transmit Timestamp Status Mode */
+  uint32_t                    TimestampAddend;              /*!< Timestamp addend value */
+  uint32_t                    TimestampSubsecondInc;        /*!< Subsecond Increment */
+
+} ETH_PTP_ConfigTypeDef;
+/**
+  *
+  */
+#endif  /* HAL_ETH_USE_PTP */
+
+/**
+  * @brief  HAL State structures definition
+  */
 typedef uint32_t HAL_ETH_StateTypeDef;
-/** 
-  * 
+/**
+  *
   */
 
-/** 
-  * @brief  ETH Handle Structure definition  
+/**
+  * @brief  HAL ETH Rx Get Buffer Function definition
+  */
+typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);  /*!< pointer to an ETH Rx Get Buffer Function */
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Rx Set App Data Function definition
+  */
+typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
+                                            uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Tx Free Function definition
+  */
+typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);  /*!< pointer to an ETH Tx Free function */
+/**
+  *
+  */
+
+/**
+  * @brief  HAL ETH Tx Free Function definition
+  */
+typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
+                                           ETH_TimeStampTypeDef *timestamp);  /*!< pointer to an ETH Tx Free function */
+/**
+  *
+  */
+
+/**
+  * @brief  ETH Handle Structure definition
   */
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 typedef struct __ETH_HandleTypeDef
 #else
 typedef struct
-#endif
+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 {
   ETH_TypeDef                *Instance;                 /*!< Register base address       */
-  
+
   ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */
-	
-  ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list 
+
+  ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list
                                                             addresses and current descriptor index  */
-		
-  ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list 
-                                                            addresses and current descriptor index  */ 
-  
-  HAL_LockTypeDef            Lock;                      /*!< Locking object             */
- 
-  __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management 
-                                                              and also related to Tx operations.
-                                                             This parameter can be a value of @ref HAL_ETH_StateTypeDef */
-  
-  __IO HAL_ETH_StateTypeDef  RxState;                   /*!< ETH state information related to Rx operations.
-                                                             This parameter can be a value of @ref HAL_ETH_StateTypeDef */
-  
-  __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine 
-                                                             This parameter can be a value of of @ref ETH_Error_Code */
-  
-  __IO uint32_t              DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
-                                                             This parameter can be a combination of @ref ETH_DMA_Status_Flags */
-  
-  __IO uint32_t              MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
-                                                             This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */ 
-    
+
+  ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list
+                                                            addresses and current descriptor index  */
+
+#ifdef HAL_ETH_USE_PTP
+  ETH_TimeStampTypeDef       TxTimestamp;               /*!< Tx Timestamp */
+#endif /* HAL_ETH_USE_PTP */
+
+  __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
+                                                              and also related to Tx operations. This parameter can
+                                                              be a value of @ref ETH_State_Codes */
+
+  __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
+                                                             This parameter can be a value of @ref ETH_Error_Code.*/
+
+  __IO uint32_t
+  DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
+                                                             This parameter can be a combination of
+                                                             @ref ETH_DMA_Status_Flags */
+
+  __IO uint32_t
+  MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
+                                                             This parameter can be a combination of
+                                                             @ref ETH_MAC_Rx_Tx_Status */
+
   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
-                                                             This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
-    
+                                                             This parameter can be a value of
+                                                             @ref ETH_MAC_Wake_Up_Event */
+
   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
-                                                             
+
+  __IO uint32_t              IsPtpConfigured;           /*!< Holds the PTP configuration status.
+                                                             This parameter can be a value of
+                                                             @ref ETH_PTP_Config_Status */
+
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 
-  void    (* TxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);   /*!< ETH Tx Complete Callback */
-  void    (* RxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Rx  Complete Callback     */
-  void    (* DMAErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH DMA Error Callback   */
-  void    (* MACErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH MAC Error Callback     */
-  void    (* PMTCallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Power Management Callback            */
-  void    (* EEECallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH EEE Callback   */
-  void    (* WakeUpCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Wake UP Callback   */
+  void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Tx Complete Callback */
+  void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback     */
+  void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Error Callback   */
+  void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH Power Management Callback            */
+  void (* EEECallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH EEE Callback   */
+  void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Wake UP Callback   */
 
-  void    (* MspInitCallback)    ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp Init callback              */
-  void    (* MspDeInitCallback)  ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp DeInit callback            */
+  void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Msp Init callback              */
+  void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp DeInit callback            */
 
-#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */                                                             
+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
+
+  pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;  /*!< ETH Rx Get Buffer Function   */
+  pETH_rxLinkCallbackTypeDef      rxLinkCallback; /*!< ETH Rx Set App Data Function */
+  pETH_txFreeCallbackTypeDef      txFreeCallback;       /*!< ETH Tx Free Function         */
+  pETH_txPtpCallbackTypeDef       txPtpCallback;  /*!< ETH Tx Handle Ptp Function */
 
 } ETH_HandleTypeDef;
-/** 
-  * 
+/**
+  *
   */
-  
+
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 /**
   * @brief  HAL ETH Callback ID enumeration definition
@@ -470,73 +596,72 @@ typedef enum
 {
   HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
   HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
-	
   HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
   HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
-  HAL_ETH_DMA_ERROR_CB_ID          = 0x04U,    /*!< ETH DMA Error Callback ID         */
-  HAL_ETH_MAC_ERROR_CB_ID          = 0x05U,    /*!< ETH MAC Error Callback ID         */
-  HAL_ETH_PMT_CB_ID                = 0x06U,     /*!< ETH Power Management Callback ID  */
-  HAL_ETH_EEE_CB_ID                = 0x07U,     /*!< ETH EEE Callback ID               */
+  HAL_ETH_ERROR_CB_ID              = 0x04U,    /*!< ETH Error Callback ID             */
+  HAL_ETH_PMT_CB_ID                = 0x06U,    /*!< ETH Power Management Callback ID  */
+  HAL_ETH_EEE_CB_ID                = 0x07U,    /*!< ETH EEE Callback ID               */
   HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
 
-
-}HAL_ETH_CallbackIDTypeDef;
+} HAL_ETH_CallbackIDTypeDef;
 
 /**
   * @brief  HAL ETH Callback pointer definition
   */
-typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
+typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
 
 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
-/** 
+/**
   * @brief  ETH MAC filter structure definition
   */
-typedef struct{
+typedef struct
+{
   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
-  
+
   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
-  
+
   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
-  
+
   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
-  
+
   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
-  
+
   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
-  
+
   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
-  
+
   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
-  
+
   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
-  
+
   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
-  
+
   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
-}ETH_MACFilterConfigTypeDef;
-/** 
-  * 
+} ETH_MACFilterConfigTypeDef;
+/**
+  *
   */
-    
-/** 
+
+/**
   * @brief  ETH Power Down structure definition
   */
-typedef struct{
+typedef struct
+{
   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
-  
+
   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
-  
+
   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
-  
+
   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
-  	
-}ETH_PowerDownConfigTypeDef;
-/** 
-  * 
+
+} ETH_PowerDownConfigTypeDef;
+/**
+  *
   */
-  
+
 /**
   * @}
   */
@@ -563,57 +688,61 @@ typedef struct{
   -----------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of TDES0 RF register
-  */ 
-#define ETH_DMATXNDESCRF_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
+  */
+#define ETH_DMATXNDESCRF_B1AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
 
-/** 
+/**
   * @brief  Bit definition of TDES1 RF register
-  */ 
-#define ETH_DMATXNDESCRF_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
+  */
+#define ETH_DMATXNDESCRF_B2AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
 
-/** 
+/**
   * @brief  Bit definition of TDES2 RF register
-  */ 
-#define ETH_DMATXNDESCRF_IOC          ((uint32_t)0x80000000U)  /*!< Interrupt on Completion */
-#define ETH_DMATXNDESCRF_TTSE         ((uint32_t)0x40000000U)  /*!< Transmit Timestamp Enable */
-#define ETH_DMATXNDESCRF_B2L          ((uint32_t)0x3FFF0000U)  /*!< Buffer 2 Length */
-#define ETH_DMATXNDESCRF_VTIR         ((uint32_t)0x0000C000U)  /*!< VLAN Tag Insertion or Replacement mask */
-#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)  /*!< Do not add a VLAN tag. */
-#define ETH_DMATXNDESCRF_VTIR_REMOVE  ((uint32_t)0x00004000U)  /*!< Remove the VLAN tag from the packets before transmission. */
-#define ETH_DMATXNDESCRF_VTIR_INSERT  ((uint32_t)0x00008000U)  /*!< Insert a VLAN tag. */
-#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)  /*!< Replace the VLAN tag. */
-#define ETH_DMATXNDESCRF_B1L          ((uint32_t)0x00003FFFU)  /*!< Buffer 1 Length */
-#define ETH_DMATXNDESCRF_HL           ((uint32_t)0x000003FFU)  /*!< Header Length */
+  */
+#define ETH_DMATXNDESCRF_IOC          0x80000000U  /*!< Interrupt on Completion */
+#define ETH_DMATXNDESCRF_TTSE         0x40000000U  /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCRF_B2L          0x3FFF0000U  /*!< Buffer 2 Length */
+#define ETH_DMATXNDESCRF_VTIR         0x0000C000U  /*!< VLAN Tag Insertion or Replacement mask */
+#define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U  /*!< Do not add a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REMOVE  0x00004000U  /*!< Remove the VLAN tag from the packets before transmission. */
+#define ETH_DMATXNDESCRF_VTIR_INSERT  0x00008000U  /*!< Insert a VLAN tag. */
+#define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U  /*!< Replace the VLAN tag. */
+#define ETH_DMATXNDESCRF_B1L          0x00003FFFU  /*!< Buffer 1 Length */
+#define ETH_DMATXNDESCRF_HL           0x000003FFU  /*!< Header Length */
 
-/** 
+/**
   * @brief  Bit definition of TDES3 RF register
-  */ 
-#define ETH_DMATXNDESCRF_OWN                                 ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXNDESCRF_CTXT                                ((uint32_t)0x40000000U)  /*!< Context Type */
-#define ETH_DMATXNDESCRF_FD                                  ((uint32_t)0x20000000U)  /*!< First Descriptor */
-#define ETH_DMATXNDESCRF_LD                                  ((uint32_t)0x10000000U)  /*!< Last Descriptor */
-#define ETH_DMATXNDESCRF_CPC                                 ((uint32_t)0x0C000000U)  /*!< CRC Pad Control mask */
-#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   ((uint32_t)0x00000000U)  /*!< CRC Pad Control: CRC and Pad Insertion */
-#define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      ((uint32_t)0x04000000U)  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
-#define ETH_DMATXNDESCRF_CPC_DISABLE                         ((uint32_t)0x08000000U)  /*!< CRC Pad Control: Disable CRC Insertion */
-#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     ((uint32_t)0x0C000000U)  /*!< CRC Pad Control: CRC Replacement */
-#define ETH_DMATXNDESCRF_SAIC                                ((uint32_t)0x03800000U)  /*!< SA Insertion Control mask*/
-#define ETH_DMATXNDESCRF_SAIC_DISABLE                        ((uint32_t)0x00000000U)  /*!< SA Insertion Control: Do not include the source address */
-#define ETH_DMATXNDESCRF_SAIC_INSERT                         ((uint32_t)0x00800000U)  /*!< SA Insertion Control: Include or insert the source address */
-#define ETH_DMATXNDESCRF_SAIC_REPLACE                        ((uint32_t)0x01000000U)  /*!< SA Insertion Control: Replace the source address */
-#define ETH_DMATXNDESCRF_THL                                 ((uint32_t)0x00780000U)  /*!< TCP Header Length */
-#define ETH_DMATXNDESCRF_TSE                                 ((uint32_t)0x00040000U)  /*!< TCP segmentation enable */
-#define ETH_DMATXNDESCRF_CIC                                 ((uint32_t)0x00030000U)  /*!< Checksum Insertion Control: 4 cases */ 
-#define ETH_DMATXNDESCRF_CIC_DISABLE                         ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is disabled */ 
-#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    ((uint32_t)0x00010000U)  /*!< Only IP header checksum calculation and insertion are enabled. */ 
-#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            ((uint32_t)0x00020000U)  /*!< IP header checksum and payload checksum calculation and insertion are
-                                                                                          enabled, but pseudo header checksum is not calculated in hardware */ 
-#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ((uint32_t)0x00030000U)  /*!< IP Header checksum and payload checksum calculation and insertion are
-                                                                                          enabled, and pseudo header checksum is calculated in hardware. */ 
-#define ETH_DMATXNDESCRF_TPL                                 ((uint32_t)0x0003FFFFU)  /*!< TCP Payload Length */
-#define ETH_DMATXNDESCRF_FL                                  ((uint32_t)0x00007FFFU)  /*!< Transmit End of Ring */
+  */
+#define ETH_DMATXNDESCRF_OWN                                 0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCRF_CTXT                                0x40000000U  /*!< Context Type */
+#define ETH_DMATXNDESCRF_FD                                  0x20000000U  /*!< First Descriptor */
+#define ETH_DMATXNDESCRF_LD                                  0x10000000U  /*!< Last Descriptor */
+#define ETH_DMATXNDESCRF_CPC                                 0x0C000000U  /*!< CRC Pad Control mask */
+#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   0x00000000U  /*!< CRC Pad Control: CRC and Pad Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      0x04000000U  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
+#define ETH_DMATXNDESCRF_CPC_DISABLE                         0x08000000U  /*!< CRC Pad Control: Disable CRC Insertion */
+#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     0x0C000000U  /*!< CRC Pad Control: CRC Replacement */
+#define ETH_DMATXNDESCRF_SAIC                                0x03800000U  /*!< SA Insertion Control mask*/
+#define ETH_DMATXNDESCRF_SAIC_DISABLE                        0x00000000U  /*!< SA Insertion Control: Do not include the source address */
+#define ETH_DMATXNDESCRF_SAIC_INSERT                         0x00800000U  /*!< SA Insertion Control: Include or insert the source address */
+#define ETH_DMATXNDESCRF_SAIC_REPLACE                        0x01000000U  /*!< SA Insertion Control: Replace the source address */
+#define ETH_DMATXNDESCRF_THL                                 0x00780000U  /*!< TCP Header Length */
+#define ETH_DMATXNDESCRF_TSE                                 0x00040000U  /*!< TCP segmentation enable */
+#define ETH_DMATXNDESCRF_CIC                                 0x00030000U  /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXNDESCRF_CIC_DISABLE                         0x00000000U  /*!< Do Nothing: Checksum Engine is disabled */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    0x00010000U  /*!< Only IP header checksum calculation and insertion are enabled. */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            0x00020000U  /*!< IP header checksum and payload checksum calculation and insertion are
+                                                                                        enabled, but pseudo header
+                                                                                        checksum is not
+                                                                                        calculated in hardware */
+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  0x00030000U  /*!< IP Header checksum and payload checksum calculation and insertion are
+                                                                                        enabled, and pseudo header
+                                                                                        checksum is
+                                                                                        calculated in hardware. */
+#define ETH_DMATXNDESCRF_TPL                                 0x0003FFFFU  /*!< TCP Payload Length */
+#define ETH_DMATXNDESCRF_FL                                  0x00007FFFU  /*!< Transmit End of Ring */
 
 /*
    DMA Tx Normal Descriptor Write Back Format
@@ -628,40 +757,39 @@ typedef struct{
   -----------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of TDES0 WBF register
-  */ 
-#define ETH_DMATXNDESCWBF_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
+  */
+#define ETH_DMATXNDESCWBF_TTSL                    0xFFFFFFFFU  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
 
-/** 
+/**
   * @brief  Bit definition of TDES1 WBF register
-  */ 
-#define ETH_DMATXNDESCWBF_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */
+  */
+#define ETH_DMATXNDESCWBF_TTSH                    0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
 
-/** 
+/**
   * @brief  Bit definition of TDES3 WBF register
-  */ 
-#define ETH_DMATXNDESCWBF_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXNDESCWBF_CTXT                    ((uint32_t)0x40000000U)  /*!< Context Type */
-#define ETH_DMATXNDESCWBF_FD                      ((uint32_t)0x20000000U)  /*!< First Descriptor */
-#define ETH_DMATXNDESCWBF_LD                      ((uint32_t)0x10000000U)  /*!< Last Descriptor */
-#define ETH_DMATXNDESCWBF_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Timestamp Status */
-#define ETH_DMATXNDESCWBF_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */
-#define ETH_DMATXNDESCWBF_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Timestamp Enable */
-#define ETH_DMATXNDESCWBF_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
-#define ETH_DMATXNDESCWBF_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */
-#define ETH_DMATXNDESCWBF_FF                      ((uint32_t)0x00002000U)  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
-#define ETH_DMATXNDESCWBF_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */
-#define ETH_DMATXNDESCWBF_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXNDESCWBF_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXNDESCWBF_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXNDESCWBF_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXNDESCWBF_CC                      ((uint32_t)0x000000F0U)  /*!< Collision Count */
-#define ETH_DMATXNDESCWBF_ED                      ((uint32_t)0x00000008U)  /*!< Excessive Deferral */
-#define ETH_DMATXNDESCWBF_UF                      ((uint32_t)0x00000004U)  /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXNDESCWBF_DB                      ((uint32_t)0x00000002U)  /*!< Deferred Bit */
-#define ETH_DMATXNDESCWBF_IHE                     ((uint32_t)0x00000004U)  /*!< IP Header Error */
-
+  */
+#define ETH_DMATXNDESCWBF_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXNDESCWBF_CTXT                    0x40000000U  /*!< Context Type */
+#define ETH_DMATXNDESCWBF_FD                      0x20000000U  /*!< First Descriptor */
+#define ETH_DMATXNDESCWBF_LD                      0x10000000U  /*!< Last Descriptor */
+#define ETH_DMATXNDESCWBF_TTSS                    0x00020000U  /*!< Tx Timestamp Status */
+#define ETH_DMATXNDESCWBF_DP                      0x04000000U  /*!< Disable Padding */
+#define ETH_DMATXNDESCWBF_TTSE                    0x02000000U  /*!< Transmit Timestamp Enable */
+#define ETH_DMATXNDESCWBF_ES                      0x00008000U  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
+#define ETH_DMATXNDESCWBF_JT                      0x00004000U  /*!< Jabber Timeout */
+#define ETH_DMATXNDESCWBF_FF                      0x00002000U  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
+#define ETH_DMATXNDESCWBF_PCE                     0x00001000U  /*!< Payload Checksum Error */
+#define ETH_DMATXNDESCWBF_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXNDESCWBF_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXNDESCWBF_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXNDESCWBF_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXNDESCWBF_CC                      0x000000F0U  /*!< Collision Count */
+#define ETH_DMATXNDESCWBF_ED                      0x00000008U  /*!< Excessive Deferral */
+#define ETH_DMATXNDESCWBF_UF                      0x00000004U  /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXNDESCWBF_DB                      0x00000002U  /*!< Deferred Bit */
+#define ETH_DMATXNDESCWBF_IHE                     0x00000004U  /*!< IP Header Error */
 
 /*
    DMA Tx Context Descriptor
@@ -676,43 +804,42 @@ typedef struct{
   -----------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of Tx context descriptor register 0
-  */ 
-#define ETH_DMATXCDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */
+  */
+#define ETH_DMATXCDESC_TTSL                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
 
-/** 
+/**
   * @brief  Bit definition of Tx context descriptor register 1
-  */ 
-#define ETH_DMATXCDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */
+  */
+#define ETH_DMATXCDESC_TTSH                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
 
-/** 
+/**
   * @brief  Bit definition of Tx context descriptor register 2
-  */ 
-#define ETH_DMATXCDESC_IVT   ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag */
-#define ETH_DMATXCDESC_MSS   ((uint32_t)0x00003FFFU)  /*!< Maximum Segment Size */
+  */
+#define ETH_DMATXCDESC_IVT                     0xFFFF0000U  /*!< Inner VLAN Tag */
+#define ETH_DMATXCDESC_MSS                     0x00003FFFU  /*!< Maximum Segment Size */
 
-/** 
+/**
   * @brief  Bit definition of Tx context descriptor register 3
   */
-#define ETH_DMATXCDESC_OWN                     ((uint32_t)0x80000000U)     /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXCDESC_CTXT                    ((uint32_t)0x40000000U)     /*!< Context Type */
-#define ETH_DMATXCDESC_OSTC                    ((uint32_t)0x08000000U)     /*!< One-Step Timestamp Correction Enable */
-#define ETH_DMATXCDESC_TCMSSV                  ((uint32_t)0x04000000U)     /*!< One-Step Timestamp Correction Input or MSS Valid */
-#define ETH_DMATXCDESC_CDE                     ((uint32_t)0x00800000U)     /*!< Context Descriptor Error */
-#define ETH_DMATXCDESC_IVTIR                   ((uint32_t)0x000C0000U)     /*!< Inner VLAN Tag Insert or Replace Mask */
-#define ETH_DMATXCDESC_IVTIR_DISABLE           ((uint32_t)0x00000000U)     /*!< Do not add the inner VLAN tag. */
-#define ETH_DMATXCDESC_IVTIR_REMOVE            ((uint32_t)0x00040000U)     /*!< Remove the inner VLAN tag from the packets before transmission. */
-#define ETH_DMATXCDESC_IVTIR_INSERT            ((uint32_t)0x00080000U)     /*!< Insert the inner VLAN tag. */
-#define ETH_DMATXCDESC_IVTIR_REPLACE           ((uint32_t)0x000C0000U)     /*!< Replace the inner VLAN tag. */
-#define ETH_DMATXCDESC_IVLTV                   ((uint32_t)0x00020000U)     /*!< Inner VLAN Tag Valid */
-#define ETH_DMATXCDESC_VLTV                    ((uint32_t)0x00010000U)     /*!< VLAN Tag Valid */
-#define ETH_DMATXCDESC_VT                      ((uint32_t)0x0000FFFFU)     /*!< VLAN Tag */
+#define ETH_DMATXCDESC_OWN                     0x80000000U     /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXCDESC_CTXT                    0x40000000U     /*!< Context Type */
+#define ETH_DMATXCDESC_OSTC                    0x08000000U     /*!< One-Step Timestamp Correction Enable */
+#define ETH_DMATXCDESC_TCMSSV                  0x04000000U     /*!< One-Step Timestamp Correction Input or MSS Valid */
+#define ETH_DMATXCDESC_CDE                     0x00800000U     /*!< Context Descriptor Error */
+#define ETH_DMATXCDESC_IVTIR                   0x000C0000U     /*!< Inner VLAN Tag Insert or Replace Mask */
+#define ETH_DMATXCDESC_IVTIR_DISABLE           0x00000000U     /*!< Do not add the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REMOVE            0x00040000U     /*!< Remove the inner VLAN tag from the packets before transmission. */
+#define ETH_DMATXCDESC_IVTIR_INSERT            0x00080000U     /*!< Insert the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVTIR_REPLACE           0x000C0000U     /*!< Replace the inner VLAN tag. */
+#define ETH_DMATXCDESC_IVLTV                   0x00020000U     /*!< Inner VLAN Tag Valid */
+#define ETH_DMATXCDESC_VLTV                    0x00010000U     /*!< VLAN Tag Valid */
+#define ETH_DMATXCDESC_VT                      0x0000FFFFU     /*!< VLAN Tag */
 
 /**
   * @}
-  */ 
-
+  */
 
 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
   * @{
@@ -731,29 +858,29 @@ typedef struct{
   -----------------------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 0 read format
   */
-#define ETH_DMARXNDESCRF_BUF1AP        ((uint32_t)0xFFFFFFFFU)  /*!< Header or Buffer 1 Address Pointer  */
+#define ETH_DMARXNDESCRF_BUF1AP           0xFFFFFFFFU  /*!< Header or Buffer 1 Address Pointer  */
 
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 2 read format
   */
-#define ETH_DMARXNDESCRF_BUF2AP        ((uint32_t)0xFFFFFFFFU)  /*!< Buffer 2 Address Pointer  */
+#define ETH_DMARXNDESCRF_BUF2AP           0xFFFFFFFFU  /*!< Buffer 2 Address Pointer  */
 
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 3 read format
   */
-#define ETH_DMARXNDESCRF_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */
-#define ETH_DMARXNDESCRF_IOC         ((uint32_t)0x40000000U)  /*!< Interrupt Enabled on Completion  */
-#define ETH_DMARXNDESCRF_BUF2V       ((uint32_t)0x02000000U)  /*!< Buffer 2 Address Valid */
-#define ETH_DMARXNDESCRF_BUF1V       ((uint32_t)0x01000000U)  /*!< Buffer 1 Address Valid */
+#define ETH_DMARXNDESCRF_OWN              0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
+#define ETH_DMARXNDESCRF_IOC              0x40000000U  /*!< Interrupt Enabled on Completion  */
+#define ETH_DMARXNDESCRF_BUF2V            0x02000000U  /*!< Buffer 2 Address Valid */
+#define ETH_DMARXNDESCRF_BUF1V            0x01000000U  /*!< Buffer 1 Address Valid */
 
 /*
   DMA Rx Normal Descriptor write back format
   ---------------------------------------------------------------------------------------------------------------------
-  RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                | 
-	---------------------------------------------------------------------------------------------------------------------
+  RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
+  ---------------------------------------------------------------------------------------------------------------------
   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
   ---------------------------------------------------------------------------------------------------------------------
   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
@@ -762,89 +889,88 @@ typedef struct{
   ---------------------------------------------------------------------------------------------------------------------
 */
 
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 0 write back format
   */
-#define ETH_DMARXNDESCWBF_IVT        ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag  */
-#define ETH_DMARXNDESCWBF_OVT        ((uint32_t)0x0000FFFFU)  /*!< Outer VLAN Tag  */
+#define ETH_DMARXNDESCWBF_IVT             0xFFFF0000U  /*!< Inner VLAN Tag  */
+#define ETH_DMARXNDESCWBF_OVT             0x0000FFFFU  /*!< Outer VLAN Tag  */
 
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 1 write back format
   */
-#define ETH_DMARXNDESCWBF_OPC             ((uint32_t)0xFFFF0000U)  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
-#define ETH_DMARXNDESCWBF_TD              ((uint32_t)0x00008000U)  /*!< Timestamp Dropped  */
-#define ETH_DMARXNDESCWBF_TSA             ((uint32_t)0x00004000U)  /*!< Timestamp Available  */
-#define ETH_DMARXNDESCWBF_PV              ((uint32_t)0x00002000U)  /*!< PTP Version  */
-#define ETH_DMARXNDESCWBF_PFT             ((uint32_t)0x00001000U)  /*!< PTP Packet Type  */
-#define ETH_DMARXNDESCWBF_PMT_NO          ((uint32_t)0x00000000U)  /*!< PTP Message Type: No PTP message received  */
-#define ETH_DMARXNDESCWBF_PMT_SYNC        ((uint32_t)0x00000100U)  /*!< PTP Message Type: SYNC (all clock types)  */
-#define ETH_DMARXNDESCWBF_PMT_FUP         ((uint32_t)0x00000200U)  /*!< PTP Message Type: Follow_Up (all clock types)  */
-#define ETH_DMARXNDESCWBF_PMT_DREQ        ((uint32_t)0x00000300U)  /*!< PTP Message Type: Delay_Req (all clock types)  */
-#define ETH_DMARXNDESCWBF_PMT_DRESP       ((uint32_t)0x00000400U)  /*!< PTP Message Type: Delay_Resp (all clock types)  */
-#define ETH_DMARXNDESCWBF_PMT_PDREQ       ((uint32_t)0x00000500U)  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
-#define ETH_DMARXNDESCWBF_PMT_PDRESP      ((uint32_t)0x00000600U)  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
-#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   ((uint32_t)0x00000700U)  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
-#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    ((uint32_t)0x00000800U)  /*!< PTP Message Type: Announce  */
-#define ETH_DMARXNDESCWBF_PMT_MANAG       ((uint32_t)0x00000900U)  /*!< PTP Message Type: Management  */
-#define ETH_DMARXNDESCWBF_PMT_SIGN        ((uint32_t)0x00000A00U)  /*!< PTP Message Type: Signaling  */
-#define ETH_DMARXNDESCWBF_PMT_RESERVED    ((uint32_t)0x00000F00U)  /*!< PTP Message Type: PTP packet with Reserved message type  */
-#define ETH_DMARXNDESCWBF_IPCE            ((uint32_t)0x00000080U)  /*!< IP Payload Error */
-#define ETH_DMARXNDESCWBF_IPCB            ((uint32_t)0x00000040U)  /*!< IP Checksum Bypassed */
-#define ETH_DMARXNDESCWBF_IPV6            ((uint32_t)0x00000020U)  /*!< IPv6 header Present */
-#define ETH_DMARXNDESCWBF_IPV4            ((uint32_t)0x00000010U)  /*!< IPv4 header Present */
-#define ETH_DMARXNDESCWBF_IPHE            ((uint32_t)0x00000008U)  /*!< IP Header Error */
-#define ETH_DMARXNDESCWBF_PT              ((uint32_t)0x00000003U)  /*!< Payload Type mask */
-#define ETH_DMARXNDESCWBF_PT_UNKNOWN      ((uint32_t)0x00000000U)  /*!< Payload Type: Unknown type or IP/AV payload not processed */
-#define ETH_DMARXNDESCWBF_PT_UDP          ((uint32_t)0x00000001U)  /*!< Payload Type: UDP */
-#define ETH_DMARXNDESCWBF_PT_TCP          ((uint32_t)0x00000002U)  /*!< Payload Type: TCP  */
-#define ETH_DMARXNDESCWBF_PT_ICMP         ((uint32_t)0x00000003U)  /*!< Payload Type: ICMP */
+#define ETH_DMARXNDESCWBF_OPC             0xFFFF0000U  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
+#define ETH_DMARXNDESCWBF_TD              0x00008000U  /*!< Timestamp Dropped  */
+#define ETH_DMARXNDESCWBF_TSA             0x00004000U  /*!< Timestamp Available  */
+#define ETH_DMARXNDESCWBF_PV              0x00002000U  /*!< PTP Version  */
+#define ETH_DMARXNDESCWBF_PFT             0x00001000U  /*!< PTP Packet Type  */
+#define ETH_DMARXNDESCWBF_PMT_NO          0x00000000U  /*!< PTP Message Type: No PTP message received  */
+#define ETH_DMARXNDESCWBF_PMT_SYNC        0x00000100U  /*!< PTP Message Type: SYNC (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_FUP         0x00000200U  /*!< PTP Message Type: Follow_Up (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_DREQ        0x00000300U  /*!< PTP Message Type: Delay_Req (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_DRESP       0x00000400U  /*!< PTP Message Type: Delay_Resp (all clock types)  */
+#define ETH_DMARXNDESCWBF_PMT_PDREQ       0x00000500U  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_PDRESP      0x00000600U  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   0x00000700U  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
+#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    0x00000800U  /*!< PTP Message Type: Announce  */
+#define ETH_DMARXNDESCWBF_PMT_MANAG       0x00000900U  /*!< PTP Message Type: Management  */
+#define ETH_DMARXNDESCWBF_PMT_SIGN        0x00000A00U  /*!< PTP Message Type: Signaling  */
+#define ETH_DMARXNDESCWBF_PMT_RESERVED    0x00000F00U  /*!< PTP Message Type: PTP packet with Reserved message type  */
+#define ETH_DMARXNDESCWBF_IPCE            0x00000080U  /*!< IP Payload Error */
+#define ETH_DMARXNDESCWBF_IPCB            0x00000040U  /*!< IP Checksum Bypassed */
+#define ETH_DMARXNDESCWBF_IPV6            0x00000020U  /*!< IPv6 header Present */
+#define ETH_DMARXNDESCWBF_IPV4            0x00000010U  /*!< IPv4 header Present */
+#define ETH_DMARXNDESCWBF_IPHE            0x00000008U  /*!< IP Header Error */
+#define ETH_DMARXNDESCWBF_PT              0x00000003U  /*!< Payload Type mask */
+#define ETH_DMARXNDESCWBF_PT_UNKNOWN      0x00000000U  /*!< Payload Type: Unknown type or IP/AV payload not processed */
+#define ETH_DMARXNDESCWBF_PT_UDP          0x00000001U  /*!< Payload Type: UDP */
+#define ETH_DMARXNDESCWBF_PT_TCP          0x00000002U  /*!< Payload Type: TCP  */
+#define ETH_DMARXNDESCWBF_PT_ICMP         0x00000003U  /*!< Payload Type: ICMP */
 
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 2 write back format
   */
-#define ETH_DMARXNDESCWBF_L3L4FM          ((uint32_t)0x20000000U)  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
-#define ETH_DMARXNDESCWBF_L4FM            ((uint32_t)0x10000000U)  /*!< Layer 4 Filter Match                  */
-#define ETH_DMARXNDESCWBF_L3FM            ((uint32_t)0x08000000U)  /*!< Layer 3 Filter Match                  */
-#define ETH_DMARXNDESCWBF_MADRM           ((uint32_t)0x07F80000U)  /*!< MAC Address Match or Hash Value       */
-#define ETH_DMARXNDESCWBF_HF              ((uint32_t)0x00040000U)  /*!< Hash Filter Status                    */
-#define ETH_DMARXNDESCWBF_DAF             ((uint32_t)0x00020000U)  /*!< Destination Address Filter Fail       */
-#define ETH_DMARXNDESCWBF_SAF             ((uint32_t)0x00010000U)  /*!< SA Address Filter Fail                */
-#define ETH_DMARXNDESCWBF_VF              ((uint32_t)0x00008000U)  /*!< VLAN Filter Status                    */
-#define ETH_DMARXNDESCWBF_ARPNR           ((uint32_t)0x00000400U)  /*!< ARP Reply Not Generated               */
+#define ETH_DMARXNDESCWBF_L3L4FM          0x20000000U  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
+#define ETH_DMARXNDESCWBF_L4FM            0x10000000U  /*!< Layer 4 Filter Match                  */
+#define ETH_DMARXNDESCWBF_L3FM            0x08000000U  /*!< Layer 3 Filter Match                  */
+#define ETH_DMARXNDESCWBF_MADRM           0x07F80000U  /*!< MAC Address Match or Hash Value       */
+#define ETH_DMARXNDESCWBF_HF              0x00040000U  /*!< Hash Filter Status                    */
+#define ETH_DMARXNDESCWBF_DAF             0x00020000U  /*!< Destination Address Filter Fail       */
+#define ETH_DMARXNDESCWBF_SAF             0x00010000U  /*!< SA Address Filter Fail                */
+#define ETH_DMARXNDESCWBF_VF              0x00008000U  /*!< VLAN Filter Status                    */
+#define ETH_DMARXNDESCWBF_ARPNR           0x00000400U  /*!< ARP Reply Not Generated               */
 
-
-/** 
+/**
   * @brief  Bit definition of Rx normal descriptor register 3 write back format
   */
-#define ETH_DMARXNDESCWBF_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit */
-#define ETH_DMARXNDESCWBF_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor */
-#define ETH_DMARXNDESCWBF_FD         ((uint32_t)0x20000000U)  /*!< First Descriptor */
-#define ETH_DMARXNDESCWBF_LD         ((uint32_t)0x10000000U)  /*!< Last Descriptor */
-#define ETH_DMARXNDESCWBF_RS2V       ((uint32_t)0x08000000U)  /*!< Receive Status RDES2 Valid */
-#define ETH_DMARXNDESCWBF_RS1V       ((uint32_t)0x04000000U)  /*!< Receive Status RDES1 Valid */
-#define ETH_DMARXNDESCWBF_RS0V       ((uint32_t)0x02000000U)  /*!< Receive Status RDES0 Valid */
-#define ETH_DMARXNDESCWBF_CE         ((uint32_t)0x01000000U)  /*!< CRC Error */
-#define ETH_DMARXNDESCWBF_GP         ((uint32_t)0x00800000U)  /*!< Giant Packet */
-#define ETH_DMARXNDESCWBF_RWT        ((uint32_t)0x00400000U)  /*!< Receive Watchdog Timeout */
-#define ETH_DMARXNDESCWBF_OE         ((uint32_t)0x00200000U)  /*!< Overflow Error */
-#define ETH_DMARXNDESCWBF_RE         ((uint32_t)0x00100000U)  /*!< Receive Error */
-#define ETH_DMARXNDESCWBF_DE         ((uint32_t)0x00080000U)  /*!< Dribble Bit Error */
-#define ETH_DMARXNDESCWBF_LT         ((uint32_t)0x00070000U)  /*!< Length/Type Field */
-#define ETH_DMARXNDESCWBF_LT_LP      ((uint32_t)0x00000000U)  /*!< The packet is a length packet */
-#define ETH_DMARXNDESCWBF_LT_TP      ((uint32_t)0x00010000U)  /*!< The packet is a type packet */
-#define ETH_DMARXNDESCWBF_LT_ARP     ((uint32_t)0x00030000U)  /*!< The packet is a ARP Request packet type */
-#define ETH_DMARXNDESCWBF_LT_VLAN    ((uint32_t)0x00040000U)  /*!< The packet is a type packet with VLAN Tag */
-#define ETH_DMARXNDESCWBF_LT_DVLAN   ((uint32_t)0x00050000U)  /*!< The packet is a type packet with Double VLAN Tag */
-#define ETH_DMARXNDESCWBF_LT_MAC     ((uint32_t)0x00060000U)  /*!< The packet is a MAC Control packet type */
-#define ETH_DMARXNDESCWBF_LT_OAM     ((uint32_t)0x00070000U)  /*!< The packet is a OAM packet type */
-#define ETH_DMARXNDESCWBF_ES         ((uint32_t)0x00008000U)  /*!< Error Summary */
-#define ETH_DMARXNDESCWBF_PL         ((uint32_t)0x00007FFFU)  /*!< Packet Length */
+#define ETH_DMARXNDESCWBF_OWN             0x80000000U  /*!< Own Bit */
+#define ETH_DMARXNDESCWBF_CTXT            0x40000000U  /*!< Receive Context Descriptor */
+#define ETH_DMARXNDESCWBF_FD              0x20000000U  /*!< First Descriptor */
+#define ETH_DMARXNDESCWBF_LD              0x10000000U  /*!< Last Descriptor */
+#define ETH_DMARXNDESCWBF_RS2V            0x08000000U  /*!< Receive Status RDES2 Valid */
+#define ETH_DMARXNDESCWBF_RS1V            0x04000000U  /*!< Receive Status RDES1 Valid */
+#define ETH_DMARXNDESCWBF_RS0V            0x02000000U  /*!< Receive Status RDES0 Valid */
+#define ETH_DMARXNDESCWBF_CE              0x01000000U  /*!< CRC Error */
+#define ETH_DMARXNDESCWBF_GP              0x00800000U  /*!< Giant Packet */
+#define ETH_DMARXNDESCWBF_RWT             0x00400000U  /*!< Receive Watchdog Timeout */
+#define ETH_DMARXNDESCWBF_OE              0x00200000U  /*!< Overflow Error */
+#define ETH_DMARXNDESCWBF_RE              0x00100000U  /*!< Receive Error */
+#define ETH_DMARXNDESCWBF_DE              0x00080000U  /*!< Dribble Bit Error */
+#define ETH_DMARXNDESCWBF_LT              0x00070000U  /*!< Length/Type Field */
+#define ETH_DMARXNDESCWBF_LT_LP           0x00000000U  /*!< The packet is a length packet */
+#define ETH_DMARXNDESCWBF_LT_TP           0x00010000U  /*!< The packet is a type packet */
+#define ETH_DMARXNDESCWBF_LT_ARP          0x00030000U  /*!< The packet is a ARP Request packet type */
+#define ETH_DMARXNDESCWBF_LT_VLAN         0x00040000U  /*!< The packet is a type packet with VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_DVLAN        0x00050000U  /*!< The packet is a type packet with Double VLAN Tag */
+#define ETH_DMARXNDESCWBF_LT_MAC          0x00060000U  /*!< The packet is a MAC Control packet type */
+#define ETH_DMARXNDESCWBF_LT_OAM          0x00070000U  /*!< The packet is a OAM packet type */
+#define ETH_DMARXNDESCWBF_ES              0x00008000U  /*!< Error Summary */
+#define ETH_DMARXNDESCWBF_PL              0x00007FFFU  /*!< Packet Length */
 
 /*
   DMA Rx context Descriptor
   ---------------------------------------------------------------------------------------------------------------------
-  RDES0 |                                     Timestamp Low[31:0]                                                     | 
-	---------------------------------------------------------------------------------------------------------------------
+  RDES0 |                                     Timestamp Low[31:0]                                                     |
+  ---------------------------------------------------------------------------------------------------------------------
   RDES1 |                                     Timestamp High[31:0]                                                    |
   ---------------------------------------------------------------------------------------------------------------------
   RDES2 |                                          Reserved                                                           |
@@ -853,21 +979,21 @@ typedef struct{
   ---------------------------------------------------------------------------------------------------------------------
 */
 
-/** 
-  * @brief  Bit definition of Rx context descriptor register 0 
+/**
+  * @brief  Bit definition of Rx context descriptor register 0
   */
-#define ETH_DMARXCDESC_RTSL        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp Low  */
+#define ETH_DMARXCDESC_RTSL                   0xFFFFFFFFU  /*!< Receive Packet Timestamp Low  */
 
-/** 
+/**
   * @brief  Bit definition of Rx context descriptor register 1
   */
-#define ETH_DMARXCDESC_RTSH        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp High  */
+#define ETH_DMARXCDESC_RTSH                   0xFFFFFFFFU  /*!< Receive Packet Timestamp High  */
 
-/** 
+/**
   * @brief  Bit definition of Rx context descriptor register 3
   */
-#define ETH_DMARXCDESC_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit  */
-#define ETH_DMARXCDESC_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor  */
+#define ETH_DMARXCDESC_OWN                    0x80000000U  /*!< Own Bit  */
+#define ETH_DMARXCDESC_CTXT                   0x40000000U  /*!< Receive Context Descriptor  */
 
 /**
   * @}
@@ -875,29 +1001,29 @@ typedef struct{
 
 /** @defgroup ETH_Frame_settings ETH frame settings
   * @{
-  */ 
-#define ETH_MAX_PACKET_SIZE      ((uint32_t)1528U)    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC                  ((uint32_t)4U)    /*!< Ethernet CRC */
-#define ETH_VLAN_TAG             ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_PAYLOAD          ((uint32_t)46U)    /*!< Minimum Ethernet payload size */
-#define ETH_MAX_PAYLOAD          ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD  ((uint32_t)9000U)    /*!< Jumbo frame payload size */
+  */
+#define ETH_MAX_PACKET_SIZE                   1528U    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER                            14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC                               4U    /*!< Ethernet CRC */
+#define ETH_VLAN_TAG                          4U    /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_PAYLOAD                       46U    /*!< Minimum Ethernet payload size */
+#define ETH_MAX_PAYLOAD                       1500U    /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD               9000U    /*!< Jumbo frame payload size */
 /**
   * @}
   */
 
 /** @defgroup ETH_Error_Code ETH Error Code
   * @{
-  */ 
-#define HAL_ETH_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */
-#define HAL_ETH_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */
-#define HAL_ETH_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */
-#define HAL_ETH_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */
-#define HAL_ETH_ERROR_DMA          ((uint32_t)0x00000008U)   /*!< DMA transfer error  */
-#define HAL_ETH_ERROR_MAC          ((uint32_t)0x00000010U)   /*!< MAC transfer error  */
+  */
+#define HAL_ETH_ERROR_NONE                    0x00000000U   /*!< No error            */
+#define HAL_ETH_ERROR_PARAM                   0x00000001U   /*!< Busy error          */
+#define HAL_ETH_ERROR_BUSY                    0x00000002U   /*!< Parameter error     */
+#define HAL_ETH_ERROR_TIMEOUT                 0x00000004U   /*!< Timeout error       */
+#define HAL_ETH_ERROR_DMA                     0x00000008U   /*!< DMA transfer error  */
+#define HAL_ETH_ERROR_MAC                     0x00000010U   /*!< MAC transfer error  */
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
+#define HAL_ETH_ERROR_INVALID_CALLBACK        0x00000020U    /*!< Invalid Callback error  */
 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 /**
   * @}
@@ -906,12 +1032,12 @@ typedef struct{
 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
   * @{
   */
-#define ETH_TX_PACKETS_FEATURES_CSUM          ((uint32_t)0x00000001U)
-#define ETH_TX_PACKETS_FEATURES_SAIC          ((uint32_t)0x00000002U)
-#define ETH_TX_PACKETS_FEATURES_VLANTAG       ((uint32_t)0x00000004U)
-#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  ((uint32_t)0x00000008U)
-#define ETH_TX_PACKETS_FEATURES_TSO           ((uint32_t)0x00000010U)
-#define ETH_TX_PACKETS_FEATURES_CRCPAD        ((uint32_t)0x00000020U)
+#define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U
+#define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U
+#define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U
+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U
+#define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U
+#define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U
 /**
   * @}
   */
@@ -941,9 +1067,9 @@ typedef struct{
   * @{
   */
 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
-#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT     
-#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT              
-#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC         
+#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
 /**
   * @}
   */
@@ -953,7 +1079,7 @@ typedef struct{
   */
 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
-#define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT 
+#define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
 /**
   * @}
@@ -964,7 +1090,7 @@ typedef struct{
   */
 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
-#define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT 
+#define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
 /**
   * @}
@@ -1010,7 +1136,6 @@ typedef struct{
 /**
   * @}
   */
-
 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
   * @{
   */
@@ -1044,9 +1169,9 @@ typedef struct{
 
 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
   * @{
-  */ 
+  */
 #define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA
-#define ETH_DMAARBITRATION_RX1_TX1   ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_RX1_TX1   0x00000000U
 #define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1
 #define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1
 #define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1
@@ -1055,7 +1180,7 @@ typedef struct{
 #define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1
 #define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1
 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
-#define ETH_DMAARBITRATION_TX1_RX1   ((uint32_t)0x00000000U)
+#define ETH_DMAARBITRATION_TX1_RX1   0x00000000U
 #define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
 #define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
 #define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
@@ -1067,130 +1192,130 @@ typedef struct{
   * @}
   */
 
- /** @defgroup ETH_Burst_Mode ETH Burst Mode  
+/** @defgroup ETH_Burst_Mode ETH Burst Mode
   * @{
-  */ 
+  */
 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
 #define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB
-#define ETH_BURSTLENGTH_UNSPECIFIED     ((uint32_t)0x00000000U)
+#define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U
 /**
   * @}
   */
-	
+
 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
   * @{
-  */ 
-#define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL   
-#define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL   
-#define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL   
-#define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL   
-#define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL  
-#define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL                  
+  */
+#define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL
+#define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL
+#define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL
+#define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL
+#define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL
+#define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL
 /**
   * @}
   */
 
 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
   * @{
-  */ 
-#define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL   
-#define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL   
-#define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL   
-#define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL   
-#define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL  
-#define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL                  
+  */
+#define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL
+#define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL
+#define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL
+#define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL
+#define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL
+#define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL
 /**
   * @}
-  */	
-	
+  */
+
 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
   * @{
-  */	
-#define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE 
-#define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE 
+  */
+#define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE
+#define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE
 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE
 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE
 #define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE
 #define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE
 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE
-#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE 
+#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE
 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE
-#define ETH_DMA_RX_IT                     ETH_DMACIER_RIE 
+#define ETH_DMA_RX_IT                     ETH_DMACIER_RIE
 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE
 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE
-#define ETH_DMA_TX_IT                     ETH_DMACIER_TIE 
+#define ETH_DMA_TX_IT                     ETH_DMACIER_TIE
 /**
   * @}
   */
 
 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
   * @{
-  */	
-#define ETH_DMA_RX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
-#define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)     
-#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)       
-#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)      
-#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2
-#define ETH_DMA_TX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)
-#define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)     
-#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)      
-#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)     
-#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2
-#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE
-#define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE
-#define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI
-#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT
-#define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS
-#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU
-#define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS
-/**
-  * @}
-  */	
-	
-/** @defgroup ETH_Transmit_Mode ETH Transmit Mode 
-  * @{
-  */ 
-#define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
-#define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS  
-#define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS  
-#define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS  
-#define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS 
-#define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS 
-#define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS 
-#define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS 
-#define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS 
+  */
+#define ETH_DMA_RX_NO_ERROR_FLAG                 0x00000000U
+#define ETH_DMA_RX_DESC_READ_ERROR_FLAG          0x00380000U
+#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         0x00300000U
+#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        0x00280000U
+#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG       0x00200000U
+#define ETH_DMA_TX_NO_ERROR_FLAG                 0x00000000U
+#define ETH_DMA_TX_DESC_READ_ERROR_FLAG          0x00070000U
+#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         0x00060000U
+#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        0x00050000U
+#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG       0x00040000U
+#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG          ETH_DMACSR_CDE
+#define ETH_DMA_FATAL_BUS_ERROR_FLAG             ETH_DMACSR_FBE
+#define ETH_DMA_EARLY_TX_IT_FLAG                 ETH_DMACSR_ERI
+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG         ETH_DMACSR_RWT
+#define ETH_DMA_RX_PROCESS_STOPPED_FLAG          ETH_DMACSR_RPS
+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG       ETH_DMACSR_RBU
+#define ETH_DMA_TX_PROCESS_STOPPED_FLAG          ETH_DMACSR_TPS
 /**
   * @}
   */
 
-/** @defgroup ETH_Receive_Mode ETH Receive Mode 
+/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
   * @{
-  */ 
-#define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
-#define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS  
-#define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS  
-#define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS  
-#define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS 
+  */
+#define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF
+#define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS
+#define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS
+#define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS
+#define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS
+#define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS
+#define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS
+#define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS
+#define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS
 /**
   * @}
   */
-	
+
+/** @defgroup ETH_Receive_Mode ETH Receive Mode
+  * @{
+  */
+#define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF
+#define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS
+#define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS
+#define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS
+#define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS
+/**
+  * @}
+  */
+
 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
   * @{
-  */ 
-#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4  
-#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28 
-#define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36  
-#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144 
-#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256 
-#define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512 
+  */
+#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4
+#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28
+#define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36
+#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144
+#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256
+#define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512
 /**
   * @}
   */
-	
+
 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
   * @{
-  */ 
+  */
 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
@@ -1208,55 +1333,55 @@ typedef struct{
 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
 /**
   * @}
-  */  
+  */
 
 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
   * @{
-  */ 
-#define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT 
-#define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT 
-#define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT  
-#define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT 
-#define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT  
-#define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT  
-#define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT 
-#define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT 
+  */
+#define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
+#define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
+#define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
+#define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
+#define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
+#define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
+#define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
+#define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
 /**
   * @}
   */
 
 /** @defgroup ETH_Speed  ETH Speed
   * @{
-  */ 
-#define ETH_SPEED_10M        ((uint32_t)0x00000000U)
+  */
+#define ETH_SPEED_10M        0x00000000U
 #define ETH_SPEED_100M       ETH_MACCR_FES
 /**
   * @}
   */
 
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode 
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
   * @{
-  */ 
+  */
 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
-#define ETH_HALFDUPLEX_MODE       ((uint32_t)0x00000000U)
+#define ETH_HALFDUPLEX_MODE       0x00000000U
 /**
   * @}
   */
-	
+
 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
   * @{
-  */ 
+  */
 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
-#define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8 
-#define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4 
-#define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1 
+#define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
+#define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
+#define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
 /**
   * @}
   */
 
 /** @defgroup ETH_Preamble_Length ETH Preamble Length
   * @{
-  */ 
+  */
 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
@@ -1266,8 +1391,8 @@ typedef struct{
 
 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
   * @{
-  */ 
-#define ETH_SOURCEADDRESS_DISABLE           ((uint32_t)0x00000000U)
+  */
+#define ETH_SOURCEADDRESS_DISABLE           0x00000000U
 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0
 #define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1
 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0
@@ -1275,10 +1400,10 @@ typedef struct{
 /**
   * @}
   */
-  
+
 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
   * @{
-  */ 
+  */
 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
@@ -1286,11 +1411,11 @@ typedef struct{
 /**
   * @}
   */
-	
+
 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
   * @{
-  */ 
-#define ETH_VLANTAGCOMPARISON_16BIT          ((uint32_t)0x00000000U)
+  */
+#define ETH_VLANTAGCOMPARISON_16BIT          0x00000000U
 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV
 /**
   * @}
@@ -1298,20 +1423,20 @@ typedef struct{
 
 /** @defgroup ETH_MAC_addresses ETH MAC addresses
   * @{
-  */ 
-#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)
-#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)
-#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)
-#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)
+  */
+#define ETH_MAC_ADDRESS0     0x00000000U
+#define ETH_MAC_ADDRESS1     0x00000008U
+#define ETH_MAC_ADDRESS2     0x00000010U
+#define ETH_MAC_ADDRESS3     0x00000018U
 /**
   * @}
-  */    
- 
+  */
+
 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
   * @{
-  */	
-#define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE 
-#define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE 
+  */
+#define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
+#define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
@@ -1322,9 +1447,9 @@ typedef struct{
 
 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
   * @{
-  */	
-#define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD 
-#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD 
+  */
+#define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
+#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
 /**
   * @}
   */
@@ -1334,27 +1459,36 @@ typedef struct{
   */
 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
-#define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL 
+#define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
-#define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT  	
+#define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
 /**
   * @}
   */
 
-/** @defgroup HAL_ETH_StateTypeDef ETH States
+/** @defgroup ETH_State_Codes ETH States
   * @{
   */
-#define HAL_ETH_STATE_RESET       ((uint32_t)0x00000000U)    /*!< Peripheral not yet Initialized or disabled */
-#define HAL_ETH_STATE_READY       ((uint32_t)0x00000010U)    /*!< Peripheral Communication started           */
-#define HAL_ETH_STATE_BUSY        ((uint32_t)0x00000023U)    /*!< an internal process is ongoing             */
-#define HAL_ETH_STATE_BUSY_TX     ((uint32_t)0x00000021U)    /*!< Transmission process is ongoing            */
-#define HAL_ETH_STATE_BUSY_RX     ((uint32_t)0x00000022U)    /*!< Reception process is ongoing               */
-#define HAL_ETH_STATE_ERROR       ((uint32_t)0x000000E0U)    /*!< Error State                                */
+#define HAL_ETH_STATE_RESET                0x00000000U    /*!< Peripheral not yet Initialized or disabled */
+#define HAL_ETH_STATE_READY                0x00000010U    /*!< Peripheral Communication started           */
+#define HAL_ETH_STATE_BUSY                 0x00000023U    /*!< an internal process is ongoing             */
+#define HAL_ETH_STATE_STARTED              0x00000023U    /*!< an internal process is started             */
+#define HAL_ETH_STATE_ERROR                0x000000E0U    /*!< Error State                                */
 /**
   * @}
   */
+
+/** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
+  * @{
+  */
+#define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U    /*!< ETH PTP Configuration not done */
+#define HAL_ETH_PTP_CONFIGURED            0x00000001U    /*!< ETH PTP Configuration done     */
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -1370,26 +1504,24 @@ typedef struct{
   */
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0)
+                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
+                                                      (__HANDLE__)->MspInitCallback = NULL;             \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                    } while(0)
 #else
 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \
-                                                     } while(0)
+                                                      (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
+                                                    } while(0)
 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
 
-/** 
+/**
   * @brief  Enables the specified ETHERNET DMA interrupts.
   * @param  __HANDLE__   : ETH Handle
   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
   *   enabled @ref ETH_DMA_Interrupts
   * @retval None
   */
-#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
 
 /**
   * @brief  Disables the specified ETHERNET DMA interrupts.
@@ -1398,7 +1530,7 @@ typedef struct{
   *   disabled. @ref ETH_DMA_Interrupts
   * @retval None
   */
-#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
 
 /**
   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
@@ -1406,7 +1538,8 @@ typedef struct{
   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
   * @retval The ETH DMA IT Source enabled or disabled
   */
-#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+  (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
 
 /**
   * @brief  Gets the ETHERNET DMA IT pending bit.
@@ -1414,65 +1547,68 @@ typedef struct{
   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
   * @retval The state of ETH DMA IT (SET or RESET)
   */
-#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
-    
+#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \
+  (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
+
 /**
   * @brief  Clears the ETHERNET DMA IT pending bit.
   * @param  __HANDLE__   : ETH Handle
   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
   * @retval None
   */
-#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
 
 /**
   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
-* @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__: ETH Handle
   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
   * @retval The state of ETH DMA FLAG (SET or RESET).
   */
-#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))  
+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
 
 /**
   * @brief  Clears the specified ETHERNET DMA flag.
-* @param  __HANDLE__: ETH Handle
+  * @param  __HANDLE__: ETH Handle
   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
   * @retval The state of ETH DMA FLAG (SET or RESET).
   */
-#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
-    
-/** 
+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
+
+/**
   * @brief  Enables the specified ETHERNET MAC interrupts.
   * @param  __HANDLE__   : ETH Handle
   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
   *   enabled @ref ETH_MAC_Interrupts
   * @retval None
   */
-#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
-    
-/** 
+
+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
+
+/**
   * @brief  Disables the specified ETHERNET MAC interrupts.
   * @param  __HANDLE__   : ETH Handle
   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
   *   enabled @ref ETH_MAC_Interrupts
   * @retval None
   */
-#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
-  
+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
+
 /**
   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
   * @param  __HANDLE__: ETH Handle
   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
   * @retval The state of ETH MAC IT (SET or RESET).
   */
-#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                   (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) 
+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACISR &\
+                                                                              ( __INTERRUPT__)) == ( __INTERRUPT__))
 
 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
-#define ETH_WAKEUP_EXTI_LINE  ((uint32_t)0x00400000U)  /* !<  86 - 64 = 22 */
+#define ETH_WAKEUP_EXTI_LINE  0x00400000U  /* !<  86 - 64 = 22 */
 
 /**
   * @brief Enable the ETH WAKEUP Exti Line.
   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
-  *   @arg ETH_WAKEUP_EXTI_LINE     
+  *   @arg ETH_WAKEUP_EXTI_LINE
   * @retval None.
   */
 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
@@ -1480,7 +1616,7 @@ typedef struct{
 /**
   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
-  *   @arg ETH_WAKEUP_EXTI_LINE  
+  *   @arg ETH_WAKEUP_EXTI_LINE
   * @retval EXTI ETH WAKEUP Line Status.
   */
 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))
@@ -1488,7 +1624,7 @@ typedef struct{
 /**
   * @brief Clear the ETH WAKEUP Exti flag.
   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
-  *   @arg ETH_WAKEUP_EXTI_LINE  
+  *   @arg ETH_WAKEUP_EXTI_LINE
   * @retval None.
   */
 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
@@ -1497,15 +1633,15 @@ typedef struct{
 /**
   * @brief Enable the ETH WAKEUP Exti Line by Core2.
   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
-  *   @arg ETH_WAKEUP_EXTI_LINE     
+  *   @arg ETH_WAKEUP_EXTI_LINE
   * @retval None.
   */
-#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__)) 
+#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__))
 
 /**
   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
-  *   @arg ETH_WAKEUP_EXTI_LINE  
+  *   @arg ETH_WAKEUP_EXTI_LINE
   * @retval EXTI ETH WAKEUP Line Status.
   */
 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))
@@ -1513,11 +1649,11 @@ typedef struct{
 /**
   * @brief Clear the ETH WAKEUP Exti flag.
   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
-  *   @arg ETH_WAKEUP_EXTI_LINE  
+  *   @arg ETH_WAKEUP_EXTI_LINE
   * @retval None.
   */
 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
-#endif
+#endif /* DUAL_CORE */
 
 /**
   * @brief  enable rising edge interrupt on selected EXTI line.
@@ -1526,7 +1662,7 @@ typedef struct{
   * @retval None
   */
 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
-                                                                (EXTI->RTSR3 |= (__EXTI_LINE__)) 
+  (EXTI->RTSR3 |= (__EXTI_LINE__))
 
 /**
   * @brief  enable falling edge interrupt on selected EXTI line.
@@ -1535,7 +1671,7 @@ typedef struct{
   * @retval None
   */
 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
-                                                                 (EXTI->FTSR3 |= (__EXTI_LINE__))
+  (EXTI->FTSR3 |= (__EXTI_LINE__))
 
 /**
   * @brief  enable falling edge interrupt on selected EXTI line.
@@ -1544,7 +1680,7 @@ typedef struct{
   * @retval None
   */
 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
-                                                                        (EXTI->FTSR3 |= (__EXTI_LINE__))
+  (EXTI->FTSR3 |= (__EXTI_LINE__))
 
 /**
   * @brief  Generates a Software interrupt on selected EXTI line.
@@ -1553,6 +1689,9 @@ typedef struct{
   * @retval None
   */
 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
+#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
+                                                           (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
 
 /**
   * @}
@@ -1566,20 +1705,20 @@ typedef struct{
 /** @addtogroup ETH_Exported_Functions
   * @{
   */
-  
+
 /** @addtogroup ETH_Exported_Functions_Group1
   * @{
-  */    
+  */
 /* Initialization and de initialization functions  **********************************/
-HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);                        
-HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);                      
-void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);                    
-void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);  
-HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
+void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
+                                           pETH_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
 
@@ -1596,26 +1735,50 @@ HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
 
-uint8_t           HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
-HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
-HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
-HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
+HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
+                                                     pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
+HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
 
-HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
-HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
+#ifdef HAL_ETH_USE_PTP
+HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
+HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
+HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
+                                            ETH_TimeTypeDef *timeoffset);
+HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
+HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
+HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
+HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
+#endif /* HAL_ETH_USE_PTP */
 
-HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);  
-HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); 
+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
+
+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                           uint32_t RegValue);
+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
+                                          uint32_t *pRegValue);
 
 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
-void              HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
+void              HAL_ETH_RxAllocateCallback(uint8_t **buff);
+void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
+void              HAL_ETH_TxFreeCallback(uint32_t *buff);
+void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
 /**
   * @}
   */
@@ -1625,23 +1788,26 @@ void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
   */
 /* Peripheral Control functions  **********************************************/
 /* MAC & DMA Configuration APIs  **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
-HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
+HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
 
 /* MAC VLAN Processing APIs    ************************************************/
-void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
+void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
+                                              uint32_t VLANIdentifier);
 
 /* MAC L2 Packet Filtering APIs  **********************************************/
-HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
-HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
-HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
+                                                const uint8_t *pMACAddr);
 
 /* MAC Power Down APIs    *****************************************************/
-void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
+void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
+                                             const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
 
@@ -1653,26 +1819,26 @@ HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFi
   * @{
   */
 /* Peripheral State functions  **************************************************/
-HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetError(ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
-uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
+HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
+uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
-  */ 
+  */
 
 #endif /* ETH */
 
@@ -1681,7 +1847,3 @@ uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
 #endif
 
 #endif /* STM32H7xx_HAL_ETH_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c
index 5672dfe4df..feb0cfd629 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.c
@@ -7,13 +7,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -34,7 +33,6 @@
   * @{
   */
 
-
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
 /** @defgroup ETHEx_Private_Constants ETHEx Private Constants
@@ -58,6 +56,9 @@
 
 #define ETH_MACTXVLAN_MASK (ETH_MACVIR_VLTI | ETH_MACVIR_CSVL | \
                             ETH_MACVIR_VLP | ETH_MACVIR_VLC)
+
+#define ETH_MAC_L4_SRSP_MASK          0x0000FFFFU
+#define ETH_MAC_L4_DSTP_MASK          0xFFFF0000U
 /**
   * @}
   */
@@ -71,7 +72,7 @@
 
 /** @defgroup ETHEx_Exported_Functions_Group1 Extended features functions
   * @brief    Extended features functions
- *
+  *
 @verbatim
  ===============================================================================
                       ##### Extended features functions #####
@@ -92,6 +93,7 @@
   *         the configuration information for ETHERNET module
   * @retval None
   */
+
 void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth)
 {
   SET_BIT(heth->Instance->MACCR, ETH_MACCR_ARP);
@@ -133,25 +135,35 @@ void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress)
   *         that contains L4 filter configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter , ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L4FilterConfigTypeDef *pL4FilterConfig)
 {
-  __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
-
-  if(pL4FilterConfig == NULL)
+  if (pL4FilterConfig == NULL)
   {
     return HAL_ERROR;
   }
 
-  /* Write configuration to (MACL3L4C0R + filter )register */
-  MODIFY_REG(*configreg, ETH_MACL4CR_MASK ,(pL4FilterConfig->Protocol |
-                                            pL4FilterConfig->SrcPortFilterMatch |
-                                              pL4FilterConfig->DestPortFilterMatch));
+  if (Filter == ETH_L4_FILTER_0)
+  {
+    /* Write configuration to MACL3L4C0R register */
+    MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
+                                                              pL4FilterConfig->SrcPortFilterMatch |
+                                                              pL4FilterConfig->DestPortFilterMatch));
 
-  configreg = ((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter));
+    /* Write configuration to MACL4A0R register */
+    WRITE_REG(heth->Instance->MACL4A0R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
 
-  /* Write configuration to (MACL4A0R + filter )register */
-  MODIFY_REG(*configreg, (ETH_MACL4AR_L4DP | ETH_MACL4AR_L4SP) , (pL4FilterConfig->SourcePort |
-                                                                                                                  (pL4FilterConfig->DestinationPort << 16)));
+  }
+  else /* Filter == ETH_L4_FILTER_1 */
+  {
+    /* Write configuration to MACL3L4C1R register */
+    MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL4CR_MASK, (pL4FilterConfig->Protocol |
+                                                              pL4FilterConfig->SrcPortFilterMatch |
+                                                              pL4FilterConfig->DestPortFilterMatch));
+
+    /* Write configuration to MACL4A1R register */
+    WRITE_REG(heth->Instance->MACL4A1R, (pL4FilterConfig->SourcePort | (pL4FilterConfig->DestinationPort << 16)));
+  }
 
   /* Enable L4 filter */
   SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
@@ -172,21 +184,40 @@ HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
   *         that contains L4 filter configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L4FilterConfigTypeDef *pL4FilterConfig)
 {
-  if(pL4FilterConfig == NULL)
+  if (pL4FilterConfig == NULL)
   {
     return HAL_ERROR;
   }
 
-  /* Get configuration to (MACL3L4C0R + filter )register */
-  pL4FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L4PEN);
-  pL4FilterConfig->DestPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
-  pL4FilterConfig->SrcPortFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+  if (Filter == ETH_L4_FILTER_0)
+  {
+    /* Get configuration from MACL3L4C0R register */
+    pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C0R, ETH_MACL3L4CR_L4PEN);
+    pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
+                                                    (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+    pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C0R,
+                                                   (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
 
-  /* Get configuration to (MACL3L4C0R + filter )register */
-  pL4FilterConfig->DestinationPort = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4DP) >> 16);
-  pL4FilterConfig->SourcePort = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL4A0R) + Filter)), ETH_MACL4AR_L4SP);
+    /* Get configuration from MACL4A0R register */
+    pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_DSTP_MASK) >> 16);
+    pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A0R, ETH_MAC_L4_SRSP_MASK);
+  }
+  else /* Filter == ETH_L4_FILTER_1 */
+  {
+    /* Get configuration from MACL3L4C1R register */
+    pL4FilterConfig->Protocol = READ_BIT(heth->Instance->MACL3L4C1R, ETH_MACL3L4CR_L4PEN);
+    pL4FilterConfig->DestPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
+                                                    (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM));
+    pL4FilterConfig->SrcPortFilterMatch = READ_BIT(heth->Instance->MACL3L4C1R,
+                                                   (ETH_MACL3L4CR_L4SPM | ETH_MACL3L4CR_L4SPIM));
+
+    /* Get configuration from MACL4A1R register */
+    pL4FilterConfig->DestinationPort = (READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_DSTP_MASK) >> 16);
+    pL4FilterConfig->SourcePort = READ_BIT(heth->Instance->MACL4A1R, ETH_MAC_L4_SRSP_MASK);
+  }
 
   return HAL_OK;
 }
@@ -204,43 +235,84 @@ HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t
   *         that contains L3 filter configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L3FilterConfigTypeDef *pL3FilterConfig)
 {
-  __IO uint32_t *configreg = ((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter));
-
-  if(pL3FilterConfig == NULL)
+  if (pL3FilterConfig == NULL)
   {
     return HAL_ERROR;
   }
 
-  /* Write configuration to (MACL3L4C0R + filter )register */
-  MODIFY_REG(*configreg, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
-                                            pL3FilterConfig->SrcAddrFilterMatch |
-                                              pL3FilterConfig->DestAddrFilterMatch |
-                                                (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
-                                                  (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+  if (Filter == ETH_L3_FILTER_0)
+  {
+    /* Write configuration to MACL3L4C0R register */
+    MODIFY_REG(heth->Instance->MACL3L4C0R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+                                                              pL3FilterConfig->SrcAddrFilterMatch |
+                                                              pL3FilterConfig->DestAddrFilterMatch |
+                                                              (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+                                                              (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+  }
+  else  /* Filter == ETH_L3_FILTER_1 */
+  {
+    /* Write configuration to MACL3L4C1R register */
+    MODIFY_REG(heth->Instance->MACL3L4C1R, ETH_MACL3CR_MASK, (pL3FilterConfig->Protocol |
+                                                              pL3FilterConfig->SrcAddrFilterMatch |
+                                                              pL3FilterConfig->DestAddrFilterMatch |
+                                                              (pL3FilterConfig->SrcAddrHigherBitsMatch << 6) |
+                                                              (pL3FilterConfig->DestAddrHigherBitsMatch << 11)));
+  }
 
-  /* Check if IPv6 protocol is selected */
-  if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+  if (Filter == ETH_L3_FILTER_0)
   {
-    /* Set the IPv6 address match */
-    /* Set Bits[31:0] of 128-bit IP addr */
-    *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip6Addr[0];
-    /* Set Bits[63:32] of 128-bit IP addr */
-    *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip6Addr[1];
-    /* update Bits[95:64] of 128-bit IP addr */
-    *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter)) = pL3FilterConfig->Ip6Addr[2];
-    /* update Bits[127:96] of 128-bit IP addr */
-    *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter)) = pL3FilterConfig->Ip6Addr[3];
+    /* Check if IPv6 protocol is selected */
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      /* Set the IPv6 address match */
+      /* Set Bits[31:0] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip6Addr[0]);
+      /* Set Bits[63:32] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip6Addr[1]);
+      /* update Bits[95:64] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A2R0R, pL3FilterConfig->Ip6Addr[2]);
+      /* update Bits[127:96] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A3R0R, pL3FilterConfig->Ip6Addr[3]);
+    }
+    else /* IPv4 protocol is selected */
+    {
+      /* Set the IPv4 source address match */
+      WRITE_REG(heth->Instance->MACL3A0R0R, pL3FilterConfig->Ip4SrcAddr);
+      /* Set the IPv4 destination address match */
+      WRITE_REG(heth->Instance->MACL3A1R0R, pL3FilterConfig->Ip4DestAddr);
+    }
   }
-  else /* IPv4 protocol is selected */
+  else  /* Filter == ETH_L3_FILTER_1 */
   {
-    /* Set the IPv4 source address match */
-    *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter)) = pL3FilterConfig->Ip4SrcAddr;
-    /* Set the IPv4 destination address match */
-    *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter)) = pL3FilterConfig->Ip4DestAddr;
+    /* Check if IPv6 protocol is selected */
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      /* Set the IPv6 address match */
+      /* Set Bits[31:0] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip6Addr[0]);
+      /* Set Bits[63:32] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[1]);
+      /* update Bits[95:64] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[2]);
+      /* update Bits[127:96] of 128-bit IP addr */
+      WRITE_REG(heth->Instance->MACL3A1R1R, pL3FilterConfig->Ip6Addr[3]);
+    }
+    else /* IPv4 protocol is selected */
+    {
+      /* Set the IPv4 source address match */
+      WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4SrcAddr);
+      /* Set the IPv4 destination address match */
+      WRITE_REG(heth->Instance->MACL3A0R1R, pL3FilterConfig->Ip4DestAddr);
+
+    }
   }
 
+  /* Enable L3 filter */
+  SET_BIT(heth->Instance->MACPFR, ETH_MACPFR_IPFE);
+
   return HAL_OK;
 }
 
@@ -257,30 +329,53 @@ HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t
   *         that will contain the L3 filter configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L3FilterConfigTypeDef *pL3FilterConfig)
 {
-  if(pL3FilterConfig == NULL)
+  if (pL3FilterConfig == NULL)
   {
     return HAL_ERROR;
   }
+  pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                       ETH_MACL3L4CR_L3PEN);
+  pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                 (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
+  pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                  (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
+  pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                      ETH_MACL3L4CR_L3HSBM) >> 6);
+  pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)),
+                                                       ETH_MACL3L4CR_L3HDBM) >> 11);
 
-  pL3FilterConfig->Protocol = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3PEN);
-  pL3FilterConfig->SrcAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM));
-  pL3FilterConfig->DestAddrFilterMatch = READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM));
-  pL3FilterConfig->SrcAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HSBM) >> 6);
-  pL3FilterConfig->DestAddrHigherBitsMatch = (READ_BIT(*((__IO uint32_t *)(&(heth->Instance->MACL3L4C0R) + Filter)), ETH_MACL3L4CR_L3HDBM) >> 11);
-
-  if(pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+  if (Filter == ETH_L3_FILTER_0)
   {
-    pL3FilterConfig->Ip6Addr[0] = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
-    pL3FilterConfig->Ip6Addr[1] = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
-    pL3FilterConfig->Ip6Addr[2] = *((__IO uint32_t *)(&(heth->Instance->MACL3A2R0R) + Filter));
-    pL3FilterConfig->Ip6Addr[3] = *((__IO uint32_t *)(&(heth->Instance->MACL3A3R0R) + Filter));
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R0R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R0R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R0R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R0R);
+    }
+    else
+    {
+      WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R0R);
+      WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R0R);
+    }
   }
-  else
+  else /* ETH_L3_FILTER_1 */
   {
-    pL3FilterConfig->Ip4SrcAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A0R0R) + Filter));
-    pL3FilterConfig->Ip4DestAddr = *((__IO uint32_t *)(&(heth->Instance->MACL3A1R0R) + Filter));
+    if (pL3FilterConfig->Protocol != ETH_L3_IPV4_MATCH)
+    {
+      WRITE_REG(pL3FilterConfig->Ip6Addr[0], heth->Instance->MACL3A0R1R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[1], heth->Instance->MACL3A1R1R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[2], heth->Instance->MACL3A2R1R);
+      WRITE_REG(pL3FilterConfig->Ip6Addr[3], heth->Instance->MACL3A3R1R);
+    }
+    else
+    {
+      WRITE_REG(pL3FilterConfig->Ip4SrcAddr, heth->Instance->MACL3A0R1R);
+      WRITE_REG(pL3FilterConfig->Ip4DestAddr, heth->Instance->MACL3A1R1R);
+    }
   }
 
   return HAL_OK;
@@ -318,22 +413,29 @@ void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth)
   *         that will contain the VLAN filter configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
 {
-  if(pVlanConfig == NULL)
+  if (pVlanConfig == NULL)
   {
     return HAL_ERROR;
   }
 
-  pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->InnerVLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
+                                                 ETH_MACVTR_EIVLRXS) >> 31) == 0U) ? DISABLE : ENABLE;
   pVlanConfig->StripInnerVLANTag  = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EIVLS);
-  pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
-  pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
-  pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
-  pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->InnerVLANTag = ((READ_BIT(heth->Instance->MACVTR,
+                                         ETH_MACVTR_ERIVLT) >> 27) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->DoubleVLANProcessing = ((READ_BIT(heth->Instance->MACVTR,
+                                                 ETH_MACVTR_EDVLP) >> 26) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagHashTableMatch = ((READ_BIT(heth->Instance->MACVTR,
+                                                  ETH_MACVTR_VTHM) >> 25) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTagInStatus = ((READ_BIT(heth->Instance->MACVTR,
+                                            ETH_MACVTR_EVLRXS) >> 24) == 0U) ? DISABLE : ENABLE;
   pVlanConfig->StripVLANTag = READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_EVLS);
-  pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR, (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
-  pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U) ? DISABLE : ENABLE;
+  pVlanConfig->VLANTypeCheck = READ_BIT(heth->Instance->MACVTR,
+                                        (ETH_MACVTR_DOVLTC | ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL));
+  pVlanConfig->VLANTagInverceMatch = ((READ_BIT(heth->Instance->MACVTR, ETH_MACVTR_VTIM) >> 17) == 0U)
+                                     ? DISABLE : ENABLE;
 
   return HAL_OK;
 }
@@ -348,7 +450,7 @@ HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
   */
 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig)
 {
-  if(pVlanConfig == NULL)
+  if (pVlanConfig == NULL)
   {
     return HAL_ERROR;
   }
@@ -356,13 +458,13 @@ HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANC
   /* Write config to MACVTR */
   MODIFY_REG(heth->Instance->MACVTR, ETH_MACRXVLAN_MASK, (((uint32_t)pVlanConfig->InnerVLANTagInStatus << 31) |
                                                           pVlanConfig->StripInnerVLANTag |
-                                                            ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
-                                                              ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
-                                                                ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
-                                                                  ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
-                                                                    pVlanConfig->StripVLANTag |
-                                                                      pVlanConfig->VLANTypeCheck |
-                                                                        ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
+                                                          ((uint32_t)pVlanConfig->InnerVLANTag << 27) |
+                                                          ((uint32_t)pVlanConfig->DoubleVLANProcessing << 26) |
+                                                          ((uint32_t)pVlanConfig->VLANTagHashTableMatch << 25) |
+                                                          ((uint32_t)pVlanConfig->VLANTagInStatus << 24) |
+                                                          pVlanConfig->StripVLANTag |
+                                                          pVlanConfig->VLANTypeCheck |
+                                                          ((uint32_t)pVlanConfig->VLANTagInverceMatch << 17)));
 
   return HAL_OK;
 }
@@ -390,14 +492,15 @@ void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable)
   *         that will contain the Tx VLAN filter configuration.
   * @retval HAL Status.
   */
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            ETH_TxVLANConfigTypeDef *pVlanConfig)
 {
   if (pVlanConfig == NULL)
   {
     return HAL_ERROR;
   }
 
-  if(VLANTag == ETH_INNER_TX_VLANTAG)
+  if (VLANTag == ETH_INNER_TX_VLANTAG)
   {
     pVlanConfig->SourceTxDesc = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_VLTI) >> 20) == 0U) ? DISABLE : ENABLE;
     pVlanConfig->SVLANType = ((READ_BIT(heth->Instance->MACIVIR, ETH_MACVIR_CSVL) >> 19) == 0U) ? DISABLE : ENABLE;
@@ -424,13 +527,14 @@ HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
   *         that contains Tx VLAN filter configuration.
   * @retval HAL Status
   */
-HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig)
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            const ETH_TxVLANConfigTypeDef *pVlanConfig)
 {
-  if(VLANTag == ETH_INNER_TX_VLANTAG)
+  if (VLANTag == ETH_INNER_TX_VLANTAG)
   {
     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
-                                                            ((uint32_t)pVlanConfig->SVLANType << 19) |
-                                                              pVlanConfig->VLANTagControl));
+                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
+                                                             pVlanConfig->VLANTagControl));
     /* Enable Double VLAN processing */
     SET_BIT(heth->Instance->MACVTR, ETH_MACVTR_EDVLP);
   }
@@ -438,7 +542,7 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
   {
     MODIFY_REG(heth->Instance->MACVIR, ETH_MACTXVLAN_MASK, (((uint32_t)pVlanConfig->SourceTxDesc << 20) |
                                                             ((uint32_t)pVlanConfig->SVLANType << 19) |
-                                                              pVlanConfig->VLANTagControl));
+                                                            pVlanConfig->VLANTagControl));
   }
 
   return HAL_OK;
@@ -454,9 +558,9 @@ HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VL
   * @param  VLANIdentifier: VLAN Identifier 16 bit value
   * @retval None
   */
-void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier)
+void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier)
 {
-  if(VLANTag == ETH_INNER_TX_VLANTAG)
+  if (VLANTag == ETH_INNER_TX_VLANTAG)
   {
     MODIFY_REG(heth->Instance->MACIVIR, ETH_MACVIR_VLT, VLANIdentifier);
   }
@@ -504,9 +608,10 @@ void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
   __HAL_ETH_MAC_ENABLE_IT(heth, ETH_MACIER_LPIIE);
 
   /* Write to LPI Control register: Enter low power mode */
-  MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE), (((uint32_t)TxAutomate << 19) |
-                                                                                                       ((uint32_t)TxClockStop << 21) |
-                                                                                                         ETH_MACLCSR_LPIEN));
+  MODIFY_REG(heth->Instance->MACLCSR, (ETH_MACLCSR_LPIEN | ETH_MACLCSR_LPITXA | ETH_MACLCSR_LPITCSE),
+             (((uint32_t)TxAutomate << 19) |
+              ((uint32_t)TxClockStop << 21) |
+              ETH_MACLCSR_LPIEN));
 }
 
 /**
@@ -524,14 +629,13 @@ void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth)
   __HAL_ETH_MAC_DISABLE_IT(heth, ETH_MACIER_LPIIE);
 }
 
-
 /**
   * @brief  Returns the ETH MAC LPI event
   * @param  heth: pointer to a ETH_HandleTypeDef structure that contains
   *         the configuration information for ETHERNET module
   * @retval ETH MAC WakeUp event
   */
-uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
+uint32_t HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth)
 {
   return heth->MACLPIEvent;
 }
@@ -551,9 +655,6 @@ uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth)
 #endif /* ETH */
 
 #endif /* HAL_ETH_MODULE_ENABLED */
-
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.h
index cec388784c..4e229bc852 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth_ex.h
@@ -6,23 +6,22 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef STM32H7xx_HAL_ETH_EX_H
 #define STM32H7xx_HAL_ETH_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 #if defined(ETH)
@@ -42,131 +41,136 @@
 /** @defgroup ETHEx_Exported_Types ETHEx Exported Types
   * @{
   */
-  
-/** 
+
+/**
   * @brief  ETH RX VLAN structure definition
   */
-typedef struct{
+typedef struct
+{
   FunctionalState InnerVLANTagInStatus;      /*!< Enables or disables Inner VLAN Tag in Rx Status  */
-	
-  uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive 
-                                                  This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
-	
+
+  uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive
+                                                  This parameter can be a value of
+                                                  @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
+
   FunctionalState InnerVLANTag;              /*!< Enables or disables Inner VLAN Tag */
 
   FunctionalState DoubleVLANProcessing;      /*!< Enable or Disable double VLAN processing */
-	
+
   FunctionalState VLANTagHashTableMatch;     /*!< Enable or Disable VLAN Tag Hash Table Match */
-	
+
   FunctionalState VLANTagInStatus;           /*!< Enable or Disable VLAN Tag in Rx status */
-	
-  uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive 
+
+  uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive
                                                   This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
-	
+
   uint32_t VLANTypeCheck;                    /*!< Enable or Disable VLAN Type Check
                                                   This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
-																				 
-  FunctionalState VLANTagInverceMatch;       /*!< Enable or disable VLAN Tag Inverse Match */																			 
-}ETH_RxVLANConfigTypeDef;
-/** 
-  * 
+
+  FunctionalState VLANTagInverceMatch;       /*!< Enable or disable VLAN Tag Inverse Match */
+} ETH_RxVLANConfigTypeDef;
+/**
+  *
   */
-  
-/** 
+
+/**
   * @brief  ETH TX VLAN structure definition
   */
-typedef struct{
+typedef struct
+{
   FunctionalState SourceTxDesc;   /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
-  
+
   FunctionalState SVLANType;      /*!< Enable or Disable insertion of SVLAN type */
-	
+
   uint32_t VLANTagControl;        /*!< Sets the VLAN tag control in tx packets
                                       This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
-}ETH_TxVLANConfigTypeDef;
-/** 
-  * 
+} ETH_TxVLANConfigTypeDef;
+/**
+  *
   */
 
-/** 
+/**
   * @brief  ETH L3 filter structure definition
   */
-typedef struct{
+typedef struct
+{
   uint32_t Protocol;                /*!< Sets the L3 filter protocol to IPv4 or IPv6
                                          This parameter can be a value of @ref ETHEx_L3_Protocol */
-  
+
   uint32_t SrcAddrFilterMatch;      /*!< Sets the L3 filter source address match
                                          This parameter can be a value of @ref ETHEx_L3_Source_Match */
-  
+
   uint32_t DestAddrFilterMatch;     /*!< Sets the L3 filter destination address match
                                          This parameter can be a value of @ref ETHEx_L3_Destination_Match */
-  
+
   uint32_t SrcAddrHigherBitsMatch;  /*!< Sets the L3 filter source address higher bits match
                                          This parameter can be a value from 0 to 31 */
-  
+
   uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
                                          This parameter can be a value from 0 to 31 */
-  
+
   uint32_t Ip4SrcAddr;              /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
                                          This parameter can be a value from 0x0 to 0xFFFFFFFF */
-  
+
   uint32_t Ip4DestAddr;             /*!< Sets the L3 filter IPv4 destination  address if IPv4 protocol is used
                                          This parameter can be a value from 0 to 0xFFFFFFFF  */
-  
+
   uint32_t Ip6Addr[4];                 /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
                                           This parameter must be a table of 4 words (4* 32 bits) */
-}ETH_L3FilterConfigTypeDef;
-/** 
-  * 
+} ETH_L3FilterConfigTypeDef;
+/**
+  *
   */
 
-/** 
+/**
   * @brief  ETH L4 filter structure definition
   */
-typedef struct{
+typedef struct
+{
   uint32_t Protocol;               /*!< Sets the L4 filter protocol to TCP or UDP
                                         This parameter can be a value of @ref ETHEx_L4_Protocol */
-  
+
   uint32_t SrcPortFilterMatch;     /*!< Sets the L4 filter source port match
                                         This parameter can be a value of @ref ETHEx_L4_Source_Match */
-  
+
   uint32_t DestPortFilterMatch;    /*!< Sets the L4 filter destination port match
                                         This parameter can be a value of @ref ETHEx_L4_Destination_Match */
-  
-  uint32_t SourcePort;             /*!< Sets the L4 filter source port 
+
+  uint32_t SourcePort;             /*!< Sets the L4 filter source port
                                         This parameter must be a value from 0x0 to 0xFFFF */
-  
-  uint32_t DestinationPort;        /*!< Sets the L4 filter destination port 
-                                        This parameter must be a value from 0x0 to 0xFFFF */	
-}ETH_L4FilterConfigTypeDef;
-/** 
-  * 
+
+  uint32_t DestinationPort;        /*!< Sets the L4 filter destination port
+                                        This parameter must be a value from 0x0 to 0xFFFF */
+} ETH_L4FilterConfigTypeDef;
+/**
+  *
   */
-  
+
 /**
   * @}
   */
-  
+
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
   * @{
   */
-    
+
 /** @defgroup ETHEx_LPI_Event ETHEx LPI Event
   * @{
-  */	
-#define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN 
-#define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX 
+  */
+#define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN
+#define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX
 #define ETH_RX_LPI_ENTRY    ETH_MACLCSR_RLPIEN
 #define ETH_RX_LPI_EXIT     ETH_MACLCSR_RLPIEX
 /**
   * @}
   */
-  
+
 /** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
   * @{
   */
-#define ETH_L3_FILTER_0                 ((uint32_t)0x00000000)
-#define ETH_L3_FILTER_1                 ((uint32_t)0x0000000C)
+#define ETH_L3_FILTER_0                 0x00000000U
+#define ETH_L3_FILTER_1                 0x0000000CU
 /**
   * @}
   */
@@ -174,8 +178,8 @@ typedef struct{
 /** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
   * @{
   */
-#define ETH_L4_FILTER_0                 ((uint32_t)0x00000000)
-#define ETH_L4_FILTER_1                 ((uint32_t)0x0000000C)
+#define ETH_L4_FILTER_0                 0x00000000U
+#define ETH_L4_FILTER_1                 0x0000000CU
 /**
   * @}
   */
@@ -184,7 +188,7 @@ typedef struct{
   * @{
   */
 #define ETH_L3_IPV6_MATCH                       ETH_MACL3L4CR_L3PEN
-#define ETH_L3_IPV4_MATCH                       ((uint32_t)0x00000000)
+#define ETH_L3_IPV4_MATCH                       0x00000000U
 /**
   * @}
   */
@@ -194,53 +198,53 @@ typedef struct{
   */
 #define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L3SAM
 #define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
-#define ETH_L3_SRC_ADDR_MATCH_DISABLE           ((uint32_t)0x00000000)
+#define ETH_L3_SRC_ADDR_MATCH_DISABLE           0x00000000U
 /**
   * @}
   */
-	
+
 /** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
   * @{
   */
 #define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L3DAM
 #define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
-#define ETH_L3_DEST_ADDR_MATCH_DISABLE          ((uint32_t)0x00000000)
+#define ETH_L3_DEST_ADDR_MATCH_DISABLE          0x00000000U
 /**
   * @}
   */
-	
+
 /** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
   * @{
   */
 #define ETH_L4_UDP_MATCH                        ETH_MACL3L4CR_L4PEN
-#define ETH_L4_TCP_MATCH                        ((uint32_t)0x00000000)
+#define ETH_L4_TCP_MATCH                        0x00000000U
 /**
   * @}
   */
-	
+
 /** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
   * @{
   */
 #define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L4SPM
-#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) 
-#define ETH_L4_SRC_PORT_MATCH_DISABLE           ((uint32_t)0x00000000)
+#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
+#define ETH_L4_SRC_PORT_MATCH_DISABLE           0x00000000U
 /**
   * @}
   */
-	
+
 /** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
   * @{
   */
 #define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L4DPM
 #define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
-#define ETH_L4_DEST_PORT_MATCH_DISABLE          ((uint32_t)0x00000000)
+#define ETH_L4_DEST_PORT_MATCH_DISABLE          0x00000000U
 /**
   * @}
   */
-  
+
 /** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
   * @{
-  */ 
+  */
 #define ETH_INNERVLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EIVLS_DONOTSTRIP
 #define ETH_INNERVLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EIVLS_STRIPIFPASS
 #define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EIVLS_STRIPIFFAILS
@@ -251,7 +255,7 @@ typedef struct{
 
 /** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
   * @{
-  */ 
+  */
 #define ETH_VLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EVLS_DONOTSTRIP
 #define ETH_VLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EVLS_STRIPIFPASS
 #define ETH_VLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EVLS_STRIPIFFAILS
@@ -259,17 +263,17 @@ typedef struct{
 /**
   * @}
   */
-  
+
 /** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
   * @{
-  */ 
+  */
 #define ETH_VLANTYPECHECK_DISABLE    ETH_MACVTR_DOVLTC
 #define ETH_VLANTYPECHECK_SVLAN      (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
-#define ETH_VLANTYPECHECK_CVLAN      ((uint32_t)0x00000000)
+#define ETH_VLANTYPECHECK_CVLAN      0x00000000U
 /**
   * @}
   */
-  
+
 /** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
   * @{
   */
@@ -279,21 +283,21 @@ typedef struct{
 #define ETH_VLANTAGCONTROL_REPLACE    (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
 /**
   * @}
-  */	
- 
+  */
+
 /** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
   * @{
-  */ 
-#define ETH_INNER_TX_VLANTAG    ((uint32_t)0x00000001U)
-#define ETH_OUTER_TX_VLANTAG    ((uint32_t)0x00000000U)
-/**
-  * @}
-  */ 
-  
+  */
+#define ETH_INNER_TX_VLANTAG    0x00000001U
+#define ETH_OUTER_TX_VLANTAG    0x00000000U
 /**
   * @}
   */
-  
+
+/**
+  * @}
+  */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup ETHEx_Exported_Functions
   * @{
@@ -305,42 +309,49 @@ typedef struct{
 /* MAC ARP Offloading APIs  ***************************************************/
 void              HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
 void              HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
-void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); 
+void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
 
 /* MAC L3 L4 Filtering APIs ***************************************************/
 void              HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
 void              HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(const ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              ETH_L4FilterConfigTypeDef *pL4FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L3FilterConfigTypeDef *pL3FilterConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter,
+                                              const ETH_L4FilterConfigTypeDef *pL4FilterConfig);
 
 /* MAC VLAN Processing APIs    ************************************************/
 void              HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
 void              HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(const ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
 HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
 void              HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
-HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
-HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
-void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(const ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            ETH_TxVLANConfigTypeDef *pVlanConfig);
+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag,
+                                            const ETH_TxVLANConfigTypeDef *pVlanConfig);
+void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag, uint32_t VLANIdentifier);
 
 /* Energy Efficient Ethernet APIs *********************************************/
-void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
+void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate,
+                                         FunctionalState TxClockStop);
 void              HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
-uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
- 
-/**
-  * @}
-  */ 
+uint32_t          HAL_ETHEx_GetMACLPIEvent(const ETH_HandleTypeDef *heth);
 
 /**
   * @}
   */
-    
+
 /**
   * @}
-  */ 
+  */
+
+/**
+  * @}
+  */
 
 /**
   * @}
@@ -353,5 +364,3 @@ uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
 #endif
 
 #endif /* STM32H7xx_HAL_ETH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c
index e49dc3ac62..fe54a0374f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.c
@@ -8,6 +8,17 @@
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### EXTI Peripheral features #####
@@ -87,7 +98,7 @@
         (++) Provide exiting handle as parameter.
         (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
 
-    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
         (++) Provide exiting handle as parameter.
 
     (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
@@ -98,23 +109,11 @@
 
     (#) Get interrupt pending bit using HAL_EXTI_GetPending().
 
-    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+    (#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
 
     (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -440,6 +439,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
   }
 #endif /*DUAL_CORE*/
 
+  /* Get default Trigger and GPIOSel configuration */
+  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+  pExtiConfig->GPIOSel = 0x00U;
+
   /* 2] Get trigger for configurable lines : rising */
   if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
   {
@@ -451,10 +454,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
     {
       pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
     }
-    else
-    {
-      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
-    }
 
     /* Get falling configuration */
     regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
@@ -472,29 +471,18 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
       assert_param(IS_EXTI_GPIO_PIN(linepos));
 
       regval = SYSCFG->EXTICR[(linepos >> 2U) & 0x03UL];
-      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3UL - (linepos & 0x03UL)))) >> 24U);
-    }
-    else
-    {
-      pExtiConfig->GPIOSel = 0x00U;
+      pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
     }
   }
-  else
-  {
-    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
-    pExtiConfig->GPIOSel = 0x00U;
-  }
+
+  /* Get default Pend Clear Source */
+  pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
 
   /* 3] Get D3 Pend Clear source */
   if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
   {
     regaddr = (__IO uint32_t *)(&EXTI->D3PMR1 + (EXTI_CONFIG_OFFSET * offset));
-    if(((*regaddr) & linepos) == 0UL)
-    {
-      /* if PMR unset, then no pend clear source is used */
-      pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
-    }
-    else
+    if(((*regaddr) & linepos) != 0UL)
     {
       /* if wakeup target is any and PMR set, the read pend clear source from  D3PCRxL/H */
       if(linepos < 16UL)
@@ -511,11 +499,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
       pExtiConfig->PendClearSource = 1UL + ((*regaddr & (pcrlinepos * pcrlinepos * 3UL)) / (pcrlinepos * pcrlinepos));
     }
   }
-  else
-  {
-    /* if line wakeup target is not any, then no pend clear source is used  */
-    pExtiConfig->PendClearSource = EXTI_D3_PENDCLR_SRC_NONE;
-  }
 
   return HAL_OK;
 }
@@ -759,6 +742,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
   uint32_t maskline;
   uint32_t offset;
 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Edge);
+
   /* Check parameters */
   assert_param(IS_EXTI_LINE(hexti->Line));
   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
@@ -805,6 +791,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
   uint32_t maskline;
   uint32_t offset;
 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Edge);
+
   /* Check parameters */
   assert_param(IS_EXTI_LINE(hexti->Line));
   assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
@@ -874,4 +863,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.h
index f31cacfc06..91d7d952a3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_exti.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -536,4 +535,3 @@ void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
 
 #endif /* STM32H7xx_HAL_EXTI_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c
index 0549620e2b..a0a86f1f24 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.c
@@ -10,7 +10,17 @@
   *           + IO operation functions
   *           + Peripheral Configuration and Control functions
   *           + Peripheral State and Error functions
+  ******************************************************************************
+  * @attention
   *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -71,7 +81,6 @@
 
       *** Polling mode operation ***
       ==============================
-
     [..]
         (#) Reception and transmission states can be monitored via the following
             functions:
@@ -96,10 +105,10 @@
 
   The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
-  Use Function @ref HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
+  Use Function HAL_FDCAN_RegisterCallback() or HAL_FDCAN_RegisterXXXCallback()
   to register an interrupt callback.
 
-  Function @ref HAL_FDCAN_RegisterCallback() allows to register following callbacks:
+  Function HAL_FDCAN_RegisterCallback() allows to register following callbacks:
     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
     (+) RxBufferNewMessageCallback   : Rx Buffer New Message Callback.
     (+) HighPriorityMessageCallback  : High Priority Message Callback.
@@ -113,17 +122,17 @@
 
   For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback, RxFifo1Callback,
   TxBufferCompleteCallback, TxBufferAbortCallback, ErrorStatusCallback, TT_ScheduleSyncCallback, TT_TimeMarkCallback,
-  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks :
-  respectively @ref HAL_FDCAN_RegisterClockCalibrationCallback(), @ref HAL_FDCAN_RegisterTxEventFifoCallback(),
-  @ref HAL_FDCAN_RegisterRxFifo0Callback(), @ref HAL_FDCAN_RegisterRxFifo1Callback(),
-  @ref HAL_FDCAN_RegisterTxBufferCompleCallback(), @ref HAL_FDCAN_RegisterTxBufferAbortCallback(),
-  @ref HAL_FDCAN_RegisterErrorStatusCallback(), @ref HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
-  @ref HAL_FDCAN_TT_RegisterTimeMarkCallback(), @ref HAL_FDCAN_TT_RegisterStopWatchCallback() and
-  @ref HAL_FDCAN_TT_RegisterGlobalTimeCallback().
+  TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated register callbacks:
+  respectively HAL_FDCAN_RegisterClockCalibrationCallback(), HAL_FDCAN_RegisterTxEventFifoCallback(),
+  HAL_FDCAN_RegisterRxFifo0Callback(), HAL_FDCAN_RegisterRxFifo1Callback(),
+  HAL_FDCAN_RegisterTxBufferCompleCallback(), HAL_FDCAN_RegisterTxBufferAbortCallback(),
+  HAL_FDCAN_RegisterErrorStatusCallback(), HAL_FDCAN_TT_RegisterScheduleSyncCallback(),
+  HAL_FDCAN_TT_RegisterTimeMarkCallback(), HAL_FDCAN_TT_RegisterStopWatchCallback() and
+  HAL_FDCAN_TT_RegisterGlobalTimeCallback().
 
-  Use function @ref HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
+  Use function HAL_FDCAN_UnRegisterCallback() to reset a callback to the default
   weak function.
-  @ref HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  HAL_FDCAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
   and the Callback ID.
   This function allows to reset following callbacks:
     (+) TxFifoEmptyCallback          : Tx Fifo Empty Callback.
@@ -138,20 +147,20 @@
   For specific callbacks ClockCalibrationCallback, TxEventFifoCallback, RxFifo0Callback,
   RxFifo1Callback, TxBufferCompleteCallback, TxBufferAbortCallback, TT_ScheduleSyncCallback,
   TT_TimeMarkCallback, TT_StopWatchCallback and TT_GlobalTimeCallback, use dedicated
-  register callbacks : respectively @ref HAL_FDCAN_UnRegisterClockCalibrationCallback(),
-  @ref HAL_FDCAN_UnRegisterTxEventFifoCallback(), @ref HAL_FDCAN_UnRegisterRxFifo0Callback(),
-  @ref HAL_FDCAN_UnRegisterRxFifo1Callback(), @ref HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
-  @ref HAL_FDCAN_UnRegisterTxBufferAbortCallback(), @ref HAL_FDCAN_UnRegisterErrorStatusCallback(),
-  @ref HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), @ref HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
-  @ref HAL_FDCAN_TT_UnRegisterStopWatchCallback() and @ref HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
+  register callbacks: respectively HAL_FDCAN_UnRegisterClockCalibrationCallback(),
+  HAL_FDCAN_UnRegisterTxEventFifoCallback(), HAL_FDCAN_UnRegisterRxFifo0Callback(),
+  HAL_FDCAN_UnRegisterRxFifo1Callback(), HAL_FDCAN_UnRegisterTxBufferCompleCallback(),
+  HAL_FDCAN_UnRegisterTxBufferAbortCallback(), HAL_FDCAN_UnRegisterErrorStatusCallback(),
+  HAL_FDCAN_TT_UnRegisterScheduleSyncCallback(), HAL_FDCAN_TT_UnRegisterTimeMarkCallback(),
+  HAL_FDCAN_TT_UnRegisterStopWatchCallback() and HAL_FDCAN_TT_UnRegisterGlobalTimeCallback().
 
-  By default, after the @ref HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
+  By default, after the HAL_FDCAN_Init() and when the state is HAL_FDCAN_STATE_RESET,
   all callbacks are set to the corresponding weak functions:
-  examples @ref HAL_FDCAN_ErrorCallback().
+  examples HAL_FDCAN_ErrorCallback().
   Exception done for MspInit and MspDeInit functions that are
-  reset to the legacy weak function in the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit() only when
+  reset to the legacy weak function in the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit() only when
   these callbacks are null (not registered beforehand).
-  if not, MspInit or MspDeInit are not null, the @ref HAL_FDCAN_Init()/ @ref HAL_FDCAN_DeInit()
+  if not, MspInit or MspDeInit are not null, the HAL_FDCAN_Init()/ HAL_FDCAN_DeInit()
   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
   Callbacks can be registered/unregistered in HAL_FDCAN_STATE_READY state only.
@@ -159,26 +168,14 @@
   in HAL_FDCAN_STATE_READY or HAL_FDCAN_STATE_RESET state,
   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_FDCAN_RegisterCallback() before calling @ref HAL_FDCAN_DeInit()
-  or @ref HAL_FDCAN_Init() function.
+  using HAL_FDCAN_RegisterCallback() before calling HAL_FDCAN_DeInit()
+  or HAL_FDCAN_Init() function.
 
   When The compilation define USE_HAL_FDCAN_REGISTER_CALLBACKS is set to 0 or
   not defined, the callback registration feature is not available and all callbacks
   are set to the corresponding weak functions.
 
   @endverbatim
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
   ******************************************************************************
   */
 
@@ -234,7 +231,7 @@
 #define FDCAN_ELEMENT_MASK_ET    ((uint32_t)0x00C00000U) /* Event type                  */
 
 #define FDCAN_MESSAGE_RAM_SIZE 0x2800U
-#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* The Message RAM has a width of 4 Bytes */
+#define FDCAN_MESSAGE_RAM_END_ADDRESS (SRAMCAN_BASE + FDCAN_MESSAGE_RAM_SIZE - 0x4U) /* Message RAM width is 4 Bytes */
 
 /**
   * @}
@@ -242,14 +239,21 @@
 
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/** @addtogroup FDCAN_Private_Variables
+  * @{
+  */
 static const uint8_t DLCtoBytes[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64};
+/**
+  * @}
+  */
 
 /* Private function prototypes -----------------------------------------------*/
 /** @addtogroup FDCAN_Private_Functions_Prototypes
   * @{
   */
 static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                   const uint8_t *pTxData, uint32_t BufferIndex);
 /**
   * @}
   */
@@ -260,8 +264,8 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
+  *  @brief    Initialization and Configuration functions
+  *
 @verbatim
   ==============================================================================
               ##### Initialization and de-initialization functions #####
@@ -356,23 +360,23 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
     hfdcan->Lock = HAL_UNLOCKED;
 
     /* Reset callbacks to legacy functions */
-    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* Legacy weak ClockCalibrationCallback    */
-    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* Legacy weak TxEventFifoCallback         */
-    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* Legacy weak RxFifo0Callback             */
-    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* Legacy weak RxFifo1Callback             */
-    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* Legacy weak TxFifoEmptyCallback         */
-    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* Legacy weak TxBufferCompleteCallback    */
-    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* Legacy weak TxBufferAbortCallback       */
-    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* Legacy weak RxBufferNewMessageCallback  */
-    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
-    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
-    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* Legacy weak TimeoutOccurredCallback     */
-    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* Legacy weak ErrorCallback               */
-    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* Legacy weak ErrorStatusCallback         */
-    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* Legacy weak TT_ScheduleSyncCallback     */
-    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* Legacy weak TT_TimeMarkCallback         */
-    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* Legacy weak TT_StopWatchCallback        */
-    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* Legacy weak TT_GlobalTimeCallback       */
+    hfdcan->ClockCalibrationCallback    = HAL_FDCAN_ClockCalibrationCallback;    /* ClockCalibrationCallback    */
+    hfdcan->TxEventFifoCallback         = HAL_FDCAN_TxEventFifoCallback;         /* TxEventFifoCallback         */
+    hfdcan->RxFifo0Callback             = HAL_FDCAN_RxFifo0Callback;             /* RxFifo0Callback             */
+    hfdcan->RxFifo1Callback             = HAL_FDCAN_RxFifo1Callback;             /* RxFifo1Callback             */
+    hfdcan->TxFifoEmptyCallback         = HAL_FDCAN_TxFifoEmptyCallback;         /* TxFifoEmptyCallback         */
+    hfdcan->TxBufferCompleteCallback    = HAL_FDCAN_TxBufferCompleteCallback;    /* TxBufferCompleteCallback    */
+    hfdcan->TxBufferAbortCallback       = HAL_FDCAN_TxBufferAbortCallback;       /* TxBufferAbortCallback       */
+    hfdcan->RxBufferNewMessageCallback  = HAL_FDCAN_RxBufferNewMessageCallback;  /* RxBufferNewMessageCallback  */
+    hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* HighPriorityMessageCallback */
+    hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* TimestampWraparoundCallback */
+    hfdcan->TimeoutOccurredCallback     = HAL_FDCAN_TimeoutOccurredCallback;     /* TimeoutOccurredCallback     */
+    hfdcan->ErrorCallback               = HAL_FDCAN_ErrorCallback;               /* ErrorCallback               */
+    hfdcan->ErrorStatusCallback         = HAL_FDCAN_ErrorStatusCallback;         /* ErrorStatusCallback         */
+    hfdcan->TT_ScheduleSyncCallback     = HAL_FDCAN_TT_ScheduleSyncCallback;     /* TT_ScheduleSyncCallback     */
+    hfdcan->TT_TimeMarkCallback         = HAL_FDCAN_TT_TimeMarkCallback;         /* TT_TimeMarkCallback         */
+    hfdcan->TT_StopWatchCallback        = HAL_FDCAN_TT_StopWatchCallback;        /* TT_StopWatchCallback        */
+    hfdcan->TT_GlobalTimeCallback       = HAL_FDCAN_TT_GlobalTimeCallback;       /* TT_GlobalTimeCallback       */
 
     if (hfdcan->MspInitCallback == NULL)
     {
@@ -524,9 +528,9 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
   /* If FD operation with BRS is selected, set the data bit timing register */
   if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
   {
-    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
-                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)    | \
-                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)    | \
+    hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos)  | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos)     | \
+                              (((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos)     | \
                               (((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
   }
 
@@ -545,19 +549,22 @@ HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan)
   /* Configure Rx FIFO 0 element size */
   if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
   {
-    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS, (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS,
+               (CvtEltSize[hfdcan->Init.RxFifo0ElmtSize] << FDCAN_RXESC_F0DS_Pos));
   }
 
   /* Configure Rx FIFO 1 element size */
   if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
   {
-    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS, (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS,
+               (CvtEltSize[hfdcan->Init.RxFifo1ElmtSize] << FDCAN_RXESC_F1DS_Pos));
   }
 
   /* Configure Rx buffer element size */
   if (hfdcan->Init.RxBuffersNbr > 0U)
   {
-    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS, (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
+    MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS,
+               (CvtEltSize[hfdcan->Init.RxBufferSize] << FDCAN_RXESC_RBDS_Pos));
   }
 
   /* By default operation mode is set to Event-driven communication.
@@ -640,7 +647,7 @@ __weak void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_MspInit could be implemented in the user file
    */
 }
@@ -655,7 +662,7 @@ __weak void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_MspDeInit could be implemented in the user file
    */
 }
@@ -752,7 +759,8 @@ HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan)
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+                                             void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -948,7 +956,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_
   * @param  pCallback pointer to the Clock Calibration Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_ClockCalibrationCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -977,7 +986,8 @@ HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef
 
 /**
   * @brief  UnRegister the Clock Calibration FDCAN Callback
-  *         Clock Calibration FDCAN Callback is redirected to the weak HAL_FDCAN_ClockCalibrationCallback() predefined callback
+  *         Clock Calibration FDCAN Callback is redirected to the weak
+  *         HAL_FDCAN_ClockCalibrationCallback() predefined callback
   * @param  hfdcan FDCAN handle
   * @retval HAL status
   */
@@ -1008,7 +1018,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeD
   * @param  pCallback pointer to the Tx Event Fifo Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TxEventFifoCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1068,7 +1079,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *h
   * @param  pCallback pointer to the Rx Fifo 0 Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo0CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1128,7 +1140,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdca
   * @param  pCallback pointer to the Rx Fifo 1 Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo1CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1188,7 +1201,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdca
   * @param  pCallback pointer to the Tx Buffer Complete Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1217,7 +1231,8 @@ HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef
 
 /**
   * @brief  UnRegister the Tx Buffer Complete FDCAN Callback
-  *         Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+  *         Tx Buffer Complete FDCAN Callback is redirected to
+  *         the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
   * @param  hfdcan FDCAN handle
   * @retval HAL status
   */
@@ -1248,7 +1263,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeD
   * @param  pCallback pointer to the Tx Buffer Abort Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                          pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1277,7 +1293,8 @@ HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *h
 
 /**
   * @brief  UnRegister the Tx Buffer Abort FDCAN Callback
-  *         Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+  *         Tx Buffer Abort FDCAN Callback is redirected to
+  *         the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
   * @param  hfdcan FDCAN handle
   * @retval HAL status
   */
@@ -1308,7 +1325,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef
   * @param  pCallback pointer to the Error Status Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_ErrorStatusCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1368,7 +1386,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *h
   * @param  pCallback pointer to the TT Schedule Synchronization Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                           pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1397,7 +1416,8 @@ HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *
 
 /**
   * @brief  UnRegister the TT Schedule Synchronization FDCAN Callback
-  *         TT Schedule Synchronization Callback is redirected to the weak HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
+  *         TT Schedule Synchronization Callback is redirected to the weak
+  *         HAL_FDCAN_TT_ScheduleSyncCallback() predefined callback
   * @param  hfdcan FDCAN handle
   * @retval HAL status
   */
@@ -1428,7 +1448,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef
   * @param  pCallback pointer to the TT Time Mark Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                       pFDCAN_TT_TimeMarkCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1488,7 +1509,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hf
   * @param  pCallback pointer to the TT Stop Watch Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TT_StopWatchCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1548,7 +1570,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *h
   * @param  pCallback pointer to the TT Global Time Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                         pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -1608,8 +1631,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
- *  @brief    FDCAN Configuration functions.
- *
+  *  @brief    FDCAN Configuration functions.
+  *
 @verbatim
   ==============================================================================
               ##### Configuration functions #####
@@ -1656,7 +1679,8 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *
   *         contains the clock calibration information
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig)
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
+                                                   const FDCAN_ClkCalUnitTypeDef *sCcuConfig)
 {
   /* Check function parameters */
   assert_param(IS_FDCAN_CLOCK_CALIBRATION(sCcuConfig->ClockCalibration));
@@ -1690,7 +1714,8 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
       SET_BIT(FDCAN_CCU->CCFG, FDCANCCU_CCFG_BCC);
 
       /* Configure clock divider */
-      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV, sCcuConfig->ClockDivider);
+      MODIFY_REG(FDCAN_CCU->CCFG, FDCANCCU_CCFG_CDIV,
+                 (sCcuConfig->ClockDivider << FDCANCCU_CCFG_CDIV_Pos));
     }
     else /* sCcuConfig->ClockCalibration == ENABLE */
     {
@@ -1700,7 +1725,8 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
       /* Configure clock calibration unit */
       MODIFY_REG(FDCAN_CCU->CCFG,
                  (FDCANCCU_CCFG_TQBT | FDCANCCU_CCFG_CFL | FDCANCCU_CCFG_OCPM),
-                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) | sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
+                 ((sCcuConfig->TimeQuantaPerBitTime << FDCANCCU_CCFG_TQBT_Pos) |
+                  sCcuConfig->CalFieldLength | (sCcuConfig->MinOscClkPeriods << FDCANCCU_CCFG_OCPM_Pos)));
 
       /* Configure the start value of the calibration watchdog counter */
       MODIFY_REG(FDCAN_CCU->CWD, FDCANCCU_CWD_WDC, sCcuConfig->WatchdogStartValue);
@@ -1724,7 +1750,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
   *         the configuration information for the specified FDCAN.
   * @retval State clock calibration state (can be a value of @arg FDCAN_calibration_state)
   */
-uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
@@ -1774,7 +1800,7 @@ HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdc
   *         This parameter can be a value of @arg FDCAN_calibration_counter.
   * @retval Value clock calibration counter value
   */
-uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
+uint32_t HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
@@ -1805,7 +1831,7 @@ uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint3
   *         contains the filter configuration information
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig)
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig)
 {
   uint32_t FilterElementW1;
   uint32_t FilterElementW2;
@@ -1954,7 +1980,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan,
   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
   *         the configuration information for the specified FDCAN.
   * @param  Mask Extended ID Mask.
-  *         This parameter must be a number between 0 and 0x1FFFFFFF
+  *         This parameter must be a number between 0 and 0x1FFFFFFF.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask)
@@ -2002,12 +2028,12 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, u
     if (RxFifo == FDCAN_RX_FIFO0)
     {
       /* Select FIFO 0 Operation Mode */
-      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, OperationMode);
+      MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0OM, (OperationMode << FDCAN_RXF0C_F0OM_Pos));
     }
     else /* RxFifo == FDCAN_RX_FIFO1 */
     {
       /* Select FIFO 1 Operation Mode */
-      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, OperationMode);
+      MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1OM, (OperationMode << FDCAN_RXF1C_F1OM_Pos));
     }
 
     /* Return function status */
@@ -2195,9 +2221,9 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
   * @brief  Get the timestamp counter value.
   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
   *         the configuration information for the specified FDCAN.
-  * @retval Value Timestamp counter value
+  * @retval Timestamp counter value
   */
-uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
+uint16_t HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan)
 {
   return (uint16_t)(hfdcan->Instance->TSCV);
 }
@@ -2239,7 +2265,8 @@ HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan)
   *         This parameter must be a number between 0x0000 and 0xFFFF
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+                                                 uint32_t TimeoutPeriod)
 {
   /* Check function parameters */
   assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
@@ -2248,7 +2275,8 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, ui
   if (hfdcan->State == HAL_FDCAN_STATE_READY)
   {
     /* Select timeout operation and configure period */
-    MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+    MODIFY_REG(hfdcan->Instance->TOCC,
+               (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
 
     /* Return function status */
     return HAL_OK;
@@ -2316,9 +2344,9 @@ HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
   * @brief  Get the timeout counter value.
   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
   *         the configuration information for the specified FDCAN.
-  * @retval Value Timeout counter value
+  * @retval Timeout counter value
   */
-uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
+uint16_t HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan)
 {
   return (uint16_t)(hfdcan->Instance->TOCV);
 }
@@ -2359,7 +2387,8 @@ HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan)
   *         This parameter must be a number between 0x00 and 0x7F.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+                                                      uint32_t TdcFilter)
 {
   /* Check function parameters */
   assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
@@ -2541,8 +2570,8 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group3 Control functions
- *  @brief    Control functions
- *
+  *  @brief    Control functions
+  *
 @verbatim
   ==============================================================================
                           ##### Control functions #####
@@ -2550,18 +2579,22 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan)
     [..]  This section provides functions allowing to:
       (+) HAL_FDCAN_Start                         : Start the FDCAN module
       (+) HAL_FDCAN_Stop                          : Stop the FDCAN module and enable access to configuration registers
-      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+      (+) HAL_FDCAN_AddMessageToTxFifoQ           : Add a message to the Tx FIFO/Queue and activate the corresponding
+                                                    transmission request
       (+) HAL_FDCAN_AddMessageToTxBuffer          : Add a message to a dedicated Tx buffer
       (+) HAL_FDCAN_EnableTxBufferRequest         : Enable transmission request
       (+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
       (+) HAL_FDCAN_AbortTxRequest                : Abort transmission request
-      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the message RAM
-      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+      (+) HAL_FDCAN_GetRxMessage                  : Get an FDCAN frame from the Rx Buffer/FIFO zone into the
+                                                    message RAM
+      (+) HAL_FDCAN_GetTxEvent                    : Get an FDCAN Tx event from the Tx Event FIFO zone
+                                                    into the message RAM
       (+) HAL_FDCAN_GetHighPriorityMessageStatus  : Get high priority message status
       (+) HAL_FDCAN_GetProtocolStatus             : Get protocol status
       (+) HAL_FDCAN_GetErrorCounters              : Get error counter values
       (+) HAL_FDCAN_IsRxBufferMessageAvailable    : Check if a new message is received in the selected Rx buffer
-      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending on the selected Tx buffer
+      (+) HAL_FDCAN_IsTxBufferMessagePending      : Check if a transmission request is pending
+                                                    on the selected Tx buffer
       (+) HAL_FDCAN_GetRxFifoFillLevel            : Return Rx FIFO fill level
       (+) HAL_FDCAN_GetTxFifoFreeLevel            : Return Tx FIFO free level
       (+) HAL_FDCAN_IsRestrictedOperationMode     : Check if the FDCAN peripheral entered Restricted Operation Mode
@@ -2690,7 +2723,8 @@ HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan)
   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                const uint8_t *pTxData)
 {
   uint32_t PutIndex;
 
@@ -2768,7 +2802,8 @@ HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDC
   *         This parameter can be a value of @arg FDCAN_Tx_location.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                 const uint8_t *pTxData, uint32_t BufferIndex)
 {
   HAL_FDCAN_StateTypeDef state = hfdcan->State;
 
@@ -2863,7 +2898,7 @@ HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, u
   *          - Any value of @arg FDCAN_Tx_location if Tx request has been submitted.
   *          - 0 if no Tx FIFO/Queue request have been submitted.
   */
-uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan)
 {
   /* Return Last Tx FIFO/Queue Request Buffer */
   return hfdcan->LatestTxFifoQRequest;
@@ -2906,7 +2941,8 @@ HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t
   * @param  pRxData pointer to a buffer where the payload of the Rx frame will be stored.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+                                         FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
 {
   uint32_t *RxAddress;
   uint8_t  *pData;
@@ -2937,17 +2973,17 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
       }
       else
       {
-        /* Check that the Rx FIFO 0 is full & overwrite mode is on*/
-        if(((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
+        /* Check that the Rx FIFO 0 is full & overwrite mode is on */
+        if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U)
         {
-          if(((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+          if (((hfdcan->Instance->RXF0C & FDCAN_RXF0C_F0OM) >> FDCAN_RXF0C_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
           {
             /* When overwrite status is on discard first message in FIFO */
             GetIndex = 1U;
           }
         }
 
-        /* Calculate Rx FIFO 0 element index*/
+        /* Calculate Rx FIFO 0 element index */
         GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos);
 
         /* Calculate Rx FIFO 0 element address */
@@ -2965,7 +3001,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
         return HAL_ERROR;
       }
 
-      /* Check that the Rx FIFO 0 is not empty */
+      /* Check that the Rx FIFO 1 is not empty */
       if ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1FL) == 0U)
       {
         /* Update error code */
@@ -2975,17 +3011,17 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
       }
       else
       {
-        /* Check that the Rx FIFO 1 is full & overwrite mode is on*/
-        if(((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
+        /* Check that the Rx FIFO 1 is full & overwrite mode is on */
+        if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U)
         {
-          if(((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
+          if (((hfdcan->Instance->RXF1C & FDCAN_RXF1C_F1OM) >> FDCAN_RXF1C_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE)
           {
             /* When overwrite status is on discard first message in FIFO */
             GetIndex = 1U;
           }
         }
 
-        /* Calculate Rx FIFO 1 element index*/
+        /* Calculate Rx FIFO 1 element index */
         GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos);
 
         /* Calculate Rx FIFO 1 element address */
@@ -3015,7 +3051,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
     /* Retrieve Identifier */
     if (pRxHeader->IdType == FDCAN_STANDARD_ID) /* Standard ID element */
     {
-      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18);
+      pRxHeader->Identifier = ((*RxAddress & FDCAN_ELEMENT_MASK_STDID) >> 18U);
     }
     else /* Extended ID element */
     {
@@ -3035,7 +3071,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
     pRxHeader->RxTimestamp = (*RxAddress & FDCAN_ELEMENT_MASK_TS);
 
     /* Retrieve DataLength */
-    pRxHeader->DataLength = (*RxAddress & FDCAN_ELEMENT_MASK_DLC);
+    pRxHeader->DataLength = ((*RxAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
 
     /* Retrieve BitRateSwitch */
     pRxHeader->BitRateSwitch = (*RxAddress & FDCAN_ELEMENT_MASK_BRS);
@@ -3044,17 +3080,17 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
     pRxHeader->FDFormat = (*RxAddress & FDCAN_ELEMENT_MASK_FDF);
 
     /* Retrieve FilterIndex */
-    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24);
+    pRxHeader->FilterIndex = ((*RxAddress & FDCAN_ELEMENT_MASK_FIDX) >> 24U);
 
     /* Retrieve NonMatchingFrame */
-    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31);
+    pRxHeader->IsFilterMatchingFrame = ((*RxAddress & FDCAN_ELEMENT_MASK_ANMF) >> 31U);
 
     /* Increment RxAddress pointer to payload of Rx FIFO element */
     RxAddress++;
 
     /* Retrieve Rx payload */
     pData = (uint8_t *)RxAddress;
-    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength >> 16]; ByteCounter++)
+    for (ByteCounter = 0; ByteCounter < DLCtoBytes[pRxHeader->DataLength]; ByteCounter++)
     {
       pRxData[ByteCounter] = pData[ByteCounter];
     }
@@ -3074,11 +3110,11 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R
       /* Clear the New Data flag of the current Rx buffer */
       if (RxLocation < FDCAN_RX_BUFFER32)
       {
-        hfdcan->Instance->NDAT1 = ((uint32_t)1 << RxLocation);
+        hfdcan->Instance->NDAT1 = ((uint32_t)1U << RxLocation);
       }
       else /* FDCAN_RX_BUFFER32 <= RxLocation <= FDCAN_RX_BUFFER63 */
       {
-        hfdcan->Instance->NDAT2 = ((uint32_t)1 << (RxLocation & 0x1FU));
+        hfdcan->Instance->NDAT2 = ((uint32_t)1U << (RxLocation & 0x1FU));
       }
     }
 
@@ -3160,7 +3196,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
     pTxEvent->TxTimestamp = (*TxEventAddress & FDCAN_ELEMENT_MASK_TS);
 
     /* Retrieve DataLength */
-    pTxEvent->DataLength = (*TxEventAddress & FDCAN_ELEMENT_MASK_DLC);
+    pTxEvent->DataLength = ((*TxEventAddress & FDCAN_ELEMENT_MASK_DLC) >> 16U);
 
     /* Retrieve BitRateSwitch */
     pTxEvent->BitRateSwitch = (*TxEventAddress & FDCAN_ELEMENT_MASK_BRS);
@@ -3172,7 +3208,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
     pTxEvent->EventType = (*TxEventAddress & FDCAN_ELEMENT_MASK_ET);
 
     /* Retrieve MessageMarker */
-    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24);
+    pTxEvent->MessageMarker = ((*TxEventAddress & FDCAN_ELEMENT_MASK_MM) >> 24U);
 
     /* Acknowledge the Tx Event FIFO that the oldest element is read so that it increments the GetIndex */
     hfdcan->Instance->TXEFA = GetIndex;
@@ -3196,7 +3232,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEven
   * @param  HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                         FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
 {
   HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
   HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
@@ -3214,7 +3251,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hf
   * @param  ProtocolStatus pointer to an FDCAN_ProtocolStatusTypeDef structure.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                              FDCAN_ProtocolStatusTypeDef *ProtocolStatus)
 {
   uint32_t StatusReg;
 
@@ -3245,7 +3283,8 @@ HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN
   * @param  ErrorCounters pointer to an FDCAN_ErrorCountersTypeDef structure.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters)
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
+                                             FDCAN_ErrorCountersTypeDef *ErrorCounters)
 {
   uint32_t CountersReg;
 
@@ -3309,7 +3348,7 @@ uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint3
   *          - 0 : No pending transmission request on TxBufferIndex.
   *          - 1 : Pending transmission request on TxBufferIndex.
   */
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex)
 {
   /* Check pending transmission request on the selected buffer */
   if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
@@ -3327,9 +3366,9 @@ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_
   *         This parameter can be one of the following values:
   *           @arg FDCAN_RX_FIFO0: Rx FIFO 0
   *           @arg FDCAN_RX_FIFO1: Rx FIFO 1
-  * @retval Level Rx FIFO fill level.
+  * @retval Rx FIFO fill level.
   */
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo)
 {
   uint32_t FillLevel;
 
@@ -3354,9 +3393,9 @@ uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
   *         elements starting from Tx FIFO GetIndex.
   * @param  hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
   *         the configuration information for the specified FDCAN.
-  * @retval Level Tx FIFO free level.
+  * @retval Tx FIFO free level.
   */
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan)
 {
   uint32_t FreeLevel;
 
@@ -3374,7 +3413,7 @@ uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan)
   *          - 0 : Normal FDCAN operation.
   *          - 1 : Restricted Operation Mode active.
   */
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan)
 {
   uint32_t OperationMode;
 
@@ -3416,8 +3455,8 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group4 TT Configuration and control functions
- *  @brief    TT Configuration and control functions
- *
+  *  @brief    TT Configuration and control functions
+  *
 @verbatim
   ==============================================================================
               ##### TT Configuration and control functions #####
@@ -3436,12 +3475,13 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd
       (+) HAL_FDCAN_TT_DisableTriggerTimeMarkPulse      : Disable trigger time mark pulse generation
       (+) HAL_FDCAN_TT_EnableHardwareGapControl         : Enable gap control by input pin fdcan1_evt
       (+) HAL_FDCAN_TT_DisableHardwareGapControl        : Disable gap control by input pin fdcan1_evt
-      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark interrupt
+      (+) HAL_FDCAN_TT_EnableTimeMarkGapControl         : Enable gap control (finish only) by register time mark IT
       (+) HAL_FDCAN_TT_DisableTimeMarkGapControl        : Disable gap control by register time mark interrupt
       (+) HAL_FDCAN_TT_SetNextIsGap                     : Transmit next reference message with Next_is_Gap = "1"
       (+) HAL_FDCAN_TT_SetEndOfGap                      : Finish a Gap by requesting start of reference message
       (+) HAL_FDCAN_TT_ConfigExternalSyncPhase          : Configure target phase used for external synchronization
-        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external schedule
+        (+) HAL_FDCAN_TT_EnableExternalSynchronization    : Synchronize the phase of the FDCAN schedule to an external
+                                                            schedule
         (+) HAL_FDCAN_TT_DisableExternalSynchronization   : Disable external schedule synchronization
       (+) HAL_FDCAN_TT_GetOperationStatus               : Get TT operation status
 
@@ -3456,7 +3496,7 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd
   * @param  pTTParams pointer to a FDCAN_TT_ConfigTypeDef structure.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams)
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams)
 {
   uint32_t tickstart;
   uint32_t RAMcounter;
@@ -3524,7 +3564,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCA
     /* Configure TUR (Time Unit Ratio) */
     MODIFY_REG(hfdcan->ttcan->TURCF,
                (FDCAN_TURCF_NCL | FDCAN_TURCF_DC),
-               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) | (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
+               (((pTTParams->TURNumerator - 0x10000U) << FDCAN_TURCF_NCL_Pos) |
+                (pTTParams->TURDenominator << FDCAN_TURCF_DC_Pos)));
 
     /* Enable local time */
     SET_BIT(hfdcan->ttcan->TURCF, FDCAN_TURCF_ELT);
@@ -3559,7 +3600,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCA
     {
       MODIFY_REG(hfdcan->ttcan->TTMLM,
                  (FDCAN_TTMLM_TXEW | FDCAN_TTMLM_ENTT),
-                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) | (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
+                 (((pTTParams->TxEnableWindow - 1U) << FDCAN_TTMLM_TXEW_Pos) |
+                  (pTTParams->ExpTxTrigNbr << FDCAN_TTMLM_ENTT_Pos)));
     }
     if (pTTParams->TimeMaster == FDCAN_TT_POTENTIAL_MASTER)
     {
@@ -3634,7 +3676,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCA
   *             - bytes 5-8, for Level 0 and Level 2
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload)
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType,
+                                                      uint32_t Identifier, uint32_t Payload)
 {
   /* Check function parameters */
   assert_param(IS_FDCAN_TT_INSTANCE(hfdcan->Instance));
@@ -3654,11 +3697,13 @@ HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdca
     /* Configure reference message identifier type, identifier and payload */
     if (IdType == FDCAN_EXTENDED_ID)
     {
-      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | Identifier));
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS),
+                 (Payload | IdType | Identifier));
     }
     else /* IdType == FDCAN_STANDARD_ID */
     {
-      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS), (Payload | IdType | (Identifier << 18)));
+      MODIFY_REG(hfdcan->ttcan->TTRMC, (FDCAN_TTRMC_RID | FDCAN_TTRMC_XTD | FDCAN_TTRMC_RMPS),
+                 (Payload | IdType | (Identifier << 18)));
     }
 
     /* Return function status */
@@ -3682,7 +3727,7 @@ HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdca
   *         contains the trigger configuration information
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig)
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig)
 {
   uint32_t CycleCode;
   uint32_t MessageNumber;
@@ -4878,7 +4923,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDe
   * @param  TTOpStatus pointer to an FDCAN_TTOperationStatusTypeDef structure.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus)
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                  FDCAN_TTOperationStatusTypeDef *TTOpStatus)
 {
   uint32_t TTStatusReg;
 
@@ -4913,8 +4959,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, F
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group5 Interrupts management
- *  @brief    Interrupts management
- *
+  *  @brief    Interrupts management
+  *
 @verbatim
   ==============================================================================
                        ##### Interrupts management #####
@@ -4984,7 +5030,8 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, ui
   *         This parameter can be a value of @arg FDCAN_Interrupt_Line.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine)
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
+                                                    uint32_t InterruptLine)
 {
   HAL_FDCAN_StateTypeDef state = hfdcan->State;
 
@@ -5030,7 +5077,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan,
   *           - FDCAN_IT_TX_ABORT_COMPLETE
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+                                                 uint32_t BufferIndexes)
 {
   HAL_FDCAN_StateTypeDef state = hfdcan->State;
 
@@ -5226,7 +5274,7 @@ HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdca
 
     if ((hfdcan->ttcan->TTIE & ITLineSelection) == 0U)
     {
-      /* Disable Interrupt line 1 */
+      /* Disable interrupt line 1 */
       CLEAR_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
     }
 
@@ -5265,6 +5313,10 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   uint32_t TTFatalErrors;
   uint32_t SWTime;
   uint32_t SWCycleCount;
+  uint32_t itsourceIE;
+  uint32_t itsourceTTIE;
+  uint32_t itflagIR;
+  uint32_t itflagTTIR;
 
   ClkCalibrationITs = (FDCAN_CCU->IR << 30);
   ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
@@ -5278,11 +5330,13 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   Errors &= hfdcan->Instance->IE;
   ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
   ErrorStatusITs &= hfdcan->Instance->IE;
+  itsourceIE = hfdcan->Instance->IE;
+  itflagIR = hfdcan->Instance->IR;
 
   /* High Priority Message interrupt management *******************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
     {
       /* Clear the High Priority Message flag */
       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
@@ -5298,9 +5352,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Transmission Abort interrupt management **********************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
     {
       /* List of aborted monitored buffers */
       AbortedBuffers = hfdcan->Instance->TXBCF;
@@ -5380,9 +5434,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Tx FIFO empty interrupt management ***************************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_FIFO_EMPTY) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
     {
       /* Clear the Tx FIFO empty flag */
       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
@@ -5398,9 +5452,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Transmission Complete interrupt management *******************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TX_COMPLETE) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
     {
       /* List of transmitted monitored buffers */
       TransmittedBuffers = hfdcan->Instance->TXBTO;
@@ -5420,9 +5474,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Rx Buffer New Message interrupt management *******************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
     {
       /* Clear the Rx Buffer New Message flag */
       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
@@ -5438,9 +5492,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Timestamp Wraparound interrupt management ********************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMESTAMP_WRAPAROUND) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
     {
       /* Clear the Timestamp Wraparound flag */
       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
@@ -5456,9 +5510,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Timeout Occurred interrupt management ************************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_TIMEOUT_OCCURRED) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
     {
       /* Clear the Timeout Occurred flag */
       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
@@ -5474,9 +5528,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   }
 
   /* Message RAM access failure interrupt management **************************/
-  if (__HAL_FDCAN_GET_IT_SOURCE(hfdcan, FDCAN_IT_RAM_ACCESS_FAILURE) != 0U)
+  if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
   {
-    if (__HAL_FDCAN_GET_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE) != 0U)
+    if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
     {
       /* Clear the Message RAM access failure flag */
       __HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
@@ -5525,6 +5579,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
       TTDistErrors &= hfdcan->ttcan->TTIE;
       TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
       TTFatalErrors &= hfdcan->ttcan->TTIE;
+      itsourceTTIE = hfdcan->ttcan->TTIE;
+      itflagTTIR = hfdcan->ttcan->TTIR;
 
       /* TT Schedule Synchronization interrupts management **********************/
       if (TTSchedSyncITs != 0U)
@@ -5557,9 +5613,9 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
       }
 
       /* TT Stop Watch interrupt management *************************************/
-      if (__HAL_FDCAN_TT_GET_IT_SOURCE(hfdcan, FDCAN_TT_IT_STOP_WATCH) != 0U)
+      if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
       {
-        if (__HAL_FDCAN_TT_GET_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH) != 0U)
+        if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
         {
           /* Retrieve Stop watch Time and Cycle count */
           SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
@@ -5632,8 +5688,8 @@ void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan)
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group6 Callback functions
- *  @brief   FDCAN Callback functions
- *
+  *  @brief   FDCAN Callback functions
+  *
 @verbatim
   ==============================================================================
                           ##### Callback functions #####
@@ -5676,7 +5732,7 @@ __weak void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint
   UNUSED(hfdcan);
   UNUSED(ClkCalibrationITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_ClockCalibrationCallback could be implemented in the user file
    */
 }
@@ -5695,7 +5751,7 @@ __weak void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
   UNUSED(hfdcan);
   UNUSED(TxEventFifoITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TxEventFifoCallback could be implemented in the user file
    */
 }
@@ -5714,7 +5770,7 @@ __weak void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
   UNUSED(hfdcan);
   UNUSED(RxFifo0ITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_RxFifo0Callback could be implemented in the user file
    */
 }
@@ -5733,7 +5789,7 @@ __weak void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFi
   UNUSED(hfdcan);
   UNUSED(RxFifo1ITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_RxFifo1Callback could be implemented in the user file
    */
 }
@@ -5749,7 +5805,7 @@ __weak void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TxFifoEmptyCallback could be implemented in the user file
    */
 }
@@ -5768,7 +5824,7 @@ __weak void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint
   UNUSED(hfdcan);
   UNUSED(BufferIndexes);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TxBufferCompleteCallback could be implemented in the user file
    */
 }
@@ -5787,7 +5843,7 @@ __weak void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_
   UNUSED(hfdcan);
   UNUSED(BufferIndexes);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TxBufferAbortCallback could be implemented in the user file
    */
 }
@@ -5803,7 +5859,7 @@ __weak void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_RxBufferNewMessageCallback could be implemented in the user file
    */
 }
@@ -5819,7 +5875,7 @@ __weak void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TimestampWraparoundCallback could be implemented in the user file
    */
 }
@@ -5835,7 +5891,7 @@ __weak void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TimeoutOccurredCallback could be implemented in the user file
    */
 }
@@ -5851,7 +5907,7 @@ __weak void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_HighPriorityMessageCallback could be implemented in the user file
    */
 }
@@ -5867,7 +5923,7 @@ __weak void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hfdcan);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_ErrorCallback could be implemented in the user file
    */
 }
@@ -5886,7 +5942,7 @@ __weak void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
   UNUSED(hfdcan);
   UNUSED(ErrorStatusITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_ErrorStatusCallback could be implemented in the user file
    */
 }
@@ -5905,7 +5961,7 @@ __weak void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint3
   UNUSED(hfdcan);
   UNUSED(TTSchedSyncITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TT_ScheduleSyncCallback could be implemented in the user file
    */
 }
@@ -5924,7 +5980,7 @@ __weak void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
   UNUSED(hfdcan);
   UNUSED(TTTimeMarkITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TT_TimeMarkCallback could be implemented in the user file
    */
 }
@@ -5947,7 +6003,7 @@ __weak void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t
   UNUSED(SWTime);
   UNUSED(SWCycleCount);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TT_StopWatchCallback could be implemented in the user file
    */
 }
@@ -5966,7 +6022,7 @@ __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_
   UNUSED(hfdcan);
   UNUSED(TTGlobTimeITs);
 
-  /* NOTE : This function Should not be modified, when the callback is needed,
+  /* NOTE: This function Should not be modified, when the callback is needed,
             the HAL_FDCAN_TT_GlobalTimeCallback could be implemented in the user file
    */
 }
@@ -5976,8 +6032,8 @@ __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_
   */
 
 /** @defgroup FDCAN_Exported_Functions_Group7 Peripheral State functions
- *  @brief   FDCAN Peripheral State functions
- *
+  *  @brief   FDCAN Peripheral State functions
+  *
 @verbatim
   ==============================================================================
                       ##### Peripheral State functions #####
@@ -5996,7 +6052,7 @@ __weak void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_
   *         the configuration information for the specified FDCAN.
   * @retval HAL state
   */
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan)
 {
   /* Return FDCAN state */
   return hfdcan->State;
@@ -6008,7 +6064,7 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan)
   *         the configuration information for the specified FDCAN.
   * @retval FDCAN Error Code
   */
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan)
 {
   /* Return FDCAN error code */
   return hfdcan->ErrorCode;
@@ -6022,7 +6078,7 @@ uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan)
   * @}
   */
 
-/** @addtogroup FDCAN_Private_Functions
+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions
   * @{
   */
 
@@ -6090,13 +6146,17 @@ static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *
   hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
   hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
   hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
-  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA + (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
-  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA + (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
-  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA + (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
+  hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA +
+                             (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
+  hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA +
+                              (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
+  hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA +
+                                 (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
   hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
   hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
 
-  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA + (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
+  hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA +
+                              (hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
 
   if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
   {
@@ -6129,9 +6189,10 @@ static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *
   * @param  pTxHeader pointer to a FDCAN_TxHeaderTypeDef structure.
   * @param  pTxData pointer to a buffer containing the payload of the Tx frame.
   * @param  BufferIndex index of the buffer to be configured.
-  * @retval HAL status
+  * @retval none
  */
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+static void FDCAN_CopyMessageToRAM(const FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                   const uint8_t *pTxData, uint32_t BufferIndex)
 {
   uint32_t TxElementW1;
   uint32_t TxElementW2;
@@ -6144,7 +6205,7 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
     TxElementW1 = (pTxHeader->ErrorStateIndicator |
                    FDCAN_STANDARD_ID |
                    pTxHeader->TxFrameType |
-                   (pTxHeader->Identifier << 18));
+                   (pTxHeader->Identifier << 18U));
   }
   else /* pTxHeader->IdType == FDCAN_EXTENDED_ID */
   {
@@ -6155,11 +6216,11 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
   }
 
   /* Build second word of Tx header element */
-  TxElementW2 = ((pTxHeader->MessageMarker << 24) |
+  TxElementW2 = ((pTxHeader->MessageMarker << 24U) |
                  pTxHeader->TxEventFifoControl |
                  pTxHeader->FDFormat |
                  pTxHeader->BitRateSwitch |
-                 pTxHeader->DataLength);
+                 (pTxHeader->DataLength << 16U));
 
   /* Calculate Tx element address */
   TxAddress = (uint32_t *)(hfdcan->msgRam.TxBufferSA + (BufferIndex * hfdcan->Init.TxElmtSize * 4U));
@@ -6171,11 +6232,11 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
   TxAddress++;
 
   /* Write Tx payload to the message RAM */
-  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength >> 16]; ByteCounter += 4U)
+  for (ByteCounter = 0; ByteCounter < DLCtoBytes[pTxHeader->DataLength]; ByteCounter += 4U)
   {
-    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24) |
-                  ((uint32_t)pTxData[ByteCounter + 2U] << 16) |
-                  ((uint32_t)pTxData[ByteCounter + 1U] << 8) |
+    *TxAddress = (((uint32_t)pTxData[ByteCounter + 3U] << 24U) |
+                  ((uint32_t)pTxData[ByteCounter + 2U] << 16U) |
+                  ((uint32_t)pTxData[ByteCounter + 1U] << 8U)  |
                   (uint32_t)pTxData[ByteCounter]);
     TxAddress++;
   }
@@ -6194,5 +6255,3 @@ static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTy
   */
 
 #endif /* FDCAN1 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h
index 6dcb610cd0..a4a137ebd7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fdcan.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -304,12 +303,15 @@ typedef struct
   uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.
                                        This parameter must be a number between:
                                         - 0 and 127, if IdType is FDCAN_STANDARD_ID
-                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */
+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID
+                                       When the frame is a Non-Filter matching frame, this parameter
+                                       is unused.                                                        */
 
   uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
-                                         Acceptance of non-matching frames may be enabled via
-                                         HAL_FDCAN_ConfigGlobalFilter().
-                                         This parameter can be 0 or 1                                    */
+                                       Acceptance of non-matching frames may be enabled via
+                                       HAL_FDCAN_ConfigGlobalFilter().
+                                       This parameter takes 0 if the frame matched an Rx filter or
+                                       1 if it did not match any Rx filter                               */
 
 } FDCAN_RxHeaderTypeDef;
 
@@ -389,52 +391,55 @@ typedef struct
 typedef struct
 {
   uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.
-                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code             */
 
-  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
-                                   frame with its BRS flag set.
-                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */
+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
+                                   of a CAN FD format frame with its BRS flag set.
+                                   This parameter can be a value of @ref FDCAN_protocol_error_code             */
 
   uint32_t Activity;          /*!< Specifies the FDCAN module communication state.
-                                   This parameter can be a value of @ref FDCAN_communication_state                           */
+                                   This parameter can be a value of @ref FDCAN_communication_state             */
 
   uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.
                                    This parameter can be:
                                     - 0 : The FDCAN is in Error_Active state
-                                    - 1 : The FDCAN is in Error_Passive state                                                */
+                                    - 1 : The FDCAN is in Error_Passive state                                  */
 
   uint32_t Warning;           /*!< Specifies the FDCAN module warning status.
                                    This parameter can be:
-                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
-                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */
+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the
+                                          Error_Warning limit of 96
+                                    - 1 : at least one of error counters has reached the Error_Warning
+                                          limit of 96                                                          */
 
   uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.
                                    This parameter can be:
                                     - 0 : The FDCAN is not in Bus_Off state
-                                    - 1 : The FDCAN is in Bus_Off state                                                      */
+                                    - 1 : The FDCAN is in Bus_Off state                                        */
 
   uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.
                                    This parameter can be:
                                     - 0 : Last received CAN FD message did not have its ESI flag set
-                                    - 1 : Last received CAN FD message had its ESI flag set                                  */
+                                    - 1 : Last received CAN FD message had its ESI flag set                    */
 
   uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.
                                    This parameter can be:
                                     - 0 : Last received CAN FD message did not have its BRS flag set
-                                    - 1 : Last received CAN FD message had its BRS flag set                                  */
+                                    - 1 : Last received CAN FD message had its BRS flag set                    */
 
-  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received
+                                   since last protocol status.
                                    This parameter can be:
-                                    - 0 : no CAN FD message received
-                                    - 1 : CAN FD message received                                                            */
+                                    - 0 : No CAN FD message received
+                                    - 1 : CAN FD message received                                              */
 
   uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
                                    This parameter can be:
                                     - 0 : No protocol exception event occurred since last read access
-                                    - 1 : Protocol exception event occurred                                                  */
+                                    - 1 : Protocol exception event occurred                                    */
 
   uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.
-                                   This parameter can be a number between 0 and 127                                          */
+                                   This parameter can be a number between 0 and 127                            */
 
 } FDCAN_ProtocolStatusTypeDef;
 
@@ -444,21 +449,24 @@ typedef struct
 typedef struct
 {
   uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.
-                                This parameter can be a number between 0 and 255                                         */
+                                This parameter can be a number between 0 and 255                               */
 
   uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.
-                                This parameter can be a number between 0 and 127                                         */
+                                This parameter can be a number between 0 and 127                               */
 
   uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
                                 This parameter can be:
-                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
-                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error
+                                       passive level of 128
+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error
+                                       passive level of 128                                                    */
 
   uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.
                                 This parameter can be a number between 0 and 255.
-                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
-                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
-                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */
+                                This counter is incremented each time when a FDCAN protocol error causes
+                                the TxErrorCnt or the RxErrorCnt to be incremented. The counter stops at 255;
+                                the next increment of TxErrorCnt or RxErrorCnt sets interrupt flag
+                                FDCAN_FLAG_ERROR_LOGGING_OVERFLOW                                              */
 
 } FDCAN_ErrorCountersTypeDef;
 
@@ -514,7 +522,7 @@ typedef struct
                                    This parameter is ignored if OperationMode is set to
                                    FDCAN_TT_COMMUNICATION_LEVEL0                                            */
 
-  uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.
+  uint32_t BasicCyclesNbr;    /*!< Specifies the number of basic cycles in the system matrix.
                                    This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */
 
   uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
@@ -529,7 +537,7 @@ typedef struct
                                    This parameter must be a number between 0 and 4095                       */
 
   uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.
-                                   It is adviced to set this parameter to the largest applicable value.
+                                   It is advised to set this parameter to the largest applicable value.
                                    This parameter must be a number between 0x10000 and 0x1FFFF              */
 
   uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.
@@ -641,7 +649,7 @@ typedef struct
                                    - 0 : No Gap in schedule
                                    - 1 : Gap time after Basic Cycle has started                                 */
 
-  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.
+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is announced.
                                   This parameter can be:
                                    - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
                                    - 1 : Reference message with Next_is_Gap = 1 received                        */
@@ -757,15 +765,15 @@ typedef struct
   */
 typedef enum
 {
-  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */
-  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
-  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */
-  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */
-  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */
-  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */
+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U,    /*!< FDCAN Tx Fifo Empty callback ID         */
+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U,    /*!< FDCAN Rx buffer new message callback ID */
+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U,    /*!< FDCAN High priority message callback ID */
+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U,    /*!< FDCAN Timestamp wraparound callback ID  */
+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U,    /*!< FDCAN Timeout occurred callback ID      */
+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U,    /*!< FDCAN Error callback ID                 */
 
-  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */
-  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */
+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U,    /*!< FDCAN MspInit callback ID               */
+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U,    /*!< FDCAN MspDeInit callback ID             */
 
 } HAL_FDCAN_CallbackIDTypeDef;
 
@@ -807,8 +815,8 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
 #define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */
 #define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */
 #define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */
-#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */
-#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Get element from empty FIFO                                            */
+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Put element in full FIFO                                               */
 #define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */
 #define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */
 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */
@@ -866,21 +874,21 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   * @{
   */
 #define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */
-#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */
-#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */
-#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */
-#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */
-#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
-#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
-#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
-#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
-#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
-#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
-#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
-#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
-#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
-#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
-#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2  */
+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4  */
+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6  */
+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8  */
+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
 /**
   * @}
   */
@@ -960,21 +968,21 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   * @{
   */
 #define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */
-#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */
-#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */
-#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */
-#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */
-#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */
-#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */
-#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */
-#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */
-#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
-#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
-#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
-#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
-#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
-#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
-#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00000001U) /*!< 1 bytes data field  */
+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00000002U) /*!< 2 bytes data field  */
+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00000003U) /*!< 3 bytes data field  */
+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00000004U) /*!< 4 bytes data field  */
+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00000005U) /*!< 5 bytes data field  */
+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00000006U) /*!< 6 bytes data field  */
+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00000007U) /*!< 7 bytes data field  */
+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00000008U) /*!< 8 bytes data field  */
+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */
+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */
+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */
+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */
+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */
+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */
 /**
   * @}
   */
@@ -1213,7 +1221,7 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   * @{
   */
 #define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */
-#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
 /**
   * @}
   */
@@ -1259,21 +1267,21 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   * @{
   */
 #define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */
-#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */
-#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */
-#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */
-#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */
-#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */
-#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */
-#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */
-#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */
-#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
-#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
-#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
-#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
-#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
-#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
-#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2  */
+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3  */
+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4  */
+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5  */
+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6  */
+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7  */
+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8  */
+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9  */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
 /**
   * @}
   */
@@ -1658,9 +1666,9 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
   * @{
   */
-#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
-#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
-#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */
+#define FDCAN_IT_ERROR_PASSIVE           FDCAN_IE_EPE   /*!< Error_Passive status changed      */
+#define FDCAN_IT_ERROR_WARNING           FDCAN_IE_EWE   /*!< Error_Warning status changed      */
+#define FDCAN_IT_BUS_OFF                 FDCAN_IE_BOE   /*!< Bus_Off status changed            */
 /**
   * @}
   */
@@ -1778,10 +1786,10 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   * @retval None
   */
 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
-#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \
-                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
-                                                      (__HANDLE__)->MspInitCallback = NULL;           \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \
+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
+                                                       (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \
+                                                       (__HANDLE__)->MspInitCallback = NULL;           \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
                                                      } while(0)
 #else
 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
@@ -1821,7 +1829,9 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   *         This parameter can be one of @arg FDCAN_Interrupts
   * @retval ITStatus
   */
-#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
+                                                       ((__HANDLE__)->Instance->IR &\
+                                                        (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
 
 /**
   * @brief  Clear the specified FDCAN interrupts.
@@ -1830,11 +1840,11 @@ typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan
   *         This parameter can be any combination of @arg FDCAN_Interrupts
   * @retval None
   */
-#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \
-do{                                                                   \
+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)                  \
+  do {                                                                   \
     ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
     FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \
-  }while(0)
+  } while(0);
 
 /**
   * @brief  Check whether the specified FDCAN flag is set or not.
@@ -1843,7 +1853,9 @@ do{                                                                   \
   *         This parameter can be one of @arg FDCAN_flags
   * @retval FlagStatus
   */
-#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? \
+                                                    ((__HANDLE__)->Instance->IR &\
+                                                     (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
 
 /**
   * @brief  Clear the specified FDCAN flags.
@@ -1852,11 +1864,11 @@ do{                                                                   \
   *         This parameter can be any combination of @arg FDCAN_flags
   * @retval None
   */
-#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \
-do{                                                              \
+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)                \
+  do {                                                              \
     ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
     FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \
-  }while(0)
+  } while(0);
 
 /** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.
   * @param  __HANDLE__ FDCAN handle.
@@ -1864,7 +1876,10 @@ do{                                                              \
   *         This parameter can be a value of @arg FDCAN_Interrupts
   * @retval ITStatus
   */
-#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? \
+                                                              ((__HANDLE__)->Instance->IE &\
+                                                               (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & \
+                                                                   (__INTERRUPT__)))
 
 /**
   * @brief  Enable the specified FDCAN TT interrupts.
@@ -1950,29 +1965,41 @@ HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
 
 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
 /* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+                                             pFDCAN_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
-HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TxEventFifoCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo0CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+                                                    pFDCAN_RxFifo1CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                             pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                          pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_ErrorStatusCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                           pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                       pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                        pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan,
+                                                         pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
 /**
@@ -1983,12 +2010,15 @@ HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *
   * @{
   */
 /* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
-uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan,
+                                                   const FDCAN_ClkCalUnitTypeDef *sCcuConfig);
+uint32_t          HAL_FDCAN_GetClockCalibrationState(const FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
-uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
-HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
-HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(const FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCAN_FilterTypeDef *sFilterConfig);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
+                                               uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
+                                               uint32_t RejectRemoteExt);
 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
@@ -1996,14 +2026,16 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint3
 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimestampCounter(const FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+                                                 uint32_t TimeoutPeriod);
 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
+uint16_t          HAL_FDCAN_GetTimeoutCounter(const FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+                                                      uint32_t TdcFilter);
 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
@@ -2020,21 +2052,27 @@ HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
 /* Control functions **********************************************************/
 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                const uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TxHeaderTypeDef *pTxHeader,
+                                                 const uint8_t *pTxData, uint32_t BufferIndex);
 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
-uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(const FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+                                         FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
-HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                         FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                              FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(const FDCAN_HandleTypeDef *hfdcan,
+                                             FDCAN_ErrorCountersTypeDef *ErrorCounters);
 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
-uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
-uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
-uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
-uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsTxBufferMessagePending(const FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
+uint32_t HAL_FDCAN_GetRxFifoFillLevel(const FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(const FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_IsRestrictedOperationMode(const FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
 /**
   * @}
@@ -2044,13 +2082,16 @@ HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfd
   * @{
   */
 /* TT Configuration and control functions**************************************/
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TT_ConfigTypeDef *pTTParams);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier,
+                                                      uint32_t Payload);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, const FDCAN_TriggerTypeDef *sTriggerConfig);
 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource,
+                                                      uint32_t TimeMarkValue, uint32_t RepeatFactor,
+                                                      uint32_t StartCycle);
 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
@@ -2064,7 +2105,8 @@ HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(const FDCAN_HandleTypeDef *hfdcan,
+                                                  FDCAN_TTOperationStatusTypeDef *TTOpStatus);
 /**
   * @}
   */
@@ -2074,8 +2116,10 @@ HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, F
   */
 /* Interrupts management ******************************************************/
 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
-HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList,
+                                                    uint32_t InterruptLine);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+                                                 uint32_t BufferIndexes);
 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
@@ -2113,8 +2157,8 @@ void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlo
   * @{
   */
 /* Peripheral State functions *************************************************/
-uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
-HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
+uint32_t HAL_FDCAN_GetError(const FDCAN_HandleTypeDef *hfdcan);
+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(const FDCAN_HandleTypeDef *hfdcan);
 /**
   * @}
   */
@@ -2190,8 +2234,8 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
-#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
-#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
+#define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_))
+#define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_))
 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
                                   ((SIZE) == FDCAN_DATA_BYTES_12) || \
                                   ((SIZE) == FDCAN_DATA_BYTES_16) || \
@@ -2377,6 +2421,10 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
                                                        ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
+
+#define FDCAN_CHECK_IT_SOURCE(__IE__, __IT__)  ((((__IE__) & (__IT__)) == (__IT__)) ? SET : RESET)
+
+#define FDCAN_CHECK_FLAG(__IR__, __FLAG__) ((((__IR__) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 /**
   * @}
   */
@@ -2414,4 +2462,3 @@ HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
 #endif /* STM32H7xx_HAL_FDCAN_H */
 
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c
index a73e8ed02e..3706941f6b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c
@@ -74,14 +74,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -110,7 +108,13 @@
   */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+  * @{
+  */
 FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
 /* Private function prototypes -----------------------------------------------*/
 /* Exported functions ---------------------------------------------------------*/
 
@@ -119,8 +123,8 @@ FLASH_ProcessTypeDef pFlash;
   */
 
 /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- *  @brief   Programming operation functions
- *
+  *  @brief   Programming operation functions
+  *
 @verbatim
  ===============================================================================
                   ##### Programming operation functions #####
@@ -169,6 +173,8 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
 #endif /* FLASH_OPTCR_PG_OTP */
   {
     bank = FLASH_BANK_1;
+    /* Prevent unused argument(s) compilation warning */
+    UNUSED(TypeProgram);
   }
 #if defined (DUAL_BANK)
   else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
@@ -335,6 +341,8 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
 #endif /* FLASH_OPTCR_PG_OTP */
   {
     bank = FLASH_BANK_1;
+    /* Prevent unused argument(s) compilation warning */
+    UNUSED(TypeProgram);
   }
 #if defined (DUAL_BANK)
   else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
@@ -651,6 +659,38 @@ void HAL_FLASH_IRQHandler(void)
     HAL_FLASH_OperationErrorCallback(temp);
   }
 
+#if (USE_FLASH_ECC == 1U)
+  /* Check FLASH Bank1 ECC single correction error flag */
+  errorflag = FLASH->SR1 & FLASH_FLAG_SNECCERR_BANK1;
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= errorflag;
+
+    /* Call User callback */
+    HAL_FLASHEx_EccCorrectionCallback();
+
+    /* Clear FLASH Bank1 ECC single correction error flag in order to allow new ECC error record */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+  }
+
+  /* Check FLASH Bank1 ECC double detection error flag */
+  errorflag = FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1;
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= errorflag;
+
+    /* Call User callback */
+    HAL_FLASHEx_EccDetectionCallback();
+
+    /* Clear FLASH Bank1 ECC double detection error flag in order to allow new ECC error record */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
+  }
+#endif /* USE_FLASH_ECC */
+
 #if defined (DUAL_BANK)
   /* Check FLASH Bank2 operation error flags */
 #if defined (FLASH_SR_OPERR)
@@ -694,6 +734,39 @@ void HAL_FLASH_IRQHandler(void)
     /* FLASH error interrupt user callback */
     HAL_FLASH_OperationErrorCallback(temp);
   }
+
+#if (USE_FLASH_ECC == 1U)
+  /* Check FLASH Bank2 ECC single correction error flag */
+  errorflag = FLASH->SR2 & FLASH_FLAG_SNECCERR_BANK2;
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+    /* Call User callback */
+    HAL_FLASHEx_EccCorrectionCallback();
+
+    /* Clear FLASH Bank2 ECC single correction error flag in order to allow new ECC error record */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+  }
+
+  /* Check FLASH Bank2 ECC double detection error flag */
+  errorflag = FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2;
+
+  if(errorflag != 0U)
+  {
+    /* Save the error code */
+    pFlash.ErrorCode |= (errorflag | 0x80000000U);
+
+    /* Call User callback */
+    HAL_FLASHEx_EccDetectionCallback();
+
+    /* Clear FLASH Bank2 ECC double detection error flag in order to allow new ECC error record */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
+  }
+
+#endif /* USE_FLASH_ECC */
 #endif /* DUAL_BANK */
 
   if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
@@ -767,8 +840,8 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
   */
 
 /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   Management functions
- *
+  *  @brief   Management functions
+  *
 @verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
@@ -928,8 +1001,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
   */
 
 /** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief   Peripheral Errors functions
- *
+  *  @brief   Peripheral Errors functions
+  *
 @verbatim
  ===============================================================================
                 ##### Peripheral Errors functions #####
@@ -967,7 +1040,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
   *            @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
   *            @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
   *            @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
-*/
+  */
 
 uint32_t HAL_FLASH_GetError(void)
 {
@@ -1001,7 +1074,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
      flag will be set */
 
   uint32_t bsyflag = FLASH_FLAG_QW_BANK1;
-  uint32_t errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+  uint32_t errorflag = 0;
   uint32_t tickstart = HAL_GetTick();
 
   assert_param(IS_FLASH_BANK_EXCLUSIVE(Bank));
@@ -1010,8 +1083,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
 
   if (Bank == FLASH_BANK_2)
   {
-    /* Get Error Flags */
-    errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
     /* Select bsyflag depending on Bank */
     bsyflag = FLASH_FLAG_QW_BANK2;
   }
@@ -1028,6 +1099,18 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank)
     }
   }
 
+  /* Get Error Flags */
+  if (Bank == FLASH_BANK_1)
+  {
+    errorflag = FLASH->SR1 & FLASH_FLAG_ALL_ERRORS_BANK1;
+  }
+#if defined (DUAL_BANK)
+  else
+  {
+    errorflag = (FLASH->SR2 & FLASH_FLAG_ALL_ERRORS_BANK2) | 0x80000000U;
+  }
+#endif /* DUAL_BANK */
+
   /* In case of error reported in Flash SR1 or SR2 register */
   if((errorflag & 0x7FFFFFFFU) != 0U)
   {
@@ -1184,4 +1267,4 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.h
index 8a47e0b0b9..a4773b5b0f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.h
@@ -6,14 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -861,4 +859,3 @@ HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank
 
 #endif /* STM32H7xx_HAL_FLASH_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c
index d0219243d8..c302c7008d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c
@@ -58,18 +58,26 @@
           (++) Perform the CRC computation
           (++) Disable CRC feature
 
+      (#) Error correction code error functions:
+          (++) Use the HAL_FLASHEx_EnableEccCorrectionInterrupt() and HAL_FLASHEx_DisableEccCorrectionInterrupt()
+               functions to enable and disable the FLASH ECC correction interruption.
+          (++) Use the HAL_FLASHEx_EnableEccDetectionInterrupt() and HAL_FLASHEx_DisableEccDetectionInterrupt()
+               functions to enable and disable the FLASH ECC Detection interruption.
+          (++) Handle ECCD interrupt by calling HAL_FLASHEx_BusFault_IRQHandler()
+          (++) Use HAL_FLASHEx_BusFault_IRQHandler() function called under BusFault_IRQHandler() interrupt subroutine
+               to handle the ECCD interrupt.
+          (++) Use HAL_FLASHEx_GetEccInfo() function to get the flash ECC fail information.
+
  @endverbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -408,7 +416,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
 
 /**
   * @brief  Program option bytes
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  * @param  pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
   *         contains the configuration information for the programming.
   *
   * @retval HAL Status
@@ -549,7 +557,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
 
 /**
   * @brief Get the Option byte configuration
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  * @param  pOBInit pointer to an FLASH_OBProgramInitTypeDef structure that
   *         contains the configuration information for the programming.
   * @note   The parameter Banks of the pOBInit structure must be set exclusively to FLASH_BANK_1 or FLASH_BANK_2,
   *         as this parameter is use to get the given Bank WRP, PCROP and secured area configuration.
@@ -820,6 +828,251 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
   * @}
   */
 
+#if (USE_FLASH_ECC == 1U)
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended ECC operation functions
+  *  @brief   Extended ECC operation functions
+  *
+@verbatim
+ ===============================================================================
+                  ##### Extended ECC operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extended FLASH
+    ECC Operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ECC correction interrupts on FLASH BANK1 and BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
+{
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+  * @brief  Disable ECC correction interrupts on FLASH BANK1 and BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
+{
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+  * @brief  Enable ECC correction interrupt on FLASH BANK1.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void)
+{
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
+}
+
+/**
+  * @brief  Disable ECC correction interrupt on FLASH BANK1.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void)
+{
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
+}
+
+#if defined (DUAL_BANK)
+/**
+  * @brief  Enable ECC correction interrupt on FLASH BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void)
+{
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
+}
+
+/**
+  * @brief  Disable ECC correction interrupt on FLASH BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void)
+{
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
+}
+#endif /* DUAL_BANK */
+
+/**
+  * @brief  Enable ECC Detection interrupts on FLASH BANK1 and BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_EnableEccDetectionInterrupt(void)
+{
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+  * @brief  Disable ECC Detection interrupts on FLASH BANK1 and BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_DisableEccDetectionInterrupt(void)
+{
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
+
+#if defined (DUAL_BANK)
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
+#endif /* DUAL_BANK */
+}
+
+/**
+  * @brief  Enable ECC Detection interrupt on FLASH BANK1.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void)
+{
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
+}
+
+/**
+  * @brief  Disable ECC correction interrupt on FLASH BANK1.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void)
+{
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
+}
+
+#if defined (DUAL_BANK)
+/**
+  * @brief  Enable ECC Detection interrupt on FLASH BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void)
+{
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
+}
+
+/**
+  * @brief  Disable ECC Detection interrupt on FLASH BANK2.
+  * @param  None
+  * @retval None
+  */
+void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void)
+{
+  __HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
+}
+#endif /* DUAL_BANK */
+
+/**
+  * @brief  Get the ECC error information.
+  * @param  pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
+  *         ECC error information.
+  * @note   This function should be called before ECC bit is cleared
+  *         (in callback function)
+  * @retval None
+  */
+void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
+{
+  uint32_t errorflag;
+
+  /* Check FLASH Bank1 ECC single correction and double detection error flags */
+  errorflag = FLASH->SR1 & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1);
+  if(errorflag != 0U)
+  {
+    pData->Area = FLASH_ECC_AREA_USER_BANK1;
+    pData->Address = ((((FLASH->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK1_BASE);
+  }
+#if defined (DUAL_BANK)
+  /* Check FLASH Bank2 ECC single correction and double detection error flags */
+  errorflag = FLASH->SR2 & (FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2);
+  if(errorflag != 0U)
+  {
+    pData->Area = FLASH_ECC_AREA_USER_BANK2;
+    pData->Address = ((((FLASH->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK2_BASE);
+  }
+#endif /* DUAL_BANK */
+}
+
+/**
+  * @brief Handle Flash ECC Detection interrupt request.
+  * @retval None
+  */
+void HAL_FLASHEx_BusFault_IRQHandler(void)
+{
+  /* Check if the ECC double error occured*/
+  if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1)  != 0)
+  {
+    /* FLASH ECC detection user callback */
+    HAL_FLASHEx_EccDetectionCallback();
+
+    /* Clear Bank 1 ECC double detection error flag
+    note : this step will clear all the informations related to the flash ECC detection
+    */
+    __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1);
+  }
+#if defined (DUAL_BANK)
+  /* Check if the ECC double error occured*/
+  if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2)  != 0)
+  {
+    /* FLASH ECC detection user callback */
+    HAL_FLASHEx_EccDetectionCallback();
+
+    /* Clear Bank 2 ECC double detection error flag
+    note : this step will clear all the informations related to the flash ECC detection
+    */
+    __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2);
+  }
+#endif /* DUAL_BANK */
+}
+
+/**
+  * @brief  FLASH ECC Correction interrupt callback.
+  * @retval None
+  */
+__weak void HAL_FLASHEx_EccCorrectionCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  FLASH ECC Detection interrupt callback.
+  * @retval None
+  */
+__weak void HAL_FLASHEx_EccDetectionCallback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+#endif /* USE_FLASH_ECC */
+
 /**
   * @}
   */
@@ -971,7 +1224,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)
   * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
   * @param  WRPSector specifies the sector(s) to be write protected.
   *          This parameter can be one of the following values:
-  *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_All
+  *            @arg WRPSector:  A combination of OB_WRP_SECTOR_0 to OB_WRP_SECTOR_7 or OB_WRP_SECTOR_ALL
   *
   * @param  Banks the specific bank to apply WRP sectors
   *          This parameter can be one of the following values:
@@ -1006,7 +1259,7 @@ static void FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
   * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
   * @param  WRPSector specifies the sector(s) to disable write protection.
   *          This parameter can be one of the following values:
-  *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *            @arg WRPSector:  A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
   *
   * @param  Banks the specific bank to apply WRP sectors
   *          This parameter can be one of the following values:
@@ -1045,7 +1298,7 @@ static void FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
 
   * @param  WRPSector gives the write protected sector(s) on the given bank .
   *          This parameter can be one of the following values:
-  *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_All
+  *          @arg WRPSector: A combination of FLASH_OB_WRP_SECTOR_0 to FLASH_OB_WRP_SECTOR_7 or FLASH_OB_WRP_SECTOR_ALL
   *
   * @param  Bank the specific bank to apply WRP sectors
   *          This parameter can be exclusively one of the following values:
@@ -1819,7 +2072,7 @@ static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig)
   */
 static uint32_t FLASH_OB_SharedRAM_GetConfig(void)
 {
-  return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);;
+  return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_TCM_AXI_SHARED);
 }
 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
 
@@ -1846,7 +2099,7 @@ static void FLASH_OB_CPUFreq_BoostConfig(uint32_t FreqBoost)
   */
 static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
 {
-  return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);;
+  return (FLASH->OPTSR2_CUR & FLASH_OPTSR2_CPUFREQ_BOOST);
 }
 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
 
@@ -1860,4 +2113,3 @@ static uint32_t FLASH_OB_CPUFreq_GetBoost(void)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h
index 96119b9c86..1ca4e7230a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h
@@ -6,14 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -178,6 +176,20 @@ typedef struct
 
 } FLASH_CRCInitTypeDef;
 
+#if (USE_FLASH_ECC == 1U)
+/**
+  * @brief  ECC Info Structure definition
+  */
+typedef struct
+{
+  uint32_t               Area;             /*!< Area from which an ECC was detected.
+                                                This parameter can be a value of @ref FLASHEx_ECC_Area  */
+
+  uint32_t               Address;          /*!< ECC error address */
+
+} FLASH_EccInfoTypeDef;
+#endif /* USE_FLASH_ECC */
+
 /**
   * @}
   */
@@ -218,6 +230,18 @@ typedef struct
   * @}
   */
 
+#if (USE_FLASH_ECC == 1U)
+/** @defgroup FLASH_ECC_Area FLASH ECC Area
+  * @brief    FLASH ECC Area
+  * @{
+  */
+#define FLASH_ECC_AREA_USER_BANK1         0x00000000U        /*!< FLASH bank 1 area */
+#define FLASH_ECC_AREA_USER_BANK2         0x00000001U        /*!< FLASH bank 2 area */
+/**
+  * @}
+  */
+#endif /* USE_FLASH_ECC */
+
 /** @defgroup FLASHEx_Option_Type FLASH Option Type
   * @{
   */
@@ -359,6 +383,8 @@ typedef struct
 #define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
 #define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
 #define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+
+/* Unused FLASH Latency defines */
 #define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */
 #define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */
 #define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
@@ -744,6 +770,9 @@ typedef struct
   * @}
   */
 #endif /* FLASH_OTPBL_LOCKBL */
+/**
+  * @}
+  */
 
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
@@ -756,9 +785,6 @@ typedef struct
   * @retval The FLASH Boot Base Address
   */
 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
- /**
-  * @}
-  */
 
 #if defined (FLASH_CR_PSIZE)
 /**
@@ -806,6 +832,9 @@ typedef struct
   *         This return value can be a value of @ref FLASHEx_Programming_Delay
   */
 #define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
+ /**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup FLASHEx_Exported_Functions
@@ -834,6 +863,38 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
   * @}
   */
 
+#if (USE_FLASH_ECC == 1U)
+/** @addtogroup FLASHEx_Exported_Functions_Group3
+  * @{
+  */
+void              HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
+void              HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
+void              HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void);
+void              HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void);
+#if defined (DUAL_BANK)
+void              HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void);
+void              HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void);
+#endif /* DUAL_BANK */
+
+void              HAL_FLASHEx_EnableEccDetectionInterrupt(void);
+void              HAL_FLASHEx_DisableEccDetectionInterrupt(void);
+void              HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void);
+void              HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void);
+#if defined (DUAL_BANK)
+void              HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void);
+void              HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void);
+#endif /* DUAL_BANK */
+
+void              HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
+void              HAL_FLASHEx_BusFault_IRQHandler(void);
+
+__weak void       HAL_FLASHEx_EccDetectionCallback(void);
+__weak void       HAL_FLASHEx_EccCorrectionCallback(void);
+/**
+  * @}
+  */
+#endif /* USE_FLASH_ECC */
+
 /**
   * @}
   */
@@ -1002,14 +1063,9 @@ void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
   * @}
   */
 
-/**
-  * @}
-  */
-
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* STM32H7xx_HAL_FLASH_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.c
index 9159210138..f4cebd05d9 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.c
@@ -9,7 +9,19 @@
   *           + Peripheral Control functions
   *           + Callback functions
   *           + IRQ handler management
-  *           + Peripheral State functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   *
   *  @verbatim
 ================================================================================
@@ -26,9 +38,10 @@
                (+++) In FMAC IRQ handler, call HAL_FMAC_IRQHandler().
           (++) In case of using DMA to control data transfer (e.g. access configured
                as FMAC_BUFFER_ACCESS_DMA):
-               (+++) Enable the DMA1 interface clock using __HAL_RCC_DMA1_CLK_ENABLE().
+               (+++) Enable the DMA interface clock using __HAL_RCC_DMA1_CLK_ENABLE()
+                     or __HAL_RCC_DMA2_CLK_ENABLE() depending on the used DMA instance.
                (+++) Enable the DMAMUX1 interface clock using __HAL_RCC_DMAMUX1_CLK_ENABLE().
-               (+++) If the initialisation of the internal buffers (coefficients, input,
+               (+++) If the initialization of the internal buffers (coefficients, input,
                      output) is done via DMA, configure and enable one DMA channel for
                      managing data transfer from memory to memory (preload channel).
                (+++) If the input buffer is accessed via DMA, configure and enable one
@@ -64,7 +77,7 @@
                Optionally, he can also disable the interrupt using __HAL_FMAC_DISABLE_IT;
                the error status will be kept, but no more interrupt will be triggered.
           (++) Write the provided coefficients into the internal memory using polling
-               mode (HAL_FMAC_FilterConfig()) or DMA (HAL_FMAC_FilterConfig_DMA()).
+               mode ( HAL_FMAC_FilterConfig() ) or DMA ( HAL_FMAC_FilterConfig_DMA() ).
                In the DMA case, HAL_FMAC_FilterConfigCallback() is called when
                the handling is over.
 
@@ -73,7 +86,7 @@
            filter. If a saturation occurs, the interruption will be triggered in loop.
            In order to recover, the user will have to:
            (++) Disable the interruption by calling __HAL_FMAC_DISABLE_IT if
-                he wishes to continue all the same.
+                the user wishes to continue all the same.
            (++) Reset the IP with the sequence HAL_FMAC_DeInit / HAL_FMAC_Init.
 
        (#) Optionally, preload input (FIR, IIR) and output (IIR) data using
@@ -137,8 +150,8 @@
       allows the user to configure dynamically the driver callbacks.
 
     [..]
-      Use Function @ref HAL_FMAC_RegisterCallback() to register a user callback.
-      Function @ref HAL_FMAC_RegisterCallback() allows to register following callbacks:
+      Use Function HAL_FMAC_RegisterCallback() to register a user callback.
+      Function HAL_FMAC_RegisterCallback() allows to register following callbacks:
       (+) ErrorCallback               : Error Callback.
       (+) HalfGetDataCallback         : Get Half Data Callback.
       (+) GetDataCallback             : Get Data Callback.
@@ -152,9 +165,9 @@
       and a pointer to the user callback function.
 
     [..]
-      Use function @ref HAL_FMAC_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function.
-      @ref HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
+      Use function HAL_FMAC_UnRegisterCallback() to reset a callback to the default
+      weak function.
+      HAL_FMAC_UnRegisterCallback() takes as parameters the HAL peripheral handle
       and the Callback ID.
       This function allows to reset following callbacks:
       (+) ErrorCallback               : Error Callback.
@@ -168,13 +181,13 @@
       (+) MspDeInitCallback           : FMAC MspDeInit.
 
     [..]
-      By default, after the @ref HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
-      all callbacks are set to the corresponding weak (surcharged) functions:
-      examples @ref HAL_FMAC_TxCpltCallback(), @ref HAL_FMAC_RxHalfCpltCallback().
+      By default, after the HAL_FMAC_Init() and when the state is HAL_FMAC_STATE_RESET
+      all callbacks are set to the corresponding weak functions:
+      examples GetDataCallback(), OutputDataReadyCallback().
       Exception done for MspInit and MspDeInit functions that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_FMAC_Init()
-      and @ref HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_FMAC_Init() and @ref HAL_FMAC_DeInit()
+      reset to the legacy weak functions in the HAL_FMAC_Init()
+      and HAL_FMAC_DeInit() only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_FMAC_Init() and HAL_FMAC_DeInit()
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
     [..]
@@ -183,29 +196,17 @@
       in HAL_FMAC_STATE_READY or HAL_FMAC_STATE_RESET state, thus registered (user)
       MspInit/DeInit callbacks can be used during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_FMAC_RegisterCallback() before calling @ref HAL_FMAC_DeInit()
-      or @ref HAL_FMAC_Init() function.
+      using HAL_FMAC_RegisterCallback() before calling HAL_FMAC_DeInit()
+      or HAL_FMAC_Init() function.
 
     [..]
       When the compilation define USE_HAL_FMAC_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registration feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak callbacks are used.
 
 
   @endverbatim
   *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -219,11 +220,10 @@
   */
 
 /** @defgroup FMAC FMAC
-  * @brief    FMAC HAL driver modules
+  * @brief    FMAC HAL driver module
   * @{
   */
 
-/* External variables --------------------------------------------------------*/
 /* Private typedef -----------------------------------------------------------*/
 /* Private defines -----------------------------------------------------------*/
 /** @defgroup  FMAC_Private_Constants   FMAC Private Constants
@@ -231,12 +231,23 @@
   */
 
 #define MAX_FILTER_DATA_SIZE_TO_HANDLE ((uint16_t) 0xFFU)
+#define MAX_PRELOAD_INDEX      0xFFU
 #define PRELOAD_ACCESS_DMA     0x00U
 #define PRELOAD_ACCESS_POLLING 0x01U
 #define POLLING_DISABLED       0U
 #define POLLING_ENABLED        1U
 #define POLLING_NOT_STOPPED    0U
 #define POLLING_STOPPED        1U
+/* FMAC polling-based communications time-out value */
+#define HAL_FMAC_TIMEOUT_VALUE         1000U
+/* FMAC reset time-out value */
+#define HAL_FMAC_RESET_TIMEOUT_VALUE   500U
+/* DMA Read Requests Enable */
+#define FMAC_DMA_REN                   FMAC_CR_DMAREN
+/* DMA Write Channel Enable */
+#define FMAC_DMA_WEN                   FMAC_CR_DMAWEN
+/* FMAC Execution Enable */
+#define FMAC_START                     FMAC_PARAM_START
 
 /**
   * @}
@@ -296,40 +307,27 @@
   ((((__HANDLE__)->Instance->PARAM) & (FMAC_PARAM_START)) >> (FMAC_PARAM_START_Pos))
 
 /**
-  * @brief  Get the threshold matching the watermak.
+  * @brief  Get the threshold matching the watermark.
   * @param  __WM__ Watermark value.
   * @retval THRESHOLD
   */
-#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) ((__WM__ == FMAC_THRESHOLD_1)? 1U: \
-                                            (__WM__ == FMAC_THRESHOLD_2)? 2U: \
-                                            (__WM__ == FMAC_THRESHOLD_4)? 4U:8U)
-
-/**
-  * @brief  Check whether the threshold is applicable.
-  * @param  __SIZE__ Size of the matching buffer.
-  * @param  __WM__ Watermark value.
-  * @param  __ACCESS__ Access to the buffer (polling, it, dma, none).
-  * @retval THRESHOLD
-  */
-#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
-                                                                      ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
-                                                                      ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
-                                                                    ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \
-                                                                     ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+#define FMAC_GET_THRESHOLD_FROM_WM(__WM__) (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+                                            ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+                                            ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U)
 
 /**
   * @}
   */
 
 /* Private variables ---------------------------------------------------------*/
-
+/* Global variables ----------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 
 static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac);
 static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac);
 static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
 static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac);
-static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
                                            uint8_t PreloadAccess);
 static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
                                             int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess);
@@ -349,7 +347,7 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma);
 static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma);
 static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
 
-/* Private functions ---------------------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
 
 /** @defgroup FMAC_Exported_Functions FMAC Exported Functions
   * @{
@@ -367,6 +365,8 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
       (+) DeInitialize the FMAC peripheral
       (+) Initialize the FMAC MSP (MCU Specific Package)
       (+) De-Initialize the FMAC MSP
+      (+) Register a User FMAC Callback
+      (+) Unregister a FMAC CallBack
 
     [..]
 
@@ -377,10 +377,12 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma);
 /**
   * @brief  Initialize the FMAC peripheral and the associated handle.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
 {
+  HAL_StatusTypeDef status;
+
   /* Check the FMAC handle allocation */
   if (hfmac == NULL)
   {
@@ -392,7 +394,7 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
 
   if (hfmac->State == HAL_FMAC_STATE_RESET)
   {
-    /* Allocate lock resource and initialize it */
+    /* Initialize lock resource */
     hfmac->Lock = HAL_UNLOCKED;
 
 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
@@ -419,36 +421,36 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
   }
 
   /* Reset pInput and pOutput */
-  hfmac->FilterParam = 0UL;
+  hfmac->FilterParam = 0U;
   FMAC_ResetDataPointers(hfmac);
 
   /* Reset FMAC unit (internal pointers) */
-  if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+  if (FMAC_Reset(hfmac) == HAL_ERROR)
   {
     /* Update FMAC error code and FMAC peripheral state */
-    hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
+    hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
     hfmac->State = HAL_FMAC_STATE_TIMEOUT;
 
-    /* Process Unlocked */
-    __HAL_UNLOCK(hfmac);
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Update FMAC error code and FMAC peripheral state */
+    hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
+    hfmac->State = HAL_FMAC_STATE_READY;
 
-    return HAL_TIMEOUT;
+    status = HAL_OK;
   }
 
-  /* Update FMAC error code and FMAC peripheral state */
-  hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
-  hfmac->State = HAL_FMAC_STATE_READY;
-
-  /* Process Unlocked */
   __HAL_UNLOCK(hfmac);
 
-  return HAL_OK;
+  return status;
 }
 
 /**
   * @brief  De-initialize the FMAC peripheral.
   * @param  hfmac pointer to a FMAC structure.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
 {
@@ -468,7 +470,7 @@ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
   hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
 
   /* Reset pInput and pOutput */
-  hfmac->FilterParam = 0UL;
+  hfmac->FilterParam = 0U;
   FMAC_ResetDataPointers(hfmac);
 
 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
@@ -486,10 +488,9 @@ HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac)
   /* Change FMAC peripheral state */
   hfmac->State = HAL_FMAC_STATE_RESET;
 
-  /* Release Lock */
+  /* Always release Lock in case of de-initialization */
   __HAL_UNLOCK(hfmac);
 
-  /* Return function status */
   return HAL_OK;
 }
 
@@ -525,8 +526,10 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
 
 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
 /**
-  * @brief  Register a User FMAC Callback
-  *         to be used instead of the weak predefined callback.
+  * @brief  Register a User FMAC Callback.
+  * @note   The User FMAC Callback is to be used instead of the weak predefined callback.
+  * @note   The HAL_FMAC_RegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register
+  *         callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  CallbackID ID of the callback to be registered.
@@ -541,13 +544,19 @@ __weak void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac)
   *           @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
   *           @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
   * @param  pCallback pointer to the Callback function.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
                                             pFMAC_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
+  /* Check the FMAC handle allocation */
+  if (hfmac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
   if (pCallback == NULL)
   {
     /* Update the error code */
@@ -555,10 +564,8 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hfmac);
 
-  if (HAL_FMAC_STATE_READY == hfmac->State)
+  if (hfmac->State == HAL_FMAC_STATE_READY)
   {
     switch (CallbackID)
     {
@@ -607,7 +614,7 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_
         break;
     }
   }
-  else if (HAL_FMAC_STATE_RESET == hfmac->State)
+  else if (hfmac->State == HAL_FMAC_STATE_RESET)
   {
     switch (CallbackID)
     {
@@ -637,15 +644,14 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hfmac);
-
   return status;
 }
 
 /**
   * @brief  Unregister a FMAC CallBack.
-  *         FMAC callback is redirected to the weak predefined callback.
+  * @note   The FMAC callback is redirected to the weak predefined callback.
+  * @note   The HAL_FMAC_UnRegisterCallback() may be called before HAL_FMAC_Init() in HAL_FMAC_STATE_RESET to register
+  *         callbacks for HAL_FMAC_MSPINIT_CB_ID and HAL_FMAC_MSPDEINIT_CB_ID.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module
   * @param  CallbackID ID of the callback to be unregistered.
@@ -659,53 +665,59 @@ HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_
   *           @arg @ref HAL_FMAC_FILTER_PRELOAD_CB_ID Filter Preload Callback ID
   *           @arg @ref HAL_FMAC_MSPINIT_CB_ID FMAC MspInit ID
   *           @arg @ref HAL_FMAC_MSPDEINIT_CB_ID FMAC MspDeInit ID
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hfmac);
+  /* Check the FMAC handle allocation */
+  if (hfmac == NULL)
+  {
+    return HAL_ERROR;
+  }
 
-  if (HAL_FMAC_STATE_READY == hfmac->State)
+  if (hfmac->State == HAL_FMAC_STATE_READY)
   {
     switch (CallbackID)
     {
       case HAL_FMAC_ERROR_CB_ID :
-        hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;                             /* Legacy weak ErrorCallback               */
+        hfmac->ErrorCallback = HAL_FMAC_ErrorCallback;                             /* Legacy weak ErrorCallback       */
         break;
 
       case HAL_FMAC_HALF_GET_DATA_CB_ID :
-        hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;                 /* Legacy weak HalfGetDataCallback         */
+        hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback;                 /* Legacy weak HalfGetDataCallback */
         break;
 
       case HAL_FMAC_GET_DATA_CB_ID :
-        hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;                         /* Legacy weak GetDataCallback             */
+        hfmac->GetDataCallback = HAL_FMAC_GetDataCallback;                         /* Legacy weak GetDataCallback     */
         break;
 
       case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID :
-        hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak HalfOutputDataReadyCallback */
+        hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak
+                                                                                      HalfOutputDataReadyCallback     */
         break;
 
       case HAL_FMAC_OUTPUT_DATA_READY_CB_ID :
-        hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;         /* Legacy weak OutputDataReadyCallback     */
+        hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback;         /* Legacy weak
+                                                                                      OutputDataReadyCallback         */
         break;
 
       case HAL_FMAC_FILTER_CONFIG_CB_ID :
-        hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;               /* Legacy weak FilterConfigCallback        */
+        hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback;               /* Legacy weak
+                                                                                      FilterConfigCallback            */
         break;
 
       case HAL_FMAC_FILTER_PRELOAD_CB_ID :
-        hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;             /* Legacy weak FilterPreloadCallback       */
+        hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback;             /* Legacy weak FilterPreloadCallba */
         break;
 
       case HAL_FMAC_MSPINIT_CB_ID :
-        hfmac->MspInitCallback = HAL_FMAC_MspInit;                                 /* Legacy weak MspInitCallback             */
+        hfmac->MspInitCallback = HAL_FMAC_MspInit;                                 /* Legacy weak MspInitCallback     */
         break;
 
       case HAL_FMAC_MSPDEINIT_CB_ID :
-        hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;                             /* Legacy weak MspDeInitCallback           */
+        hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit;                             /* Legacy weak MspDeInitCallback   */
         break;
 
       default :
@@ -717,7 +729,7 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
         break;
     }
   }
-  else if (HAL_FMAC_STATE_RESET == hfmac->State)
+  else if (hfmac->State == HAL_FMAC_STATE_RESET)
   {
     switch (CallbackID)
     {
@@ -747,9 +759,6 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
     status = HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hfmac);
-
   return status;
 }
 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
@@ -778,38 +787,40 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
   */
 
 /**
-  * @brief  Configure the FMAC filter according to the parameters
+  * @brief  Configure the FMAC filter.
+  * @note   The configuration is done according to the parameters
   *         specified in the FMAC_FilterConfigTypeDef structure.
   *         The provided data will be loaded using polling mode.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
-  * @param  sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+  * @param  pConfig pointer to a FMAC_FilterConfigTypeDef structure that
   *         contains the FMAC configuration information.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
-HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
 {
-  return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_POLLING));
+  return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_POLLING));
 }
 
 /**
-  * @brief  Configure the FMAC filter according to the parameters
+  * @brief  Configure the FMAC filter.
+  * @note   The configuration is done according to the parameters
   *         specified in the FMAC_FilterConfigTypeDef structure.
   *         The provided data will be loaded using DMA.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
-  * @param  sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+  * @param  pConfig pointer to a FMAC_FilterConfigTypeDef structure that
   *         contains the FMAC configuration information.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
-HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig)
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig)
 {
-  return (FMAC_FilterConfig(hfmac, sConfig, PRELOAD_ACCESS_DMA));
+  return (FMAC_FilterConfig(hfmac, pConfig, PRELOAD_ACCESS_DMA));
 }
 
 /**
   * @brief  Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
-  *         They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+  * @note   The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
   *         The provided data will be loaded using polling mode.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
@@ -821,10 +832,10 @@ HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_Filt
   *         If not needed, it should be set to NULL.
   * @param  OutputSize Size of the output vector.
   *         As pOutput is used for preloading data, it cannot be bigger than the output memory area.
-  * @note   The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+  * @note   The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
   *         (each call filling partly the buffers). In case of overflow (too much data provided through
   *         all these calls), an error will be returned.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
                                          int16_t *pOutput, uint8_t OutputSize)
@@ -834,7 +845,7 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pIn
 
 /**
   * @brief  Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
-  *         They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+  * @note   The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
   *         The provided data will be loaded using DMA.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
@@ -846,10 +857,10 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pIn
   *         If not needed, it should be set to NULL.
   * @param  OutputSize Size of the output vector.
   *         As pOutput is used for preloading data, it cannot be bigger than the output memory area.
-  * @note   The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+  * @note   The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
   *         (each call filling partly the buffers). In case of overflow (too much data provided through
   *         all these calls), an error will be returned.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
                                              int16_t *pOutput, uint8_t OutputSize)
@@ -867,21 +878,21 @@ HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t
   *         If it is set to NULL, the output will not be read and it will be up to
   *         an external IP to empty the output buffer.
   * @param  pOutputSize pointer to the size of the output buffer. The number of read data will be written here.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
 {
-  uint32_t tmpcr = 0UL;
+  uint32_t tmpcr = 0U;
   HAL_StatusTypeDef status;
 
   /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) != 0UL)
+  if (FMAC_GET_START_BIT(hfmac) != 0U)
   {
     return HAL_ERROR;
   }
 
   /* Check that a valid configuration was done previously */
-  if (hfmac->FilterParam == 0UL)
+  if (hfmac->FilterParam == 0U)
   {
     return HAL_ERROR;
   }
@@ -936,34 +947,27 @@ HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutp
 
     /* Reset the busy flag (do not overwrite the possible write and read flag) */
     hfmac->State = HAL_FMAC_STATE_READY;
-
-    /* Return function status */
-    return status;
   }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    status = HAL_ERROR;
   }
+
+  return status;
 }
 
 /**
-  * @brief  Provide a new input buffer that will be loaded into the FMAC
-  *         input memory area.
+  * @brief  Provide a new input buffer that will be loaded into the FMAC input memory area.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  pInput New input vector (additional input data).
   * @param  pInputSize Size of the input vector (if all the data can't be
   *         written, it will be updated with the number of data read from FMAC).
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize)
 {
-  /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) == 0UL)
-  {
-    return HAL_ERROR;
-  }
+  HAL_StatusTypeDef status;
 
   /* Check the function parameters */
   if ((pInput == NULL) || (pInputSize == NULL))
@@ -975,6 +979,12 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *
     return HAL_ERROR;
   }
 
+  /* Check the START bit state */
+  if (FMAC_GET_START_BIT(hfmac) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the FMAC configuration */
   if (hfmac->InputAccess == FMAC_BUFFER_ACCESS_NONE)
   {
@@ -984,40 +994,36 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *
   /* Check whether the previous input vector has been handled */
   if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize)))
   {
-    return HAL_BUSY;
+    return HAL_ERROR;
   }
 
   /* Check that FMAC was initialized and that no writing is already ongoing */
   if (hfmac->WrState == HAL_FMAC_STATE_READY)
   {
     /* Register the new input buffer */
-    return (FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize));
+    status = FMAC_AppendFilterDataUpdateState(hfmac, pInput, pInputSize);
   }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    status = HAL_ERROR;
   }
+
+  return status;
 }
 
 /**
-  * @brief  Provide a new output buffer to be filled with the data
-  *         computed by FMAC unit.
+  * @brief  Provide a new output buffer to be filled with the data computed by FMAC unit.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  pOutput New output vector.
   * @param  pOutputSize Size of the output vector (if the vector can't
   *         be entirely filled, pOutputSize will be updated with the number
   *         of data read from FMAC).
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize)
 {
-  /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) == 0UL)
-  {
-    return HAL_ERROR;
-  }
+  HAL_StatusTypeDef status;
 
   /* Check the function parameters */
   if ((pOutput == NULL) || (pOutputSize == NULL))
@@ -1029,6 +1035,12 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i
     return HAL_ERROR;
   }
 
+  /* Check the START bit state */
+  if (FMAC_GET_START_BIT(hfmac) == 0U)
+  {
+    return HAL_ERROR;
+  }
+
   /* Check the FMAC configuration */
   if (hfmac->OutputAccess == FMAC_BUFFER_ACCESS_NONE)
   {
@@ -1038,25 +1050,27 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i
   /* Check whether the previous output vector has been handled */
   if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize)))
   {
-    return HAL_BUSY;
+    return HAL_ERROR;
   }
 
   /* Check that FMAC was initialized and that not reading is already ongoing */
   if (hfmac->RdState == HAL_FMAC_STATE_READY)
   {
     /* Register the new output buffer */
-    return (FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize));
+    status = FMAC_ConfigFilterOutputBufferUpdateState(hfmac, pOutput, pOutputSize);
   }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    status = HAL_ERROR;
   }
+
+  return status;
 }
 
 /**
-  * @brief  Write the previously provided user's input data and
-  *         fill the previously provided user's output buffer,
+  * @brief  Handle the input and/or output data in polling mode
+  * @note   This function writes the previously provided user's input data and
+  *         fills the previously provided user's output buffer,
   *         according to the existing FMAC configuration (polling mode only).
   *         The function returns when the input data has been handled or
   *         when the output data is filled. The possible unused data isn't
@@ -1066,7 +1080,7 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  Timeout timeout value.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout)
 {
@@ -1075,9 +1089,10 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti
   uint8_t inpollingover = POLLING_NOT_STOPPED;
   uint8_t outpolling;
   uint8_t outpollingover = POLLING_NOT_STOPPED;
+  HAL_StatusTypeDef status;
 
   /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) == 0UL)
+  if (FMAC_GET_START_BIT(hfmac) == 0U)
   {
     return HAL_ERROR;
   }
@@ -1162,41 +1177,40 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti
     /* Reset the busy flag (do not overwrite the possible write and read flag) */
     hfmac->State = HAL_FMAC_STATE_READY;
 
-    /* Return function status */
     if ((HAL_GetTick() - tickstart) >= Timeout)
     {
-      return HAL_TIMEOUT;
+      hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+      status = HAL_ERROR;
     }
     else
     {
-      return HAL_OK;
+      status = HAL_OK;
     }
   }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    status = HAL_ERROR;
   }
+
+  return status;
 }
 
 /**
   * @brief  Stop the FMAC processing.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
 {
-
-  /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) == 0UL)
-  {
-    return HAL_ERROR;
-  }
+  HAL_StatusTypeDef status;
 
   /* Check handle state is ready */
   if (hfmac->State == HAL_FMAC_STATE_READY)
   {
+    /* Change the FMAC state */
+    hfmac->State = HAL_FMAC_STATE_BUSY;
+
     /* Set the START bit to 0 (stop the previously configured filter) */
     CLEAR_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START);
 
@@ -1214,25 +1228,30 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac)
     }
 
     /* Reset FMAC unit (internal pointers) */
-    if (FMAC_Reset(hfmac) == HAL_TIMEOUT)
+    if (FMAC_Reset(hfmac) == HAL_ERROR)
     {
       /* Update FMAC error code and FMAC peripheral state */
       hfmac->ErrorCode = HAL_FMAC_ERROR_RESET;
       hfmac->State = HAL_FMAC_STATE_TIMEOUT;
-      return HAL_TIMEOUT;
+      status = HAL_ERROR;
+    }
+    else
+    {
+      /* Reset the data pointers */
+      FMAC_ResetDataPointers(hfmac);
+
+      status = HAL_OK;
     }
 
-    /* Reset the data pointers */
-    FMAC_ResetDataPointers(hfmac);
-
-    /* Return function status */
-    return HAL_OK;
+    /* Reset the busy flag */
+    hfmac->State = HAL_FMAC_STATE_READY;
   }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    status = HAL_ERROR;
   }
+
+  return status;
 }
 
 /**
@@ -1398,7 +1417,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
 
   /* Check if the read interrupt is enabled and if Y buffer empty flag isn't set */
   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_RIEN);
-  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0UL))
+  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_YEMPTY) == 0U) && (itsource != 0U))
   {
     /* Read some data if possible (Y size is used as a pseudo timeout in order
        to not get stuck too long under IT if FMAC keeps on processing input
@@ -1425,7 +1444,7 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
 
   /* Check if the write interrupt is enabled and if X1 buffer full flag isn't set */
   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_WIEN);
-  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0UL))
+  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_X1FULL) == 0U) && (itsource != 0U))
   {
     /* Write some data if possible (X1 size is used as a pseudo timeout in order
        to not get stuck too long under IT if FMAC keep on processing input
@@ -1452,21 +1471,21 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
 
   /* Check if the overflow error interrupt is enabled and if overflow error flag is raised */
   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_OVFLIEN);
-  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0UL))
+  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL) != 0U) && (itsource != 0U))
   {
     hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
   }
 
   /* Check if the underflow error interrupt is enabled and if underflow error flag is raised */
   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_UNFLIEN);
-  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0UL))
+  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL) != 0U) && (itsource != 0U))
   {
     hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
   }
 
   /* Check if the saturation error interrupt is enabled and if saturation error flag is raised */
   itsource = __HAL_FMAC_GET_IT_SOURCE(hfmac, FMAC_IT_SATIEN);
-  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0UL))
+  if ((__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT) != 0U) && (itsource != 0U))
   {
     hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
   }
@@ -1487,29 +1506,30 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac)
   * @}
   */
 
-/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State functions
-  * @brief    Peripheral State functions.
+/** @defgroup FMAC_Exported_Functions_Group5 Peripheral State and Error functions
+  * @brief    Peripheral State and Error functions.
   *
 @verbatim
   ==============================================================================
-                      ##### Peripheral State functions #####
+                 ##### Peripheral State and Error functions #####
   ==============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
+    [..]  This subsection provides functions allowing to
+      (+) Check the FMAC state
+      (+) Get error code
 
 @endverbatim
   * @{
   */
 
 /**
-  * @brief  Return the FMAC handle state.
+  * @brief  Return the FMAC state.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
-  * @retval HAL state
+  * @retval HAL_FMAC_StateTypeDef FMAC state
   */
-HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac)
 {
-  /* Return FMAC handle state */
+  /* Return FMAC state */
   return hfmac->State;
 }
 
@@ -1518,9 +1538,9 @@ HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac)
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @note   The returned error is a bit-map combination of possible errors.
-  * @retval Error bit-map
+  * @retval uint32_t Error bit-map based on @ref FMAC_Error_Code
   */
-uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
+uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac)
 {
   /* Return FMAC error code */
   return hfmac->ErrorCode;
@@ -1546,7 +1566,7 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac)
 /**
   * @brief  Perform a reset of the FMAC unit.
   * @param  hfmac FMAC handle.
-  * @retval FMAC status
+  * @retval HAL_StatusTypeDef HAL status
   */
 static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
 {
@@ -1559,11 +1579,12 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
   SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
 
   /* Wait until flag is reset */
-  while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0UL)
+  while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
   {
     if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
     {
-      return HAL_TIMEOUT;
+      hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+      return HAL_ERROR;
     }
   }
 
@@ -1574,7 +1595,7 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
 /**
   * @brief  Reset the data pointers of the FMAC unit.
   * @param  hfmac FMAC handle.
-  * @retval FMAC status
+  * @retval None
   */
 static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
 {
@@ -1585,7 +1606,7 @@ static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
 /**
   * @brief  Reset the input data pointers of the FMAC unit.
   * @param  hfmac FMAC handle.
-  * @retval FMAC status
+  * @retval None
   */
 static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
 {
@@ -1598,7 +1619,7 @@ static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
 /**
   * @brief  Reset the output data pointers of the FMAC unit.
   * @param  hfmac FMAC handle.
-  * @retval FMAC status
+  * @retval None
   */
 static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
 {
@@ -1609,19 +1630,17 @@ static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
 }
 
 /**
-  * @brief  Configure the FMAC filter according to the parameters
-            specified in the FMAC_FilterConfigTypeDef structure.
+  * @brief  Configure the FMAC filter.
+  * @note   The configuration is done according to the parameters
+  *         specified in the FMAC_FilterConfigTypeDef structure.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
-  * @param  sConfig pointer to a FMAC_FilterConfigTypeDef structure that
+  * @param  pConfig pointer to a FMAC_FilterConfigTypeDef structure that
   *         contains the FMAC configuration information.
-  * @param  PreloadAccess buffer preload method
-  *         This parameter can be one of the following values:
-  *           @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU
-  *           @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA
-  * @retval HAL status
+  * @param  PreloadAccess access mode used for the preload (polling or DMA).
+  * @retval HAL_StatusTypeDef HAL status
   */
-static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig,
+static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig,
                                            uint8_t PreloadAccess)
 {
   uint32_t tickstart;
@@ -1631,193 +1650,193 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte
 #endif /* USE_FULL_ASSERT */
 
   /* Check the parameters */
-  assert_param(IS_FMAC_THRESHOLD(sConfig->InputThreshold));
-  assert_param(IS_FMAC_THRESHOLD(sConfig->OutputThreshold));
-  assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->InputAccess));
-  assert_param(IS_FMAC_BUFFER_ACCESS(sConfig->OutputAccess));
-  assert_param(IS_FMAC_CLIP_STATE(sConfig->Clip));
-  assert_param(IS_FMAC_FILTER_FUNCTION(sConfig->Filter));
-  assert_param(IS_FMAC_PARAM_P(sConfig->Filter, sConfig->P));
-  assert_param(IS_FMAC_PARAM_Q(sConfig->Filter, sConfig->Q));
-  assert_param(IS_FMAC_PARAM_R(sConfig->Filter, sConfig->R));
+  assert_param(IS_FMAC_THRESHOLD(pConfig->InputThreshold));
+  assert_param(IS_FMAC_THRESHOLD(pConfig->OutputThreshold));
+  assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->InputAccess));
+  assert_param(IS_FMAC_BUFFER_ACCESS(pConfig->OutputAccess));
+  assert_param(IS_FMAC_CLIP_STATE(pConfig->Clip));
+  assert_param(IS_FMAC_FILTER_FUNCTION(pConfig->Filter));
+  assert_param(IS_FMAC_PARAM_P(pConfig->Filter, pConfig->P));
+  assert_param(IS_FMAC_PARAM_Q(pConfig->Filter, pConfig->Q));
+  assert_param(IS_FMAC_PARAM_R(pConfig->Filter, pConfig->R));
 
   /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) != 0UL)
+  if (FMAC_GET_START_BIT(hfmac) != 0U)
   {
     return HAL_ERROR;
   }
 
   /* Check handle state is ready */
-  if (hfmac->State == HAL_FMAC_STATE_READY)
+  if (hfmac->State != HAL_FMAC_STATE_READY)
   {
-    /* Change the FMAC state */
-    hfmac->State = HAL_FMAC_STATE_BUSY;
+    return HAL_ERROR;
+  }
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
+  /* Change the FMAC state */
+  hfmac->State = HAL_FMAC_STATE_BUSY;
 
-    /* Indicate that there is no valid configuration done */
-    hfmac->FilterParam = 0UL;
+  /* Get tick */
+  tickstart = HAL_GetTick();
 
-    /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
-    if (sConfig->InputBufferSize != 0U)
-    {
-      MODIFY_REG(hfmac->Instance->X1BUFCFG,                                                                   \
-                 (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE),                                         \
-                 (((((uint32_t)(sConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos)     & FMAC_X1BUFCFG_X1_BASE) | \
-                  ((((uint32_t)(sConfig->InputBufferSize))  << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE)));
-    }
+  /* Indicate that there is no valid configuration done */
+  hfmac->FilterParam = 0U;
 
-    /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
-    if (sConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
-    {
-      /* Check the parameter */
-      assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), sConfig->InputThreshold, sConfig->InputAccess));
+  /* FMAC_X1BUFCFG: Configure the input buffer within the internal memory if required */
+  if (pConfig->InputBufferSize != 0U)
+  {
+    MODIFY_REG(hfmac->Instance->X1BUFCFG,                                                                   \
+               (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE),                                         \
+               (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos)     & FMAC_X1BUFCFG_X1_BASE) | \
+                ((((uint32_t)(pConfig->InputBufferSize))  << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \
+                 FMAC_X1BUFCFG_X1_BUF_SIZE)));
+  }
 
-      MODIFY_REG(hfmac->Instance->X1BUFCFG, \
-                 FMAC_X1BUFCFG_FULL_WM,     \
-                 ((sConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
-    }
+  /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */
+  if (pConfig->InputThreshold != FMAC_THRESHOLD_NO_VALUE)
+  {
+    /* Check the parameter */
+    assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_X1_SIZE(hfmac), pConfig->InputThreshold, pConfig->InputAccess));
 
-    /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
-    if (sConfig->CoeffBufferSize != 0U)
-    {
-      MODIFY_REG(hfmac->Instance->X2BUFCFG,                                                                   \
-                 (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE),                                         \
-                 (((((uint32_t)(sConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos)     & FMAC_X2BUFCFG_X2_BASE) | \
-                  ((((uint32_t)(sConfig->CoeffBufferSize))  << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE)));
-    }
+    MODIFY_REG(hfmac->Instance->X1BUFCFG, \
+               FMAC_X1BUFCFG_FULL_WM,     \
+               ((pConfig->InputThreshold) & FMAC_X1BUFCFG_FULL_WM));
+  }
 
-    /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
-    if (sConfig->OutputBufferSize != 0U)
-    {
-      MODIFY_REG(hfmac->Instance->YBUFCFG,                                                                    \
-                 (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE),                                             \
-                 (((((uint32_t)(sConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos)     & FMAC_YBUFCFG_Y_BASE) |    \
-                  ((((uint32_t)(sConfig->OutputBufferSize))  << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
-    }
+  /* FMAC_X2BUFCFG: Configure the coefficient buffer within the internal memory */
+  if (pConfig->CoeffBufferSize != 0U)
+  {
+    MODIFY_REG(hfmac->Instance->X2BUFCFG,                                                                   \
+               (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE),                                         \
+               (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos)     & FMAC_X2BUFCFG_X2_BASE) | \
+                ((((uint32_t)(pConfig->CoeffBufferSize))  << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\
+                 FMAC_X2BUFCFG_X2_BUF_SIZE)));
+  }
 
-    /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
-    if (sConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
-    {
-      /* Check the parameter */
-      assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), sConfig->OutputThreshold, sConfig->OutputAccess));
+  /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */
+  if (pConfig->OutputBufferSize != 0U)
+  {
+    MODIFY_REG(hfmac->Instance->YBUFCFG,                                                                    \
+               (FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE),                                             \
+               (((((uint32_t)(pConfig->OutputBaseAddress)) << FMAC_YBUFCFG_Y_BASE_Pos)     & FMAC_YBUFCFG_Y_BASE) |    \
+                ((((uint32_t)(pConfig->OutputBufferSize))  << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) & FMAC_YBUFCFG_Y_BUF_SIZE)));
+  }
 
-      MODIFY_REG(hfmac->Instance->YBUFCFG, \
-                 FMAC_YBUFCFG_EMPTY_WM,    \
-                 ((sConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
-    }
+  /* FMAC_YBUFCFG: Configure the output threshold if valid when compared to the configured Y size */
+  if (pConfig->OutputThreshold != FMAC_THRESHOLD_NO_VALUE)
+  {
+    /* Check the parameter */
+    assert_param(IS_FMAC_THRESHOLD_APPLICABLE(FMAC_GET_Y_SIZE(hfmac), pConfig->OutputThreshold, pConfig->OutputAccess));
 
-    /* CR: Configure the clip feature */
-    tmpcr = sConfig->Clip & FMAC_CR_CLIPEN;
+    MODIFY_REG(hfmac->Instance->YBUFCFG, \
+               FMAC_YBUFCFG_EMPTY_WM,    \
+               ((pConfig->OutputThreshold) & FMAC_YBUFCFG_EMPTY_WM));
+  }
 
-    /* CR: If IT or DMA will be used, enable error interrupts.
-      * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
-    if ((sConfig->InputAccess  == FMAC_BUFFER_ACCESS_DMA) || (sConfig->InputAccess  == FMAC_BUFFER_ACCESS_IT) ||
-        (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (sConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
-    {
-      tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
-    }
+  /* FMAC_CR: Configure the clip feature */
+  tmpcr = pConfig->Clip & FMAC_CR_CLIPEN;
 
-    /* CR: write the value */
-    WRITE_REG(hfmac->Instance->CR, tmpcr);
+  /* FMAC_CR: If IT or DMA will be used, enable error interrupts.
+    * Being more a debugging feature, FMAC_CR_SATIEN isn't enabled by default. */
+  if ((pConfig->InputAccess  == FMAC_BUFFER_ACCESS_DMA) || (pConfig->InputAccess  == FMAC_BUFFER_ACCESS_IT) ||
+      (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_DMA) || (pConfig->OutputAccess == FMAC_BUFFER_ACCESS_IT))
+  {
+    tmpcr |= FMAC_IT_UNFLIEN | FMAC_IT_OVFLIEN;
+  }
 
-    /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
-    hfmac->InputAccess = sConfig->InputAccess;
-    hfmac->OutputAccess = sConfig->OutputAccess;
+  /* FMAC_CR: write the value */
+  WRITE_REG(hfmac->Instance->CR, tmpcr);
 
-    /* Check whether the configured X2 is big enough for the filter */
+  /* Save the input/output accesses in order to configure RIEN, WIEN, DMAREN and DMAWEN during filter start */
+  hfmac->InputAccess = pConfig->InputAccess;
+  hfmac->OutputAccess = pConfig->OutputAccess;
+
+  /* Check whether the configured X2 is big enough for the filter */
 #if defined(USE_FULL_ASSERT)
-    x2size = FMAC_GET_X2_SIZE(hfmac);
+  x2size = FMAC_GET_X2_SIZE(hfmac);
 #endif /* USE_FULL_ASSERT */
-    assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= sConfig->P)) || \
-                 ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)sConfig->P + (uint32_t)sConfig->Q))));
+  assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \
+               ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
+                (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q))));
 
-    /* Build the PARAM value that will be used when starting the filter */
-    hfmac->FilterParam = (FMAC_PARAM_START | sConfig->Filter |                   \
-                          ((((uint32_t)(sConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
-                          ((((uint32_t)(sConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
-                          ((((uint32_t)(sConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
+  /* Build the PARAM value that will be used when starting the filter */
+  hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter |                   \
+                        ((((uint32_t)(pConfig->P)) << FMAC_PARAM_P_Pos) & FMAC_PARAM_P) | \
+                        ((((uint32_t)(pConfig->Q)) << FMAC_PARAM_Q_Pos) & FMAC_PARAM_Q) | \
+                        ((((uint32_t)(pConfig->R)) << FMAC_PARAM_R_Pos) & FMAC_PARAM_R));
 
-    /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
-    if ((sConfig->pCoeffB != NULL) && (sConfig->CoeffBSize != 0U))
+  /* Initialize the coefficient buffer if required (pCoeffA for FIR only) */
+  if ((pConfig->pCoeffB != NULL) && (pConfig->CoeffBSize != 0U))
+  {
+    /* FIR/IIR: The provided coefficients should match X2 size */
+    assert_param(((uint32_t)pConfig->CoeffASize + (uint32_t)pConfig->CoeffBSize) <= x2size);
+    /* FIR/IIR: The size of pCoeffB should match the parameter P */
+    assert_param(pConfig->CoeffBSize >= pConfig->P);
+    /* pCoeffA should be provided for IIR but not for FIR */
+    /* IIR : if pCoeffB is provided, pCoeffA should also be there */
+    /* IIR: The size of pCoeffA should match the parameter Q */
+    assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
+                  (pConfig->pCoeffA == NULL) && (pConfig->CoeffASize == 0U)) ||
+                 ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
+                  (pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U) &&
+                  (pConfig->CoeffASize >= pConfig->Q)));
+
+    /* Write number of values to be loaded, the data load function and start the operation */
+    WRITE_REG(hfmac->Instance->PARAM,                      \
+              (((uint32_t)(pConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
+               ((uint32_t)(pConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
+               FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
+
+    if (PreloadAccess == PRELOAD_ACCESS_POLLING)
     {
-      /* FIR/IIR: The provided coefficients should match X2 size */
-      assert_param(((uint32_t)sConfig->CoeffASize + (uint32_t)sConfig->CoeffBSize) <= x2size);
-      /* FIR/IIR: The size of pCoeffB should match the parameter P */
-      assert_param(sConfig->CoeffBSize >= sConfig->P);
-      /* pCoeffA should be provided for IIR but not for FIR */
-      /* IIR : if pCoeffB is provided, pCoeffA should also be there */
-      /* IIR: The size of pCoeffA should match the parameter Q */
-      assert_param(((sConfig->Filter == FMAC_FUNC_CONVO_FIR) &&
-                    (sConfig->pCoeffA == NULL) && (sConfig->CoeffASize == 0U)) ||
-                   ((sConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) &&
-                    (sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U) &&
-                    (sConfig->CoeffASize >= sConfig->Q)));
+      /* Load the buffer into the internal memory */
+      FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffB), pConfig->CoeffBSize);
 
-      /* Write number of values to be loaded, the data load function and start the operation */
-      WRITE_REG(hfmac->Instance->PARAM,                      \
-                (((uint32_t)(sConfig->CoeffBSize) << FMAC_PARAM_P_Pos) | \
-                 ((uint32_t)(sConfig->CoeffASize) << FMAC_PARAM_Q_Pos) | \
-                 FMAC_FUNC_LOAD_X2 | FMAC_PARAM_START));
-
-      if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+      /* Load pCoeffA if needed */
+      if ((pConfig->pCoeffA != NULL) && (pConfig->CoeffASize != 0U))
       {
         /* Load the buffer into the internal memory */
-        FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffB), sConfig->CoeffBSize);
-
-        /* Load pCoeffA if needed */
-        if ((sConfig->pCoeffA != NULL) && (sConfig->CoeffASize != 0U))
-        {
-          /* Load the buffer into the internal memory */
-          FMAC_WritePreloadDataIncrementPtr(hfmac, &(sConfig->pCoeffA), sConfig->CoeffASize);
-        }
-
-        /* Wait for the end of the writing */
-        if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
-        {
-          hfmac->State = HAL_FMAC_STATE_TIMEOUT;
-          return HAL_TIMEOUT;
-        }
-
-        /* Change the FMAC state */
-        hfmac->State = HAL_FMAC_STATE_READY;
+        FMAC_WritePreloadDataIncrementPtr(hfmac, &(pConfig->pCoeffA), pConfig->CoeffASize);
       }
-      else
+
+      /* Wait for the end of the writing */
+      if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
       {
-        hfmac->pInput = sConfig->pCoeffA;
-        hfmac->InputCurrentSize = sConfig->CoeffASize;
-
-        /* Set the FMAC DMA transfer complete callback */
-        hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
-        hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
-        /* Set the DMA error callback */
-        hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
-        /* Enable the DMA stream managing FMAC preload data write */
-        return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)sConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
-                                 sConfig->CoeffBSize));
+        hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+        hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+        return HAL_ERROR;
       }
+
+      /* Change the FMAC state */
+      hfmac->State = HAL_FMAC_STATE_READY;
     }
     else
     {
-      /* Change the FMAC state */
-      hfmac->State = HAL_FMAC_STATE_READY;
+      hfmac->pInput = pConfig->pCoeffA;
+      hfmac->InputCurrentSize = pConfig->CoeffASize;
+
+      /* Set the FMAC DMA transfer complete callback */
+      hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+      hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterConfig;
+      /* Set the DMA error callback */
+      hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+      /* Enable the DMA stream managing FMAC preload data write */
+      return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pConfig->pCoeffB, (uint32_t)&hfmac->Instance->WDATA,
+                               pConfig->CoeffBSize));
     }
   }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    /* Change the FMAC state */
+    hfmac->State = HAL_FMAC_STATE_READY;
   }
 
-  /* Return function status */
   return HAL_OK;
 }
 
 /**
   * @brief  Preload the input (FIR, IIR) and output data (IIR) of the FMAC filter.
-  *         They will be used by FMAC as soon as HAL_FMAC_FilterStart is called.
+  * @note   The set(s) of data will be used by FMAC as soon as @ref HAL_FMAC_FilterStart is called.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  pInput Preloading of the first elements of the input buffer (X1).
@@ -1828,28 +1847,26 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte
   *         If not needed, it should be set to NULL.
   * @param  OutputSize Size of the output vector.
   *         As pOutput is used for preloading data, it cannot be bigger than the output memory area.
-  * @param  PreloadAccess buffer preload method
-  *         This parameter can be one of the following values:
-  *           @arg @ref PRELOAD_ACCESS_POLLING preloading using CPU
-  *           @arg @ref PRELOAD_ACCESS_DMA Get preloading using DMA
-  * @note   The input and the output buffers can be filled by calling several times HAL_FMAC_FilterPreload
+  * @param  PreloadAccess access mode used for the preload (polling or DMA).
+  * @note   The input and the output buffers can be filled by calling several times @ref HAL_FMAC_FilterPreload
   *         (each call filling partly the buffers). In case of overflow (too much data provided through
   *         all these calls), an error will be returned.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
                                             int16_t *pOutput, uint8_t OutputSize, uint8_t PreloadAccess)
 {
   uint32_t tickstart;
+  HAL_StatusTypeDef status;
 
   /* Check the START bit state */
-  if (FMAC_GET_START_BIT(hfmac) != 0UL)
+  if (FMAC_GET_START_BIT(hfmac) != 0U)
   {
     return HAL_ERROR;
   }
 
   /* Check that a valid configuration was done previously */
-  if (hfmac->FilterParam == 0UL)
+  if (hfmac->FilterParam == 0U)
   {
     return HAL_ERROR;
   }
@@ -1867,122 +1884,126 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *
   }
 
   /* Check handle state is ready */
-  if (hfmac->State == HAL_FMAC_STATE_READY)
+  if (hfmac->State != HAL_FMAC_STATE_READY)
   {
-    /* Change the FMAC state */
-    hfmac->State = HAL_FMAC_STATE_BUSY;
+    return HAL_ERROR;
+  }
 
-    /* Get tick */
-    tickstart = HAL_GetTick();
+  /* Change the FMAC state */
+  hfmac->State = HAL_FMAC_STATE_BUSY;
 
-    /* Preload the input buffer if required */
-    if ((pInput != NULL) && (InputSize != 0U))
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Preload the input buffer if required */
+  if ((pInput != NULL) && (InputSize != 0U))
+  {
+    /* Write number of values to be loaded, the data load function and start the operation */
+    WRITE_REG(hfmac->Instance->PARAM, \
+              (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+
+    if (PreloadAccess == PRELOAD_ACCESS_POLLING)
     {
-      /* Write number of values to be loaded, the data load function and start the operation */
-      WRITE_REG(hfmac->Instance->PARAM, \
-                (((uint32_t)InputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_X1 | FMAC_PARAM_START));
+      /* Load the buffer into the internal memory */
+      FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
 
-      if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+      /* Wait for the end of the writing */
+      if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
       {
-        /* Load the buffer into the internal memory */
-        FMAC_WritePreloadDataIncrementPtr(hfmac, &pInput, InputSize);
-
-        /* Wait for the end of the writing */
-        if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
-        {
-          hfmac->State = HAL_FMAC_STATE_TIMEOUT;
-          return HAL_TIMEOUT;
-        }
+        hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+        hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+        return HAL_ERROR;
       }
-      else
-      {
-        hfmac->pInput = pOutput;
-        hfmac->InputCurrentSize = OutputSize;
-
-        /* Set the FMAC DMA transfer complete callback */
-        hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
-        hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
-        /* Set the DMA error callback */
-        hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
-        /* Enable the DMA stream managing FMAC preload data write */
-        return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
-      }
-    }
-
-    /* Preload the output buffer if required */
-    if ((pOutput != NULL) && (OutputSize != 0U))
-    {
-      /* Write number of values to be loaded, the data load function and start the operation */
-      WRITE_REG(hfmac->Instance->PARAM, \
-                (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
-
-      if (PreloadAccess == PRELOAD_ACCESS_POLLING)
-      {
-        /* Load the buffer into the internal memory */
-        FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
-
-        /* Wait for the end of the writing */
-        if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
-        {
-          hfmac->State = HAL_FMAC_STATE_TIMEOUT;
-          return HAL_TIMEOUT;
-        }
-      }
-      else
-      {
-        hfmac->pInput = NULL;
-        hfmac->InputCurrentSize = 0U;
-
-        /* Set the FMAC DMA transfer complete callback */
-        hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
-        hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
-        /* Set the DMA error callback */
-        hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
-
-        /* Enable the DMA stream managing FMAC preload data write */
-        return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
-      }
-    }
-
-    /* Update the error codes */
-    if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
-    {
-      hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
-    }
-    if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
-    {
-      hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
-    }
-
-    /* Change the FMAC state */
-    hfmac->State = HAL_FMAC_STATE_READY;
-
-    /* Return function status */
-    if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
-    {
-      return HAL_OK;
     }
     else
     {
-      return HAL_ERROR;
+      hfmac->pInput = pOutput;
+      hfmac->InputCurrentSize = OutputSize;
+
+      /* Set the FMAC DMA transfer complete callback */
+      hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+      hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+      /* Set the DMA error callback */
+      hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+      /* Enable the DMA stream managing FMAC preload data write */
+      return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pInput, (uint32_t)&hfmac->Instance->WDATA, InputSize));
     }
   }
+
+  /* Preload the output buffer if required */
+  if ((pOutput != NULL) && (OutputSize != 0U))
+  {
+    /* Write number of values to be loaded, the data load function and start the operation */
+    WRITE_REG(hfmac->Instance->PARAM, \
+              (((uint32_t)OutputSize << FMAC_PARAM_P_Pos) | FMAC_FUNC_LOAD_Y | FMAC_PARAM_START));
+
+    if (PreloadAccess == PRELOAD_ACCESS_POLLING)
+    {
+      /* Load the buffer into the internal memory */
+      FMAC_WritePreloadDataIncrementPtr(hfmac, &pOutput, OutputSize);
+
+      /* Wait for the end of the writing */
+      if (FMAC_WaitOnStartUntilTimeout(hfmac, tickstart, HAL_FMAC_TIMEOUT_VALUE) != HAL_OK)
+      {
+        hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
+        hfmac->State = HAL_FMAC_STATE_TIMEOUT;
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      hfmac->pInput = NULL;
+      hfmac->InputCurrentSize = 0U;
+
+      /* Set the FMAC DMA transfer complete callback */
+      hfmac->hdmaPreload->XferHalfCpltCallback = NULL;
+      hfmac->hdmaPreload->XferCpltCallback = FMAC_DMAFilterPreload;
+      /* Set the DMA error callback */
+      hfmac->hdmaPreload->XferErrorCallback = FMAC_DMAError;
+
+      /* Enable the DMA stream managing FMAC preload data write */
+      return (HAL_DMA_Start_IT(hfmac->hdmaPreload, (uint32_t)pOutput, (uint32_t)&hfmac->Instance->WDATA, OutputSize));
+    }
+  }
+
+  /* Update the error codes */
+  if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_OVFL))
+  {
+    hfmac->ErrorCode |= HAL_FMAC_ERROR_OVFL;
+  }
+  if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_UNFL))
+  {
+    hfmac->ErrorCode |= HAL_FMAC_ERROR_UNFL;
+  }
+  if (__HAL_FMAC_GET_FLAG(hfmac, FMAC_FLAG_SAT))
+  {
+    hfmac->ErrorCode |= HAL_FMAC_ERROR_SAT;
+  }
+
+  /* Change the FMAC state */
+  hfmac->State = HAL_FMAC_STATE_READY;
+
+  /* Return function status */
+  if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
+  {
+    status = HAL_OK;
+  }
   else
   {
-    /* Return function status */
-    return HAL_BUSY;
+    status = HAL_ERROR;
   }
+  return status;
 }
 
 /**
   * @brief  Write data into FMAC internal memory through WDATA and increment input buffer pointer.
-  *         This function is only used with preload functions.
+  * @note   This function is only used with preload functions.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  ppData pointer to pointer to the data buffer.
   * @param  Size size of the data buffer.
-  * @retval none
+  * @retval None
   */
 static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t **ppData, uint8_t Size)
 {
@@ -2001,33 +2022,31 @@ static void FMAC_WritePreloadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, int16_t
   * @param  hfmac FMAC handle.
   * @param  Tickstart Tick start value.
   * @param  Timeout Timeout duration.
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, uint32_t Tickstart, uint32_t Timeout)
 {
   /* Wait until flag changes */
-  while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+  while (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
   {
     if ((HAL_GetTick() - Tickstart) > Timeout)
     {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hfmac);
+      hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
 
-      return HAL_TIMEOUT;
+      return HAL_ERROR;
     }
   }
   return HAL_OK;
 }
 
 /**
-  * @brief  Register the new input buffer, update DMA configuration
-  *         if needed and change the FMAC state.
+  * @brief  Register the new input buffer, update DMA configuration if needed and change the FMAC state.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  pInput New input vector (additional input data).
   * @param  pInputSize Size of the input vector (if all the data can't be
   *         written, it will be updated with the number of data read from FMAC).
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pInput,
                                                           uint16_t *pInputSize)
@@ -2060,20 +2079,18 @@ static HAL_StatusTypeDef FMAC_AppendFilterDataUpdateState(FMAC_HandleTypeDef *hf
     hfmac->pInputSize = pInputSize;
   }
 
-  /* Return function status */
   return HAL_OK;
 }
 
 /**
-  * @brief  Register the new output buffer, update DMA configuration
-  *         if needed and change the FMAC state.
+  * @brief  Register the new output buffer, update DMA configuration if needed and change the FMAC state.
   * @param  hfmac pointer to a FMAC_HandleTypeDef structure that contains
   *         the configuration information for FMAC module.
   * @param  pOutput New output vector.
   * @param  pOutputSize Size of the output vector (if the vector can't
   *         be entirely filled, pOutputSize will be updated with the number
   *         of data read from FMAC).
-  * @retval HAL status
+  * @retval HAL_StatusTypeDef HAL status
   */
 static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTypeDef *hfmac, int16_t *pOutput,
                                                                   uint16_t *pOutputSize)
@@ -2082,7 +2099,7 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp
   hfmac->OutputCurrentSize = 0U;
 
   /* Check whether a valid pointer was provided */
-  if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0UL))
+  if ((pOutput == NULL) || (pOutputSize == NULL) || (*pOutputSize == 0U))
   {
     /* The user will have to provide a valid configuration later */
     hfmac->pOutput = NULL;
@@ -2119,7 +2136,6 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp
     hfmac->RdState = HAL_FMAC_STATE_BUSY_RD;
   }
 
-  /* Return function status */
   return HAL_OK;
 }
 
@@ -2128,7 +2144,7 @@ static HAL_StatusTypeDef FMAC_ConfigFilterOutputBufferUpdateState(FMAC_HandleTyp
   * @param  hfmac FMAC handle.
   * @param  MaxSizeToRead Maximum number of data to read (this serves as a timeout
   *         if FMAC continuously writes into the output buffer).
-  * @retval HAL status
+  * @retval None
   */
 static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToRead)
 {
@@ -2137,7 +2153,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz
   uint32_t tmpvalue;
 
   /* Check if there is data to read */
-  if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0UL)
+  if (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) != 0U)
   {
     return;
   }
@@ -2166,7 +2182,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz
     *(hfmac->pOutput) = (int16_t)tmpvalue;
     hfmac->pOutput++;
     hfmac->OutputCurrentSize++;
-  } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0UL);
+  } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_YEMPTY) == 0U);
 
   /* Y buffer empty flag has just be raised, read the threshold */
   threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_Y_EMPTY_WM(hfmac)) - 1U;
@@ -2192,7 +2208,7 @@ static void FMAC_ReadDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSiz
   * @param  hfmac FMAC handle.
   * @param  MaxSizeToWrite Maximum number of data to write (this serves as a timeout
   *         if FMAC continuously empties the input buffer).
-  * @retval HAL status
+  * @retval None
   */
 static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSizeToWrite)
 {
@@ -2200,7 +2216,7 @@ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSi
   uint16_t threshold;
 
   /* Check if there is room in FMAC */
-  if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0UL)
+  if (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) != 0U)
   {
     return;
   }
@@ -2228,7 +2244,7 @@ static void FMAC_WriteDataIncrementPtr(FMAC_HandleTypeDef *hfmac, uint16_t MaxSi
     WRITE_REG(hfmac->Instance->WDATA, (((uint32_t)(*(hfmac->pInput))) & FMAC_WDATA_WDATA));
     hfmac->pInput++;
     hfmac->InputCurrentSize++;
-  } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0UL);
+  } while (READ_BIT(hfmac->Instance->SR, FMAC_SR_X1FULL) == 0U);
 
   /* X1 buffer full flag has just be raised, read the threshold */
   threshold = (uint16_t)FMAC_GET_THRESHOLD_FROM_WM(FMAC_GET_X1_FULL_WM(hfmac)) - 1U;
@@ -2357,7 +2373,7 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
   else
   {
     /* Wait for the end of the writing */
-    for (index = 0U; index < 0xFFU; index++)
+    for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
     {
       if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
       {
@@ -2365,8 +2381,8 @@ static void FMAC_DMAFilterConfig(DMA_HandleTypeDef *hdma)
       }
     }
 
-    /* If 'START' is still set, there was an error: set FMAC handle state to error */
-    if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+    /* If 'START' is still set, there was a timeout: set FMAC handle state to timeout */
+    if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
     {
       hfmac->State = HAL_FMAC_STATE_TIMEOUT;
     }
@@ -2409,16 +2425,16 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma)
   FMAC_HandleTypeDef *hfmac = (FMAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Wait for the end of the X1 writing */
-  for (index = 0U; index < 0xFFU; index++)
+  for (index = 0U; index < MAX_PRELOAD_INDEX; index++)
   {
-    if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0UL)
+    if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) == 0U)
     {
       break;
     }
   }
 
   /* If 'START' is still set, there was an error: set FMAC handle state to error */
-  if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0UL)
+  if (READ_BIT(hfmac->Instance->PARAM, FMAC_PARAM_START) != 0U)
   {
     hfmac->State = HAL_FMAC_STATE_TIMEOUT;
     hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
@@ -2454,7 +2470,6 @@ static void FMAC_DMAFilterPreload(DMA_HandleTypeDef *hdma)
     /* nothing to do */
   }
 
-  /* Return function status */
   if (hfmac->ErrorCode == HAL_FMAC_ERROR_NONE)
   {
     /* Change the FMAC state */
@@ -2516,5 +2531,3 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma)
 
 #endif /* HAL_FMAC_MODULE_ENABLED */
 #endif /* FMAC */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.h
index 8eb9941e62..bd37972fd6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_fmac.h
@@ -2,18 +2,16 @@
   ******************************************************************************
   * @file    stm32h7xx_hal_fmac.h
   * @author  MCD Application Team
-  * @brief   This file contains all the functions prototypes for the FMAC firmware
-  *          library.
+  * @brief   Header for stm32h7xx_hal_fmac.c module
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -71,10 +69,12 @@ typedef struct
   uint32_t                   FilterParam;        /*!< Filter configuration (operation and parameters).
                                                       Set to 0 if no valid configuration was applied. */
 
-  uint8_t                    InputAccess;       /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
+  uint8_t                    InputAccess;       /*!< Access to the input buffer (internal memory area):
+                                                     DMA, IT, Polling, None.
                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
 
-  uint8_t                    OutputAccess;      /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
+  uint8_t                    OutputAccess;      /*!< Access to the output buffer (internal memory area):
+                                                     DMA, IT, Polling, None.
                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
 
   int16_t                    *pInput;            /*!< Pointer to FMAC input data buffer */
@@ -82,20 +82,23 @@ typedef struct
   uint16_t                   InputCurrentSize;   /*!< Number of the input elements already written into FMAC */
 
   uint16_t                   *pInputSize;        /*!< Number of input elements to write (memory allocated to pInput).
-                                                      In case of early interruption of the filter operation, its value will be updated. */
+                                                      In case of early interruption of the filter operation,
+                                                      its value will be updated. */
 
   int16_t                    *pOutput;           /*!< Pointer to FMAC output data buffer */
 
   uint16_t                   OutputCurrentSize;  /*!< Number of the output elements already read from FMAC */
 
   uint16_t                   *pOutputSize;       /*!< Number of output elements to read (memory allocated to pOutput).
-                                                      In case of early interruption of the filter operation, its value will be updated. */
+                                                      In case of early interruption of the filter operation,
+                                                      its value will be updated. */
 
   DMA_HandleTypeDef          *hdmaIn;            /*!< FMAC peripheral input data DMA handle parameters */
 
   DMA_HandleTypeDef          *hdmaOut;           /*!< FMAC peripheral output data DMA handle parameters */
 
-  DMA_HandleTypeDef          *hdmaPreload;       /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */
+  DMA_HandleTypeDef          *hdmaPreload;       /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle
+                                                      parameters */
 
 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
   void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac);               /*!< FMAC error callback                  */
@@ -136,7 +139,7 @@ typedef struct
 
 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
 /**
-  * @brief  FMAC Callback ID structure definition
+  * @brief  FMAC Callback ID enumeration definition
   */
 typedef enum
 {
@@ -164,34 +167,41 @@ typedef  void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac);  /*!< pointer
   */
 typedef struct
 {
-  uint8_t                    InputBaseAddress;  /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
-                                                     Ignored if InputBufferSize is set to 0 (previous configuration kept).
-                                                     NB: the buffers can overlap or even coincide exactly. */
+  uint8_t                    InputBaseAddress;  /*!< Base address of the input buffer (X1) within the internal memory
+                                                     (0x00 to 0xFF). Ignored if InputBufferSize is set to 0
+                                                     (previous configuration kept).
+                                                     Note: the buffers can overlap or even coincide exactly. */
 
-  uint8_t                    InputBufferSize;   /*!< Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+  uint8_t                    InputBufferSize;   /*!< Number of 16-bit words allocated to the input buffer
+                                                     (including the optional "headroom").
                                                      0 if a previous configuration should be kept. */
 
-  uint32_t                   InputThreshold;    /*!< Input threshold: the buffer full flag will be set if the number of free spaces
-                                                     in the buffer is inferior to this threshold.
-                                                     This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+  uint32_t                   InputThreshold;    /*!< Input threshold: the buffer full flag will be set if the number
+                                                     of free spaces in the buffer is lower than this threshold.
+                                                     This parameter can be a value
+                                                     of @ref FMAC_Data_Buffer_Threshold. */
 
-  uint8_t                    CoeffBaseAddress;  /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
-                                                     Ignored if CoeffBufferSize is set to 0 (previous configuration kept).
-                                                     NB: the buffers can overlap or even coincide exactly. */
+  uint8_t                    CoeffBaseAddress;  /*!< Base address of the coefficient buffer (X2) within the internal
+                                                     memory (0x00 to 0xFF). Ignored if CoeffBufferSize is set to 0
+                                                     (previous configuration kept).
+                                                     Note: the buffers can overlap or even coincide exactly. */
 
-  uint8_t                    CoeffBufferSize;   /*!< Number of 16-bit addresses allocated to the coefficient buffer.
+  uint8_t                    CoeffBufferSize;   /*!< Number of 16-bit words allocated to the coefficient buffer.
                                                      0 if a previous configuration should be kept. */
 
-  uint8_t                    OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
-                                                     Ignored if OuputBufferSize is set to 0 (previous configuration kept).
-                                                     NB: the buffers can overlap or even coincide exactly. */
+  uint8_t                    OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal
+                                                     memory (0x00 to 0xFF). Ignored if OuputBufferSize is set to 0
+                                                     (previous configuration kept).
+                                                     Note: the buffers can overlap or even coincide exactly. */
 
-  uint8_t                    OutputBufferSize;  /*!< Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+  uint8_t                    OutputBufferSize;  /*!< Number of 16-bit words allocated to the output buffer
+                                                    (including the optional "headroom").
                                                      0 if a previous configuration should be kept. */
 
-  uint32_t                   OutputThreshold;   /*!< Output threshold: the buffer empty flag will be set if the number of unread values
-                                                     in the buffer is inferior to this threshold.
-                                                     This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */
+  uint32_t                   OutputThreshold;   /*!< Output threshold: the buffer empty flag will be set if the number
+                                                     of unread values in the buffer is lower than this threshold.
+                                                     This parameter can be a value
+                                                     of @ref FMAC_Data_Buffer_Threshold. */
 
   int16_t                    *pCoeffA;          /*!< [IIR only] Initialization of the coefficient vector A.
                                                      If not needed, it should be set to NULL. */
@@ -199,21 +209,27 @@ typedef struct
   uint8_t                    CoeffASize;        /*!< Size of the coefficient vector A. */
 
   int16_t                    *pCoeffB;          /*!< Initialization of the coefficient vector B.
-                                                     If not needed (re-use of a previously loaded buffer), it should be set to NULL. */
+                                                     If not needed (re-use of a previously loaded buffer),
+                                                     it should be set to NULL. */
 
   uint8_t                    CoeffBSize;        /*!< Size of the coefficient vector B. */
 
-  uint8_t                    InputAccess;       /*!< Access to the input buffer (internal memory area): DMT, IT, Polling, None.
+  uint8_t                    InputAccess;       /*!< Access to the input buffer (internal memory area):
+                                                     DMA, IT, Polling, None.
                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
 
-  uint8_t                    OutputAccess;      /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
+  uint8_t                    OutputAccess;      /*!< Access to the output buffer (internal memory area):
+                                                     DMA, IT, Polling, None.
                                                      This parameter can be a value of @ref FMAC_Buffer_Access. */
 
-  uint32_t                   Clip;              /*!< Enable or disable the clipping feature (wrapping when the q1.15 range is exceeded).
+  uint32_t                   Clip;              /*!< Enable or disable the clipping feature. If the q1.15 range
+                                                     is exceeded, wrapping is done when the clipping feature is disabled
+                                                     and saturation is done when the clipping feature is enabled.
                                                      This parameter can be a value of @ref FMAC_Clip_State. */
 
   uint32_t                   Filter;            /*!< Filter type.
-                                                     This parameter can be a value of @ref FMAC_Functions (filter related values). */
+                                                     This parameter can be a value
+                                                     of @ref FMAC_Functions (filter related values). */
 
   uint8_t                    P;                 /*!< Parameter P (vector length, number of filter taps, etc.). */
 
@@ -238,17 +254,17 @@ typedef struct
 /** @defgroup FMAC_Error_Code FMAC Error code
   * @{
   */
-#define HAL_FMAC_ERROR_NONE                0x00000000UL /*!< No error               */
-#define HAL_FMAC_ERROR_SAT                 0x00000001UL /*!< Saturation error       */
-#define HAL_FMAC_ERROR_UNFL                0x00000002UL /*!< Underflow error        */
-#define HAL_FMAC_ERROR_OVFL                0x00000004UL /*!< Overflow error         */
-#define HAL_FMAC_ERROR_DMA                 0x00000008UL /*!< DMA error              */
-#define HAL_FMAC_ERROR_RESET               0x00000010UL /*!< Reset error            */
-#define HAL_FMAC_ERROR_PARAM               0x00000020UL /*!< Parameter error        */
+#define HAL_FMAC_ERROR_NONE                0x00000000U /*!< No error               */
+#define HAL_FMAC_ERROR_SAT                 0x00000001U /*!< Saturation error       */
+#define HAL_FMAC_ERROR_UNFL                0x00000002U /*!< Underflow error        */
+#define HAL_FMAC_ERROR_OVFL                0x00000004U /*!< Overflow error         */
+#define HAL_FMAC_ERROR_DMA                 0x00000008U /*!< DMA error              */
+#define HAL_FMAC_ERROR_RESET               0x00000010U /*!< Reset error            */
+#define HAL_FMAC_ERROR_PARAM               0x00000020U /*!< Parameter error        */
 #if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
-#define HAL_FMAC_ERROR_INVALID_CALLBACK    0x00000040UL /*!< Invalid Callback error */
+#define HAL_FMAC_ERROR_INVALID_CALLBACK    0x00000040U /*!< Invalid Callback error */
 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
-#define HAL_FMAC_ERROR_TIMEOUT             0x00000080UL /*!< Timeout error          */
+#define HAL_FMAC_ERROR_TIMEOUT             0x00000080U /*!< Timeout error          */
 
 /**
   * @}
@@ -257,11 +273,11 @@ typedef struct
 /** @defgroup FMAC_Functions FMAC Functions
   * @{
   */
-#define FMAC_FUNC_LOAD_X1                  ((uint32_t)(FMAC_PARAM_FUNC_0))                                        /*!< Load X1 buffer                            */
-#define FMAC_FUNC_LOAD_X2                  ((uint32_t)(FMAC_PARAM_FUNC_1))                                        /*!< Load X2 buffer                            */
-#define FMAC_FUNC_LOAD_Y                   ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0))                    /*!< Load Y buffer                             */
-#define FMAC_FUNC_CONVO_FIR                ((uint32_t)(FMAC_PARAM_FUNC_3))                                        /*!< Convolution (FIR filter)                  */
-#define FMAC_FUNC_IIR_DIRECT_FORM_1        ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0))                    /*!< IIR filter (direct form 1)                */
+#define FMAC_FUNC_LOAD_X1                  (FMAC_PARAM_FUNC_0)                        /*!< Load X1 buffer             */
+#define FMAC_FUNC_LOAD_X2                  (FMAC_PARAM_FUNC_1)                        /*!< Load X2 buffer             */
+#define FMAC_FUNC_LOAD_Y                   (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)    /*!< Load Y buffer              */
+#define FMAC_FUNC_CONVO_FIR                (FMAC_PARAM_FUNC_3)                        /*!< Convolution (FIR filter)   */
+#define FMAC_FUNC_IIR_DIRECT_FORM_1        (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)    /*!< IIR filter (direct form 1) */
 /**
   * @}
   */
@@ -270,15 +286,23 @@ typedef struct
   * @{
   * @note     This parameter sets a watermark for buffer full (input) or buffer empty (output).
   */
-#define FMAC_THRESHOLD_1                   0x00000000UL    /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
-                                                                Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */
-#define FMAC_THRESHOLD_2                   0x01000000UL    /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
-                                                                Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */
-#define FMAC_THRESHOLD_4                   0x02000000UL    /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
-                                                                Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */
-#define FMAC_THRESHOLD_8                   0x03000000UL    /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
-                                                                Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */
-#define FMAC_THRESHOLD_NO_VALUE            0xFFFFFFFFUL    /*!< The configured threshold value shouldn't be changed */
+#define FMAC_THRESHOLD_1                   0x00000000U    /*!< Input: Buffer full flag set if the number of free spaces
+                                                               in the buffer is less than 1.
+                                                               Output: Buffer empty flag set if the number
+                                                               of unread values in the buffer is less than 1. */
+#define FMAC_THRESHOLD_2                   0x01000000U    /*!< Input: Buffer full flag set if the number of free spaces
+                                                               in the buffer is less than 2.
+                                                               Output: Buffer empty flag set if the number
+                                                               of unread values in the buffer is less than 2. */
+#define FMAC_THRESHOLD_4                   0x02000000U    /*!< Input: Buffer full flag set if the number of free spaces
+                                                               in the buffer is less than 4.
+                                                               Output: Buffer empty flag set if the number
+                                                               of unread values in the buffer is less than 4. */
+#define FMAC_THRESHOLD_8                   0x03000000U    /*!< Input: Buffer full flag set if the number of free spaces
+                                                               in the buffer is less than 8.
+                                                               Output: Buffer empty flag set if the number
+                                                               of unread values in the buffer is less than 8. */
+#define FMAC_THRESHOLD_NO_VALUE            0xFFFFFFFFU    /*!< The configured threshold value shouldn't be changed */
 /**
   * @}
   */
@@ -287,7 +311,7 @@ typedef struct
   * @{
   */
 #define FMAC_BUFFER_ACCESS_NONE            0x00U           /*!< Buffer handled by an external IP (ADC for instance) */
-#define FMAC_BUFFER_ACCESS_DMA             0x01U           /*!< Buffer accessed through the FMAC DMA */
+#define FMAC_BUFFER_ACCESS_DMA             0x01U           /*!< Buffer accessed through DMA */
 #define FMAC_BUFFER_ACCESS_POLLING         0x02U           /*!< Buffer accessed through polling */
 #define FMAC_BUFFER_ACCESS_IT              0x03U           /*!< Buffer accessed through interruptions */
 /**
@@ -297,7 +321,7 @@ typedef struct
 /** @defgroup FMAC_Clip_State FMAC Clip State
   * @{
   */
-#define FMAC_CLIP_DISABLED                 0x00000000UL    /*!< Clipping disabled */
+#define FMAC_CLIP_DISABLED                 0x00000000U     /*!< Clipping disabled */
 #define FMAC_CLIP_ENABLED                  FMAC_CR_CLIPEN  /*!< Clipping enabled */
 /**
   * @}
@@ -310,7 +334,8 @@ typedef struct
 #define FMAC_FLAG_X1FULL                   FMAC_SR_X1FULL  /*!< X1 Buffer Full Flag */
 #define FMAC_FLAG_OVFL                     FMAC_SR_OVFL    /*!< Overflow Error Flag */
 #define FMAC_FLAG_UNFL                     FMAC_SR_UNFL    /*!< Underflow Error Flag */
-#define FMAC_FLAG_SAT                      FMAC_SR_SAT     /*!< Saturation Error Flag (this helps in debugging a filter) */
+#define FMAC_FLAG_SAT                      FMAC_SR_SAT     /*!< Saturation Error Flag
+                                                                (this helps in debugging a filter) */
 /**
   * @}
   */
@@ -322,62 +347,32 @@ typedef struct
 #define FMAC_IT_WIEN                       FMAC_CR_WIEN    /*!< Write Interrupt Enable */
 #define FMAC_IT_OVFLIEN                    FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
 #define FMAC_IT_UNFLIEN                    FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
-#define FMAC_IT_SATIEN                     FMAC_CR_SATIEN  /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
+#define FMAC_IT_SATIEN                     FMAC_CR_SATIEN  /*!< Saturation Error Interrupt Enable
+                                                                (this helps in debugging a filter) */
 /**
   * @}
   */
 
-/** @defgroup FMAC_DMAR DMA Read Request Enable bit
+/**
+  * @}
+  */
+
+
+/* Exported variables --------------------------------------------------------*/
+/** @defgroup FMAC_Exported_variables FMAC Exported variables
   * @{
   */
-#define FMAC_DMA_REN                       FMAC_CR_DMAREN  /*!< DMA Read Requests Enable */
 /**
   * @}
   */
 
-/** @defgroup FMAC_DMAW DMA Write Request Enable bit
-  * @{
-  */
-#define FMAC_DMA_WEN                       FMAC_CR_DMAWEN  /*!< DMA Write Channel Enable */
-/**
-  * @}
-  */
-
-/** @defgroup FMAC_DMAS DMA START bit
-  * @{
-  */
-#define FMAC_START                         FMAC_PARAM_START  /*!< DMA Start */
-/**
-  * @}
-  */
-
-/** @defgroup FMAC_TimeOut_Value    FMAC polling-based communications time-out value
-  * @{
-  */
-#define HAL_FMAC_TIMEOUT_VALUE             1000UL          /*!< FMAC polling-based communications time-out value */
-/**
-  * @}
-  */
-
-/** @defgroup FMAC_Reset_TimeOut_Value    FMAC reset time-out value
-  * @{
-  */
-#define HAL_FMAC_RESET_TIMEOUT_VALUE       500UL           /*!< FMAC reset time-out value */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup FMAC_Exported_Macros FMAC Exported Macros
   * @{
   */
 
-/** @brief  Reset FMAC handle state.
+/**
+  * @brief  Reset FMAC handle state.
   * @param  __HANDLE__ FMAC handle.
   * @retval None
   */
@@ -392,10 +387,10 @@ typedef struct
 #endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
 
 /**
-  * @brief  Enable the FMAC interrupt when result is ready
+  * @brief  Enable the specified FMAC interrupt
   * @param  __HANDLE__ FMAC handle.
   * @param  __INTERRUPT__ FMAC Interrupt.
-  *         This parameter can be one of the following values:
+  *         This parameter can be any combination of the following values:
   *            @arg @ref FMAC_IT_RIEN    Read interrupt enable
   *            @arg @ref FMAC_IT_WIEN    Write interrupt enable
   *            @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
@@ -410,7 +405,7 @@ typedef struct
   * @brief  Disable the FMAC interrupt
   * @param  __HANDLE__ FMAC handle.
   * @param  __INTERRUPT__ FMAC Interrupt.
-  *         This parameter can be one of the following values:
+  *         This parameter can be any combination of the following values:
   *            @arg @ref FMAC_IT_RIEN    Read interrupt enable
   *            @arg @ref FMAC_IT_WIEN    Write interrupt enable
   *            @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
@@ -421,10 +416,11 @@ typedef struct
 #define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
   (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
 
-/** @brief  Check whether the specified FMAC interrupt occurred or not.
+/**
+  * @brief  Check whether the specified FMAC interrupt occurred or not.
   * @param  __HANDLE__ FMAC handle.
   * @param  __INTERRUPT__ FMAC interrupt to check.
-  *         This parameter can be one of the following values:
+  *         This parameter can be any combination of the following values:
   *            @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
   *            @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
   *            @arg @ref FMAC_FLAG_OVFL   Overflow Error Flag
@@ -435,7 +431,8 @@ typedef struct
 #define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
   (((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
 
-/** @brief  Clear specified FMAC interrupt status. Dummy macro as the
+/**
+  * @brief  Clear specified FMAC interrupt status. Dummy macro as the
             interrupt status flags are read-only.
   * @param  __HANDLE__ FMAC handle.
   * @param  __INTERRUPT__ FMAC interrupt to clear.
@@ -443,10 +440,11 @@ typedef struct
   */
 #define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__)   /* Dummy macro */
 
-/** @brief  Check whether the specified FMAC status flag is set or not.
+/**
+  * @brief  Check whether the specified FMAC status flag is set or not.
   * @param  __HANDLE__ FMAC handle.
   * @param  __FLAG__ FMAC flag to check.
-  *         This parameter can be one of the following values:
+  *         This parameter can be any combination of the following values:
   *            @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
   *            @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
   *            @arg @ref FMAC_FLAG_OVFL   Overflow Error Flag
@@ -457,7 +455,8 @@ typedef struct
 #define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
   ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
-/** @brief  Clear specified FMAC status flag. Dummy macro as no
+/**
+  * @brief  Clear specified FMAC status flag. Dummy macro as no
             flag can be cleared.
   * @param  __HANDLE__ FMAC handle.
   * @param  __FLAG__ FMAC flag to clear.
@@ -465,7 +464,8 @@ typedef struct
   */
 #define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__)     /* Dummy macro */
 
-/** @brief  Check whether the specified FMAC interrupt is enabled or not.
+/**
+  * @brief  Check whether the specified FMAC interrupt is enabled or not.
   * @param  __HANDLE__ FMAC handle.
   * @param  __INTERRUPT__ FMAC interrupt to check.
   *         This parameter can be one of the following values:
@@ -483,8 +483,24 @@ typedef struct
   * @}
   */
 
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup  FMAC_Private_Macros
+/* Private defines -----------------------------------------------------------*/
+/** @addtogroup  FMAC_Private_Constants
+  * @{
+  */
+
+#define FMAC_PARAM_P_MAX_IIR  64U /*!< Maximum value of P parameter with IIR */
+#define FMAC_PARAM_P_MAX_FIR 127U /*!< Maximum value of P parameter with FIR */
+#define FMAC_PARAM_P_MIN       2U /*!< Minimum value of P parameter */
+#define FMAC_PARAM_Q_MAX      63U /*!< Maximum value of Q parameter */
+#define FMAC_PARAM_Q_MIN       1U /*!< Minimum value of Q parameter */
+#define FMAC_PARAM_R_MAX       7U /*!< Maximum value of R parameter */
+
+/**
+  * @}
+  */
+
+/* Private Macros-----------------------------------------------------------*/
+/** @addtogroup  FMAC_Private_Macros FMAC Private Macros
   * @{
   */
 
@@ -500,7 +516,7 @@ typedef struct
                                         ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
 
 /**
-  * @brief  Verify the FMAC load function.
+  * @brief  Verify the FMAC load function used for input data, output data or coefficients.
   * @param  __FUNCTION__ ID of the load function.
   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
   */
@@ -509,7 +525,7 @@ typedef struct
                                              ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
 
 /**
-  * @brief  Verify the FMAC load function.
+  * @brief  Verify the FMAC load function used with N values as input or output data.
   * @param  __FUNCTION__ ID of the load function.
   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
   */
@@ -517,7 +533,7 @@ typedef struct
                                                ((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
 
 /**
-  * @brief  Verify the FMAC load function.
+  * @brief  Verify the FMAC load function used with N + M values as coefficients.
   * @param  __FUNCTION__ ID of the load function.
   * @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
   */
@@ -549,10 +565,12 @@ typedef struct
   * @param  __FUNCTION__ ID of the filter function.
   * @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
   */
-#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               && \
-                                                (((__P__) >= 2U) && ((__P__) <= 127U)))               || \
-                                               (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
-                                                (((__P__) >= 2U) && ((__P__) <= 64U))) )
+#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ((((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               && \
+                                               (((__P__) >= FMAC_PARAM_P_MIN) && \
+                                                ((__P__) <= FMAC_PARAM_P_MAX_FIR))) || \
+                                              (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
+                                               (((__P__) >= FMAC_PARAM_P_MIN) && \
+                                                ((__P__) <= FMAC_PARAM_P_MAX_IIR))))
 
 /**
   * @brief  Verify the FMAC filter parameter Q.
@@ -562,7 +580,7 @@ typedef struct
   */
 #define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)                || \
                                                (((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)       && \
-                                                (((__Q__) >= 1U) && ((__Q__) <= 63U))) )
+                                                (((__Q__) >= FMAC_PARAM_Q_MIN) && ((__Q__) <= FMAC_PARAM_Q_MAX))) )
 
 /**
   * @brief  Verify the FMAC filter parameter R.
@@ -572,7 +590,7 @@ typedef struct
   */
 #define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR)               || \
                                                 ((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))      && \
-                                               ((__R__) <= 7U))
+                                               ((__R__) <= FMAC_PARAM_R_MAX))
 
 /**
   * @brief  Verify the FMAC buffer access.
@@ -592,6 +610,21 @@ typedef struct
 #define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED)                  || \
                                             ((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
 
+/**
+  * @brief  Check whether the threshold is applicable.
+  * @param  __SIZE__ Size of the matching buffer.
+  * @param  __WM__ Watermark value.
+  * @param  __ACCESS__ Access to the buffer (polling, it, dma, none).
+  * @retval THRESHOLD
+  */
+#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
+  (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
+                    ((__WM__) == FMAC_THRESHOLD_2)? 2U: \
+                    ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
+   ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
+     ((__WM__) == FMAC_THRESHOLD_1))|| \
+    ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
+
 /**
   * @}
   */
@@ -624,8 +657,8 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
-HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *sConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
+HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
 HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
                                          int16_t *pOutput, uint8_t OutputSize);
 HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
@@ -667,8 +700,8 @@ void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
   * @{
   */
 /* Peripheral State functions *************************************************/
-HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
-uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
+HAL_FMAC_StateTypeDef HAL_FMAC_GetState(const FMAC_HandleTypeDef *hfmac);
+uint32_t HAL_FMAC_GetError(const FMAC_HandleTypeDef *hfmac);
 /**
   * @}
   */
@@ -692,5 +725,3 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
 #endif
 
 #endif /* STM32H7xx_HAL_FMAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c
index bed9b624dd..14fd90a6bc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c
@@ -10,7 +10,18 @@
   *           + Modify physical buffer addresses.
   *           + Modify cache and pre-fetch parameters.
   *           + Error management.
-  *         
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -121,17 +132,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -890,4 +890,3 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h
index 8248bede25..819f3eadf9 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -450,4 +449,3 @@ uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
 
 #endif /* STM32H7xx_HAL_GFXMMU_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c
index 8d0a5f66b2..3580f78a5b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c
@@ -8,6 +8,17 @@
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### GPIO Peripheral features #####
@@ -90,17 +101,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -122,14 +122,6 @@
 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
   * @{
   */
-#define GPIO_MODE             (0x00000003U)
-#define ANALOG_MODE           (0x00000008U)
-#define EXTI_MODE             (0x10000000U)
-#define GPIO_MODE_IT          (0x00010000U)
-#define GPIO_MODE_EVT         (0x00020000U)
-#define RISING_EDGE           (0x00100000U)
-#define FALLING_EDGE          (0x00200000U)
-#define GPIO_OUTPUT_TYPE      (0x00000010U)
 
 #if defined(DUAL_CORE)
 #define EXTI_CPU1             (0x01000000U)
@@ -187,7 +179,6 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
   assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
   assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
 
   /* Configure the port pins */
   while (((GPIO_Init->Pin) >> position) != 0x00U)
@@ -199,11 +190,11 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
     {
       /*--------------------- GPIO Mode Configuration ------------------------*/
       /* In case of Output or Alternate function mode selection */
-      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
-          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
       {
         /* Check the Speed parameter */
         assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+
         /* Configure the IO Speed */
         temp = GPIOx->OSPEEDR;
         temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
@@ -213,18 +204,24 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         /* Configure the IO Output Type */
         temp = GPIOx->OTYPER;
         temp &= ~(GPIO_OTYPER_OT0 << position) ;
-        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
         GPIOx->OTYPER = temp;
       }
 
+      if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+      {
+       /* Check the Pull parameter */
+       assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
       /* Activate the Pull-up or Pull down resistor for the current IO */
       temp = GPIOx->PUPDR;
       temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
       temp |= ((GPIO_Init->Pull) << (position * 2U));
       GPIOx->PUPDR = temp;
+      }
 
       /* In case of Alternate function mode selection */
-      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
       {
         /* Check the Alternate function parameters */
         assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
@@ -245,7 +242,7 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 
       /*--------------------- EXTI Mode Configuration ------------------------*/
       /* Configure the External Interrupt or event for the current IO */
-      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
       {
         /* Enable SYSCFG Clock */
         __HAL_RCC_SYSCFG_CLK_ENABLE();
@@ -255,27 +252,10 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
         temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
         SYSCFG->EXTICR[position >> 2U] = temp;
 
-        /* Clear EXTI line configuration */
-        temp = EXTI_CurrentCPU->IMR1;
-        temp &= ~(iocurrent);
-        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI_CurrentCPU->IMR1 = temp;
-
-        temp = EXTI_CurrentCPU->EMR1;
-        temp &= ~(iocurrent);
-        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
-        {
-          temp |= iocurrent;
-        }
-        EXTI_CurrentCPU->EMR1 = temp;
-
         /* Clear Rising Falling edge configuration */
         temp = EXTI->RTSR1;
         temp &= ~(iocurrent);
-        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
         {
           temp |= iocurrent;
         }
@@ -283,11 +263,28 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 
         temp = EXTI->FTSR1;
         temp &= ~(iocurrent);
-        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
         {
           temp |= iocurrent;
         }
         EXTI->FTSR1 = temp;
+
+        temp = EXTI_CurrentCPU->EMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->EMR1 = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI_CurrentCPU->IMR1;
+        temp &= ~(iocurrent);
+        if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI_CurrentCPU->IMR1 = temp;
       }
     }
 
@@ -338,8 +335,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
         EXTI_CurrentCPU->EMR1 &= ~(iocurrent);
 
         /* Clear Rising Falling edge configuration */
-        EXTI->RTSR1 &= ~(iocurrent);
         EXTI->FTSR1 &= ~(iocurrent);
+        EXTI->RTSR1 &= ~(iocurrent);
 
         tmp = 0x0FUL << (4U * (position & 0x03U));
         SYSCFG->EXTICR[position >> 2U] &= ~tmp;
@@ -556,4 +553,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.h
index 52f8ecddc1..1cd9178bbd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -108,29 +107,26 @@ typedef enum
 
 /** @defgroup GPIO_mode_define  GPIO mode define
   * @brief GPIO Configuration Mode
-  *        Elements values convention: 0xX0yz00YZ
-  *           - X  : GPIO mode or EXTI Mode
-  *           - y  : External IT or Event trigger detection
-  *           - z  : IO configuration on External IT or Event
-  *           - Y  : Output type (Push Pull or Open Drain)
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  *        Elements values convention: 0x00WX00YZ
+  *           - W  : EXTI trigger detection on 3 bits
+  *           - X  : EXTI mode (IT or Event) on 2 bits
+  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
+  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
   * @{
   */
-#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
+#define GPIO_MODE_INPUT                 MODE_INPUT                                                  /*!< Input Floating Mode                                                */
+#define GPIO_MODE_OUTPUT_PP             (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                                              */
+#define GPIO_MODE_OUTPUT_OD             (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                                             */
+#define GPIO_MODE_AF_PP                 (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode                                  */
+#define GPIO_MODE_AF_OD                 (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode                                 */
+#define GPIO_MODE_ANALOG                MODE_ANALOG                                                 /*!< Analog Mode                                                        */
+#define GPIO_MODE_IT_RISING             (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define GPIO_MODE_IT_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define GPIO_MODE_IT_RISING_FALLING     (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
 
-#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
-
-#define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
-
-#define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+#define GPIO_MODE_EVT_RISING            (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                    /*!< External Event Mode with Rising edge trigger detection             */
+#define GPIO_MODE_EVT_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                   /*!< External Event Mode with Falling edge trigger detection            */
+#define GPIO_MODE_EVT_RISING_FALLING    (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)  /*!< External Event Mode with Rising/Falling edge trigger detection     */
 /**
   * @}
   */
@@ -286,7 +282,25 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
 /** @defgroup GPIO_Private_Constants GPIO Private Constants
   * @{
   */
-
+#define GPIO_MODE_Pos                           0u
+#define GPIO_MODE                               (0x3uL << GPIO_MODE_Pos)
+#define MODE_INPUT                              (0x0uL << GPIO_MODE_Pos)
+#define MODE_OUTPUT                             (0x1uL << GPIO_MODE_Pos)
+#define MODE_AF                                 (0x2uL << GPIO_MODE_Pos)
+#define MODE_ANALOG                             (0x3uL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos                         4u
+#define OUTPUT_TYPE                             (0x1uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP                               (0x0uL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD                               (0x1uL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos                           16u
+#define EXTI_MODE                               (0x3uL << EXTI_MODE_Pos)
+#define EXTI_IT                                 (0x1uL << EXTI_MODE_Pos)
+#define EXTI_EVT                                (0x2uL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos                         20u
+#define TRIGGER_MODE                            (0x7uL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING                          (0x1uL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING                         (0x2uL << TRIGGER_MODE_Pos)
+#define TRIGGER_LEVEL                           (0x4uL << TRIGGER_MODE_Pos)
 /**
   * @}
   */
@@ -343,4 +357,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
 
 #endif /* STM32H7xx_HAL_GPIO_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio_ex.h
index dc56483a4c..9d6cb56c2c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -55,7 +54,12 @@ extern "C" {
 #define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
 #define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
 #define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
-#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
+#if defined(PWR_CPUCR_RETDS_CD) /* CPU domain power down Deepsleep */
+#define GPIO_AF0_CSLEEP        ((uint8_t)0x00)  /* CSLEEP Alternate Function mapping                                                       */
+#define GPIO_AF0_CSTOP         ((uint8_t)0x00)  /* CSTOP Alternate Function mapping                                                        */
+#define GPIO_AF0_NDSTOP2       ((uint8_t)0x00)  /* NDSTOP2 Alternate Function mapping                                                      */
+#endif /* PWR_CPUCR_RETDS_CD */
+#if defined(PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
 #define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
 #define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
 #define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
@@ -486,4 +490,3 @@ extern "C" {
 
 #endif /* STM32H7xx_HAL_GPIO_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c
index bdfea698e3..f8818af457 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c
@@ -12,6 +12,17 @@
   *           + Peripheral State methods
   *           + HASH or HMAC processing suspension/resumption
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                      ##### How to use this driver #####
@@ -71,7 +82,8 @@
              well the computed digest.
 
         (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
-              (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+              (+++) HASH processing: once initialization is done, MDMAT bit must be set
+               through __HAL_HASH_SET_MDMAT() macro.
              From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
              Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
              macro then wrap-up the HASH processing in feeding the last input buffer through the
@@ -111,7 +123,7 @@
       (#) HAL in interruption mode (interruptions driven)
 
         (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
-        This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+        This is why, for driver implementation simplicity s sake, user is requested to enter a message the
         length of which is a multiple of 4 bytes.
 
         (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
@@ -119,34 +131,36 @@
         and not extra bits.
 
         (##) If user needs to perform a hash computation of a large input buffer that is spread around various places
-        in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it
-        becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+        in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes
+        necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
         It is advised to the user to
        (+++) achieve the first formatting operation by software then enter the data
-       (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs.
+       (+++) while the Peripheral is processing the first input set, carry out the second formatting
+        operation by software, to be ready when DINIS occurs.
        (+++) repeat step 2 until the whole message is processed.
 
      [..]
       (#) HAL in DMA mode
 
         (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
-        The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer
-        to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the
-        end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at
-        the end of the intermediary transfers.
+        The same field described above in HASH_STR is used to specify which bits to discard at the end of the
+        DMA transfer to process only the message bits and not extra bits. Due to hardware implementation,
+        this is possible only at the end of the complete message. When several DMA transfers are needed to
+        enter the message, this is not applicable at the end of the intermediary transfers.
 
-        (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data
-        by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment
-        required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode.
+        (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive
+        chunks of data by software while the DMA transfer and processing is on-going for the first parts of
+        the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the
+        software formatting operation is more complex than in the IT mode.
 
      *** Callback registration ***
      ===================================
      [..]
       (#) The compilation define  USE_HAL_HASH_REGISTER_CALLBACKS when set to 1
           allows the user to configure dynamically the driver callbacks.
-          Use function @ref HAL_HASH_RegisterCallback() to register a user callback.
+          Use function HAL_HASH_RegisterCallback() to register a user callback.
 
-      (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks:
+      (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks:
             (+) InCpltCallback    : callback for input completion.
             (+) DgstCpltCallback  : callback for digest computation completion.
             (+) ErrorCallback     : callback for error.
@@ -155,9 +169,9 @@
           This function takes as parameters the HAL peripheral handle, the Callback ID
           and a pointer to the user callback function.
 
-      (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default
+      (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default
           weak (surcharged) function.
-          @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+          HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle,
           and the Callback ID.
           This function allows to reset following callbacks:
             (+) InCpltCallback    : callback for input completion.
@@ -166,13 +180,13 @@
             (+) MspInitCallback   : HASH MspInit.
             (+) MspDeInitCallback : HASH MspDeInit.
 
-      (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
+      (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET
           all callbacks are reset to the corresponding legacy weak (surcharged) functions:
-          examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback()
+          examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback()
           Exception done for MspInit and MspDeInit callbacks that are respectively
-          reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init
-          and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
-          If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit
+          reset to the legacy weak (surcharged) functions in the HAL_HASH_Init
+          and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand)
+          If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit
           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
           Callbacks can be registered/unregistered in READY state only.
@@ -180,8 +194,8 @@
           in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
           during the Init/DeInit.
           In that case first register the MspInit/MspDeInit user callbacks
-          using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit
-          or @ref HAL_HASH_Init function.
+          using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit
+          or HAL_HASH_Init function.
 
           When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or
           not defined, the callback registering feature is not available
@@ -189,17 +203,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -269,9 +272,10 @@
   */
 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size);
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Timeout);
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
 static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash);
 static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash);
 static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout);
@@ -284,8 +288,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
   */
 
 /** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization, configuration and call-back functions.
- *
+  *  @brief    Initialization, configuration and call-back functions.
+  *
 @verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
@@ -324,11 +328,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
 {
   /* Check the hash handle allocation */
-  if(hhash == NULL)
+  if (hhash == NULL)
   {
     return HAL_ERROR;
   }
-  
+
   /* Check the parameters */
   assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
 
@@ -340,9 +344,10 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
 
     /* Reset Callback pointers in HAL_HASH_STATE_RESET only */
     hhash->InCpltCallback =  HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
-    hhash->DgstCpltCallback =  HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
+    hhash->DgstCpltCallback =  HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+                                                             completion callback */
     hhash->ErrorCallback =  HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
-    if(hhash->MspInitCallback == NULL)
+    if (hhash->MspInitCallback == NULL)
     {
       hhash->MspInitCallback = HAL_HASH_MspInit;
     }
@@ -351,7 +356,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
     hhash->MspInitCallback(hhash);
   }
 #else
-  if(hhash->State == HAL_HASH_STATE_RESET)
+  if (hhash->State == HAL_HASH_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hhash->Lock = HAL_UNLOCKED;
@@ -361,7 +366,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
   }
 #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
 
-    /* Change the HASH state */
+  /* Change the HASH state */
   hhash->State = HAL_HASH_STATE_BUSY;
 
   /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */
@@ -379,7 +384,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
   /* Set the data type bit */
   MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType);
   /* Reset MDMAT bit */
-__HAL_HASH_RESET_MDMAT();
+  __HAL_HASH_RESET_MDMAT();
   /* Reset HASH handle status */
   hhash->Status = HAL_OK;
 
@@ -401,7 +406,7 @@ __HAL_HASH_RESET_MDMAT();
 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
 {
   /* Check the HASH handle allocation */
-  if(hhash == NULL)
+  if (hhash == NULL)
   {
     return HAL_ERROR;
   }
@@ -420,13 +425,13 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
   hhash->DigestCalculationDisable = RESET;
 
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-    if(hhash->MspDeInitCallback == NULL)
-    {
-      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
-    }
+  if (hhash->MspDeInitCallback == NULL)
+  {
+    hhash->MspDeInitCallback = HAL_HASH_MspDeInit;
+  }
 
-    /* DeInit the low level hardware */
-    hhash->MspDeInitCallback(hhash);
+  /* DeInit the low level hardware */
+  hhash->MspDeInitCallback(hhash);
 #else
   /* DeInit the low level hardware: CLOCK, NVIC */
   HAL_HASH_MspDeInit(hhash);
@@ -549,11 +554,12 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
   * @param pCallback pointer to the Callback function
   * @retval status
   */
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+                                            pHASH_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(pCallback == NULL)
+  if (pCallback == NULL)
   {
     /* Update the error code */
     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
@@ -562,64 +568,64 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_
   /* Process locked */
   __HAL_LOCK(hhash);
 
-  if(HAL_HASH_STATE_READY == hhash->State)
+  if (HAL_HASH_STATE_READY == hhash->State)
   {
     switch (CallbackID)
     {
-    case HAL_HASH_INPUTCPLT_CB_ID :
-      hhash->InCpltCallback = pCallback;
-      break;
+      case HAL_HASH_INPUTCPLT_CB_ID :
+        hhash->InCpltCallback = pCallback;
+        break;
 
-    case HAL_HASH_DGSTCPLT_CB_ID :
-      hhash->DgstCpltCallback = pCallback;
-      break;
+      case HAL_HASH_DGSTCPLT_CB_ID :
+        hhash->DgstCpltCallback = pCallback;
+        break;
 
-    case HAL_HASH_ERROR_CB_ID :
-      hhash->ErrorCallback = pCallback;
-      break;
+      case HAL_HASH_ERROR_CB_ID :
+        hhash->ErrorCallback = pCallback;
+        break;
 
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = pCallback;
-      break;
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = pCallback;
+        break;
 
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = pCallback;
-      break;
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = pCallback;
+        break;
 
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
-  else if(HAL_HASH_STATE_RESET == hhash->State)
+  else if (HAL_HASH_STATE_RESET == hhash->State)
   {
     switch (CallbackID)
     {
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = pCallback;
-      break;
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = pCallback;
+        break;
 
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = pCallback;
-      break;
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = pCallback;
+        break;
 
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else
   {
     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
+    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
   }
 
   /* Release Lock */
@@ -642,69 +648,70 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_
   */
 HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID)
 {
-HAL_StatusTypeDef status = HAL_OK;
+  HAL_StatusTypeDef status = HAL_OK;
 
   /* Process locked */
   __HAL_LOCK(hhash);
 
-  if(HAL_HASH_STATE_READY == hhash->State)
+  if (HAL_HASH_STATE_READY == hhash->State)
   {
     switch (CallbackID)
     {
-    case HAL_HASH_INPUTCPLT_CB_ID :
-      hhash->InCpltCallback = HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
-      break;
+      case HAL_HASH_INPUTCPLT_CB_ID :
+        hhash->InCpltCallback = HAL_HASH_InCpltCallback;     /* Legacy weak (surcharged) input completion callback */
+        break;
 
-    case HAL_HASH_DGSTCPLT_CB_ID :
-      hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */
-      break;
+      case HAL_HASH_DGSTCPLT_CB_ID :
+        hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation
+                                                                completion callback */
+        break;
 
-    case HAL_HASH_ERROR_CB_ID :
-      hhash->ErrorCallback = HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
-      break;
+      case HAL_HASH_ERROR_CB_ID :
+        hhash->ErrorCallback = HAL_HASH_ErrorCallback;       /* Legacy weak (surcharged) error callback */
+        break;
 
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
-      break;
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
+        break;
 
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
-      break;
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
+        break;
 
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
-  else if(HAL_HASH_STATE_RESET == hhash->State)
+  else if (HAL_HASH_STATE_RESET == hhash->State)
   {
     switch (CallbackID)
     {
-    case HAL_HASH_MSPINIT_CB_ID :
-      hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
-      break;
+      case HAL_HASH_MSPINIT_CB_ID :
+        hhash->MspInitCallback = HAL_HASH_MspInit;           /* Legacy weak (surcharged) Msp Init */
+        break;
 
-    case HAL_HASH_MSPDEINIT_CB_ID :
-      hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
-      break;
+      case HAL_HASH_MSPDEINIT_CB_ID :
+        hhash->MspDeInitCallback = HAL_HASH_MspDeInit;       /* Legacy weak (surcharged) Msp DeInit */
+        break;
 
-    default :
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
-      break;
+      default :
+        /* Update the error code */
+        hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else
   {
-     /* Update the error code */
-     hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
-     /* update return status */
-      status =  HAL_ERROR;
+    /* Update the error code */
+    hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
   }
 
   /* Release Lock */
@@ -718,8 +725,8 @@ HAL_StatusTypeDef status = HAL_OK;
   */
 
 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
- *  @brief   HASH processing functions using polling mode.
- *
+  *  @brief   HASH processing functions using polling mode.
+  *
 @verbatim
  ===============================================================================
                  ##### Polling mode HASH processing functions #####
@@ -757,7 +764,9 @@ HAL_StatusTypeDef status = HAL_OK;
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint8_t *pOutBuffer,
+                                     uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
 }
@@ -782,9 +791,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+  return  HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
 }
 
 /**
@@ -797,7 +806,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
 }
@@ -813,7 +823,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint8_t *pOutBuffer,
+                                      uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
 }
@@ -838,9 +850,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+  return  HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
 }
 
 /**
@@ -853,7 +865,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                           uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
 }
@@ -863,8 +876,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
   */
 
 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
- *  @brief   HASH processing functions using interrupt mode.
- *
+  *  @brief   HASH processing functions using interrupt mode.
+  *
 @verbatim
  ===============================================================================
                  ##### Interruption mode HASH processing functions #####
@@ -900,9 +913,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
   * @param  pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                        uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
 }
 
 /**
@@ -923,9 +937,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5);
+  return  HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
 }
 
 /**
@@ -937,9 +951,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
   * @param  pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
 }
 
 /**
@@ -952,9 +967,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                         uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
 }
 
 
@@ -976,9 +992,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1);
+  return  HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
 }
 
 /**
@@ -990,9 +1006,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                              uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
 }
 
 /**
@@ -1025,8 +1042,8 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
   */
 
 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
- *  @brief   HASH processing functions using DMA mode.
- *
+  *  @brief   HASH processing functions using DMA mode.
+  *
 @verbatim
  ===============================================================================
                     ##### DMA mode HASH processing functions #####
@@ -1062,7 +1079,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
 }
@@ -1077,9 +1094,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
 {
-   return HASH_Finish(hhash, pOutBuffer, Timeout);
+  return HASH_Finish(hhash, pOutBuffer, Timeout);
 }
 
 /**
@@ -1092,7 +1109,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
 }
@@ -1108,9 +1125,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
 {
-   return HASH_Finish(hhash, pOutBuffer, Timeout);
+  return HASH_Finish(hhash, pOutBuffer, Timeout);
 }
 
 /**
@@ -1118,8 +1135,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
   */
 
 /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
- *  @brief   HMAC processing functions using polling mode.
- *
+  *  @brief   HMAC processing functions using polling mode.
+  *
 @verbatim
  ===============================================================================
                  ##### Polling mode HMAC processing functions #####
@@ -1149,7 +1166,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint8_t *pOutBuffer,
+                                     uint32_t Timeout)
 {
   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5);
 }
@@ -1167,7 +1186,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint8_t *pOutBuffer,
+                                      uint32_t Timeout)
 {
   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1);
 }
@@ -1178,8 +1199,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
 
 
 /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
- *  @brief   HMAC processing functions using interrupt mode.
- *
+  *  @brief   HMAC processing functions using interrupt mode.
+  *
 @verbatim
  ===============================================================================
                  ##### Interrupt mode HMAC processing functions #####
@@ -1208,7 +1229,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf
   * @param  pOutBuffer pointer to the computed digest. Digest size is 16 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                        uint8_t *pOutBuffer)
 {
   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5);
 }
@@ -1225,7 +1247,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB
   * @param  pOutBuffer pointer to the computed digest. Digest size is 20 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                         uint8_t *pOutBuffer)
 {
   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1);
 }
@@ -1235,10 +1258,9 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
   */
 
 
-
 /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
- *  @brief   HMAC processing functions using DMA modes.
- *
+  *  @brief   HMAC processing functions using DMA modes.
+  *
 @verbatim
  ===============================================================================
                  ##### DMA mode HMAC processing functions #####
@@ -1278,7 +1300,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
 }
@@ -1303,7 +1325,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
 }
@@ -1313,8 +1335,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
   */
 
 /** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions
- *  @brief   Peripheral State functions.
- *
+  *  @brief   Peripheral State functions.
+  *
 @verbatim
  ===============================================================================
                       ##### Peripheral State methods #####
@@ -1350,7 +1372,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  hhash HASH handle.
   * @retval HAL HASH state
   */
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
+HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash)
 {
   return hhash->State;
 }
@@ -1363,7 +1385,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
   * @param  hhash HASH handle.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
+HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash)
 {
   return hhash->Status;
 }
@@ -1381,7 +1403,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash)
   *         must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long.
   * @retval None
   */
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
 {
   uint32_t mem_ptr = (uint32_t)pMemBuffer;
   uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1391,20 +1413,21 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
   UNUSED(hhash);
 
   /* Save IMR register content */
-  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI);
-  mem_ptr+=4U;
+  *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI);
+  mem_ptr += 4U;
   /* Save STR register content */
-  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW);
-  mem_ptr+=4U;
+  *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW);
+  mem_ptr += 4U;
   /* Save CR register content */
-  *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT);
-  mem_ptr+=4U;
+  *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO |
+                                    HASH_CR_LKEY | HASH_CR_MDMAT);
+  mem_ptr += 4U;
   /* By default, save all CSRs registers */
-  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
   {
-    *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr);
-    mem_ptr+=4U;
-    csr_ptr+=4U;
+    *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr);
+    mem_ptr += 4U;
+    csr_ptr += 4U;
   }
 }
 
@@ -1421,7 +1444,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
   *         beforehand).
   * @retval None
   */
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer)
 {
   uint32_t mem_ptr = (uint32_t)pMemBuffer;
   uint32_t csr_ptr = (uint32_t)HASH->CSR;
@@ -1431,25 +1454,25 @@ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer)
   UNUSED(hhash);
 
   /* Restore IMR register content */
-  WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr)));
-  mem_ptr+=4U;
+  WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr)));
+  mem_ptr += 4U;
   /* Restore STR register content */
-  WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr)));
-  mem_ptr+=4U;
+  WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr)));
+  mem_ptr += 4U;
   /* Restore CR register content */
-  WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr)));
-  mem_ptr+=4U;
+  WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr)));
+  mem_ptr += 4U;
 
   /* Reset the HASH processor before restoring the Context
   Swap Registers (CSR) */
   __HAL_HASH_INIT();
 
   /* By default, restore all CSR registers */
-  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--)
+  for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--)
   {
-    WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr)));
-    mem_ptr+=4U;
-    csr_ptr+=4U;
+    WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr)));
+    mem_ptr += 4U;
+    csr_ptr += 4U;
   }
 }
 
@@ -1492,7 +1515,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
   else
   {
 
-   /* Make sure there is enough time to suspend the processing */
+    /* Make sure there is enough time to suspend the processing */
     tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR;
 
     if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
@@ -1505,7 +1528,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
     /* Wait for BUSY flag to be reset */
     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
     {
-       return HAL_TIMEOUT;
+      return HAL_TIMEOUT;
     }
 
     if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET)
@@ -1516,7 +1539,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
     /* Wait for BUSY flag to be set */
     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
     {
-       return HAL_TIMEOUT;
+      return HAL_TIMEOUT;
     }
     /* Disable DMA channel */
     /* Note that the Abort function will
@@ -1524,13 +1547,13 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
       - Unlock
       - Set the State
     */
-    if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+    if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
     {
       return HAL_ERROR;
     }
 
     /* Clear DMAE bit */
-    CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+    CLEAR_BIT(HASH->CR, HASH_CR_DMAE);
 
     /* Wait for BUSY flag to be reset */
     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
@@ -1564,19 +1587,22 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
     {
 
       /* Compute how many words were supposed to be transferred by DMA */
-      tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ?  ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U));
+      tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \
+                                             ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U));
 
-      /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported
-        by HASH Peripheral, correct it */
+      /* If discrepancy between the number of words reported by DMA Peripheral and
+        the numbers of words entered as reported by HASH Peripheral, correct it */
       /* tmp_words_already_pushed reflects the number of words that were already pushed before
          the start of DMA transfer (multi-buffer processing case) */
       tmp_words_already_pushed = hhash->NbWordsAlreadyPushed;
-      if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U)  != HASH_NBW_PUSHED())
+      if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - \
+            tmp_remaining_DMATransferSize_inWords) % 16U) != HASH_NBW_PUSHED())
       {
         tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */
       }
 
-      /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */
+      /* Accordingly, update the input pointer that points at the next word to be
+         transferred to the Peripheral by DMA */
       hhash->pHashInBuffPtr +=  4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ;
 
       /* And store in HashInCount the remaining size to transfer (in bytes) */
@@ -1596,8 +1622,8 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
   * @brief  Return the HASH handle error code.
   * @param  hhash pointer to a HASH_HandleTypeDef structure.
   * @retval HASH Error Code
-*/
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
+  */
+uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash)
 {
   /* Return HASH Error Code */
   return hhash->ErrorCode;
@@ -1624,10 +1650,10 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash)
   */
 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
 {
-  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   uint32_t inputaddr;
   uint32_t buffersize;
-  HAL_StatusTypeDef status ;
+  HAL_StatusTypeDef status;
 
   if (hhash->State != HAL_HASH_STATE_SUSPENDED)
   {
@@ -1726,19 +1752,21 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
         }
       }
 
-    /* Configure the Number of valid bits in last word of the message */
-    __HAL_HASH_SET_NBVALIDBITS(buffersize);
+      /* Configure the Number of valid bits in last word of the message */
+      __HAL_HASH_SET_NBVALIDBITS(buffersize);
 
       /* Set the HASH DMA transfer completion call back */
       hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
 
       /* Enable the DMA In DMA stream */
-    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
+      status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+                                (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \
+                                 (buffersize / 4U)));
 
-    /* Enable DMA requests */
-    SET_BIT(HASH->CR, HASH_CR_DMAE);
+      /* Enable DMA requests */
+      SET_BIT(HASH->CR, HASH_CR_DMAE);
 
-          /* Return function status */
+      /* Return function status */
       if (status != HAL_OK)
       {
         /* Update HASH state machine to error */
@@ -1747,9 +1775,9 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
       else
       {
         /* Change HASH state */
-        hhash->State = HAL_HASH_STATE_READY;
+        hhash->State = HAL_HASH_STATE_BUSY;
       }
-  }
+    }
   }
 
   return;
@@ -1764,14 +1792,14 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
   */
 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
 {
-  HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   if (hhash->State != HAL_HASH_STATE_SUSPENDED)
   {
     hhash->ErrorCode |= HAL_HASH_ERROR_DMA;
     /* Set HASH state to ready to prevent any blocking issue in user code
        present in HAL_HASH_ErrorCallback() */
-    hhash->State= HAL_HASH_STATE_READY;
+    hhash->State = HAL_HASH_STATE_READY;
     /* Set HASH handle status to error */
     hhash->Status = HAL_ERROR;
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
@@ -1796,23 +1824,24 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma)
   *         suspension time is stored in the handle for resumption later on.
   * @retval HAL status
   */
-static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   uint32_t buffercounter;
   __IO uint32_t inputaddr = (uint32_t) pInBuffer;
+  uint32_t tmp;
 
-  for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
+  for (buffercounter = 0U; buffercounter < (Size / 4U); buffercounter++)
   {
     /* Write input data 4 bytes at a time */
-    HASH->DIN = *(uint32_t*)inputaddr;
-    inputaddr+=4U;
+    HASH->DIN = *(uint32_t *)inputaddr;
+    inputaddr += 4U;
 
     /* If the suspension flag has been raised and if the processing is not about
     to end, suspend processing */
-    if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
+    if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && (((buffercounter * 4U) + 4U) < Size))
     {
       /* wait for flag BUSY not set before  Wait for DINIS = 1*/
-      if (buffercounter >=64U)
+      if ((buffercounter * 4U) >= 64U)
       {
         if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
         {
@@ -1831,16 +1860,16 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
         if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
         {
           /* Save current reading and writing locations of Input and Output buffers */
-          hhash->pHashInBuffPtr =  (uint8_t *)inputaddr;
+          hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
           /* Save the number of bytes that remain to be processed at this point */
-          hhash->HashInCount    =  Size - (buffercounter + 4U);
+          hhash->HashInCount    =  Size - ((buffercounter * 4U) + 4U);
         }
         else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
         {
           /* Save current reading and writing locations of Input and Output buffers */
-          hhash->pHashKeyBuffPtr  =  (uint8_t *)inputaddr;
+          hhash->pHashKeyBuffPtr  = (uint8_t *)inputaddr;
           /* Save the number of bytes that remain to be processed at this point */
-          hhash->HashKeyCount  =  Size - (buffercounter + 4U);
+          hhash->HashKeyCount  =  Size - ((buffercounter * 4U) + 4U);
         }
         else
         {
@@ -1859,6 +1888,52 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
   }   /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4)                 */
 
   /* At this point, all the data have been entered to the Peripheral: exit */
+
+  if ((Size % 4U) != 0U)
+  {
+    if (hhash->Init.DataType == HASH_DATATYPE_16B)
+    {
+      /* Write remaining input data */
+
+      if ((Size % 4U) <= 2U)
+      {
+        HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+      }
+      if ((Size % 4U) == 3U)
+      {
+        HASH->DIN = *(uint32_t *)inputaddr;
+      }
+
+    }
+    else if ((hhash->Init.DataType == HASH_DATATYPE_8B)
+             || (hhash->Init.DataType == HASH_DATATYPE_1B))  /* byte swap or bit swap or */
+    {
+      /* Write remaining input data */
+      if ((Size % 4U) == 1U)
+      {
+        HASH->DIN = (uint32_t) * (uint8_t *)inputaddr;
+      }
+      if ((Size % 4U) == 2U)
+      {
+        HASH->DIN = (uint32_t) * (uint16_t *)inputaddr;
+      }
+      if ((Size % 4U) == 3U)
+      {
+        tmp  = *(uint8_t *)inputaddr;
+        tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U;
+        tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U;
+        HASH->DIN = tmp;
+      }
+
+    }
+    else
+    {
+      HASH->DIN = *(uint32_t *)inputaddr;
+    }
+    /*hhash->HashInCount += 4U;*/
+  }
+
+
   return  HAL_OK;
 }
 
@@ -1868,72 +1943,71 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB
   * @param  Size message digest size in bytes.
   * @retval None
   */
-static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
+static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size)
 {
   uint32_t msgdigest = (uint32_t)pMsgDigest;
 
-  switch(Size)
+  switch (Size)
   {
     /* Read the message digest */
     case 16:  /* MD5 */
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    break;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+      break;
     case 20:  /* SHA1 */
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-      msgdigest+=4U;
-      *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    break;
-  case 28:  /* SHA224 */
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
-    break;
-  case 32:   /* SHA256 */
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
-    msgdigest+=4U;
-    *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
-    break;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+      break;
+    case 28:  /* SHA224 */
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+      break;
+    case 32:   /* SHA256 */
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]);
+      msgdigest += 4U;
+      *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]);
+      break;
     default:
-    break;
+      break;
   }
 }
 
 
-
 /**
   * @brief  Handle HASH processing Timeout.
   * @param  hhash HASH handle.
@@ -1942,19 +2016,20 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
   * @param  Timeout Timeout duration.
   * @retval HAL status
   */
-static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Timeout)
 {
   uint32_t tickstart = HAL_GetTick();
 
   /* Wait until flag is set */
-  if(Status == RESET)
+  if (Status == RESET)
   {
-    while(__HAL_HASH_GET_FLAG(Flag) == RESET)
+    while (__HAL_HASH_GET_FLAG(Flag) == RESET)
     {
       /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY)
       {
-        if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
         {
           /* Set State to Ready to be able to restart later on */
           hhash->State  = HAL_HASH_STATE_READY;
@@ -1971,12 +2046,12 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash,
   }
   else
   {
-    while(__HAL_HASH_GET_FLAG(Flag) != RESET)
+    while (__HAL_HASH_GET_FLAG(Flag) != RESET)
     {
       /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
+      if (Timeout != HAL_MAX_DELAY)
       {
-        if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
         {
           /* Set State to Ready to be able to restart later on */
           hhash->State  = HAL_HASH_STATE_READY;
@@ -2009,10 +2084,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
   if (hhash->State == HAL_HASH_STATE_BUSY)
   {
     /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */
-    if(hhash->HashITCounter == 0U)
+    if (hhash->HashITCounter == 0U)
     {
       /* Disable Interrupts */
-      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+      __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
       /* HASH state set back to Ready to prevent any issue in user code
          present in HAL_HASH_ErrorCallback() */
       hhash->State = HAL_HASH_STATE_READY;
@@ -2020,9 +2095,9 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
     }
     else if (hhash->HashITCounter == 1U)
     {
-     /* This is the first call to HASH_IT, the first input data are about to be
-        entered in the Peripheral. A specific processing is carried out at this point to
-        start-up the processing. */
+      /* This is the first call to HASH_IT, the first input data are about to be
+         entered in the Peripheral. A specific processing is carried out at this point to
+         start-up the processing. */
       hhash->HashITCounter = 2U;
     }
     else
@@ -2039,7 +2114,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
       HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH());
 
       /* Disable Interrupts */
-      __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+      __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
       /* Change the HASH state */
       hhash->State = HAL_HASH_STATE_READY;
       /* Reset HASH state machine */
@@ -2060,10 +2135,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
 
       /* If the suspension flag has been raised and if the processing is not about
          to end, suspend processing */
-      if ( (hhash->HashInCount != 0U) &&  (hhash->SuspendRequest == HAL_HASH_SUSPEND))
+      if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND))
       {
         /* Disable Interrupts */
-        __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+        __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
 
         /* Reset SuspendRequest */
         hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
@@ -2092,7 +2167,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
           if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
           {
             /* Disable Interrupts */
-            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+            __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
             return HAL_TIMEOUT;
           }
           /* Initialization start for HMAC STEP 2 */
@@ -2100,7 +2175,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
           __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize);  /* Set NBLW for the input message */
           hhash->HashInCount = hhash->HashBuffSize;         /* Set the input data size (in bytes) */
           hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr;   /* Set the input data address */
-          hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start of a new phase */
+          hhash->HashITCounter = 1;                         /* Set ITCounter to 1 to indicate the start
+                                                               of a new phase */
           __HAL_HASH_ENABLE_IT(HASH_IT_DINI);               /* Enable IT (was disabled in HASH_Write_Block_Data) */
         }
         else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
@@ -2109,7 +2185,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
           if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
           {
             /* Disable Interrupts */
-            __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+            __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
             return HAL_TIMEOUT;
           }
           /* Initialization start for HMAC STEP 3 */
@@ -2117,7 +2193,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash)
           __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);   /* Set NBLW for the key */
           hhash->HashInCount = hhash->Init.KeySize;          /* Set the key size (in bytes) */
           hhash->pHashInBuffPtr = hhash->Init.pKey;          /* Set the key address */
-          hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start of a new phase */
+          hhash->HashITCounter = 1;                          /* Set ITCounter to 1 to indicate the start
+                                                                of a new phase */
           __HAL_HASH_ENABLE_IT(HASH_IT_DINI);                /* Enable IT (was disabled in HASH_Write_Block_Data) */
         }
         else
@@ -2151,28 +2228,28 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
   uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED;
 
   /* If there are more than 64 bytes remaining to be entered */
-  if(hhash->HashInCount > 64U)
+  if (hhash->HashInCount > 64U)
   {
     inputaddr = (uint32_t)hhash->pHashInBuffPtr;
     /* Write the Input block in the Data IN register
       (16 32-bit words, or 64 bytes are entered) */
-    for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
+    for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U)
     {
-      HASH->DIN = *(uint32_t*)inputaddr;
-      inputaddr+=4U;
+      HASH->DIN = *(uint32_t *)inputaddr;
+      inputaddr += 4U;
     }
     /* If this is the start of input data entering, an additional word
       must be entered to start up the HASH processing */
-    if(hhash->HashITCounter == 2U)
+    if (hhash->HashITCounter == 2U)
     {
-      HASH->DIN = *(uint32_t*)inputaddr;
-      if(hhash->HashInCount >= 68U)
+      HASH->DIN = *(uint32_t *)inputaddr;
+      if (hhash->HashInCount >= 68U)
       {
         /* There are still data waiting to be entered in the Peripheral.
            Decrement buffer counter and set pointer to the proper
            memory location for the next data entering round. */
         hhash->HashInCount -= 68U;
-        hhash->pHashInBuffPtr+= 68U;
+        hhash->pHashInBuffPtr += 68U;
       }
       else
       {
@@ -2186,7 +2263,7 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
          Decrement buffer counter and set pointer to the proper
         memory location for the next data entering round.*/
       hhash->HashInCount -= 64U;
-      hhash->pHashInBuffPtr+= 64U;
+      hhash->pHashInBuffPtr += 64U;
     }
   }
   else
@@ -2202,10 +2279,10 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
     __HAL_HASH_DISABLE_IT(HASH_IT_DINI);
 
     /* Write the Input block in the Data IN register */
-    for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++)
+    for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++)
     {
-      HASH->DIN = *(uint32_t*)inputaddr;
-      inputaddr+=4U;
+      HASH->DIN = *(uint32_t *)inputaddr;
+      inputaddr += 4U;
     }
 
     if (hhash->Accumulation == 1U)
@@ -2219,9 +2296,9 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
       hhash->State = HAL_HASH_STATE_READY;
       /* Call Input data transfer complete call back */
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-        hhash->InCpltCallback(hhash);
+      hhash->InCpltCallback(hhash);
 #else
-        HAL_HASH_InCpltCallback(hhash);
+      HAL_HASH_InCpltCallback(hhash);
 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
     }
     else
@@ -2251,7 +2328,8 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash)
 static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout)
 {
   /* Ensure first that Phase is correct */
-  if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
+  if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2)
+      && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3))
   {
     /* Change the HASH state */
     hhash->State = HAL_HASH_STATE_READY;
@@ -2348,11 +2426,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
   }
 
 
- /* HMAC Step 3 processing.
-     After phase check, HMAC_Processing() may
-     - directly start up from this point in resumption case
-       if the same Step 3 processing was suspended previously
-    - or fall through from the Step 2 processing carried out hereabove */
+  /* HMAC Step 3 processing.
+      After phase check, HMAC_Processing() may
+      - directly start up from this point in resumption case
+        if the same Step 3 processing was suspended previously
+     - or fall through from the Step 2 processing carried out hereabove */
   if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)
   {
     /************************** STEP 3 ******************************************/
@@ -2380,7 +2458,7 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
     __HAL_HASH_START_DIGEST();
 
     /* Wait for DCIS flag to be set */
-     if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
+    if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -2392,14 +2470,14 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
     hhash->Phase = HAL_HASH_PHASE_READY;
   }
 
-   /* Change the HASH state */
-   hhash->State = HAL_HASH_STATE_READY;
+  /* Change the HASH state */
+  hhash->State = HAL_HASH_STATE_READY;
 
-   /* Process Unlock */
-   __HAL_UNLOCK(hhash);
+  /* Process Unlock */
+  __HAL_UNLOCK(hhash);
 
-   /* Return function status */
-   return HAL_OK;
+  /* Return function status */
+  return HAL_OK;
 }
 
 
@@ -2415,7 +2493,9 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                             uint8_t *pOutBuffer,
+                             uint32_t Timeout, uint32_t Algorithm)
 {
   uint8_t *pInBuffer_tmp;  /* input data address, input parameter of HASH_WriteData()         */
   uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */
@@ -2423,7 +2503,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint
 
 
   /* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
     if ((pInBuffer == NULL) || (pOutBuffer == NULL))
@@ -2436,20 +2516,20 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     __HAL_LOCK(hhash);
 
     /* Check if initialization phase has not been already performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
     {
       /* Change the HASH state */
       hhash->State = HAL_HASH_STATE_BUSY;
 
       /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+      MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
 
       /* Configure the number of valid bits in last word of the message */
       __HAL_HASH_SET_NBVALIDBITS(Size);
 
       /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
       input parameters of HASH_WriteData() */
-      pInBuffer_tmp = pInBuffer;   /* pInBuffer_tmp is set to the input data address */
+      pInBuffer_tmp = (uint8_t *)pInBuffer;   /* pInBuffer_tmp is set to the input data address */
       Size_tmp = Size;             /* Size_tmp contains the input data size in bytes */
 
       /* Set the phase */
@@ -2465,7 +2545,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
         /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
         to the API input parameters but to those saved beforehand by HASH_WriteData()
         when the processing was suspended */
-        pInBuffer_tmp = hhash->pHashInBuffPtr;
+        pInBuffer_tmp = (uint8_t *)hhash->pHashInBuffPtr;
         Size_tmp = hhash->HashInCount;
       }
       /* ... or multi-buffer HASH processing end */
@@ -2473,7 +2553,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
       {
         /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
         input parameters of HASH_WriteData() */
-        pInBuffer_tmp = pInBuffer;
+        pInBuffer_tmp = (uint8_t *)pInBuffer;
         Size_tmp = Size;
         /* Configure the number of valid bits in last word of the message */
         __HAL_HASH_SET_NBVALIDBITS(Size);
@@ -2551,7 +2631,8 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                  uint32_t Algorithm)
 {
   uint8_t *pInBuffer_tmp;   /* input data address, input parameter of HASH_WriteData()         */
   uint32_t Size_tmp;  /* input data size (in bytes), input parameter of HASH_WriteData() */
@@ -2564,7 +2645,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
   }
 
   /* Initiate HASH processing in case of start or resumption */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
     if ((pInBuffer == NULL) || (Size == 0U))
@@ -2573,7 +2654,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
       return  HAL_ERROR;
     }
 
-     /* Process Locked */
+    /* Process Locked */
     __HAL_LOCK(hhash);
 
     /* If resuming the HASH processing */
@@ -2585,7 +2666,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
       /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set
          to the API input parameters but to those saved beforehand by HASH_WriteData()
          when the processing was suspended */
-      pInBuffer_tmp = hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
+      pInBuffer_tmp = (uint8_t *)hhash->pHashInBuffPtr;  /* pInBuffer_tmp is set to the input data address */
       Size_tmp = hhash->HashInCount;          /* Size_tmp contains the input data size in bytes */
 
     }
@@ -2596,14 +2677,14 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
 
       /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as
          input parameters of HASH_WriteData() */
-      pInBuffer_tmp = pInBuffer;    /* pInBuffer_tmp is set to the input data address */
+      pInBuffer_tmp = (uint8_t *)pInBuffer;    /* pInBuffer_tmp is set to the input data address */
       Size_tmp = Size;              /* Size_tmp contains the input data size in bytes */
 
       /* Check if initialization phase has already be performed */
-      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      if (hhash->Phase == HAL_HASH_PHASE_READY)
       {
         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
       }
 
       /* Set the phase */
@@ -2654,7 +2735,8 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint32_t Algorithm)
 {
   HAL_HASH_StateTypeDef State_tmp = hhash->State;
   __IO uint32_t inputaddr = (uint32_t) pInBuffer;
@@ -2667,7 +2749,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
   }
 
   /* Initiate HASH processing in case of start or resumption */
-  if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
     if ((pInBuffer == NULL) || (Size == 0U))
@@ -2676,7 +2758,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
       return  HAL_ERROR;
     }
 
-     /* Process Locked */
+    /* Process Locked */
     __HAL_LOCK(hhash);
 
     /* If resuming the HASH processing */
@@ -2691,15 +2773,15 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
       hhash->State = HAL_HASH_STATE_BUSY;
 
       /* Check if initialization phase has already be performed */
-      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      if (hhash->Phase == HAL_HASH_PHASE_READY)
       {
         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
         hhash->HashITCounter = 1;
       }
       else
       {
-         hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
+        hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */
       }
 
       /* Set the phase */
@@ -2709,13 +2791,13 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
        fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
        Therefore, first words are manually entered until DINIS raises, or until there
        is not more data to enter. */
-      while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
+      while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U))
       {
 
         /* Write input data 4 bytes at a time */
-        HASH->DIN = *(uint32_t*)inputaddr;
-        inputaddr+=4U;
-        SizeVar-=4U;
+        HASH->DIN = *(uint32_t *)inputaddr;
+        inputaddr += 4U;
+        SizeVar -= 4U;
       }
 
       /* If DINIS is still not set or if all the data have been fed, stop here */
@@ -2736,10 +2818,10 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
                                                   to be fed to the Peripheral */
       hhash->pHashInBuffPtr = (uint8_t *)inputaddr;       /* Points at data which will be fed to the Peripheral at
                                                   the next interruption */
-     /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
-        the information describing where the HASH process is stopped.
-        These variables are used later on to resume the HASH processing at the
-        correct location. */
+      /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+         the information describing where the HASH process is stopped.
+         These variables are used later on to resume the HASH processing at the
+         correct location. */
 
     }
 
@@ -2764,7 +2846,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
 }
 
 
-
 /**
   * @brief  Initialize the HASH peripheral, next process pInBuffer then
   *         read the computed digest in interruption mode.
@@ -2776,16 +2857,18 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                uint8_t *pOutBuffer,
+                                uint32_t Algorithm)
 {
-   HAL_HASH_StateTypeDef State_tmp = hhash->State;
+  HAL_HASH_StateTypeDef State_tmp = hhash->State;
   __IO uint32_t inputaddr = (uint32_t) pInBuffer;
   uint32_t polling_step = 0U;
   uint32_t initialization_skipped = 0U;
   uint32_t SizeVar = Size;
 
   /* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
     if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL))
@@ -2804,26 +2887,39 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     hhash->HashITCounter = 1;
 
     /* Check if initialization phase has already be performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
     {
       /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-      MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+      MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
 
       /* Configure the number of valid bits in last word of the message */
-     __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+      __HAL_HASH_SET_NBVALIDBITS(SizeVar);
 
 
       hhash->HashInCount = SizeVar;            /* Counter used to keep track of number of data
                                                   to be fed to the Peripheral */
       hhash->pHashInBuffPtr = pInBuffer;       /* Points at data which will be fed to the Peripheral at
                                                   the next interruption */
-     /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
-        the information describing where the HASH process is stopped.
-        These variables are used later on to resume the HASH processing at the
-        correct location. */
+      /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain
+         the information describing where the HASH process is stopped.
+         These variables are used later on to resume the HASH processing at the
+         correct location. */
 
       hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
     }
+    else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U))
+    {
+      if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
+      {
+        /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual.
+        Update HashInCount and pHashInBuffPtr accordingly. */
+        hhash->HashInCount = SizeVar;
+        hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+        /* Update the configuration of the number of valid bits in last word of the message */
+        __HAL_HASH_SET_NBVALIDBITS(SizeVar);
+        hhash->pHashOutBuffPtr = pOutBuffer;  /* Points at the computed digest */
+      }
+    }
     else
     {
       initialization_skipped = 1; /* info user later on in case of multi-buffer */
@@ -2832,17 +2928,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     /* Set the phase */
     hhash->Phase = HAL_HASH_PHASE_PROCESS;
 
-   /* If DINIS is equal to 0 (for example if an incomplete block has been previously
-     fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
-     Therefore, first words are manually entered until DINIS raises. */
-    while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
+    /* If DINIS is equal to 0 (for example if an incomplete block has been previously
+      fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set.
+      Therefore, first words are manually entered until DINIS raises. */
+    while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U))
     {
       polling_step = 1U; /* note that some words are entered before enabling the interrupt */
 
       /* Write input data 4 bytes at a time */
-      HASH->DIN = *(uint32_t*)inputaddr;
-      inputaddr+=4U;
-      SizeVar-=4U;
+      HASH->DIN = *(uint32_t *)inputaddr;
+      inputaddr += 4U;
+      SizeVar -= 4U;
     }
 
     if (polling_step == 1U)
@@ -2854,7 +2950,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
         hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
 
         /* Start the Digest calculation */
-         __HAL_HASH_START_DIGEST();
+        __HAL_HASH_START_DIGEST();
         /* Process Unlock */
         __HAL_UNLOCK(hhash);
 
@@ -2871,7 +2967,8 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
            Update HashInCount and pHashInBuffPtr accordingly. */
         hhash->HashInCount = SizeVar;
         hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
-        __HAL_HASH_SET_NBVALIDBITS(SizeVar);  /* Update the configuration of the number of valid bits in last word of the message */
+        /* Update the configuration of the number of valid bits in last word of the message */
+        __HAL_HASH_SET_NBVALIDBITS(SizeVar);
         hhash->pHashOutBuffPtr = pOutBuffer;  /* Points at the computed digest */
         if (initialization_skipped == 1U)
         {
@@ -2883,11 +2980,11 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
         /* DINIS is not set but it remains a few data to enter (not enough for a full word).
            Manually enter the last bytes before enabling DCIE. */
         __HAL_HASH_SET_NBVALIDBITS(SizeVar);
-        HASH->DIN = *(uint32_t*)inputaddr;
+        HASH->DIN = *(uint32_t *)inputaddr;
 
-         /* Start the Digest calculation */
+        /* Start the Digest calculation */
         hhash->pHashOutBuffPtr = pOutBuffer;     /* Points at the computed digest */
-         __HAL_HASH_START_DIGEST();
+        __HAL_HASH_START_DIGEST();
         /* Process Unlock */
         __HAL_UNLOCK(hhash);
 
@@ -2904,7 +3001,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     __HAL_UNLOCK(hhash);
 
     /* Enable Interrupts */
-    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+    __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
 
     /* Return function status */
     return HAL_OK;
@@ -2932,7 +3029,8 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                 uint32_t Algorithm)
 {
   uint32_t inputaddr;
   uint32_t inputSize;
@@ -2944,15 +3042,15 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
      (case of multi-buffer HASH processing) */
   assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
 
-   /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  /* If State is ready or suspended, start or resume polling-based HASH processing */
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
-    if ( (pInBuffer == NULL ) || (Size == 0U) ||
-    /* Check phase coherency. Phase must be
-       either READY (fresh start)
-       or PROCESS (multi-buffer HASH management) */
-       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
+    if ((pInBuffer == NULL) || (Size == 0U) ||
+        /* Check phase coherency. Phase must be
+           either READY (fresh start)
+           or PROCESS (multi-buffer HASH management) */
+        ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash)))))
     {
       hhash->State = HAL_HASH_STATE_READY;
       return  HAL_ERROR;
@@ -2972,10 +3070,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
          If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the
          API is processing a new input data message in case of multi-buffer HASH
          computation. */
-      if(hhash->Phase == HAL_HASH_PHASE_READY)
+      if (hhash->Phase == HAL_HASH_PHASE_READY)
       {
         /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT);
 
         /* Set the phase */
         hhash->Phase = HAL_HASH_PHASE_PROCESS;
@@ -3015,7 +3113,9 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
 
     /* Enable the DMA In DMA stream */
-    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \
+                              (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) : \
+                               (inputSize / 4U)));
 
     /* Enable DMA requests */
     SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3046,10 +3146,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
 {
 
-  if(hhash->State == HAL_HASH_STATE_READY)
+  if (hhash->State == HAL_HASH_STATE_READY)
   {
     /* Check parameter */
     if (pOutBuffer == NULL)
@@ -3107,15 +3207,18 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                             uint8_t *pOutBuffer,
+                             uint32_t Timeout, uint32_t Algorithm)
 {
-    HAL_HASH_StateTypeDef State_tmp = hhash->State;
+  HAL_HASH_StateTypeDef State_tmp = hhash->State;
 
-   /* If State is ready or suspended, start or resume polling-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  /* If State is ready or suspended, start or resume polling-based HASH processing */
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+        || (pOutBuffer == NULL))
     {
       hhash->State = HAL_HASH_STATE_READY;
       return  HAL_ERROR;
@@ -3128,28 +3231,34 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     hhash->State = HAL_HASH_STATE_BUSY;
 
     /* Check if initialization phase has already be performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
+    if (hhash->Phase == HAL_HASH_PHASE_READY)
     {
       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
-      if(hhash->Init.KeySize > 64U)
+      if (hhash->Init.KeySize > 64U)
       {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+                   Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
       }
       else
       {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+                   Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
       }
       /* Set the phase to Step 1 */
       hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
       /* Resort to hhash internal fields to feed the Peripheral.
          Parameters will be updated in case of suspension to contain the proper
          information at resumption time. */
-      hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address                                              */
-      hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input parameter for Step 2     */
-      hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input parameter for Step 2        */
-      hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process             */
-      hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */
-      hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1 and Step 3    */
+      hhash->pHashOutBuffPtr  = pOutBuffer;            /* Output digest address    */
+      hhash->pHashInBuffPtr   = pInBuffer;             /* Input data address, HMAC_Processing input
+                                                          parameter for Step 2     */
+      hhash->HashInCount      = Size;                  /* Input data size, HMAC_Processing input
+                                                          parameter for Step 2        */
+      hhash->HashBuffSize     = Size;                  /* Store the input buffer size for the whole HMAC process*/
+      hhash->pHashKeyBuffPtr  = hhash->Init.pKey;      /* Key address, HMAC_Processing input parameter for Step
+                                                          1 and Step 3 */
+      hhash->HashKeyCount     = hhash->Init.KeySize;   /* Key size, HMAC_Processing input parameter for Step 1
+                                                          and Step 3    */
     }
 
     /* Carry out HMAC processing */
@@ -3163,7 +3272,6 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
 }
 
 
-
 /**
   * @brief  Initialize the HASH peripheral in HMAC mode, next process pInBuffer then
   *         read the computed digest in interruption mode.
@@ -3177,15 +3285,18 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                uint8_t *pOutBuffer,
+                                uint32_t Algorithm)
 {
-    HAL_HASH_StateTypeDef State_tmp = hhash->State;
+  HAL_HASH_StateTypeDef State_tmp = hhash->State;
 
   /* If State is ready or suspended, start or resume IT-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
-    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL))
+    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U)
+        || (pOutBuffer == NULL))
     {
       hhash->State = HAL_HASH_STATE_READY;
       return  HAL_ERROR;
@@ -3204,13 +3315,15 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     if (hhash->Phase == HAL_HASH_PHASE_READY)
     {
       /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */
-      if(hhash->Init.KeySize > 64U)
+      if (hhash->Init.KeySize > 64U)
       {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+                   Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
       }
       else
       {
-        MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+        MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+                   Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
       }
 
       /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount
@@ -3255,7 +3368,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     __HAL_UNLOCK(hhash);
 
     /* Enable Interrupts */
-    __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI);
+    __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI);
 
     /* Return function status */
     return HAL_OK;
@@ -3268,7 +3381,6 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
 }
 
 
-
 /**
   * @brief  Initialize the HASH peripheral in HMAC mode then initiate the required
   *         DMA transfers to feed the key and the input buffer to the Peripheral.
@@ -3284,24 +3396,25 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @param  Algorithm HASH algorithm.
   * @retval HAL status
   */
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm)
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                 uint32_t Algorithm)
 {
   uint32_t inputaddr;
   uint32_t inputSize;
   HAL_StatusTypeDef status ;
   HAL_HASH_StateTypeDef State_tmp = hhash->State;
-   /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
-      is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
-   assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
+  /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation
+     is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */
+  assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size));
   /* If State is ready or suspended, start or resume DMA-based HASH processing */
-if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
+  if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
   {
     /* Check input parameters */
-    if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) ||
-   /* Check phase coherency. Phase must be
-       either READY (fresh start)
-       or one of HMAC PROCESS steps (multi-buffer HASH management) */
-       ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
+    if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) ||
+        /* Check phase coherency. Phase must be
+            either READY (fresh start)
+            or one of HMAC PROCESS steps (multi-buffer HASH management) */
+        ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash)))))
     {
       hhash->State = HAL_HASH_STATE_READY;
       return  HAL_ERROR;
@@ -3314,63 +3427,65 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     /* If not a case of resumption after suspension */
     if (hhash->State == HAL_HASH_STATE_READY)
     {
-    /* Check whether or not initialization phase has already be performed */
-    if(hhash->Phase == HAL_HASH_PHASE_READY)
-    {
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
-      /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
-         At the same time, ensure MDMAT bit is cleared. */
-      if(hhash->Init.KeySize > 64U)
+      /* Check whether or not initialization phase has already be performed */
+      if (hhash->Phase == HAL_HASH_PHASE_READY)
       {
-        MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+        /* Change the HASH state */
+        hhash->State = HAL_HASH_STATE_BUSY;
+        /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits.
+           At the same time, ensure MDMAT bit is cleared. */
+        if (hhash->Init.KeySize > 64U)
+        {
+          MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+                     Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
+        }
+        else
+        {
+          MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT,
+                     Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
+        }
+        /* Store input aparameters in handle fields to manage steps transition
+           or possible HMAC suspension/resumption */
+        hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
+        hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
+        hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
+        hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
+        hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
+
+        /* Set DMA input parameters */
+        inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
+        inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
+
+        /* Configure the number of valid bits in last word of the key */
+        __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
+
+        /* Set the phase to Step 1 */
+        hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
+
       }
-      else
-      {
-        MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
-      }
-      /* Store input aparameters in handle fields to manage steps transition
-         or possible HMAC suspension/resumption */
-      hhash->HashInCount = hhash->Init.KeySize;   /* Initial size for first DMA transfer (key size)      */
-      hhash->pHashKeyBuffPtr = hhash->Init.pKey;  /* Key address                                         */
-      hhash->pHashInBuffPtr  = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */
-      hhash->pHashMsgBuffPtr = pInBuffer;         /* Input data address                                  */
-      hhash->HashBuffSize = Size;                 /* input data size (in bytes)                          */
-
-      /* Set DMA input parameters */
-      inputaddr = (uint32_t)(hhash->Init.pKey);   /* Address passed to DMA (start by entering Key message) */
-      inputSize = hhash->Init.KeySize;            /* Size for first DMA transfer (in bytes) */
-
-      /* Configure the number of valid bits in last word of the key */
-      __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
-
-      /* Set the phase to Step 1 */
-      hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1;
-
-    }
       else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)
-    {
-      /* Process a new input data message in case of multi-buffer HMAC processing
-        (this is not a resumption case) */
+      {
+        /* Process a new input data message in case of multi-buffer HMAC processing
+          (this is not a resumption case) */
 
-      /* Change the HASH state */
-      hhash->State = HAL_HASH_STATE_BUSY;
+        /* Change the HASH state */
+        hhash->State = HAL_HASH_STATE_BUSY;
 
-      /* Save input parameters to be able to manage possible suspension/resumption */
+        /* Save input parameters to be able to manage possible suspension/resumption */
         hhash->HashInCount = Size;                /* Input message address       */
         hhash->pHashInBuffPtr = pInBuffer;        /* Input message size in bytes */
 
-      /* Set DMA input parameters */
+        /* Set DMA input parameters */
         inputaddr = (uint32_t)pInBuffer;           /* Input message address       */
         inputSize = Size;                          /* Input message size in bytes */
 
-      if (hhash->DigestCalculationDisable == RESET)
-      {
-        /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
-       __HAL_HASH_RESET_MDMAT();
-        __HAL_HASH_SET_NBVALIDBITS(inputSize);
+        if (hhash->DigestCalculationDisable == RESET)
+        {
+          /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */
+          __HAL_HASH_RESET_MDMAT();
+          __HAL_HASH_SET_NBVALIDBITS(inputSize);
+        }
       }
-    }
       else
       {
         /* Phase not aligned with handle READY state */
@@ -3381,7 +3496,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     }
     else
     {
-       /* Resumption case (phase may be Step 1, 2 or 3) */
+      /* Resumption case (phase may be Step 1, 2 or 3) */
 
       /* Change the HASH state */
       hhash->State = HAL_HASH_STATE_BUSY;
@@ -3404,7 +3519,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
     hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
 
     /* Enable the DMA In DMA stream */
-    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
+    status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN,  \
+                              (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \
+                               : (inputSize / 4U)));
+
     /* Enable DMA requests */
     SET_BIT(HASH->CR, HASH_CR_DMAE);
 
@@ -3440,6 +3558,3 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED
   * @}
   */
 
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.h
index 605ee83150..dea1930b8f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,7 +21,7 @@
 #define STM32H7xx_HAL_HASH_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -51,7 +50,7 @@ typedef struct
 
   uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */
 
-  uint8_t* pKey;        /*!< The key is used only in HMAC operation. */
+  uint8_t *pKey;        /*!< The key is used only in HMAC operation. */
 
 } HASH_InitTypeDef;
 
@@ -66,7 +65,7 @@ typedef enum
   HAL_HASH_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                            */
   HAL_HASH_STATE_ERROR             = 0x07U,    /*!< Error state                              */
   HAL_HASH_STATE_SUSPENDED         = 0x08U     /*!< Suspended state                          */
-}HAL_HASH_StateTypeDef;
+} HAL_HASH_StateTypeDef;
 
 /**
   * @brief HAL phase structures definition
@@ -81,7 +80,7 @@ typedef enum
                                               (step 2 consists in entering the message text) */
   HAL_HASH_PHASE_HMAC_STEP_3       = 0x05U     /*!< HASH peripheral is in HMAC step 3 processing phase
                                               (step 3 consists in entering the outer hash function key) */
-}HAL_HASH_PhaseTypeDef;
+} HAL_HASH_PhaseTypeDef;
 
 /**
   * @brief HAL HASH mode suspend definitions
@@ -90,7 +89,7 @@ typedef enum
 {
   HAL_HASH_SUSPEND_NONE            = 0x00U,    /*!< HASH peripheral suspension not requested */
   HAL_HASH_SUSPEND                 = 0x01U     /*!< HASH peripheral suspension is requested  */
-}HAL_HASH_SuspendTypeDef;
+} HAL_HASH_SuspendTypeDef;
 
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)
 /**
@@ -103,7 +102,7 @@ typedef enum
   HAL_HASH_INPUTCPLT_CB_ID         = 0x02U,    /*!< HASH input completion callback ID */
   HAL_HASH_DGSTCPLT_CB_ID          = 0x03U,    /*!< HASH digest computation completion callback ID */
   HAL_HASH_ERROR_CB_ID             = 0x04U,    /*!< HASH error callback ID     */
-}HAL_HASH_CallbackIDTypeDef;
+} HAL_HASH_CallbackIDTypeDef;
 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
 
@@ -118,13 +117,13 @@ typedef struct
 {
   HASH_InitTypeDef           Init;             /*!< HASH required parameters */
 
-  uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */
+  uint8_t const              *pHashInBuffPtr;  /*!< Pointer to input buffer */
 
   uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
 
   uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
 
-  uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
+  uint8_t const              *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
 
   uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */
 
@@ -155,15 +154,15 @@ typedef struct
   __IO  uint32_t             Accumulation;     /*!< HASH multi buffers accumulation flag */
 
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-  void    (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash);    /*!< HASH input completion callback */
+  void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash);         /*!< HASH input completion callback */
 
-  void    (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash);  /*!< HASH digest computation completion callback */
+  void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash);       /*!< HASH digest computation completion callback */
 
-  void    (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash);     /*!< HASH error callback */
+  void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash);          /*!< HASH error callback */
 
-  void    (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash);   /*!< HASH Msp Init callback */
+  void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash);        /*!< HASH Msp Init callback */
 
-  void    (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */
+  void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash);      /*!< HASH Msp DeInit callback */
 
 #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */
 } HASH_HandleTypeDef;
@@ -172,7 +171,7 @@ typedef struct
 /**
   * @brief  HAL HASH Callback pointer definition
   */
-typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */
+typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash);  /*!< pointer to a HASH common callback functions */
 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
 /**
@@ -244,13 +243,6 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 #define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */
 #define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */
 
-/**
-  * @}
-  */
-/** @defgroup HASH_alias HASH API alias
-  * @{
-  */
-#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
 /**
   * @}
   */
@@ -288,8 +280,8 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \
-                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
-                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
+                                        ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
+                                        ((HASH->SR & (__FLAG__)) == (__FLAG__)) )
 
 
 /** @brief  Clear the specified HASH flag.
@@ -366,7 +358,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @brief Set the number of valid bits in the last word written in data register DIN.
   * @param  __SIZE__ size in bytes of last data written in Data register.
   * @retval None
-*/
+  */
 #define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
 
 /**
@@ -389,8 +381,8 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @retval Digest length
   */
 #define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20U : \
-                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28U : \
-                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32U : 16U ) ) )
+                              ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28U : \
+                               ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32U : 16U ) ) )
 /**
   * @brief  Return number of words already pushed in the FIFO.
   * @retval Number of words already pushed in the FIFO
@@ -424,7 +416,8 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @param __SIZE__ input data buffer size.
   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
   */
-#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET)\
+                                                            || (((__SIZE__) % 4U) == 0U))
 /**
   * @brief Ensure that handle phase is set to HASH processing.
   * @param __HANDLE__ HASH handle.
@@ -467,7 +460,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
 void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID,
+                                            pHASH_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */
 
@@ -482,12 +476,18 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
 
 
 /* HASH processing using polling  *********************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint8_t *pOutBuffer,
+                                      uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint8_t *pOutBuffer,
+                                     uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                           uint8_t *pOutBuffer, uint32_t Timeout);
 
 
 /**
@@ -499,12 +499,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p
   */
 
 /* HASH processing using IT  **************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                         uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                              uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                        uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer);
 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /**
   * @}
@@ -515,10 +519,10 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
   */
 
 /* HASH processing using DMA  *************************************************/
-HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
 
 /**
   * @}
@@ -529,8 +533,12 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu
   */
 
 /* HASH-MAC processing using polling  *****************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                      uint8_t *pOutBuffer,
+                                      uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint8_t *pOutBuffer,
+                                     uint32_t Timeout);
 
 /**
   * @}
@@ -540,8 +548,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff
   * @{
   */
 
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                        uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                         uint8_t *pOutBuffer);
 
 /**
   * @}
@@ -552,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn
   */
 
 /* HASH-HMAC processing using DMA  ********************************************/
-HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
 
 /**
   * @}
@@ -565,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn
 
 
 /* Peripheral State methods  **************************************************/
-HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
-HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
-void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
-void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
+HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash);
+HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash);
+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer);
 void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
 HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
-uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
+uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash);
 
 /**
   * @}
@@ -588,15 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
   */
 
 /* Private functions */
-HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
-HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
-HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                             uint8_t *pOutBuffer,
+                             uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                  uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                     uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                uint8_t *pOutBuffer,
+                                uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                 uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                             uint8_t *pOutBuffer,
+                             uint32_t Timeout, uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                uint8_t *pOutBuffer,
+                                uint32_t Algorithm);
+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                 uint32_t Algorithm);
 
 /**
   * @}
@@ -618,4 +640,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer,
 
 #endif /* STM32H7xx_HAL_HASH_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c
index 2ddac61211..00c4340c98 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c
@@ -14,6 +14,17 @@
   *         and SHA-256.
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                      ##### HASH peripheral extended features  #####
@@ -39,14 +50,15 @@
              User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as
              well the computed digest.
 
-        (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, 
+        (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer,
              except for the last one.
              User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as
              well the computed digest.
 
         (##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
 
-              (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+              (+++) HASH processing: once initialization is done, MDMAT bit must be set through
+               __HAL_HASH_SET_MDMAT() macro.
              From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
              Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
              macro then wrap-up the HASH processing in feeding the last input buffer through the
@@ -68,25 +80,12 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal.h"
 
 
-
-
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
@@ -107,8 +106,8 @@
   */
 
 /** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
- *  @brief   HASH extended processing functions using polling mode.
- *
+  *  @brief   HASH extended processing functions using polling mode.
+  *
 @verbatim
  ===============================================================================
                ##### Polling mode HASH extended processing functions #####
@@ -147,7 +146,8 @@
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
 }
@@ -172,9 +172,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+  return  HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
 }
 
 /**
@@ -187,7 +187,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                               uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
 }
@@ -203,7 +204,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
 }
@@ -228,9 +230,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+  return  HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
 }
 
 /**
@@ -243,7 +245,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p
   * @param  Timeout Timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                               uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
 }
@@ -253,8 +256,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
   */
 
 /** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
- *  @brief   HASH extended processing functions using interrupt mode.
- *
+  *  @brief   HASH extended processing functions using interrupt mode.
+  *
 @verbatim
  ===============================================================================
           ##### Interruption mode HASH extended processing functions #####
@@ -285,9 +288,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
   * @param  pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
 }
 
 /**
@@ -308,9 +312,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224);
+  return  HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
 }
 
 /**
@@ -322,9 +326,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                  uint32_t Size,
+                                                  uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
 }
 
 /**
@@ -337,9 +343,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
   * @param  pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
 }
 
 /**
@@ -360,9 +367,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes, must be a multiple of 4.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
-  return  HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256);
+  return  HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
 }
 
 /**
@@ -374,9 +381,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                  uint32_t Size,
+                                                  uint8_t *pOutBuffer)
 {
-  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256);
+  return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
 }
 
 /**
@@ -384,8 +393,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
   */
 
 /** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
- *  @brief   HASH extended processing functions using DMA mode.
- *
+  *  @brief   HASH extended processing functions using DMA mode.
+  *
 @verbatim
  ===============================================================================
                 ##### DMA mode HASH extended  processing functions #####
@@ -413,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
   */
 
 
-
-
 /**
   * @brief  Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer
   *         to feed the input buffer to the Peripheral.
@@ -425,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
 }
@@ -440,9 +447,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
 {
-   return HASH_Finish(hhash, pOutBuffer, Timeout);
+  return HASH_Finish(hhash, pOutBuffer, Timeout);
 }
 
 /**
@@ -455,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
 }
@@ -470,9 +477,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout)
 {
-   return HASH_Finish(hhash, pOutBuffer, Timeout);
+  return HASH_Finish(hhash, pOutBuffer, Timeout);
 }
 
 /**
@@ -480,8 +487,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
   */
 
 /** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
- *  @brief   HMAC extended processing functions using polling mode.
- *
+  *  @brief   HMAC extended processing functions using polling mode.
+  *
 @verbatim
  ===============================================================================
              ##### Polling mode HMAC extended processing functions #####
@@ -498,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
   */
 
 
-
 /**
   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
   *         read the computed digest.
@@ -512,7 +518,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224);
 }
@@ -530,7 +537,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  Timeout Timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout)
 {
   return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256);
 }
@@ -541,8 +549,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
 
 
 /** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
- *  @brief   HMAC extended processing functions using interruption mode.
- *
+  *  @brief   HMAC extended processing functions using interruption mode.
+  *
 @verbatim
  ===============================================================================
              ##### Interrupt mode HMAC extended processing functions #####
@@ -559,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
   */
 
 
-
 /**
   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then
   *         read the computed digest in interrupt mode.
@@ -572,7 +579,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @param  pOutBuffer pointer to the computed digest. Digest size is 28 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer)
 {
   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224);
 }
@@ -589,22 +597,21 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  pOutBuffer pointer to the computed digest. Digest size is 32 bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer)
 {
   return  HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256);
 }
 
 
-
-
 /**
   * @}
   */
 
 
 /** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
- *  @brief   HMAC extended processing functions using DMA mode.
- *
+  *  @brief   HMAC extended processing functions using DMA mode.
+  *
 @verbatim
  ===============================================================================
               ##### DMA mode HMAC extended processing functions #####
@@ -626,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
   */
 
 
-
 /**
   * @brief  Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required
   *         DMA transfers to feed the key and the input buffer to the Peripheral.
@@ -646,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
 }
@@ -670,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
 }
@@ -681,8 +687,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
   */
 
 /** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
- *  @brief   HMAC extended processing functions in multi-buffer DMA mode.
- *
+  *  @brief   HMAC extended processing functions in multi-buffer DMA mode.
+  *
 @verbatim
  ===============================================================================
       ##### Multi-buffer DMA mode HMAC extended processing functions #####
@@ -746,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   hhash->DigestCalculationDisable = SET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
@@ -767,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   if (hhash->DigestCalculationDisable != SET)
   {
@@ -793,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   hhash->DigestCalculationDisable = RESET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5);
@@ -816,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   hhash->DigestCalculationDisable = SET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
@@ -837,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   if (hhash->DigestCalculationDisable != SET)
   {
@@ -863,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   hhash->DigestCalculationDisable = RESET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1);
@@ -885,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size)
 {
   hhash->DigestCalculationDisable = SET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
@@ -906,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   if (hhash->DigestCalculationDisable != SET)
   {
@@ -932,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size)
 {
   hhash->DigestCalculationDisable = RESET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224);
@@ -954,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size)
 {
   hhash->DigestCalculationDisable = SET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
@@ -975,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size)
 {
   if (hhash->DigestCalculationDisable != SET)
   {
@@ -1001,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @param  Size length of the input buffer in bytes.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size)
 {
   hhash->DigestCalculationDisable = RESET;
   return  HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256);
@@ -1025,6 +1035,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
   * @}
   */
 
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.h
index 2d8459d874..2ac9297a91 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,7 +21,7 @@
 #define STM32H7xx_HAL_HASH_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -51,12 +50,16 @@
   * @{
   */
 
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                               uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                               uint8_t *pOutBuffer, uint32_t Timeout);
 
 /**
   * @}
@@ -66,12 +69,18 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_
   * @{
   */
 
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                  uint32_t Size,
+                                                  uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                  uint32_t Size,
+                                                  uint8_t *pOutBuffer);
 
 /**
   * @}
@@ -80,10 +89,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin
 /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
   * @{
   */
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout);
 
 /**
   * @}
@@ -92,8 +101,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p
 /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
   * @{
   */
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                          uint8_t *pOutBuffer, uint32_t Timeout);
 /**
   * @}
   */
@@ -102,8 +113,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI
   * @{
   */
 
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size,
+                                             uint8_t *pOutBuffer);
 
 /**
   * @}
@@ -113,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t
   * @{
   */
 
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
 
 /**
   * @}
@@ -124,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
   * @{
   */
 
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
 
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size);
 
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer,
+                                                uint32_t Size);
 /**
   * @}
   */
@@ -162,4 +179,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8
 
 #endif /* STM32H7xx_HAL_HASH_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c
index 1e5a89af1a..e1fbd00433 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
@@ -40,17 +51,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -61,7 +61,6 @@
   */
 
 #ifdef HAL_HCD_MODULE_ENABLED
-
 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 
 /** @defgroup HCD HCD
@@ -110,8 +109,6 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
   */
 HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
 {
-  USB_OTG_GlobalTypeDef *USBx;
-
   /* Check the HCD handle allocation */
   if (hhcd == NULL)
   {
@@ -121,8 +118,6 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
   /* Check the parameters */
   assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
 
-  USBx = hhcd->Instance;
-
   if (hhcd->State == HAL_HCD_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
@@ -151,23 +146,29 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
 
   hhcd->State = HAL_HCD_STATE_BUSY;
 
-  /* Disable DMA mode for FS instance */
-  if ((USBx->CID & (0x1U << 8)) == 0U)
-  {
-    hhcd->Init.dma_enable = 0U;
-  }
-
   /* Disable the Interrupts */
   __HAL_HCD_DISABLE(hhcd);
 
   /* Init the Core (common init.) */
-  (void)USB_CoreInit(hhcd->Instance, hhcd->Init);
+  if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+  {
+    hhcd->State = HAL_HCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
 
-  /* Force Host Mode*/
-  (void)USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE);
+  /* Force Host Mode */
+  if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK)
+  {
+    hhcd->State = HAL_HCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
 
   /* Init Host */
-  (void)USB_HostInit(hhcd->Instance, hhcd->Init);
+  if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK)
+  {
+    hhcd->State = HAL_HCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
 
   hhcd->State = HAL_HCD_STATE_READY;
 
@@ -198,24 +199,22 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
   *          This parameter can be a value from 0 to32K
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
-                                  uint8_t ch_num,
-                                  uint8_t epnum,
-                                  uint8_t dev_address,
-                                  uint8_t speed,
-                                  uint8_t ep_type,
-                                  uint16_t mps)
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum,
+                                  uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps)
 {
   HAL_StatusTypeDef status;
+  uint32_t HostCoreSpeed;
+  uint32_t HCcharMps = mps;
 
   __HAL_LOCK(hhcd);
   hhcd->hc[ch_num].do_ping = 0U;
   hhcd->hc[ch_num].dev_addr = dev_address;
-  hhcd->hc[ch_num].max_packet = mps;
   hhcd->hc[ch_num].ch_num = ch_num;
   hhcd->hc[ch_num].ep_type = ep_type;
   hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
 
+  (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num);
+
   if ((epnum & 0x80U) == 0x80U)
   {
     hhcd->hc[ch_num].ep_is_in = 1U;
@@ -225,15 +224,27 @@ HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
     hhcd->hc[ch_num].ep_is_in = 0U;
   }
 
-  hhcd->hc[ch_num].speed = speed;
+  HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
+
+  if (ep_type == EP_TYPE_ISOC)
+  {
+    /* FS device plugged to HS HUB */
+    if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
+    {
+      if (HCcharMps > ISO_SPLT_MPS)
+      {
+        /* ISO Max Packet Size for Split mode */
+        HCcharMps = ISO_SPLT_MPS;
+      }
+    }
+  }
+
+  hhcd->hc[ch_num].speed = speed;
+  hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps;
+
+  status =  USB_HC_Init(hhcd->Instance, ch_num, epnum,
+                        dev_address, speed, ep_type, (uint16_t)HCcharMps);
 
-  status =  USB_HC_Init(hhcd->Instance,
-                        ch_num,
-                        epnum,
-                        dev_address,
-                        speed,
-                        ep_type,
-                        mps);
   __HAL_UNLOCK(hhcd);
 
   return status;
@@ -251,7 +262,7 @@ HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
   HAL_StatusTypeDef status = HAL_OK;
 
   __HAL_LOCK(hhcd);
-  (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+  (void)USB_HC_Halt(hhcd->Instance, ch_num);
   __HAL_UNLOCK(hhcd);
 
   return status;
@@ -390,24 +401,41 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
   switch (ep_type)
   {
     case EP_TYPE_CTRL:
-      if ((token == 1U) && (direction == 0U)) /*send data */
+      if (token == 1U) /* send data */
       {
-        if (length == 0U)
+        if (direction == 0U)
         {
-          /* For Status OUT stage, Length==0, Status Out PID = 1 */
-          hhcd->hc[ch_num].toggle_out = 1U;
-        }
+          if (length == 0U)
+          {
+            /* For Status OUT stage, Length == 0U, Status Out PID = 1 */
+            hhcd->hc[ch_num].toggle_out = 1U;
+          }
 
-        /* Set the Data Toggle bit as per the Flag */
-        if (hhcd->hc[ch_num].toggle_out == 0U)
-        {
-          /* Put the PID 0 */
-          hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+          /* Set the Data Toggle bit as per the Flag */
+          if (hhcd->hc[ch_num].toggle_out == 0U)
+          {
+            /* Put the PID 0 */
+            hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+          }
+          else
+          {
+            /* Put the PID 1 */
+            hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+          }
         }
         else
         {
-          /* Put the PID 1 */
-          hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+          if (hhcd->hc[ch_num].do_ssplit == 1U)
+          {
+            if (hhcd->hc[ch_num].toggle_in == 0U)
+            {
+              hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+            }
+            else
+            {
+              hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
+            }
+          }
         }
       }
       break;
@@ -495,7 +523,8 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
 {
   USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t i, interrupt;
+  uint32_t i;
+  uint32_t interrupt;
 
   /* Ensure that we are in device mode */
   if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
@@ -537,14 +566,22 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
 
       if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U)
       {
+        /* Flush USB Fifo */
+        (void)USB_FlushTxFifo(USBx, 0x10U);
+        (void)USB_FlushRxFifo(USBx);
+
+        if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
+        {
+          /* Restore FS Clock */
+          (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
+        }
+
         /* Handle Host Port Disconnect Interrupt */
 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
         hhcd->DisconnectCallback(hhcd);
 #else
         HAL_HCD_Disconnect_Callback(hhcd);
 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-
-        (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ);
       }
     }
 
@@ -566,16 +603,6 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
     }
 
-    /* Handle Rx Queue Level Interrupts */
-    if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
-    {
-      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
-      HCD_RXQLVL_IRQHandler(hhcd);
-
-      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-    }
-
     /* Handle Host channel Interrupt */
     if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
     {
@@ -596,6 +623,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
       }
       __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
     }
+
+    /* Handle Rx Queue Level Interrupts */
+    if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U)
+    {
+      USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+
+      HCD_RXQLVL_IRQHandler(hhcd);
+
+      USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
+    }
   }
 }
 
@@ -950,7 +987,8 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *
 
 /**
   * @brief  Unregister the USB HCD Host Channel Notify URB Change Callback
-  *         USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
+  *         USB HCD Host Channel Notify URB Change Callback is redirected
+  *         to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback
   * @param  hhcd HCD handle
   * @retval HAL status
   */
@@ -1008,8 +1046,11 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef
 HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
 {
   __HAL_LOCK(hhcd);
-  __HAL_HCD_ENABLE(hhcd);
+  /* Enable port power */
   (void)USB_DriveVbus(hhcd->Instance, 1U);
+
+  /* Enable global interrupt */
+  __HAL_HCD_ENABLE(hhcd);
   __HAL_UNLOCK(hhcd);
 
   return HAL_OK;
@@ -1064,7 +1105,7 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
   * @param  hhcd HCD handle
   * @retval HAL state
   */
-HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
+HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd)
 {
   return hhcd->State;
 }
@@ -1083,7 +1124,7 @@ HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
   *            URB_ERROR/
   *            URB_STALL
   */
-HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
 {
   return hhcd->hc[chnum].urb_state;
 }
@@ -1096,7 +1137,7 @@ HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnu
   *         This parameter can be a value from 1 to 15
   * @retval last transfer size in byte
   */
-uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
 {
   return hhcd->hc[chnum].xfer_count;
 }
@@ -1118,7 +1159,7 @@ uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
   *            HC_BBLERR/
   *            HC_DATATGLERR
   */
-HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
+HCD_HCStateTypeDef  HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum)
 {
   return hhcd->hc[chnum].state;
 }
@@ -1143,6 +1184,54 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
   return (USB_GetHostSpeed(hhcd->Instance));
 }
 
+/**
+  * @brief  Set host channel Hub information.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @param  addr Hub address
+  * @param  PortNbr Hub port number
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                        uint8_t addr, uint8_t PortNbr)
+{
+  uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance);
+
+  /* LS/FS device plugged to HS HUB */
+  if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED))
+  {
+    hhcd->hc[ch_num].do_ssplit = 1U;
+
+    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U))
+    {
+      hhcd->hc[ch_num].toggle_in = 1U;
+    }
+  }
+
+  hhcd->hc[ch_num].hub_addr = addr;
+  hhcd->hc[ch_num].hub_port_nbr = PortNbr;
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Clear host channel hub information.
+  * @param  hhcd HCD handle
+  * @param  ch_num Channel number.
+  *         This parameter can be a value from 1 to 15
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
+{
+  hhcd->hc[ch_num].do_ssplit = 0U;
+  hhcd->hc[ch_num].do_csplit = 0U;
+  hhcd->hc[ch_num].hub_addr = 0U;
+  hhcd->hc[ch_num].hub_port_nbr = 0U;
+
+  return HAL_OK;
+}
 /**
   * @}
   */
@@ -1163,101 +1252,86 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
   */
 static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
-  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t ch_num = (uint32_t)chnum;
-
   uint32_t tmpreg;
 
-  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+  if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
   {
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    hhcd->hc[chnum].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR))
   {
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR);
-    hhcd->hc[ch_num].state = HC_BBLERR;
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR);
+    hhcd->hc[chnum].state = HC_BBLERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
   {
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+    hhcd->hc[chnum].state = HC_STALL;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    hhcd->hc[ch_num].state = HC_STALL;
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    hhcd->hc[ch_num].state = HC_DATATGLERR;
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
-  {
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    hhcd->hc[ch_num].state = HC_XACTERR;
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+    hhcd->hc[chnum].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
   else
   {
     /* ... */
   }
 
-  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
+  if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
   {
+    /* Clear any pending ACK IT */
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
+
+    if (hhcd->hc[chnum].do_csplit == 1U)
+    {
+      hhcd->hc[chnum].do_csplit = 0U;
+      __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+    }
+
     if (hhcd->Init.dma_enable != 0U)
     {
-      hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \
-                                    (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
+      hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
     }
 
-    hhcd->hc[ch_num].state = HC_XFRC;
-    hhcd->hc[ch_num].ErrCnt = 0U;
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
+    hhcd->hc[chnum].state = HC_XFRC;
+    hhcd->hc[chnum].ErrCnt = 0U;
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
 
-    if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
-        (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
+    if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+        (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
     {
-      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-      __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
     }
-    else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
+    else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) ||
+             (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC))
     {
-      USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
-      hhcd->hc[ch_num].urb_state = URB_DONE;
+      USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
+      hhcd->hc[chnum].urb_state = URB_DONE;
 
 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-      hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+      hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
 #else
-      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
-#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
-    }
-    else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)
-    {
-      hhcd->hc[ch_num].urb_state = URB_DONE;
-      hhcd->hc[ch_num].toggle_in ^= 1U;
-
-#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
-      hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
-#else
-      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+      HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
     }
     else
@@ -1267,95 +1341,220 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 
     if (hhcd->Init.dma_enable == 1U)
     {
-      if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U)
+      if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U)
       {
-        hhcd->hc[ch_num].toggle_in ^= 1U;
+        hhcd->hc[chnum].toggle_in ^= 1U;
       }
     }
     else
     {
-      hhcd->hc[ch_num].toggle_in ^= 1U;
+      hhcd->hc[chnum].toggle_in ^= 1U;
     }
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
   {
-    __HAL_HCD_MASK_HALT_HC_INT(ch_num);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
 
-    if (hhcd->hc[ch_num].state == HC_XFRC)
+    if (hhcd->hc[chnum].do_ssplit == 1U)
     {
-      hhcd->hc[ch_num].urb_state = URB_DONE;
+      hhcd->hc[chnum].do_csplit = 1U;
+      hhcd->hc[chnum].state = HC_ACK;
+
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
     }
-    else if (hhcd->hc[ch_num].state == HC_STALL)
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+
+    if (hhcd->hc[chnum].state == HC_XFRC)
     {
-      hhcd->hc[ch_num].urb_state = URB_STALL;
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_DONE;
     }
-    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
-             (hhcd->hc[ch_num].state == HC_DATATGLERR))
+    else if (hhcd->hc[chnum].state == HC_STALL)
     {
-      hhcd->hc[ch_num].ErrCnt++;
-      if (hhcd->hc[ch_num].ErrCnt > 2U)
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_STALL;
+    }
+    else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
+             (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].ErrCnt++;
+      if (hhcd->hc[chnum].ErrCnt > 2U)
       {
-        hhcd->hc[ch_num].ErrCnt = 0U;
-        hhcd->hc[ch_num].urb_state = URB_ERROR;
+        hhcd->hc[chnum].ErrCnt = 0U;
+
+        if (hhcd->hc[chnum].do_ssplit == 1U)
+        {
+          hhcd->hc[chnum].do_csplit = 0U;
+          hhcd->hc[chnum].ep_ss_schedule = 0U;
+          __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+        }
+
+        hhcd->hc[chnum].urb_state = URB_ERROR;
       }
       else
       {
-        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
 
+        if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+            (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+        {
+          /* re-activate the channel */
+          tmpreg = USBx_HC(chnum)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(chnum)->HCCHAR = tmpreg;
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NYET)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+        {
+          hhcd->hc[chnum].NyetErrCnt++;
+          if (hhcd->hc[chnum].NyetErrCnt > 2U)
+          {
+            hhcd->hc[chnum].NyetErrCnt = 0U;
+            hhcd->hc[chnum].do_csplit = 0U;
+
+            if (hhcd->hc[chnum].ErrCnt < 3U)
+            {
+              hhcd->hc[chnum].ep_ss_schedule = 1U;
+            }
+            __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+            hhcd->hc[chnum].urb_state = URB_ERROR;
+          }
+          else
+          {
+            hhcd->hc[chnum].urb_state = URB_NOTREADY;
+          }
+        }
+        else
+        {
+          hhcd->hc[chnum].urb_state = URB_NOTREADY;
+        }
+
+        if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+            (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+        {
+          /* re-activate the channel */
+          tmpreg = USBx_HC(chnum)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(chnum)->HCCHAR = tmpreg;
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_ACK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        /* Set Complete split and re-activate the channel */
+        USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+        USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
+        USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK;
+
+        if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+            (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+        {
+          /* re-activate the channel */
+          tmpreg = USBx_HC(chnum)->HCCHAR;
+          tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+          tmpreg |= USB_OTG_HCCHAR_CHENA;
+          USBx_HC(chnum)->HCCHAR = tmpreg;
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NAK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+      if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+          (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+      {
         /* re-activate the channel */
-        tmpreg = USBx_HC(ch_num)->HCCHAR;
+        tmpreg = USBx_HC(chnum)->HCCHAR;
         tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
         tmpreg |= USB_OTG_HCCHAR_CHENA;
-        USBx_HC(ch_num)->HCCHAR = tmpreg;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
       }
     }
-    else if (hhcd->hc[ch_num].state == HC_NAK)
+    else if (hhcd->hc[chnum].state == HC_BBLERR)
     {
-      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
-
-      /* re-activate the channel */
-      tmpreg = USBx_HC(ch_num)->HCCHAR;
-      tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
-      tmpreg |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(ch_num)->HCCHAR = tmpreg;
-    }
-    else if (hhcd->hc[ch_num].state == HC_BBLERR)
-    {
-      hhcd->hc[ch_num].ErrCnt++;
-      hhcd->hc[ch_num].urb_state = URB_ERROR;
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].ErrCnt++;
+      hhcd->hc[chnum].urb_state = URB_ERROR;
     }
     else
     {
-      /* ... */
-    }
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
-    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
-  {
-    if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)
-    {
-      hhcd->hc[ch_num].ErrCnt = 0U;
-      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    }
-    else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) ||
-             (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
-    {
-      hhcd->hc[ch_num].ErrCnt = 0U;
-
-      if (hhcd->Init.dma_enable == 0U)
+      if (hhcd->hc[chnum].state == HC_HALTED)
       {
-        hhcd->hc[ch_num].state = HC_NAK;
-        __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-        (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+        return;
+      }
+    }
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+    hhcd->hc[chnum].state = HC_NYET;
+
+    if (hhcd->hc[chnum].do_ssplit == 0U)
+    {
+      hhcd->hc[chnum].ErrCnt = 0U;
+    }
+
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
+  {
+    if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+    {
+      hhcd->hc[chnum].ErrCnt = 0U;
+      hhcd->hc[chnum].state = HC_NAK;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+    }
+    else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) ||
+             (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+    {
+      hhcd->hc[chnum].ErrCnt = 0U;
+
+      if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U))
+      {
+        hhcd->hc[chnum].state = HC_NAK;
+        (void)USB_HC_Halt(hhcd->Instance, chnum);
       }
     }
     else
     {
       /* ... */
     }
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+
+    if (hhcd->hc[chnum].do_csplit == 1U)
+    {
+      hhcd->hc[chnum].do_csplit = 0U;
+      __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+      __HAL_HCD_UNMASK_ACK_HC_INT(chnum);
+    }
+
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
   }
   else
   {
@@ -1372,186 +1571,237 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
   */
 static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
 {
-  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t ch_num = (uint32_t)chnum;
   uint32_t tmpreg;
   uint32_t num_packets;
 
-  if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR)
+  if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR))
   {
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR);
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
+    hhcd->hc[chnum].state = HC_XACTERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK))
   {
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_ACK);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
 
-    if (hhcd->hc[ch_num].do_ping == 1U)
+    if (hhcd->hc[chnum].do_ping == 1U)
     {
-      hhcd->hc[ch_num].do_ping = 0U;
-      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
-      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+      hhcd->hc[chnum].do_ping = 0U;
+      hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      hhcd->hc[chnum].state = HC_ACK;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+    }
+
+    if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U))
+    {
+      if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC)
+      {
+        hhcd->hc[chnum].do_csplit = 1U;
+      }
+
+      hhcd->hc[chnum].state = HC_ACK;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
+
+      /* reset error_count */
+      hhcd->hc[chnum].ErrCnt = 0U;
     }
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR))
   {
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC))
   {
-    hhcd->hc[ch_num].ErrCnt = 0U;
+    hhcd->hc[chnum].ErrCnt = 0U;
 
     /* transaction completed with NYET state, update do ping state */
-    if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
+    if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
     {
-      hhcd->hc[ch_num].do_ping = 1U;
-      __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
+      hhcd->hc[chnum].do_ping = 1U;
+      __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
     }
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC);
-    hhcd->hc[ch_num].state = HC_XFRC;
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET)
-  {
-    hhcd->hc[ch_num].state = HC_NYET;
-    hhcd->hc[ch_num].do_ping = 1U;
-    hhcd->hc[ch_num].ErrCnt = 0U;
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET);
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL)
-  {
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL);
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    hhcd->hc[ch_num].state = HC_STALL;
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK)
-  {
-    hhcd->hc[ch_num].ErrCnt = 0U;
-    hhcd->hc[ch_num].state = HC_NAK;
 
-    if (hhcd->hc[ch_num].do_ping == 0U)
+    if (hhcd->hc[chnum].do_csplit != 0U)
     {
-      if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH)
+      hhcd->hc[chnum].do_csplit = 0U;
+      __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+    }
+
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
+    hhcd->hc[chnum].state = HC_XFRC;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET))
+  {
+    hhcd->hc[chnum].state = HC_NYET;
+
+    if (hhcd->hc[chnum].do_ssplit == 0U)
+    {
+      hhcd->hc[chnum].do_ping = 1U;
+    }
+
+    hhcd->hc[chnum].ErrCnt = 0U;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+    hhcd->hc[chnum].state = HC_STALL;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK))
+  {
+    hhcd->hc[chnum].ErrCnt = 0U;
+    hhcd->hc[chnum].state = HC_NAK;
+
+    if (hhcd->hc[chnum].do_ping == 0U)
+    {
+      if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH)
       {
-        hhcd->hc[ch_num].do_ping = 1U;
+        hhcd->hc[chnum].do_ping = 1U;
       }
     }
 
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
   }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR)
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR))
   {
     if (hhcd->Init.dma_enable == 0U)
     {
-      hhcd->hc[ch_num].state = HC_XACTERR;
-      __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-      (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
+      hhcd->hc[chnum].state = HC_XACTERR;
+      (void)USB_HC_Halt(hhcd->Instance, chnum);
     }
     else
     {
-      hhcd->hc[ch_num].ErrCnt++;
-      if (hhcd->hc[ch_num].ErrCnt > 2U)
+      hhcd->hc[chnum].ErrCnt++;
+      if (hhcd->hc[chnum].ErrCnt > 2U)
       {
-        hhcd->hc[ch_num].ErrCnt = 0U;
-        hhcd->hc[ch_num].urb_state = URB_ERROR;
-        HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+        hhcd->hc[chnum].ErrCnt = 0U;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+        hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+        HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
       }
       else
       {
-        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
-      }
-    }
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR);
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR)
-  {
-    __HAL_HCD_UNMASK_HALT_HC_INT(ch_num);
-    (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK);
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR);
-    hhcd->hc[ch_num].state = HC_DATATGLERR;
-  }
-  else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH)
-  {
-    __HAL_HCD_MASK_HALT_HC_INT(ch_num);
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
 
-    if (hhcd->hc[ch_num].state == HC_XFRC)
-    {
-      hhcd->hc[ch_num].urb_state  = URB_DONE;
-      if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
-          (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
-      {
-        if (hhcd->Init.dma_enable == 1U)
-        {
-          if (hhcd->hc[ch_num].xfer_len > 0U)
-          {
-            num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet;
-
-            if ((num_packets & 1U) != 0U)
-            {
-              hhcd->hc[ch_num].toggle_out ^= 1U;
-            }
-          }
-        }
-        else
-        {
-          hhcd->hc[ch_num].toggle_out ^= 1U;
-        }
-      }
-    }
-    else if (hhcd->hc[ch_num].state == HC_NAK)
-    {
-      hhcd->hc[ch_num].urb_state = URB_NOTREADY;
-    }
-    else if (hhcd->hc[ch_num].state == HC_NYET)
-    {
-      hhcd->hc[ch_num].urb_state  = URB_NOTREADY;
-    }
-    else if (hhcd->hc[ch_num].state == HC_STALL)
-    {
-      hhcd->hc[ch_num].urb_state  = URB_STALL;
-    }
-    else if ((hhcd->hc[ch_num].state == HC_XACTERR) ||
-             (hhcd->hc[ch_num].state == HC_DATATGLERR))
-    {
-      hhcd->hc[ch_num].ErrCnt++;
-      if (hhcd->hc[ch_num].ErrCnt > 2U)
-      {
-        hhcd->hc[ch_num].ErrCnt = 0U;
-        hhcd->hc[ch_num].urb_state = URB_ERROR;
-      }
-      else
-      {
-        hhcd->hc[ch_num].urb_state = URB_NOTREADY;
-
-        /* re-activate the channel  */
-        tmpreg = USBx_HC(ch_num)->HCCHAR;
+        /* Re-activate the channel  */
+        tmpreg = USBx_HC(chnum)->HCCHAR;
         tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
         tmpreg |= USB_OTG_HCCHAR_CHENA;
-        USBx_HC(ch_num)->HCCHAR = tmpreg;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
+      }
+    }
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR))
+  {
+    hhcd->hc[chnum].state = HC_DATATGLERR;
+    (void)USB_HC_Halt(hhcd->Instance, chnum);
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+  }
+  else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH))
+  {
+    __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+
+    if (hhcd->hc[chnum].state == HC_XFRC)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_DONE;
+
+      if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) ||
+          (hhcd->hc[chnum].ep_type == EP_TYPE_INTR))
+      {
+        if (hhcd->Init.dma_enable == 0U)
+        {
+          hhcd->hc[chnum].toggle_out ^= 1U;
+        }
+
+        if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U))
+        {
+          num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet;
+
+          if ((num_packets & 1U) != 0U)
+          {
+            hhcd->hc[chnum].toggle_out ^= 1U;
+          }
+        }
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_ACK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NAK)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+      if (hhcd->hc[chnum].do_csplit == 1U)
+      {
+        hhcd->hc[chnum].do_csplit = 0U;
+        __HAL_HCD_CLEAR_HC_CSPLT(chnum);
+      }
+    }
+    else if (hhcd->hc[chnum].state == HC_NYET)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state  = URB_NOTREADY;
+    }
+    else if (hhcd->hc[chnum].state == HC_STALL)
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].urb_state  = URB_STALL;
+    }
+    else if ((hhcd->hc[chnum].state == HC_XACTERR) ||
+             (hhcd->hc[chnum].state == HC_DATATGLERR))
+    {
+      hhcd->hc[chnum].state = HC_HALTED;
+      hhcd->hc[chnum].ErrCnt++;
+      if (hhcd->hc[chnum].ErrCnt > 2U)
+      {
+        hhcd->hc[chnum].ErrCnt = 0U;
+        hhcd->hc[chnum].urb_state = URB_ERROR;
+      }
+      else
+      {
+        hhcd->hc[chnum].urb_state = URB_NOTREADY;
+
+        /* re-activate the channel  */
+        tmpreg = USBx_HC(chnum)->HCCHAR;
+        tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+        tmpreg |= USB_OTG_HCCHAR_CHENA;
+        USBx_HC(chnum)->HCCHAR = tmpreg;
       }
     }
     else
     {
-      /* ... */
+      return;
     }
 
-    __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH);
-    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state);
+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
+    hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#else
+    HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
   }
   else
   {
-    /* ... */
+    return;
   }
 }
 
@@ -1562,17 +1812,17 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
   */
 static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
 {
-  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t pktsts;
   uint32_t pktcnt;
   uint32_t GrxstspReg;
   uint32_t xferSizePktCnt;
   uint32_t tmpreg;
-  uint32_t ch_num;
+  uint32_t chnum;
 
   GrxstspReg = hhcd->Instance->GRXSTSP;
-  ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
+  chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM;
   pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17;
   pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4;
 
@@ -1580,33 +1830,33 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
   {
     case GRXSTS_PKTSTS_IN:
       /* Read the data into the host buffer. */
-      if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0))
+      if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0))
       {
-        if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len)
+        if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len)
         {
           (void)USB_ReadPacket(hhcd->Instance,
-                               hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt);
+                               hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt);
 
           /* manage multiple Xfer */
-          hhcd->hc[ch_num].xfer_buff += pktcnt;
-          hhcd->hc[ch_num].xfer_count += pktcnt;
+          hhcd->hc[chnum].xfer_buff += pktcnt;
+          hhcd->hc[chnum].xfer_count += pktcnt;
 
           /* get transfer size packet count */
-          xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
+          xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19;
 
-          if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U))
+          if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U))
           {
             /* re-activate the channel when more packets are expected */
-            tmpreg = USBx_HC(ch_num)->HCCHAR;
+            tmpreg = USBx_HC(chnum)->HCCHAR;
             tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
             tmpreg |= USB_OTG_HCCHAR_CHENA;
-            USBx_HC(ch_num)->HCCHAR = tmpreg;
-            hhcd->hc[ch_num].toggle_in ^= 1U;
+            USBx_HC(chnum)->HCCHAR = tmpreg;
+            hhcd->hc[chnum].toggle_in ^= 1U;
           }
         }
         else
         {
-          hhcd->hc[ch_num].urb_state = URB_ERROR;
+          hhcd->hc[chnum].urb_state = URB_ERROR;
         }
       }
       break;
@@ -1628,9 +1878,10 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
   */
 static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
 {
-  USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+  const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  __IO uint32_t hprt0, hprt0_dup;
+  __IO uint32_t hprt0;
+  __IO uint32_t hprt0_dup;
 
   /* Handle Host Port Interrupts */
   hprt0 = USBx_HPRT0;
@@ -1650,7 +1901,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
       HAL_HCD_Connect_Callback(hhcd);
 #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */
     }
-    hprt0_dup  |= USB_OTG_HPRT_PCDET;
+    hprt0_dup |= USB_OTG_HPRT_PCDET;
   }
 
   /* Check whether Port Enable Changed */
@@ -1660,7 +1911,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
 
     if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
     {
-      if (hhcd->Init.phy_itface  == USB_OTG_EMBEDDED_PHY)
+      if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
       {
         if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
         {
@@ -1675,7 +1926,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
       {
         if (hhcd->Init.speed == HCD_SPEED_FULL)
         {
-          USBx_HOST->HFIR = 60000U;
+          USBx_HOST->HFIR = HFIR_60_MHZ;
         }
       }
 #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)
@@ -1723,5 +1974,3 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h
index 82862629ce..b19622bd6d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -111,11 +110,16 @@ typedef struct
 #define HCD_SPEED_HIGH               USBH_HS_SPEED
 #define HCD_SPEED_FULL               USBH_FSLS_SPEED
 #define HCD_SPEED_LOW                USBH_FSLS_SPEED
+/**
+  * @}
+  */
 
+/** @defgroup HCD_Device_Speed HCD Device Speed
+  * @{
+  */
 #define HCD_DEVICE_SPEED_HIGH               0U
 #define HCD_DEVICE_SPEED_FULL               1U
 #define HCD_DEVICE_SPEED_LOW                2U
-
 /**
   * @}
   */
@@ -153,7 +157,12 @@ typedef struct
 #define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
 #define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
 
-#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance)\
+                                                             & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \
+  ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__))
+
 #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
 #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
 
@@ -162,6 +171,9 @@ typedef struct
 #define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
 #define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
 #define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_SET_HC_CSPLT(chnum)                 (USBx_HC(chnum)->HCSPLT   |= USB_OTG_HCSPLT_COMPLSPLT)
+#define __HAL_HCD_CLEAR_HC_CSPLT(chnum)               (USBx_HC(chnum)->HCSPLT   &= ~USB_OTG_HCSPLT_COMPLSPLT)
+#define __HAL_HCD_CLEAR_HC_SSPLT(chnum)               (USBx_HC(chnum)->HCSPLT   &= ~USB_OTG_HCSPLT_SPLITEN)
 /**
   * @}
   */
@@ -243,6 +255,11 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n
                                            uint8_t token, uint8_t *pbuff,
                                            uint16_t length, uint8_t do_ping);
 
+HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num,
+                                        uint8_t addr, uint8_t PortNbr);
+
+HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
+
 /* Non-Blocking mode: Interrupt */
 void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
 void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
@@ -271,16 +288,13 @@ HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
 /** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
-HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
-HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd);
+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum);
 uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
 uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 
-/**
-  * @}
-  */
 
 /**
   * @}
@@ -296,11 +310,14 @@ uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 /* Private functions prototypes ----------------------------------------------*/
 
 /**
- * @}
- */
+  * @}
+  */
 /**
- * @}
- */
+  * @}
+  */
+/**
+  * @}
+  */
 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 #ifdef __cplusplus
@@ -308,5 +325,3 @@ uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
 #endif
 
 #endif /* STM32H7xx_HAL_HCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c
index 582ebbd405..2e11610e89 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c
@@ -49,6 +49,18 @@
   *           + Waveform Timer Burst Status Get
   *           + Waveform Timer Push-Pull Status Get
   *           + Peripheral State Get
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
 ==============================================================================
                       ##### Simple mode v.s. waveform mode #####
@@ -70,6 +82,8 @@
        operates in waveform mode, all the HRTIM features are accessible without
        any restriction. HRTIM waveform modes are managed through the set of
        functions named HAL_HRTIM_Waveform<Function>
+
+==============================================================================
                       ##### How to use this driver #####
 ==============================================================================
     [..]
@@ -339,18 +353,6 @@
      callbacks are set to the corresponding weak functions.
 
   @endverbatim
-
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
   ******************************************************************************
   */
 
@@ -422,18 +424,18 @@ static uint32_t TimerIdxToTimerId[] =
   * @{
   */
 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
-                                    HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+                                    const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
 
 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
                                         uint32_t TimerIdx,
-                                        HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+                                        const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
 
 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
-                                        HRTIM_TimerCfgTypeDef * pTimerCfg);
+                                        const HRTIM_TimerCfgTypeDef * pTimerCfg);
 
 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
                                             uint32_t TimerIdx,
-                                            HRTIM_TimerCfgTypeDef * pTimerCfg);
+                                            const HRTIM_TimerCfgTypeDef * pTimerCfg);
 
 
 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
@@ -444,29 +446,29 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
                                 uint32_t TimerIdx,
                                 uint32_t Output,
-                                HRTIM_OutputCfgTypeDef * pOutputCfg);
+                                const HRTIM_OutputCfgTypeDef * pOutputCfg);
 
 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
                               uint32_t Event,
-                              HRTIM_EventCfgTypeDef * pEventCfg);
+                              const HRTIM_EventCfgTypeDef * pEventCfg);
 
 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
                                   uint32_t TimerIdx,
                                   uint32_t Event);
 
-static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
                                       uint32_t TimerIdx,
                                       uint32_t OCChannel);
 
-static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
                                        uint32_t TimerIdx,
                                        uint32_t OCChannel);
 
-static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
+static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
                                                           uint32_t TimerIdx);
 
-static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
-                                         DMA_HandleTypeDef * hdma);
+static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
+                                         const DMA_HandleTypeDef * hdma);
 
 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
                                       uint32_t TimerIdx);
@@ -741,7 +743,7 @@ __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
   */
 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
                                            uint32_t TimerIdx,
-                                           HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+                                           const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
 {
   /* Check the parameters */
   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
@@ -1203,7 +1205,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
                                                  uint32_t TimerIdx,
                                                  uint32_t OCChannel,
-                                                 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
+                                                 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
 {
   uint32_t CompareUnit = (uint32_t)RESET;
   HRTIM_OutputCfgTypeDef OutputCfg;
@@ -1618,13 +1620,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
   /* Check the parameters */
   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
 
-  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
   {
      return HAL_BUSY;
   }
-  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  if(hhrtim->State == HAL_HRTIM_STATE_READY)
   {
-    if ((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
+    if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -1823,7 +1825,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
                                                   uint32_t TimerIdx,
                                                   uint32_t PWMChannel,
-                                                  HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
+                                                  const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
 {
   HRTIM_OutputCfgTypeDef OutputCfg;
   uint32_t hrtim_timcr;
@@ -2235,13 +2237,13 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
   /* Check the parameters */
   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
 
-  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
   {
      return HAL_BUSY;
   }
-  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  if(hhrtim->State == HAL_HRTIM_STATE_READY)
   {
-    if ((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
+    if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -2489,7 +2491,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
                                                       uint32_t TimerIdx,
                                                       uint32_t CaptureChannel,
-                                                      HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
+                                                      const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
 {
   HRTIM_EventCfgTypeDef EventCfg;
 
@@ -3144,7 +3146,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
                                                        uint32_t TimerIdx,
                                                        uint32_t OnePulseChannel,
-                                                       HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
+                                                       const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
 {
   HRTIM_OutputCfgTypeDef OutputCfg;
   HRTIM_EventCfgTypeDef EventCfg;
@@ -3566,7 +3568,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
   *       controller
   */
 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
-                                            HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
+                                            const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
 {
   uint32_t hrtim_bmcr;
 
@@ -3647,7 +3649,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
   */
 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
                                         uint32_t Event,
-                                        HRTIM_EventCfgTypeDef* pEventCfg)
+                                        const HRTIM_EventCfgTypeDef* pEventCfg)
 {
   /* Check parameters */
   assert_param(IS_HRTIM_EVENT(Event));
@@ -3734,7 +3736,7 @@ HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
   */
 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
                                         uint32_t Fault,
-                                        HRTIM_FaultCfgTypeDef* pFaultCfg)
+                                        const HRTIM_FaultCfgTypeDef* pFaultCfg)
 {
   uint32_t hrtim_fltinr1;
   uint32_t hrtim_fltinr2;
@@ -3946,7 +3948,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
   */
 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
                                              uint32_t ADCTrigger,
-                                             HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
+                                             const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
 {
   uint32_t hrtim_cr1;
 
@@ -4098,7 +4100,7 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
   */
 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
                                                 uint32_t TimerIdx,
-                                                HRTIM_TimerCfgTypeDef * pTimerCfg)
+                                                const HRTIM_TimerCfgTypeDef * pTimerCfg)
 {
   /* Check parameters */
   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
@@ -4200,7 +4202,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
                                                       uint32_t TimerIdx,
                                                       uint32_t Event,
-                                                      HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
+                                                      const HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
 {
   /* Check parameters */
   assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
@@ -4329,7 +4331,7 @@ HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrt
   */
 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
                                            uint32_t TimerIdx,
-                                           HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
+                                           const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
 {
   uint32_t hrtim_dtr;
 
@@ -4394,7 +4396,7 @@ HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
   */
 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
                                               uint32_t TimerIdx,
-                                              HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
+                                              const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
 {
   uint32_t hrtim_chpr;
 
@@ -4420,9 +4422,9 @@ HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
   hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
 
   /* Update the HRTIM registers */
-  MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ |                                                           HRTIM_CHPR_CARDTY |
-                                                             HRTIM_CHPR_STRPW) ,
-                                                             hrtim_chpr);
+  MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
+             (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
+             hrtim_chpr);
 
   hhrtim->State = HAL_HRTIM_STATE_READY;
 
@@ -4579,7 +4581,7 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
                                                   uint32_t TimerIdx,
                                                   uint32_t CompareUnit,
-                                                  HRTIM_CompareCfgTypeDef* pCompareCfg)
+                                                  const HRTIM_CompareCfgTypeDef* pCompareCfg)
 {
   /* Check parameters */
   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
@@ -4780,7 +4782,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
                                                   uint32_t TimerIdx,
                                                   uint32_t CaptureUnit,
-                                                  HRTIM_CaptureCfgTypeDef* pCaptureCfg)
+                                                  const HRTIM_CaptureCfgTypeDef* pCaptureCfg)
 {
   /* Check parameters */
   assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
@@ -4866,7 +4868,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
                                                 uint32_t TimerIdx,
                                                 uint32_t Output,
-                                                HRTIM_OutputCfgTypeDef * pOutputCfg)
+                                                const HRTIM_OutputCfgTypeDef * pOutputCfg)
 {
   /* Check parameters */
   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
@@ -5329,7 +5331,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
   /* Check the parameters */
   assert_param(IS_HRTIM_TIMERID(Timers));
 
-  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
   {
      return HAL_BUSY;
   }
@@ -5764,13 +5766,13 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
   /* Check the parameters */
   assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
 
-  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
   {
      return HAL_BUSY;
   }
-  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  if(hhrtim->State == HAL_HRTIM_STATE_READY)
   {
-    if ((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
+    if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
     {
       return HAL_ERROR;
     }
@@ -5926,7 +5928,7 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
   * @param  hhrtim pointer to HAL HRTIM handle
   * @retval HAL state
   */
-HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim)
 {
   /* Return HRTIM state */
   return hhrtim->State;
@@ -5948,7 +5950,7 @@ HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
   *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
   * @retval Captured value
   */
-uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
                                     uint32_t TimerIdx,
                                     uint32_t CaptureUnit)
 {
@@ -5976,11 +5978,6 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
   default:
    {
        captured_value = 0xFFFFFFFFUL;
-
-       hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhrtim);
       break;
     }
 
@@ -6016,11 +6013,11 @@ uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
   * @note Returned output level is taken before the output stage (chopper,
   *        polarity).
   */
-uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef * hhrtim,
                                           uint32_t TimerIdx,
                                           uint32_t Output)
 {
-  uint32_t output_level = (uint32_t)RESET;
+  uint32_t output_level;
 
   /* Check parameters */
   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
@@ -6064,20 +6061,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
 
   default:
     {
-      hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhrtim);
-
+      output_level = 0xFFFFFFFFUL;
       break;
     }
   }
 
-  if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
-  {
-     return (uint32_t)HAL_ERROR;
-  }
-
   return output_level;
 }
 
@@ -6105,16 +6093,19 @@ uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
   * @retval Output state
   */
-uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
                                           uint32_t TimerIdx,
                                           uint32_t Output)
 {
-  uint32_t output_bit = (uint32_t)RESET;
+  uint32_t output_bit;
   uint32_t output_state;
 
   /* Check parameters */
   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(TimerIdx);
+
   /* Set output state according to output control status and output disable status */
   switch (Output)
   {
@@ -6180,20 +6171,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
 
   default:
     {
-      hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhrtim);
-
+      output_bit = 0UL;
       break;
     }
   }
 
-  if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
-  {
-     return (uint32_t)HAL_ERROR;
-  }
-
   if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
   {
     /* Output is enabled: output in RUN state (whatever output disable status is)*/
@@ -6241,11 +6223,11 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
   * @retval Delayed protection status
   */
-uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef * hhrtim,
                                               uint32_t TimerIdx,
                                               uint32_t Output)
 {
-  uint32_t delayed_protection_status = (uint32_t)RESET;
+  uint32_t delayed_protection_status;
 
   /* Check parameters */
   assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
@@ -6293,20 +6275,11 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
 
   default:
     {
-      hhrtim->State = HAL_HRTIM_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hhrtim);
-
+      delayed_protection_status = 0xFFFFFFFFUL;
       break;
     }
   }
 
-  if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
-  {
-     return (uint32_t)HAL_ERROR;
-  }
-
   return delayed_protection_status;
 }
 
@@ -6315,7 +6288,7 @@ uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
   * @param  hhrtim pointer to HAL HRTIM handle
   * @retval Burst mode controller status
   */
-uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
+uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef * hhrtim)
 {
   uint32_t burst_mode_status;
 
@@ -6338,7 +6311,7 @@ uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
   * @retval Burst mode controller status
   */
-uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
                                             uint32_t TimerIdx)
 {
   uint32_t current_pushpull_status;
@@ -6366,7 +6339,7 @@ uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
   *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
   * @retval Idle Push Pull Status
   */
-uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef * hhrtim,
                                          uint32_t TimerIdx)
 {
   uint32_t idle_pushpull_status;
@@ -7496,7 +7469,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
   * @retval None
   */
 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
-                                     HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+                                    const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
 {
   uint32_t hrtim_mcr;
 
@@ -7525,8 +7498,8 @@ static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
   * @retval None
   */
 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
-                                         uint32_t TimerIdx ,
-                                         HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
+                                        uint32_t TimerIdx ,
+                                        const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
 {
   uint32_t hrtim_timcr;
 
@@ -7554,7 +7527,7 @@ static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
   * @retval None
   */
 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
-                                         HRTIM_TimerCfgTypeDef * pTimerCfg)
+                                        const HRTIM_TimerCfgTypeDef * pTimerCfg)
 {
   uint32_t hrtim_mcr;
   uint32_t hrtim_bmcr;
@@ -7609,7 +7582,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
   */
 static void  HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
                                              uint32_t TimerIdx,
-                                             HRTIM_TimerCfgTypeDef * pTimerCfg)
+                                             const HRTIM_TimerCfgTypeDef * pTimerCfg)
 {
   uint32_t hrtim_timcr;
   uint32_t hrtim_timfltr;
@@ -7861,7 +7834,7 @@ static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
 static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
                                 uint32_t TimerIdx,
                                 uint32_t Output,
-                                HRTIM_OutputCfgTypeDef * pOutputCfg)
+                                const HRTIM_OutputCfgTypeDef * pOutputCfg)
 {
   uint32_t hrtim_outr;
   uint32_t hrtim_dtr;
@@ -7951,7 +7924,7 @@ static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
   */
 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
                               uint32_t Event,
-                              HRTIM_EventCfgTypeDef *pEventCfg)
+                              const HRTIM_EventCfgTypeDef *pEventCfg)
 {
   uint32_t hrtim_eecr1;
   uint32_t hrtim_eecr2;
@@ -8215,7 +8188,7 @@ static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
   * @retval Interrupt to enable or disable
   */
-static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
                                       uint32_t TimerIdx,
                                       uint32_t OCChannel)
 {
@@ -8321,7 +8294,7 @@ static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
   *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
   * @retval DMA request to enable or disable
   */
-static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
+static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef * hhrtim,
                                        uint32_t TimerIdx,
                                        uint32_t OCChannel)
 {
@@ -8408,7 +8381,7 @@ static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
   return dma_request;
 }
 
-static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
+static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef * hhrtim,
                                                           uint32_t TimerIdx)
 {
   DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
@@ -8458,8 +8431,8 @@ static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef *
   return hdma;
 }
 
-static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
-                                         DMA_HandleTypeDef * hdma)
+static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef * hhrtim,
+                                         const DMA_HandleTypeDef * hdma)
 {
   uint32_t timed_idx = 0xFFFFFFFFU;
 
@@ -9290,5 +9263,3 @@ static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h
index 798ad823aa..7b709f3e7b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -996,7 +995,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
   * @{
   * @brief Constants defining the events that can be selected to configure the
-  *        set crossbar of a timer output
+  *        reset crossbar of a timer output
   */
 #define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */
 #define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
@@ -1010,15 +1009,15 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */
 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */
 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_RST1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_RST1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_RST1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_RST1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_RST1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_RST1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_RST1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_RST1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_RST1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
 #define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */
 #define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */
 #define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */
@@ -1137,21 +1136,21 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
   *        by a timer
   */
 #define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 1U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 2U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from counter reset/roll-over to Compare 3U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 4U */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR1 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR2 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR3 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                                                                           /*!< Blanking from another timing unit: TIMFLTR4 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR5 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR6 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR7 source */
-#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR8 source */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Windowing from counter reset/roll-over to Compare 2U */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                           /*!< Windowing from counter reset/roll-over to Compare 3U */
-#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                          /*!< Blanking from counter reset/roll-over to Compare 1U  */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                          /*!< Blanking from counter reset/roll-over to Compare 2U  */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                  /*!< Blanking from counter reset/roll-over to Compare 3U  */
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                          /*!< Blanking from counter reset/roll-over to Compare 4U  */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                  /*!< Blanking from another timing unit: TIMFLTR1 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                  /*!< Blanking from another timing unit: TIMFLTR2 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                          /*!< Blanking from another timing unit: TIMFLTR3 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                          /*!< Blanking from another timing unit: TIMFLTR4 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                  /*!< Blanking from another timing unit: TIMFLTR5 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                  /*!< Blanking from another timing unit: TIMFLTR6 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                          /*!< Blanking from another timing unit: TIMFLTR7 source   */
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                  /*!< Blanking from another timing unit: TIMFLTR8 source   */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                          /*!< Windowing from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                          /*!< Windowing from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source    */
 /**
   * @}
   */
@@ -1173,9 +1172,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
   * @brief Constants defining division ratio between the timer clock frequency
   *        (fHRTIM) and the dead-time generator clock (fDTG)
   */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    (0x00000000U)                                                   /*!< fDTG = fHRTIM * 8U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4U */
-#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2U */
 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */
 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */
@@ -1346,10 +1342,10 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
   * @brief Constants defining the source and event to be sent on the
   *        synchronization outputs
   */
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
 /**
   * @}
   */
@@ -2420,10 +2416,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
                ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
 
 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
-                (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
-                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
-                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
-                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
+                (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
                  ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
@@ -3203,7 +3196,7 @@ void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
 
 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
                                            uint32_t TimerIdx,
-                                           HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
+                                           const HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
 /**
   * @}
   */
@@ -3245,7 +3238,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
                                                  uint32_t TimerIdx,
                                                  uint32_t OCChannel,
-                                                 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
+                                                 const HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
                                          uint32_t TimerIdx,
@@ -3285,7 +3278,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
                                                   uint32_t TimerIdx,
                                                   uint32_t PWMChannel,
-                                                  HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
+                                                  const HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
                                           uint32_t TimerIdx,
@@ -3325,7 +3318,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
                                                       uint32_t TimerIdx,
                                                       uint32_t CaptureChannel,
-                                                      HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
+                                                      const HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
                                               uint32_t TimerIdx,
@@ -3365,7 +3358,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
                                                        uint32_t TimerIdx,
                                                        uint32_t OnePulseChannel,
-                                                       HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
+                                                       const HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
                                                uint32_t TimerIdx,
@@ -3391,18 +3384,18 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
 * @{
 */
 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
-                                            HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
+                                            const HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
                                         uint32_t Event,
-                                        HRTIM_EventCfgTypeDef* pEventCfg);
+                                        const HRTIM_EventCfgTypeDef* pEventCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
                                                  uint32_t Prescaler);
 
 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
                                         uint32_t Fault,
-                                        HRTIM_FaultCfgTypeDef* pFaultCfg);
+                                        const HRTIM_FaultCfgTypeDef* pFaultCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
                                                  uint32_t Prescaler);
@@ -3413,7 +3406,7 @@ void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
 
 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
                                              uint32_t ADCTrigger,
-                                             HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
+                                             const HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
 
 /**
   * @}
@@ -3425,22 +3418,22 @@ HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
 /* Waveform related functions *************************************************/
 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
                                                 uint32_t TimerIdx,
-                                                HRTIM_TimerCfgTypeDef * pTimerCfg);
+                                                const HRTIM_TimerCfgTypeDef * pTimerCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
                                                   uint32_t TimerIdx,
                                                   uint32_t CompareUnit,
-                                                  HRTIM_CompareCfgTypeDef* pCompareCfg);
+                                                  const HRTIM_CompareCfgTypeDef* pCompareCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
                                                   uint32_t TimerIdx,
                                                   uint32_t CaptureUnit,
-                                                  HRTIM_CaptureCfgTypeDef* pCaptureCfg);
+                                                  const HRTIM_CaptureCfgTypeDef* pCaptureCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
                                                  uint32_t TimerIdx,
                                                  uint32_t Output,
-                                                 HRTIM_OutputCfgTypeDef * pOutputCfg);
+                                                 const HRTIM_OutputCfgTypeDef * pOutputCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
                                                    uint32_t TimerIdx,
@@ -3450,15 +3443,15 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
                                                       uint32_t TimerIdx,
                                                       uint32_t Event,
-                                                      HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
+                                                      const HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
                                            uint32_t TimerIdx,
-                                           HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
+                                           const HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
                                               uint32_t TimerIdx,
-                                              HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
+                                              const HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
 
 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
                                            uint32_t TimerIdx,
@@ -3523,30 +3516,30 @@ HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
 * @{
 */
 /* HRTIM peripheral state functions */
-HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef* hhrtim);
 
-uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef * hhrtim,
                                     uint32_t TimerIdx,
                                     uint32_t CaptureUnit);
 
-uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
                                           uint32_t TimerIdx,
                                           uint32_t Output);
 
-uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
+uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef * hhrtim,
                                           uint32_t TimerIdx,
                                           uint32_t Output);
 
-uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
                                               uint32_t TimerIdx,
                                               uint32_t Output);
 
-uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
+uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim);
 
-uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
                                             uint32_t TimerIdx);
 
-uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
                                          uint32_t TimerIdx);
 
 /**
@@ -3642,5 +3635,3 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *       h
 #endif
 
 #endif /* STM32H7xx_HAL_HRTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.c
index 78ae43b97a..1d17bacb86 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.c
@@ -14,6 +14,17 @@
   *           + IRQ handler management
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -71,17 +82,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
     /*take success when MasterID match and take bit set*/
     return HAL_OK;
   }
-#else
+#else  
   /* Read the RLR register to take the semaphore */
   if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
   {
@@ -445,5 +445,3 @@ __weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.h
index df57b77305..45f6e07d97 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hsem.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -130,12 +129,12 @@ extern "C" {
 HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
 /* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
 HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
-/* HSEM Check semaphore state Taken or not   **********************************/
-uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
 /* HSEM Release  **************************************************************/
 void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
 /* HSEM Release All************************************************************/
 void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
+/* HSEM Check semaphore state Taken or not   **********************************/
+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
 
 /**
   * @}
@@ -210,5 +209,3 @@ void HAL_HSEM_IRQHandler(void);
 #endif
 
 #endif /* STM32H7xx_HAL_HSEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c
index 09b3e2a156..74bd220127 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c
@@ -9,6 +9,17 @@
   *           + IO operation functions
   *           + Peripheral State and Errors functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -19,7 +30,7 @@
     (#) Declare a I2C_HandleTypeDef handle structure, for example:
         I2C_HandleTypeDef  hi2c;
 
-    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
+    (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
         (##) Enable the I2Cx interface clock
         (##) I2C pins configuration
             (+++) Enable the clock for the I2C GPIOs
@@ -28,7 +39,8 @@
             (+++) Configure the I2Cx interrupt priority
             (+++) Enable the NVIC I2C IRQ Channel
         (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream or channel depends on Instance
+            (+++) Declare a DMA_HandleTypeDef handle structure for
+                  the transmit or receive stream or channel depends on Instance
             (+++) Enable the DMAx interface clock using
             (+++) Configure the DMA handle parameters
             (+++) Configure the DMA Tx or Rx stream or channel depends on Instance
@@ -39,49 +51,49 @@
     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
 
-    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
-        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
+    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
+        (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
 
-    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
+    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
 
     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
 
     *** Polling mode IO operation ***
     =================================
     [..]
-      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
+      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
+      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
+      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
+      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
 
     *** Polling mode IO MEM operation ***
     =====================================
     [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
+      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
+      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
 
 
     *** Interrupt mode IO operation ***
     ===================================
     [..]
-      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
-      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
-      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
-      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
-      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+      (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
            This action will inform Master to generate a Stop condition to discard the communication.
 
 
@@ -92,120 +104,135 @@
           when a direction change during transfer
     [..]
       (+) A specific option field manage the different steps of a sequential transfer
-      (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
-      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
+      (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
+      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in
+           no sequential mode
       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
                             and data to transfer without a final stop condition
-      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
-                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface
-                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
-                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
+      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with
+                            start condition, address and data to transfer without a final stop condition,
+                            an then permit a call the same master sequential interface several times
+                            (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT()
+                            or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA())
       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
                             if no direction change and without a final stop condition in both cases
       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
-                            and with new data to transfer if the direction change or manage only the new data to transfer
+                            and with new data to transfer if the direction change or manage only the new data to
+                            transfer
                             if no direction change and with a final stop condition in both cases
-      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
-                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
-                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
-                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
-                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
+      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition
+                            after several call of the same master sequential interface several times
+                            (link with option I2C_FIRST_AND_NEXT_FRAME).
+                            Usage can, transfer several bytes one by one using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME.
+                             Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or
+                              Receive sequence permit to call the opposite interface Receive or Transmit
                               without stopping the communication and so generate a restart condition.
-      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
+      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after
+                            each call of the same master sequential
                             interface.
-                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
-                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
-                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
-                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
+                            Usage can, transfer several bytes one by one with a restart with slave address between
+                            each bytes using
+                              HAL_I2C_Master_Seq_Transmit_IT
+                              or HAL_I2C_Master_Seq_Receive_IT
+                              or HAL_I2C_Master_Seq_Transmit_DMA
+                              or HAL_I2C_Master_Seq_Receive_DMA
+                              with option I2C_FIRST_FRAME then I2C_OTHER_FRAME.
+                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic
+                            generation of STOP condition.
 
       (+) Different sequential I2C interfaces are listed below:
-      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
-            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
-      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
-      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
-            or using @ref HAL_I2C_Master_Seq_Receive_DMA()
-      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
-      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
-      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
-      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
-      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
-           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
-      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
-      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
-            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
-      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
-      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
-            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
-      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
-      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-      (++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
+      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
+      (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
+            HAL_I2C_DisableListen_IT()
+      (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can
+           add their own code to check the Address Match Code and the transmission direction request by master
+           (Write/Read).
+      (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can
+          add their own code by customization of function pointer HAL_I2C_ListenCpltCallback()
+      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA()
+      (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and
+            users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
+      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using
+            HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA()
+      (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
            This action will inform Master to generate a Stop condition to discard the communication.
 
     *** Interrupt mode IO MEM operation ***
     =======================================
     [..]
       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
-          @ref HAL_I2C_Mem_Write_IT()
-      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+          HAL_I2C_Mem_Write_IT()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
-          @ref HAL_I2C_Mem_Read_IT()
-      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+          HAL_I2C_Mem_Read_IT()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
 
     *** DMA mode IO operation ***
     ==============================
     [..]
       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
+          HAL_I2C_Master_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
+          HAL_I2C_Master_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
+          HAL_I2C_Slave_Transmit_DMA()
+      (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
-          @ref HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
-      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
-      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
-      (+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
+          HAL_I2C_Slave_Receive_DMA()
+      (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
+      (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
+      (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
+      (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
            This action will inform Master to generate a Stop condition to discard the communication.
 
     *** DMA mode IO MEM operation ***
     =================================
     [..]
       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
-          @ref HAL_I2C_Mem_Write_DMA()
-      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
+          HAL_I2C_Mem_Write_DMA()
+      (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
-          @ref HAL_I2C_Mem_Read_DMA()
-      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
-      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
+          HAL_I2C_Mem_Read_DMA()
+      (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
+      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_I2C_ErrorCallback()
 
 
      *** I2C HAL driver macros list ***
@@ -213,23 +240,23 @@
      [..]
        Below the list of most used macros in I2C HAL driver.
 
-      (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
-      (+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
-      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
-      (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
+      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
+      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
+      (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
+      (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
+      (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
+      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
+      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
 
      *** Callback registration ***
      =============================================
     [..]
      The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
+     Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback()
      to register an interrupt callback.
     [..]
-     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
+     Function HAL_I2C_RegisterCallback() allows to register following callbacks:
        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
@@ -244,11 +271,11 @@
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.
     [..]
-     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
+     For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback().
     [..]
-     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
+     Use function HAL_I2C_UnRegisterCallback to reset a callback to the default
      weak function.
-     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
      and the Callback ID.
      This function allows to reset following callbacks:
        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
@@ -263,24 +290,24 @@
        (+) MspInitCallback      : callback for Msp Init.
        (+) MspDeInitCallback    : callback for Msp DeInit.
     [..]
-     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
+     For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback().
     [..]
-     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET
      all callbacks are set to the corresponding weak functions:
-     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
+     examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback().
      Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
+     reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when
      these callbacks are null (not registered beforehand).
-     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
+     If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]
-     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
      Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
      Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
-     or @ref HAL_I2C_Init() function.
+     using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit()
+     or HAL_I2C_Init() function.
     [..]
      When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
@@ -290,18 +317,6 @@
        (@) You can refer to the I2C HAL driver header file for more useful macros
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -336,28 +351,48 @@
 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
 
 #define MAX_NBYTE_SIZE      255U
-#define SlaveAddr_SHIFT     7U
-#define SlaveAddr_MSK       0x06U
+#define SLAVE_ADDR_SHIFT     7U
+#define SLAVE_ADDR_MSK       0x06U
 
 /* Private define for @ref PreviousState usage */
-#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */
-#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
-#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
-#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
-#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \
+                                                         (uint32_t)HAL_I2C_STATE_BUSY_RX) & \
+                                              (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY))))
+/*!< Mask State define, keep only RX and TX bits */
+#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))
+/*!< Default Value */
+#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MASTER))
+/*!< Master Busy RX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_SLAVE))
+/*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
+#define I2C_STATE_MEM_BUSY_TX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy TX, combinaison of State LSB and Mode enum */
+#define I2C_STATE_MEM_BUSY_RX     ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \
+                                              (uint32_t)HAL_I2C_MODE_MEM))
+/*!< Memory Busy RX, combinaison of State LSB and Mode enum */
 
 
 /* Private define to centralize the enable/disable of Interrupts */
-#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */
-#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */
+#define I2C_XFER_TX_IT          (uint16_t)(0x0001U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_RX_IT          (uint16_t)(0x0002U)   /*!< Bit field can be combinated with
+                                                         @ref I2C_XFER_LISTEN_IT */
+#define I2C_XFER_LISTEN_IT      (uint16_t)(0x8000U)   /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT
+                                                         and @ref I2C_XFER_RX_IT */
 
-#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /* Bit definition to manage addition of global Error and NACK treatment */
-#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /* Bit definition to manage only STOP evenement */
-#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /* Bit definition to manage only Reload of NBYTE */
+#define I2C_XFER_ERROR_IT       (uint16_t)(0x0010U)   /*!< Bit definition to manage addition of global Error
+                                                         and NACK treatment */
+#define I2C_XFER_CPLT_IT        (uint16_t)(0x0020U)   /*!< Bit definition to manage only STOP evenement */
+#define I2C_XFER_RELOAD_IT      (uint16_t)(0x0040U)   /*!< Bit definition to manage only Reload of NBYTE */
 
 /* Private define Sequential Transfer Options default/reset value */
 #define I2C_NO_OPTION_FRAME     (0xFFFF0000U)
@@ -365,7 +400,16 @@
   * @}
   */
 
-/* Private macro -------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup I2C_Private_Macro
+  * @{
+  */
+/* Macro to get remaining data to transfer on DMA side */
+#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__)     __HAL_DMA_GET_COUNTER(__HANDLE__)
+/**
+  * @}
+  */
+
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 
@@ -380,6 +424,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
 
+
 /* Private functions to handle IT transfer */
 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
 static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
@@ -390,24 +435,38 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
 
 /* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                                uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                               uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart);
 
 /* Private functions for I2C transfer IRQ handler */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                        uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                         uint32_t ITSources);
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources);
 
 /* Private functions to handle flags during polling transfer */
 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
                                                     uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                             uint32_t Tickstart);
 
 /* Private functions to centralize the enable/disable of Interrupts */
 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
@@ -549,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
   /* Configure I2Cx: Addressing Master mode */
   if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
   {
-    hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+    SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
+  }
+  else
+  {
+    /* Clear the I2C ADD10 bit */
+    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
   }
   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
@@ -559,7 +623,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
   hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
 
   /* Configure I2Cx: Dual mode and Own Address2 */
-  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
+  hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
+                          (hi2c->Init.OwnAddress2Masks << 8));
 
   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
   /* Configure I2Cx: Generalcall and NoStretch mode */
@@ -658,6 +723,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
 /**
   * @brief  Register a User I2C Callback
   *         To be used instead of the weak predefined callback
+  * @note   The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+  *         to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  CallbackID ID of the callback to be registered
@@ -688,8 +755,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hi2c);
 
   if (HAL_I2C_STATE_READY == hi2c->State)
   {
@@ -778,14 +843,14 @@ HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
   return status;
 }
 
 /**
   * @brief  Unregister an I2C Callback
   *         I2C callback is redirected to the weak predefined callback
+  * @note   The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET
+  *         to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  CallbackID ID of the callback to be unregistered
@@ -808,9 +873,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
   if (HAL_I2C_STATE_READY == hi2c->State)
   {
     switch (CallbackID)
@@ -898,8 +960,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
   return status;
 }
 
@@ -922,8 +982,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hi2c);
 
   if (HAL_I2C_STATE_READY == hi2c->State)
   {
@@ -938,8 +996,6 @@ HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_Add
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
   return status;
 }
 
@@ -954,9 +1010,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hi2c);
-
   if (HAL_I2C_STATE_READY == hi2c->State)
   {
     hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */
@@ -970,8 +1023,6 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
   return status;
 }
 
@@ -1065,10 +1116,11 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
-                                          uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout)
 {
   uint32_t tickstart;
+  uint32_t xfermode;
 
   if (hi2c->State == HAL_I2C_STATE_READY)
   {
@@ -1092,17 +1144,40 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
     hi2c->XferCount = Size;
     hi2c->XferISR   = NULL;
 
-    /* Send Slave Address */
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
     if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+      xfermode = I2C_RELOAD_MODE;
     }
     else
     {
       hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+      xfermode = I2C_AUTOEND_MODE;
+    }
+
+    if (hi2c->XferSize > 0U)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      /* Send Slave Address */
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+                         I2C_GENERATE_START_WRITE);
     }
 
     while (hi2c->XferCount > 0U)
@@ -1132,12 +1207,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
         if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
         }
         else
         {
           hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
         }
       }
     }
@@ -1180,8 +1257,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout)
 {
   uint32_t tickstart;
 
@@ -1212,12 +1289,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
     if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
     }
     else
     {
       hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
     }
 
     while (hi2c->XferCount > 0U)
@@ -1248,12 +1327,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
         if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
         }
         else
         {
           hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
         }
       }
     }
@@ -1294,9 +1375,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout)
 {
   uint32_t tickstart;
+  uint16_t tmpXferCount;
+  HAL_StatusTypeDef error;
 
   if (hi2c->State == HAL_I2C_STATE_READY)
   {
@@ -1331,6 +1415,19 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
       return HAL_ERROR;
     }
 
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+    }
+
     /* Clear ADDR flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
 
@@ -1376,26 +1473,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
       hi2c->XferCount--;
     }
 
-    /* Wait until STOP flag is set */
-    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
-    {
-      /* Disable Address Acknowledge */
-      hi2c->Instance->CR2 |= I2C_CR2_NACK;
+    /* Wait until AF flag is set */
+    error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
 
-      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+    if (error != HAL_OK)
+    {
+      /* Check that I2C transfer finished */
+      /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+      /* Mean XferCount == 0 */
+
+      tmpXferCount = hi2c->XferCount;
+      if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
       {
-        /* Normal use case for Transmitter mode */
-        /* A NACK is generated to confirm the end of transfer */
+        /* Reset ErrorCode to NONE */
         hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
       }
       else
       {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
         return HAL_ERROR;
       }
     }
+    else
+    {
+      /* Flush TX register */
+      I2C_Flush_TXDR(hi2c);
 
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      /* Clear AF flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Wait until STOP flag is set */
+      if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+      {
+        /* Disable Address Acknowledge */
+        hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+        return HAL_ERROR;
+      }
+
+      /* Clear STOP flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
 
     /* Wait until BUSY flag is reset */
     if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
@@ -1431,7 +1550,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout)
 {
   uint32_t tickstart;
 
@@ -1455,6 +1575,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr  = pData;
     hi2c->XferCount = Size;
+    hi2c->XferSize = hi2c->XferCount;
     hi2c->XferISR   = NULL;
 
     /* Enable Address Acknowledge */
@@ -1497,6 +1618,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
           hi2c->pBuffPtr++;
 
           hi2c->XferCount--;
+          hi2c->XferSize--;
         }
 
         return HAL_ERROR;
@@ -1509,6 +1631,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData,
       hi2c->pBuffPtr++;
 
       hi2c->XferCount--;
+      hi2c->XferSize--;
     }
 
     /* Wait until STOP flag is set */
@@ -1595,7 +1718,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
 
     /* Send Slave Address */
     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+    if (hi2c->XferSize > 0U)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
+    else
+    {
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
+                         I2C_GENERATE_START_WRITE);
+    }
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -1606,7 +1748,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
 
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
 
     return HAL_OK;
@@ -1627,7 +1770,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
   * @param  Size Amount of data to be sent
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                            uint16_t Size)
 {
   uint32_t xfermode;
 
@@ -1675,7 +1819,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
 
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
 
     return HAL_OK;
@@ -1715,6 +1860,20 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Slave_ISR_IT;
 
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
@@ -1724,7 +1883,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD
 
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
 
     return HAL_OK;
@@ -1773,7 +1933,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
 
     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
     /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
 
     return HAL_OK;
@@ -1799,6 +1960,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
 {
   uint32_t xfermode;
   HAL_StatusTypeDef dmaxferstatus;
+  uint32_t sizetoxfer = 0U;
 
   if (hi2c->State == HAL_I2C_STATE_READY)
   {
@@ -1831,6 +1993,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
       xfermode = I2C_AUTOEND_MODE;
     }
 
+    if (hi2c->XferSize > 0U)
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      sizetoxfer = hi2c->XferSize;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
     if (hi2c->XferSize > 0U)
     {
       if (hi2c->hdmatx != NULL)
@@ -1846,7 +2022,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
         hi2c->hdmatx->XferAbortCallback = NULL;
 
         /* Enable the DMA stream or channel depends on Instance */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+                                         (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
       }
       else
       {
@@ -1867,7 +2044,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
       {
         /* Send Slave Address */
         /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
+                           xfermode, I2C_GENERATE_START_WRITE);
 
         /* Update XferCount value */
         hi2c->XferCount -= hi2c->XferSize;
@@ -1906,7 +2084,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
 
       /* Send Slave Address */
       /* Set NBYTES to write and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_WRITE);
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -1916,7 +2095,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
                 process unlock */
       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
       /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
     }
 
@@ -1990,7 +2170,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
         hi2c->hdmarx->XferAbortCallback = NULL;
 
         /* Enable the DMA stream or channel depends on Instance */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
       }
       else
       {
@@ -2050,7 +2231,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
 
       /* Send Slave Address */
       /* Set NBYTES to read and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -2058,10 +2240,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
       /* Note : The I2C interrupts must be enabled after unlocking current process
                 to avoid the risk of I2C interrupt handle execution before current
                 process unlock */
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* Enable ERR, TC, STOP, NACK, RXI interrupt */
       /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
     }
 
     return HAL_OK;
@@ -2105,37 +2288,87 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
     hi2c->XferISR     = I2C_Slave_ISR_DMA;
 
-    if (hi2c->hdmatx != NULL)
+    /* Preload TX data if no stretch enable */
+    if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
     {
-      /* Set the I2C DMA transfer complete callback */
-      hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
 
-      /* Set the DMA error callback */
-      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
 
-      /* Set the unused DMA callbacks to NULL */
-      hi2c->hdmatx->XferHalfCpltCallback = NULL;
-      hi2c->hdmatx->XferAbortCallback = NULL;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
 
-      /* Enable the DMA stream or channel depends on Instance */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+    if (hi2c->XferCount != 0U)
+    {
+      if (hi2c->hdmatx != NULL)
+      {
+        /* Set the I2C DMA transfer complete callback */
+        hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
+
+        /* Set the DMA error callback */
+        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
+
+        /* Set the unused DMA callbacks to NULL */
+        hi2c->hdmatx->XferHalfCpltCallback = NULL;
+        hi2c->hdmatx->XferAbortCallback = NULL;
+
+        /* Enable the DMA stream or channel depends on Instance */
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx,
+                                         (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                                         hi2c->XferSize);
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_LISTEN;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
+
+      if (dmaxferstatus == HAL_OK)
+      {
+        /* Enable Address Acknowledge */
+        hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        /* Note : The I2C interrupts must be enabled after unlocking current process
+                  to avoid the risk of I2C interrupt handle execution before current
+                  process unlock */
+        /* Enable ERR, STOP, NACK, ADDR interrupts */
+        I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
+
+        /* Enable DMA Request */
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+      else
+      {
+        /* Update I2C state */
+        hi2c->State     = HAL_I2C_STATE_LISTEN;
+        hi2c->Mode      = HAL_I2C_MODE_NONE;
+
+        /* Update I2C error code */
+        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
+
+        return HAL_ERROR;
+      }
     }
     else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    if (dmaxferstatus == HAL_OK)
     {
       /* Enable Address Acknowledge */
       hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -2144,27 +2377,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p
       __HAL_UNLOCK(hi2c);
 
       /* Note : The I2C interrupts must be enabled after unlocking current process
-                to avoid the risk of I2C interrupt handle execution before current
-                process unlock */
+      to avoid the risk of I2C interrupt handle execution before current
+      process unlock */
       /* Enable ERR, STOP, NACK, ADDR interrupts */
       I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-    }
-    else
-    {
-      /* Update I2C state */
-      hi2c->State     = HAL_I2C_STATE_LISTEN;
-      hi2c->Mode      = HAL_I2C_MODE_NONE;
-
-      /* Update I2C error code */
-      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
     }
 
     return HAL_OK;
@@ -2221,7 +2437,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
       hi2c->hdmarx->XferAbortCallback = NULL;
 
       /* Enable the DMA stream or channel depends on Instance */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                       hi2c->XferSize);
     }
     else
     {
@@ -2277,6 +2494,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
     return HAL_BUSY;
   }
 }
+
 /**
   * @brief  Write an amount of data in blocking mode to a specific memory address
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2374,12 +2592,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
         if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
         }
         else
         {
           hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
         }
       }
 
@@ -2474,12 +2694,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
     if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
+                         I2C_GENERATE_START_READ);
     }
     else
     {
       hi2c->XferSize = hi2c->XferCount;
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
     }
 
     do
@@ -2510,12 +2732,14 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
         if (hi2c->XferCount > MAX_NBYTE_SIZE)
         {
           hi2c->XferSize = MAX_NBYTE_SIZE;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
+                             I2C_NO_STARTSTOP);
         }
         else
         {
           hi2c->XferSize = hi2c->XferCount;
-          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                             I2C_NO_STARTSTOP);
         }
       }
     } while (hi2c->XferCount > 0U);
@@ -2561,9 +2785,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tickstart;
-  uint32_t xfermode;
-
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
@@ -2583,40 +2804,38 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
     hi2c->Mode        = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
 
     /* Prepare transfer parameters */
+    hi2c->XferSize    = 0U;
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
+    hi2c->XferISR     = I2C_Mem_ISR_IT;
+    hi2c->Devaddress  = DevAddress;
 
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
     {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
     }
+    /* If Memory address size is 16Bit */
     else
     {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
 
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
     /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -2627,7 +2846,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
 
     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
 
     return HAL_OK;
@@ -2653,9 +2873,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tickstart;
-  uint32_t xfermode;
-
   /* Check the parameters */
   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
 
@@ -2675,9 +2892,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
     hi2c->Mode        = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
@@ -2686,29 +2900,29 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_IT;
+    hi2c->XferISR     = I2C_Mem_ISR_IT;
+    hi2c->Devaddress  = DevAddress;
 
-    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
     {
-      hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
     }
+    /* If Memory address size is 16Bit */
     else
     {
-      hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
-    }
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
 
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
     /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
-
-    /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -2717,10 +2931,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
               to avoid the risk of I2C interrupt handle execution before current
               process unlock */
 
-    /* Enable ERR, TC, STOP, NACK, RXI interrupt */
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
     /* possible to enable all of these */
-    /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+      I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
 
     return HAL_OK;
   }
@@ -2729,6 +2944,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
     return HAL_BUSY;
   }
 }
+
 /**
   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -2744,8 +2960,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                         uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tickstart;
-  uint32_t xfermode;
   HAL_StatusTypeDef dmaxferstatus;
 
   /* Check the parameters */
@@ -2767,9 +2981,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
     hi2c->Mode        = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
@@ -2778,27 +2989,36 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
+    hi2c->XferISR     = I2C_Mem_ISR_DMA;
+    hi2c->Devaddress  = DevAddress;
 
     if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
     }
     else
     {
       hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
     }
 
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
     {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
-    }
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
 
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
+    }
 
     if (hi2c->hdmatx != NULL)
     {
@@ -2813,7 +3033,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
       hi2c->hdmatx->XferAbortCallback = NULL;
 
       /* Enable the DMA stream or channel depends on Instance */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
     }
     else
     {
@@ -2832,12 +3053,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 
     if (dmaxferstatus == HAL_OK)
     {
-      /* Send Slave Address */
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
+      /* Send Slave Address and Memory Address */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -2845,11 +3062,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
       /* Note : The I2C interrupts must be enabled after unlocking current process
                 to avoid the risk of I2C interrupt handle execution before current
                 process unlock */
-      /* Enable ERR and NACK interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
     }
     else
     {
@@ -2889,8 +3106,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
 {
-  uint32_t tickstart;
-  uint32_t xfermode;
   HAL_StatusTypeDef dmaxferstatus;
 
   /* Check the parameters */
@@ -2912,9 +3127,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     /* Process Locked */
     __HAL_LOCK(hi2c);
 
-    /* Init tickstart for timeout management*/
-    tickstart = HAL_GetTick();
-
     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
     hi2c->Mode        = HAL_I2C_MODE_MEM;
     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
@@ -2923,25 +3135,35 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
-    hi2c->XferISR     = I2C_Master_ISR_DMA;
+    hi2c->XferISR     = I2C_Mem_ISR_DMA;
+    hi2c->Devaddress  = DevAddress;
 
     if (hi2c->XferCount > MAX_NBYTE_SIZE)
     {
       hi2c->XferSize = MAX_NBYTE_SIZE;
-      xfermode = I2C_RELOAD_MODE;
     }
     else
     {
       hi2c->XferSize = hi2c->XferCount;
-      xfermode = I2C_AUTOEND_MODE;
     }
 
-    /* Send Slave Address and Memory Address */
-    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+    /* If Memory address size is 8Bit */
+    if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
     {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-      return HAL_ERROR;
+      /* Prefetch Memory Address */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+    /* If Memory address size is 16Bit */
+    else
+    {
+      /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */
+      hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
+
+      /* Prepare Memaddress buffer for LSB part */
+      hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress);
     }
 
     if (hi2c->hdmarx != NULL)
@@ -2957,7 +3179,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
       hi2c->hdmarx->XferAbortCallback = NULL;
 
       /* Enable the DMA stream or channel depends on Instance */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                       hi2c->XferSize);
     }
     else
     {
@@ -2976,11 +3199,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
 
     if (dmaxferstatus == HAL_OK)
     {
-      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
-      /* Update XferCount value */
-      hi2c->XferCount -= hi2c->XferSize;
+      /* Send Slave Address and Memory Address */
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -2988,11 +3208,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
       /* Note : The I2C interrupts must be enabled after unlocking current process
                 to avoid the risk of I2C interrupt handle execution before current
                 process unlock */
-      /* Enable ERR and NACK interrupts */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
-
-      /* Enable DMA Request */
-      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* possible to enable all of these */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
     }
     else
     {
@@ -3028,12 +3248,15 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+                                        uint32_t Timeout)
 {
   uint32_t tickstart;
 
   __IO uint32_t I2C_Trials = 0UL;
 
+  HAL_StatusTypeDef status = HAL_OK;
+
   FlagStatus tmp1;
   FlagStatus tmp2;
 
@@ -3091,53 +3314,64 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         /* Wait until STOPF flag is reset */
         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
-          return HAL_ERROR;
+          /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */
+          if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+          {
+            /* Clear STOP Flag */
+            __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+            /* Reset the error code for next trial */
+            hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+          }
+          else
+          {
+            status = HAL_ERROR;
+          }
         }
+        else
+        {
+          /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
 
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+          /* Clear STOP Flag */
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
-        /* Device is ready */
-        hi2c->State = HAL_I2C_STATE_READY;
+          /* Device is ready */
+          hi2c->State = HAL_I2C_STATE_READY;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
 
-        return HAL_OK;
+          return HAL_OK;
+        }
       }
       else
       {
-        /* Wait until STOPF flag is reset */
-        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
-        {
-          return HAL_ERROR;
-        }
+        /* A non acknowledge is detected, this mean that device not respond to its address,
+           a new trial must be performed */
 
         /* Clear NACK Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 
-        /* Clear STOP Flag, auto generated with autoend*/
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-      }
-
-      /* Check if the maximum allowed number of trials has been reached */
-      if (I2C_Trials == Trials)
-      {
-        /* Generate Stop */
-        hi2c->Instance->CR2 |= I2C_CR2_STOP;
-
         /* Wait until STOPF flag is reset */
         if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
         {
-          return HAL_ERROR;
+          status = HAL_ERROR;
+        }
+        else
+        {
+          /* Clear STOP Flag, auto generated with autoend*/
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
         }
-
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
       }
 
       /* Increment Trials */
       I2C_Trials++;
+
+      if ((I2C_Trials < Trials) && (status == HAL_ERROR))
+      {
+        status = HAL_OK;
+      }
+
     } while (I2C_Trials < Trials);
 
     /* Update I2C state */
@@ -3174,6 +3408,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
 {
   uint32_t xfermode;
   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
+  uint32_t sizetoxfer = 0U;
 
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3205,9 +3440,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
       xfermode = hi2c->XferOptions;
     }
 
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+                                  (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      sizetoxfer = hi2c->XferSize;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
     /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
     {
       xferrequest = I2C_NO_STARTSTOP;
     }
@@ -3224,7 +3476,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
     }
 
     /* Send Slave Address and set NBYTES to write */
-    I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+    if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+    {
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+    }
+    else
+    {
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+    }
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
@@ -3232,6 +3491,10 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
     /* Note : The I2C interrupts must be enabled after unlocking current process
               to avoid the risk of I2C interrupt handle execution before current
               process unlock */
+    /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+    /* possible to enable all of these */
+    /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+       I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
 
     return HAL_OK;
@@ -3260,6 +3523,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
   uint32_t xfermode;
   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
   HAL_StatusTypeDef dmaxferstatus;
+  uint32_t sizetoxfer = 0U;
 
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3291,9 +3555,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
       xfermode = hi2c->XferOptions;
     }
 
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
+                                  (XferOptions == I2C_FIRST_AND_LAST_FRAME)))
+    {
+      /* Preload TX register */
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      sizetoxfer = hi2c->XferSize;
+      hi2c->XferCount--;
+      hi2c->XferSize--;
+    }
+
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
     /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
     {
       xferrequest = I2C_NO_STARTSTOP;
     }
@@ -3324,7 +3605,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
         hi2c->hdmatx->XferAbortCallback = NULL;
 
         /* Enable the DMA stream or channel depends on Instance */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
+                                         (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
       }
       else
       {
@@ -3344,7 +3626,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
       if (dmaxferstatus == HAL_OK)
       {
         /* Send Slave Address and set NBYTES to write */
-        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+        if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+        {
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+        }
+        else
+        {
+          I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+        }
 
         /* Update XferCount value */
         hi2c->XferCount -= hi2c->XferSize;
@@ -3383,7 +3672,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
 
       /* Send Slave Address */
       /* Set NBYTES to write and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
+      if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
+      {
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
+      }
+      else
+      {
+        I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
+      }
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -3393,7 +3689,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
                 process unlock */
       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
       /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
     }
 
@@ -3453,9 +3750,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_
       xfermode = hi2c->XferOptions;
     }
 
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
     /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
     {
       xferrequest = I2C_NO_STARTSTOP;
     }
@@ -3539,9 +3838,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
       xfermode = hi2c->XferOptions;
     }
 
-    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */
+    /* If transfer direction not change and there is no request to start another frame,
+       do not generate Restart Condition */
     /* Mean Previous state is same as current state */
-    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
+    if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \
+        (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0))
     {
       xferrequest = I2C_NO_STARTSTOP;
     }
@@ -3572,7 +3873,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
         hi2c->hdmarx->XferAbortCallback = NULL;
 
         /* Enable the DMA stream or channel depends on Instance */
-        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData,
+                                         hi2c->XferSize);
       }
       else
       {
@@ -3631,7 +3933,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
 
       /* Send Slave Address */
       /* Set NBYTES to read and generate START condition */
-      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
+      I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
+                         I2C_GENERATE_START_READ);
 
       /* Process Unlocked */
       __HAL_UNLOCK(hi2c);
@@ -3639,10 +3942,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
       /* Note : The I2C interrupts must be enabled after unlocking current process
                 to avoid the risk of I2C interrupt handle execution before current
                 process unlock */
-      /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+      /* Enable ERR, TC, STOP, NACK, RXI interrupt */
       /* possible to enable all of these */
-      /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
-      I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
+      /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
+        I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
+      I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
     }
 
     return HAL_OK;
@@ -3666,6 +3970,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
                                                 uint32_t XferOptions)
 {
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
@@ -3725,7 +4032,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t
     hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Slave_ISR_IT;
 
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
     {
       /* Clear ADDR flag after prepare the transfer parameters */
       /* This action will generate an acknowledge to the Master */
@@ -3762,6 +4070,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t
 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
                                                  uint32_t XferOptions)
 {
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
   HAL_StatusTypeDef dmaxferstatus;
 
   /* Check the parameters */
@@ -3796,7 +4106,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
           hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
 
           /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
           hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
 
           /* Abort DMA RX */
@@ -3818,7 +4128,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
         if (hi2c->hdmatx != NULL)
         {
           /* Set the I2C DMA Abort callback :
-           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
+          will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
           hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
 
           /* Abort DMA TX */
@@ -3862,7 +4172,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
       hi2c->hdmatx->XferAbortCallback = NULL;
 
       /* Enable the DMA stream or channel depends on Instance */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
+                                       hi2c->XferSize);
     }
     else
     {
@@ -3902,7 +4213,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
       return HAL_ERROR;
     }
 
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET))
     {
       /* Clear ADDR flag after prepare the transfer parameters */
       /* This action will generate an acknowledge to the Master */
@@ -3912,15 +4224,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+
     /* Note : The I2C interrupts must be enabled after unlocking current process
     to avoid the risk of I2C interrupt handle execution before current
     process unlock */
     /* Enable ERR, STOP, NACK, ADDR interrupts */
     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
-
     return HAL_OK;
   }
   else
@@ -3942,6 +4254,9 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_
 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
                                                uint32_t XferOptions)
 {
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
+
   /* Check the parameters */
   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
 
@@ -4001,7 +4316,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t
     hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Slave_ISR_IT;
 
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
     {
       /* Clear ADDR flag after prepare the transfer parameters */
       /* This action will generate an acknowledge to the Master */
@@ -4038,6 +4354,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t
 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
                                                 uint32_t XferOptions)
 {
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  FlagStatus tmp;
   HAL_StatusTypeDef dmaxferstatus;
 
   /* Check the parameters */
@@ -4138,7 +4456,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t
       hi2c->hdmarx->XferAbortCallback = NULL;
 
       /* Enable the DMA stream or channel depends on Instance */
-      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
+      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR,
+                                       (uint32_t)pData, hi2c->XferSize);
     }
     else
     {
@@ -4178,7 +4497,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t
       return HAL_ERROR;
     }
 
-    if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+    tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
+    if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET))
     {
       /* Clear ADDR flag after prepare the transfer parameters */
       /* This action will generate an acknowledge to the Master */
@@ -4188,15 +4508,15 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
 
+    /* Enable DMA Request */
+    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+
     /* Note : The I2C interrupts must be enabled after unlocking current process
     to avoid the risk of I2C interrupt handle execution before current
     process unlock */
     /* REnable ADDR interrupt */
     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
 
-    /* Enable DMA Request */
-    hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
-
     return HAL_OK;
   }
   else
@@ -4330,7 +4650,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
   *                the configuration information for the specified I2C.
   * @retval None
   */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Get current IT Flags and IT sources value */
   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
@@ -4356,7 +4676,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   uint32_t tmperror;
 
   /* I2C Bus error interrupt occurred ------------------------------------*/
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
 
@@ -4365,7 +4686,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   }
 
   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
 
@@ -4374,7 +4696,8 @@ void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
   }
 
   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
-  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
+  if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET))
   {
     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
 
@@ -4580,7 +4903,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
   *                the configuration information for the specified I2C.
   * @retval HAL state
   */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
 {
   /* Return I2C handle state */
   return hi2c->State;
@@ -4592,7 +4915,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
   *         the configuration information for I2C module
   * @retval HAL mode
   */
-HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
+HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
 {
   return hi2c->Mode;
 }
@@ -4603,7 +4926,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
   *              the configuration information for the specified I2C.
   * @retval I2C Error Code
   */
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
+uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
 {
   return hi2c->ErrorCode;
 }
@@ -4628,7 +4951,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
 {
   uint16_t devaddress;
   uint32_t tmpITFlags = ITFlags;
@@ -4636,7 +4960,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
   /* Process Locked */
   __HAL_LOCK(hi2c);
 
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -4649,7 +4974,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
     /* Flush TX register */
     I2C_Flush_TXDR(hi2c);
   }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
   {
     /* Remove RXNE flag on temporary variable as read done */
     tmpITFlags &= ~I2C_FLAG_RXNE;
@@ -4663,18 +4989,25 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
     hi2c->XferSize--;
     hi2c->XferCount--;
   }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
+           ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+            (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
   {
     /* Write data to TXDR */
-    hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+    if (hi2c->XferCount != 0U)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
 
-    /* Increment Buffer pointer */
-    hi2c->pBuffPtr++;
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
 
-    hi2c->XferSize--;
-    hi2c->XferCount--;
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
   }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
   {
     if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
     {
@@ -4690,11 +5023,13 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
         hi2c->XferSize = hi2c->XferCount;
         if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
         {
-          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             hi2c->XferOptions, I2C_NO_STARTSTOP);
         }
         else
         {
-          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+          I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize,
+                             I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
         }
       }
     }
@@ -4714,7 +5049,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
       }
     }
   }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
   {
     if (hi2c->XferCount == 0U)
     {
@@ -4745,7 +5081,151 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
     /* Nothing to do */
   }
 
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, tmpITFlags);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                        uint32_t ITSources)
+{
+  uint32_t direction = I2C_GENERATE_START_WRITE;
+  uint32_t tmpITFlags = ITFlags;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    /* No need to generate STOP, it is automatically done */
+    /* Error callback will be send during stop flag treatment */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  {
+    /* Remove RXNE flag on temporary variable as read done */
+    tmpITFlags &= ~I2C_FLAG_RXNE;
+
+    /* Read data from RXDR */
+    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
+
+    /* Increment Buffer pointer */
+    hi2c->pBuffPtr++;
+
+    hi2c->XferSize--;
+    hi2c->XferCount--;
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    if (hi2c->Memaddress == 0xFFFFFFFFU)
+    {
+      /* Write data to TXDR */
+      hi2c->Instance->TXDR = *hi2c->pBuffPtr;
+
+      /* Increment Buffer pointer */
+      hi2c->pBuffPtr++;
+
+      hi2c->XferSize--;
+      hi2c->XferCount--;
+    }
+    else
+    {
+      /* Write LSB part of Memory Address */
+      hi2c->Instance->TXDR = hi2c->Memaddress;
+
+      /* Reset Memaddress content */
+      hi2c->Memaddress = 0xFFFFFFFFU;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
+    {
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
+
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      direction = I2C_GENERATE_START_READ;
+    }
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_RELOAD_MODE, direction);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+
+      /* Set NBYTES to write and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_AUTOEND_MODE, direction);
+    }
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Master complete process */
     I2C_ITMasterCplt(hi2c, tmpITFlags);
@@ -4765,7 +5245,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                          uint32_t ITSources)
 {
   uint32_t tmpoptions = hi2c->XferOptions;
   uint32_t tmpITFlags = ITFlags;
@@ -4774,13 +5255,14 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
   __HAL_LOCK(hi2c);
 
   /* Check if STOPF is set */
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Slave complete process */
     I2C_ITSlaveCplt(hi2c, tmpITFlags);
   }
-
-  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
   {
     /* Check that I2C transfer finished */
     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -4788,8 +5270,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
     /* So clear Flag NACKF only */
     if (hi2c->XferCount == 0U)
     {
-      /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
       if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
       {
         /* Call I2C Listen complete process */
         I2C_ITListenCplt(hi2c, tmpITFlags);
@@ -4828,7 +5311,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
       }
     }
   }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
   {
     if (hi2c->XferCount > 0U)
     {
@@ -4854,11 +5338,12 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
   {
     I2C_ITAddrCplt(hi2c, tmpITFlags);
   }
-  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
   {
     /* Write data to TXDR only if XferCount not reach "0" */
     /* A TXIS flag can be set, during STOP treatment      */
-    /* Check if all data have already been sent */
+    /* Check if all Data have already been sent */
     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
     if (hi2c->XferCount > 0U)
     {
@@ -4900,7 +5385,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                            uint32_t ITSources)
 {
   uint16_t devaddress;
   uint32_t xfermode;
@@ -4908,7 +5394,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
   /* Process Locked */
   __HAL_LOCK(hi2c);
 
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
   {
     /* Clear NACK Flag */
     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -4924,7 +5411,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
     /* Flush TX register */
     I2C_Flush_TXDR(hi2c);
   }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
   {
     /* Disable TC interrupt */
     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
@@ -4985,7 +5473,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
       }
     }
   }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
   {
     if (hi2c->XferCount == 0U)
     {
@@ -5011,7 +5500,156 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
     }
   }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  {
+    /* Call I2C Master complete process */
+    I2C_ITMasterCplt(hi2c, ITFlags);
+  }
+  else
+  {
+    /* Nothing to do */
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hi2c);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  ITFlags Interrupt flags to handle.
+  * @param  ITSources Interrupt sources enabled.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                         uint32_t ITSources)
+{
+  uint32_t direction = I2C_GENERATE_START_WRITE;
+
+  /* Process Locked */
+  __HAL_LOCK(hi2c);
+
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  {
+    /* Clear NACK Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Set corresponding Error Code */
+    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+    /* No need to generate STOP, it is automatically done */
+    /* But enable STOP interrupt, to treat it */
+    /* Error callback will be send during stop flag treatment */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
+
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
+  {
+    /* Write LSB part of Memory Address */
+    hi2c->Instance->TXDR = hi2c->Memaddress;
+
+    /* Reset Memaddress content */
+    hi2c->Memaddress = 0xFFFFFFFFU;
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable only Error interrupt */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    if (hi2c->XferCount != 0U)
+    {
+      /* Prepare the new XferSize to transfer */
+      if (hi2c->XferCount > MAX_NBYTE_SIZE)
+      {
+        hi2c->XferSize = MAX_NBYTE_SIZE;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
+      }
+      else
+      {
+        hi2c->XferSize = hi2c->XferCount;
+        I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                           I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
+      }
+
+      /* Update XferCount value */
+      hi2c->XferCount -= hi2c->XferSize;
+
+      /* Enable DMA Request */
+      if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+      }
+      else
+      {
+        hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+      }
+    }
+    else
+    {
+      /* Wrong size Status regarding TCR flag event */
+      /* Call the corresponding callback to inform upper layer of End of Transfer */
+      I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
+  {
+    /* Disable Interrupt related to address step */
+    I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
+
+    /* Enable only Error and NACK interrupt for data transfer */
+    I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
+
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      direction = I2C_GENERATE_START_READ;
+    }
+
+    if (hi2c->XferCount > MAX_NBYTE_SIZE)
+    {
+      hi2c->XferSize = MAX_NBYTE_SIZE;
+
+      /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_RELOAD_MODE, direction);
+    }
+    else
+    {
+      hi2c->XferSize = hi2c->XferCount;
+
+      /* Set NBYTES to write and generate RESTART */
+      I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
+                         I2C_AUTOEND_MODE, direction);
+    }
+
+    /* Update XferCount value */
+    hi2c->XferCount -= hi2c->XferSize;
+
+    /* Enable DMA Request */
+    if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
+    {
+      hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
+    }
+    else
+    {
+      hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+    }
+  }
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Master complete process */
     I2C_ITMasterCplt(hi2c, ITFlags);
@@ -5035,7 +5673,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
   * @param  ITSources Interrupt sources enabled.
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags,
+                                           uint32_t ITSources)
 {
   uint32_t tmpoptions = hi2c->XferOptions;
   uint32_t treatdmanack = 0U;
@@ -5045,13 +5684,14 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
   __HAL_LOCK(hi2c);
 
   /* Check if STOPF is set */
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
+  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
   {
     /* Call I2C Slave complete process */
     I2C_ITSlaveCplt(hi2c, ITFlags);
   }
-
-  if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
   {
     /* Check that I2C transfer finished */
     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@@ -5065,7 +5705,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
       {
         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
         {
-          if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
           {
             treatdmanack = 1U;
           }
@@ -5077,7 +5717,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
       {
         if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
         {
-          if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+          if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
           {
             treatdmanack = 1U;
           }
@@ -5086,8 +5726,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
 
       if (treatdmanack == 1U)
       {
-        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
         if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+          /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+             Warning[Pa134]: left and right operands are identical */
         {
           /* Call I2C Listen complete process */
           I2C_ITListenCplt(hi2c, ITFlags);
@@ -5148,7 +5789,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
     }
   }
-  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+  else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \
+           (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
   {
     I2C_ITAddrCplt(hi2c, ITFlags);
   }
@@ -5175,8 +5817,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                                uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                                uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                                uint32_t Tickstart)
 {
   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
 
@@ -5229,8 +5872,9 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                               uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
+                                               uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
+                                               uint32_t Tickstart)
 {
   I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
 
@@ -5298,7 +5942,7 @@ static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
     /* If 10bits addressing mode is selected */
     if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
     {
-      if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+      if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK))
       {
         slaveaddrcode = ownadd1code;
         hi2c->AddrEventCount++;
@@ -5646,6 +6290,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
 {
   uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
   uint32_t tmpITFlags = ITFlags;
+  uint32_t tmpoptions = hi2c->XferOptions;
   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
 
   /* Clear STOP Flag */
@@ -5662,6 +6307,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
   }
+  else if (tmpstate == HAL_I2C_STATE_LISTEN)
+  {
+    I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
+    hi2c->PreviousState = I2C_STATE_NONE;
+  }
   else
   {
     /* Do nothing */
@@ -5684,7 +6334,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
 
     if (hi2c->hdmatx != NULL)
     {
-      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx);
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx);
     }
   }
   else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET)
@@ -5694,7 +6344,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
 
     if (hi2c->hdmarx != NULL)
     {
-      hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx);
+      hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx);
     }
   }
   else
@@ -5728,6 +6378,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
   }
 
+  if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
+      (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
+  {
+    /* Check that I2C transfer finished */
+    /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+    /* Mean XferCount == 0*/
+    /* So clear Flag NACKF only */
+    if (hi2c->XferCount == 0U)
+    {
+      if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
+        /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
+           Warning[Pa134]: left and right operands are identical */
+      {
+        /* Call I2C Listen complete process */
+        I2C_ITListenCplt(hi2c, tmpITFlags);
+      }
+      else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+        /* Flush TX register */
+        I2C_Flush_TXDR(hi2c);
+
+        /* Last Byte is Transmitted */
+        /* Call I2C Slave Sequential complete process */
+        I2C_ITSlaveSeqCplt(hi2c);
+      }
+      else
+      {
+        /* Clear NACK Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+      }
+    }
+    else
+    {
+      /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
+      /* Clear NACK Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+      /* Set ErrorCode corresponding to a Non-Acknowledge */
+      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+
+      if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
+      {
+        /* Call the corresponding callback to inform upper layer of End of Transfer */
+        I2C_ITError(hi2c, hi2c->ErrorCode);
+      }
+    }
+  }
+
   hi2c->Mode = HAL_I2C_MODE_NONE;
   hi2c->XferISR = NULL;
 
@@ -5855,6 +6556,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
 {
   HAL_I2C_StateTypeDef tmpstate = hi2c->State;
+
   uint32_t tmppreviousstate;
 
   /* Reset handle parameters */
@@ -5882,18 +6584,36 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
     /* Disable all interrupts */
     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
 
+    /* Flush TX register */
+    I2C_Flush_TXDR(hi2c);
+
     /* If state is an abort treatment on going, don't change state */
     /* This change will be do later */
     if (hi2c->State != HAL_I2C_STATE_ABORT)
     {
       /* Set HAL_I2C_STATE_READY */
       hi2c->State         = HAL_I2C_STATE_READY;
+
+      /* Check if a STOPF is detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+      {
+        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+        {
+          __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+          hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+        }
+
+        /* Clear STOP Flag */
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+      }
+
     }
     hi2c->XferISR       = NULL;
   }
 
   /* Abort DMA TX transfer if any */
   tmppreviousstate = hi2c->PreviousState;
+
   if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
                                  (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
   {
@@ -6025,7 +6745,8 @@ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
   */
 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   /* Disable DMA Request */
   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -6053,7 +6774,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
     }
 
     /* Enable the DMA stream or channel depends on Instance */
-    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize) != HAL_OK)
+    if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR,
+                         hi2c->XferSize) != HAL_OK)
     {
       /* Call the corresponding callback to inform upper layer of End of Transfer */
       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
@@ -6066,6 +6788,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
   }
 }
 
+
 /**
   * @brief  DMA I2C slave transmit process complete callback.
   * @param  hdma DMA handle
@@ -6073,7 +6796,8 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
   uint32_t tmpoptions = hi2c->XferOptions;
 
   if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME))
@@ -6093,6 +6817,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
   }
 }
 
+
 /**
   * @brief DMA I2C master receive process complete callback.
   * @param  hdma DMA handle
@@ -6100,7 +6825,8 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   /* Disable DMA Request */
   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -6128,7 +6854,8 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
     }
 
     /* Enable the DMA stream or channel depends on Instance */
-    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize) != HAL_OK)
+    if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr,
+                         hi2c->XferSize) != HAL_OK)
     {
       /* Call the corresponding callback to inform upper layer of End of Transfer */
       I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
@@ -6141,6 +6868,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
   }
 }
 
+
 /**
   * @brief  DMA I2C slave receive process complete callback.
   * @param  hdma DMA handle
@@ -6148,10 +6876,11 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
   uint32_t tmpoptions = hi2c->XferOptions;
 
-  if ((__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U) && \
+  if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \
       (tmpoptions != I2C_NO_OPTION_FRAME))
   {
     /* Disable DMA Request */
@@ -6168,6 +6897,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
   }
 }
 
+
 /**
   * @brief  DMA I2C communication error callback.
   * @param hdma DMA handle
@@ -6176,11 +6906,12 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 {
   uint32_t treatdmaerror = 0U;
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   if (hi2c->hdmatx != NULL)
   {
-    if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
+    if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U)
     {
       treatdmaerror = 1U;
     }
@@ -6188,7 +6919,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 
   if (hi2c->hdmarx != NULL)
   {
-    if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
+    if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U)
     {
       treatdmaerror = 1U;
     }
@@ -6205,6 +6936,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
   }
 }
 
+
 /**
   * @brief DMA I2C communication abort callback
   *        (To be called at end of DMA Abort procedure).
@@ -6213,7 +6945,8 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
   */
 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
 {
-  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   /* Reset AbortCpltCallback */
   if (hi2c->hdmatx != NULL)
@@ -6228,12 +6961,14 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
   I2C_TreatErrorCallback(hi2c);
 }
 
+
 /**
-  * @brief  This function handles I2C Communication Timeout.
+  * @brief  This function handles I2C Communication Timeout. It waits
+  *                until a flag is no longer in the specified status.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  Flag Specifies the I2C flag to check.
-  * @param  Status The new Flag status (SET or RESET).
+  * @param  Status The actual Flag status (SET or RESET).
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
@@ -6243,18 +6978,27 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
 {
   while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
   {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
       {
-        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-        hi2c->State = HAL_I2C_STATE_READY;
-        hi2c->Mode = HAL_I2C_MODE_NONE;
+        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-        return HAL_ERROR;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+          return HAL_ERROR;
+        }
       }
     }
   }
@@ -6269,12 +7013,13 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
 {
   while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
   {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
     {
       return HAL_ERROR;
     }
@@ -6283,6 +7028,47 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
     if (Timeout != HAL_MAX_DELAY)
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
+        {
+          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+          hi2c->State = HAL_I2C_STATE_READY;
+          hi2c->Mode = HAL_I2C_MODE_NONE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hi2c);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2C.
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
+{
+  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+  {
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
+    {
+      return HAL_ERROR;
+    }
+
+    /* Check for the Timeout */
+    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    {
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
       {
         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
         hi2c->State = HAL_I2C_STATE_READY;
@@ -6298,40 +7084,6 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
   return HAL_OK;
 }
 
-/**
-  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
-  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
-  *                the configuration information for the specified I2C.
-  * @param  Timeout Timeout duration
-  * @param  Tickstart Tick start value
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
-{
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
-  {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
-    {
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State = HAL_I2C_STATE_READY;
-      hi2c->Mode = HAL_I2C_MODE_NONE;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
 /**
   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
@@ -6340,18 +7092,21 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
+                                                        uint32_t Tickstart)
 {
-  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+  HAL_StatusTypeDef status = HAL_OK;
+
+  while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
   {
-    /* Check if a NACK is detected */
-    if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+    /* Check if an error is detected */
+    if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
     {
-      return HAL_ERROR;
+      status = HAL_ERROR;
     }
 
     /* Check if a STOPF is detected */
-    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+    if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
     {
       /* Check if an RXNE is pending */
       /* Store Last receive data if any */
@@ -6359,97 +7114,181 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
       {
         /* Return HAL_OK */
         /* The Reading of data from RXDR will be done in caller function */
-        return HAL_OK;
+        status = HAL_OK;
       }
-      else
+
+      /* Check a no-acknowledge have been detected */
+      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
       {
+        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+        hi2c->ErrorCode = HAL_I2C_ERROR_AF;
+
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
 
         /* Clear Configuration Register 2 */
         I2C_RESET_CR2(hi2c);
 
-        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
         hi2c->State = HAL_I2C_STATE_READY;
         hi2c->Mode = HAL_I2C_MODE_NONE;
 
         /* Process Unlocked */
         __HAL_UNLOCK(hi2c);
 
-        return HAL_ERROR;
+        status = HAL_ERROR;
+      }
+      else
+      {
+        hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
       }
     }
 
     /* Check for the Timeout */
-    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+    if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
     {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-      hi2c->State = HAL_I2C_STATE_READY;
+      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
+      {
+        hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
+        hi2c->State = HAL_I2C_STATE_READY;
 
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
+        /* Process Unlocked */
+        __HAL_UNLOCK(hi2c);
 
-      return HAL_ERROR;
+        status = HAL_ERROR;
+      }
     }
   }
-  return HAL_OK;
+  return status;
 }
 
 /**
-  * @brief  This function handles Acknowledge failed detection during an I2C Communication.
+  * @brief  This function handles errors detection during an I2C Communication.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
   * @param  Timeout Timeout duration
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
 {
-  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t itflag   = hi2c->Instance->ISR;
+  uint32_t error_code = 0;
+  uint32_t tickstart = Tickstart;
+  uint32_t tmp1;
+  HAL_I2C_ModeTypeDef tmp2;
+
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
   {
-    /* Wait until STOP Flag is reset */
+    /* Clear NACKF Flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+    /* Wait until STOP Flag is set or timeout occurred */
     /* AutoEnd should be initiate after AF */
-    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+    while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
     {
       /* Check for the Timeout */
       if (Timeout != HAL_MAX_DELAY)
       {
-        if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
         {
-          hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-          hi2c->State = HAL_I2C_STATE_READY;
-          hi2c->Mode = HAL_I2C_MODE_NONE;
+          tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
+          tmp2 = hi2c->Mode;
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
+          /* In case of I2C still busy, try to regenerate a STOP manually */
+          if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
+              (tmp1 != I2C_CR2_STOP) && \
+              (tmp2 != HAL_I2C_MODE_SLAVE))
+          {
+            /* Generate Stop */
+            hi2c->Instance->CR2 |= I2C_CR2_STOP;
 
-          return HAL_ERROR;
+            /* Update Tick with new reference */
+            tickstart = HAL_GetTick();
+          }
+
+          while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+          {
+            /* Check for the Timeout */
+            if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
+            {
+              error_code |= HAL_I2C_ERROR_TIMEOUT;
+
+              status = HAL_ERROR;
+
+              break;
+            }
+          }
         }
       }
     }
 
-    /* Clear NACKF Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+    /* In case STOP Flag is detected, clear it */
+    if (status == HAL_OK)
+    {
+      /* Clear STOP Flag */
+      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    }
 
-    /* Clear STOP Flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+    error_code |= HAL_I2C_ERROR_AF;
 
+    status = HAL_ERROR;
+  }
+
+  /* Refresh Content of Status register */
+  itflag = hi2c->Instance->ISR;
+
+  /* Then verify if an additional errors occurs */
+  /* Check if a Bus error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
+  {
+    error_code |= HAL_I2C_ERROR_BERR;
+
+    /* Clear BERR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Over-Run/Under-Run error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
+  {
+    error_code |= HAL_I2C_ERROR_OVR;
+
+    /* Clear OVR flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
+
+    status = HAL_ERROR;
+  }
+
+  /* Check if an Arbitration Loss error occurred */
+  if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
+  {
+    error_code |= HAL_I2C_ERROR_ARLO;
+
+    /* Clear ARLO flag */
+    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
+
+    status = HAL_ERROR;
+  }
+
+  if (status != HAL_OK)
+  {
     /* Flush TX register */
     I2C_Flush_TXDR(hi2c);
 
     /* Clear Configuration Register 2 */
     I2C_RESET_CR2(hi2c);
 
-    hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
+    hi2c->ErrorCode |= error_code;
     hi2c->State = HAL_I2C_STATE_READY;
     hi2c->Mode = HAL_I2C_MODE_NONE;
 
     /* Process Unlocked */
     __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
   }
-  return HAL_OK;
+
+  return status;
 }
 
 /**
@@ -6479,12 +7318,16 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin
   assert_param(IS_TRANSFER_MODE(Mode));
   assert_param(IS_TRANSFER_REQUEST(Request));
 
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+                             (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                             (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
+
   /* update CR2 register */
-  MODIFY_REG(hi2c->Instance->CR2,
+  MODIFY_REG(hi2c->Instance->CR2, \
              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
-               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
-             (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
-                        (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+               (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
+               I2C_CR2_START | I2C_CR2_STOP)), tmp);
 }
 
 /**
@@ -6498,8 +7341,9 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
 {
   uint32_t tmpisr = 0U;
 
-  if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
-      (hi2c->XferISR == I2C_Slave_ISR_DMA))
+  if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
+      (hi2c->XferISR != I2C_Slave_ISR_DMA) && \
+      (hi2c->XferISR != I2C_Mem_ISR_DMA))
   {
     if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
     {
@@ -6507,6 +7351,51 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
     }
 
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
+    if (InterruptRequest == I2C_XFER_ERROR_IT)
+    {
+      /* Enable ERR and NACK interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
+    }
+
+    if (InterruptRequest == I2C_XFER_CPLT_IT)
+    {
+      /* Enable STOP interrupts */
+      tmpisr |= I2C_IT_STOPI;
+    }
+  }
+
+  else
+  {
+    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+    {
+      /* Enable ERR, STOP, NACK and ADDR interrupts */
+      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
+    }
+
+    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+    {
+      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
+      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
+    }
+
     if (InterruptRequest == I2C_XFER_ERROR_IT)
     {
       /* Enable ERR and NACK interrupts */
@@ -6525,32 +7414,6 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
       tmpisr |= I2C_IT_TCI;
     }
   }
-  else
-  {
-    if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
-    {
-      /* Enable ERR, STOP, NACK, and ADDR interrupts */
-      tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
-    }
-
-    if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
-    {
-      /* Enable ERR, TC, STOP, NACK and RXI interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
-    }
-
-    if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
-    {
-      /* Enable ERR, TC, STOP, NACK and TXI interrupts */
-      tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
-    }
-
-    if (InterruptRequest == I2C_XFER_CPLT_IT)
-    {
-      /* Enable STOP interrupts */
-      tmpisr |= I2C_IT_STOPI;
-    }
-  }
 
   /* Enable interrupts only at the end */
   /* to avoid the risk of I2C interrupt handle execution before */
@@ -6663,5 +7526,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h
index 9962ac1327..c524cbce37 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -48,29 +47,30 @@ extern "C" {
 typedef struct
 {
   uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                  This parameter calculated by referring to I2C initialization
-                                         section in Reference manual */
+                                     This parameter calculated by referring to I2C initialization section
+                                     in Reference manual */
 
   uint32_t OwnAddress1;         /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
+                                     This parameter can be a 7-bit or 10-bit address. */
 
   uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */
+                                     This parameter can be a value of @ref I2C_ADDRESSING_MODE */
 
   uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
+                                     This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
 
   uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
+                                     This parameter can be a 7-bit address. */
 
-  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
-                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
+                                     mode is selected.
+                                     This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
 
   uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
+                                     This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
 
   uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
+                                     This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
 
 } I2C_InitTypeDef;
 
@@ -118,8 +118,6 @@ typedef enum
   HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
                                                  process is ongoing                         */
   HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
 
 } HAL_I2C_StateTypeDef;
 
@@ -200,12 +198,14 @@ typedef struct __I2C_HandleTypeDef
 
   __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
 
-  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */
+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
+  /*!< I2C transfer IRQ handler function pointer */
 
   DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
 
   DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
 
+
   HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
 
   __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
@@ -216,21 +216,37 @@ typedef struct __I2C_HandleTypeDef
 
   __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
 
+  __IO uint32_t              Devaddress;     /*!< I2C Target device address                 */
+
+  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                 */
+
 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */
-  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */
-  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */
-  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */
-  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */
+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Listen Complete callback              */
+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Tx Transfer completed callback */
+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Memory Rx Transfer completed callback */
+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Error callback                        */
+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Abort callback                        */
 
-  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */
+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+  /*!< I2C Slave Address Match callback */
 
-  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */
+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
+  /*!< I2C Msp DeInit callback                   */
 
 #endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
 } I2C_HandleTypeDef;
@@ -259,8 +275,11 @@ typedef enum
 /**
   * @brief  HAL I2C Callback pointer definition
   */
-typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
-typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
+/*!< pointer to an I2C callback function */
+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
+                                          uint16_t AddrMatchCode);
+/*!< pointer to an I2C Address Match callback function */
 
 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 /**
@@ -440,14 +459,14 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
   * @retval None
   */
 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
-                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
+                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                                   } while(0)
 #else
 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 
 /** @brief  Enable the specified I2C interrupt.
   * @param  __HANDLE__ specifies the I2C Handle.
@@ -542,26 +561,27 @@ typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans
   *
   * @retval None
   */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
-                                                    : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
+                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))
 
 /** @brief  Enable the specified I2C peripheral.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
-#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+#define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
 /** @brief  Disable the specified I2C peripheral.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
-#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+#define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
   * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
 /**
   * @}
   */
@@ -601,12 +621,14 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
   */
 /* IO operation functions  ****************************************************/
 /******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
-                                          uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                          uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+                                         uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
                                          uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
                                     uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
@@ -686,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
   * @{
   */
 /* Peripheral State, Mode and Error functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
 
 /**
   * @}
@@ -757,10 +779,14 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
                                                         ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
 
 #define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
-                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
+                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
+                                                                          I2C_CR2_RD_WRN)))
 
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
-#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
+                                                              >> 16U))
+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
+                                                             >> 16U))
 #define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
 #define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
 #define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
@@ -772,10 +798,15 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
                                                                          (uint16_t)(0xFF00U))) >> 8U)))
 #define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
 
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
-                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+                                                                (~I2C_CR2_RD_WRN)) : \
+                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START) | \
+                                                                 (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
 
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) &  ((__FLAG__) & I2C_FLAG_MASK)) == \
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
                                                     ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
 #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
 /**
@@ -805,5 +836,3 @@ uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
 
 
 #endif /* STM32H7xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c
index 26a046bdb8..d9b8e46c62 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c
@@ -5,8 +5,21 @@
   * @brief   I2C Extended HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of I2C Extended peripheral:
-  *           + Extended features functions
+  *           + Filter Mode Functions
+  *           + WakeUp Mode Functions
+  *           + FastModePlus Functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                ##### I2C peripheral Extended features  #####
@@ -32,18 +45,6 @@
           (++) HAL_I2CEx_EnableFastModePlus()
           (++) HAL_I2CEx_DisableFastModePlus()
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -71,17 +72,15 @@
   * @{
   */
 
-/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
-  * @brief    Extended features functions
+/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
+  * @brief    Filter Mode Functions
   *
 @verbatim
  ===============================================================================
-                      ##### Extended features functions #####
+                      ##### Filter Mode Functions #####
  ===============================================================================
     [..] This section provides functions allowing to:
       (+) Configure Noise Filters
-      (+) Configure Wake Up Feature
-      (+) Configure Fast Mode Plus
 
 @endverbatim
   * @{
@@ -182,6 +181,23 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
     return HAL_BUSY;
   }
 }
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @brief    WakeUp Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### WakeUp Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
 
 /**
   * @brief  Enable I2C wakeup from Stop mode(s).
@@ -260,6 +276,23 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
     return HAL_BUSY;
   }
 }
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
 
 /**
   * @brief Enable the I2C fast mode plus driving capability.
@@ -322,11 +355,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
   /* Disable fast mode plus driving capability for selected pin */
   CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
 }
-
 /**
   * @}
   */
-
 /**
   * @}
   */
@@ -339,5 +370,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h
index 79099801b9..e701b8b089 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -67,7 +66,7 @@ extern "C" {
 #define I2C_FASTMODEPLUS_I2C5           SYSCFG_PMCR_I2C5_FMP                           /*!< Enable Fast Mode Plus on I2C5 pins */
 #else
 #define I2C_FASTMODEPLUS_I2C5           (uint32_t)(0x00001000U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported  */
-#endif
+#endif /* SYSCFG_PMCR_I2C5_FMP */
 /**
   * @}
   */
@@ -90,7 +89,7 @@ extern "C" {
   * @{
   */
 
-/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
+/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
   * @{
   */
 /* Peripheral Control functions  ************************************************/
@@ -100,7 +99,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
   * @}
   */
 
-/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
   * @{
   */
 HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
@@ -109,7 +108,7 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
   * @}
   */
 
-/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
   * @{
   */
 void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
@@ -118,7 +117,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
   * @}
   */
 
-
 /**
   * @}
   */
@@ -141,7 +139,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 
 #define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
 
-#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))
 #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
@@ -150,28 +147,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
                                          (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
-#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
-#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
-#elif defined(SYSCFG_PMCR_I2C1_FMP)
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \
-                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
-#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
 /**
   * @}
   */
@@ -198,5 +173,3 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
 #endif
 
 #endif /* STM32H7xx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.c
index fa1a7cbb2c..d449267694 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.c
@@ -8,6 +8,17 @@
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral State and Errors functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                   ##### How to use this driver #####
@@ -117,6 +128,7 @@
             (+) TxRxCpltCallback      : I2S TxRx Completed callback
             (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
             (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
+            (+) TxRxHalfCpltCallback  : I2S TxRx Half Completed callback
             (+) ErrorCallback         : I2S Error callback
             (+) MspInitCallback       : I2S Msp Init callback
             (+) MspDeInitCallback     : I2S Msp DeInit callback
@@ -134,6 +146,7 @@
             (+) TxRxCpltCallback      : I2S TxRx Completed callback
             (+) TxHalfCpltCallback    : I2S Tx Half Completed callback
             (+) RxHalfCpltCallback    : I2S Rx Half Completed callback
+            (+) TxRxHalfCpltCallback  : I2S TxRx Half Completed callback
             (+) ErrorCallback         : I2S Error callback
             (+) MspInitCallback       : I2S Msp Init callback
             (+) MspDeInitCallback     : I2S Msp DeInit callback
@@ -157,22 +170,10 @@
 
        When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
        not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
+       and weak callbacks are used.
 
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -191,7 +192,13 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+/** @defgroup I2S_Private_Define I2S Private Define
+  * @{
+  */
 #define I2S_TIMEOUT 0xFFFFUL
+/**
+  * @}
+  */
 
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
@@ -211,7 +218,7 @@ static void               I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s);
 static void               I2S_Receive_16Bit_IT(I2S_HandleTypeDef *hi2s);
 static void               I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s);
 static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
-                                                        uint32_t Timeout);
+                                                        uint32_t Tickstart, uint32_t Timeout);
 /**
   * @}
   */
@@ -356,12 +363,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
 
       /* Get the source clock value: based on System Clock value */
 #if defined (SPI_SPI6I2S_SUPPORT)
-      if (hi2s->Instance == SPI6) 
-      {        
-        /* SPI6 source clock */  
+      if (hi2s->Instance == SPI6)
+      {
+        /* SPI6 source clock */
         i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI6);
       }
-      else 
+      else
       {
         /* SPI1,SPI2 and SPI3 share the same source clock */
         i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
@@ -369,7 +376,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
 #else
       /* SPI1,SPI2 and SPI3 share the same source clock */
       i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI123);
-#endif
+#endif  /* SPI_SPI6I2S_SUPPORT */
 
       /* Compute the Real divider depending on the MCLK output state, with a floating point */
       if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
@@ -414,7 +421,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
     }
 
     MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_I2SDIV                 | SPI_I2SCFGR_ODD),
-                                        ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
+               ((i2sdiv << SPI_I2SCFGR_I2SDIV_Pos) | (i2sodd << SPI_I2SCFGR_ODD_Pos)));
   }
 
   /*-------------------------- I2Sx I2SCFGR Configuration --------------------*/
@@ -425,10 +432,10 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
                                        SPI_I2SCFGR_DATLEN   | SPI_I2SCFGR_CHLEN      | \
                                        SPI_I2SCFGR_CKPOL    | SPI_I2SCFGR_WSINV      | \
                                        SPI_I2SCFGR_DATFMT   | SPI_I2SCFGR_MCKOE),
-                                      (SPI_I2SCFGR_I2SMOD   | hi2s->Init.Mode        | \
-                                       hi2s->Init.Standard  | hi2s->Init.DataFormat  | \
-                                       hi2s->Init.CPOL      | hi2s->Init.WSInversion | \
-                                       hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
+             (SPI_I2SCFGR_I2SMOD   | hi2s->Init.Mode        | \
+              hi2s->Init.Standard  | hi2s->Init.DataFormat  | \
+              hi2s->Init.CPOL      | hi2s->Init.WSInversion | \
+              hi2s->Init.Data24BitAlignment | hi2s->Init.MCLKOutput));
   /*Clear status register*/
   WRITE_REG(hi2s->Instance->IFCR, 0x0FF8);
 
@@ -536,9 +543,12 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
   *                the configuration information for the specified I2S.
   * @param  CallbackID ID of the callback to be registered
   * @param  pCallback pointer to the Callback function
+  * @note   The HAL_I2S_RegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+  *         to register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+                                           pI2S_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -549,8 +559,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hi2s);
 
   if (HAL_I2S_STATE_READY == hi2s->State)
   {
@@ -567,7 +575,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
       case HAL_I2S_TX_RX_COMPLETE_CB_ID :
         hi2s->TxRxCpltCallback = pCallback;
         break;
-        
+
       case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
         hi2s->TxHalfCpltCallback = pCallback;
         break;
@@ -580,7 +588,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
       case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
         hi2s->TxRxHalfCpltCallback = pCallback;
         break;
-        
+
       case HAL_I2S_ERROR_CB_ID :
         hi2s->ErrorCallback = pCallback;
         break;
@@ -632,8 +640,6 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
   return status;
 }
 
@@ -643,15 +649,14 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call
   * @param  hi2s Pointer to a I2S_HandleTypeDef structure that contains
   *                the configuration information for the specified I2S.
   * @param  CallbackID ID of the callback to be unregistered
+  * @note   The HAL_I2S_UnRegisterCallback() may be called before HAL_I2S_Init() in HAL_I2S_STATE_RESET
+  *         to un-register callbacks for HAL_I2S_MSPINIT_CB_ID and HAL_I2S_MSPDEINIT_CB_ID
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hi2s);
-
   if (HAL_I2S_STATE_READY == hi2s->State)
   {
     switch (CallbackID)
@@ -679,7 +684,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
       case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID :
         hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback;  /* Legacy weak TxRxHalfCpltCallback */
         break;
-        
+
       case HAL_I2S_ERROR_CB_ID :
         hi2s->ErrorCallback = HAL_I2S_ErrorCallback;                  /* Legacy weak ErrorCallback        */
         break;
@@ -731,8 +736,6 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
   return status;
 }
 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
@@ -801,30 +804,33 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
   *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout)
 {
 #if defined (__GNUC__)
   __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
 #endif /* __GNUC__ */
+  uint32_t tickstart;
 
   if ((pData == NULL) || (Size == 0UL))
   {
     return  HAL_ERROR;
   }
 
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
   /* Process Locked */
   __HAL_LOCK(hi2s);
 
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
 
   /* Set state and reset error code */
   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr  = pData;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pData;
   hi2s->TxXferSize  = Size;
   hi2s->TxXferCount = Size;
 
@@ -845,13 +851,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
 
 
   /* Wait until TXP flag is set */
-  if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
+  if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
   {
     /* Set the error code */
     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
     hi2s->State = HAL_I2S_STATE_READY;
     __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
+    return HAL_TIMEOUT;
   }
 
   while (hi2s->TxXferCount > 0UL)
@@ -859,7 +865,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
     if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
     {
       /* Transmit data in 32 Bit mode */
-      hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
+      hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
       hi2s->pTxBuffPtr += 2;
       hi2s->TxXferCount--;
     }
@@ -867,9 +873,9 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
     {
       /* Transmit data in 16 Bit mode */
 #if defined (__GNUC__)
-      *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
+      *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
 #else
-      *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
+      *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
 #endif /* __GNUC__ */
 
       hi2s->pTxBuffPtr++;
@@ -877,13 +883,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
     }
 
     /* Wait until TXP flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, Timeout) != HAL_OK)
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXP, SET, tickstart, Timeout) != HAL_OK)
     {
       /* Set the error code */
       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
       hi2s->State = HAL_I2S_STATE_READY;
       __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
+      return HAL_TIMEOUT;
     }
 
     /* Check if an underrun occurs */
@@ -924,20 +930,23 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
 #if defined (__GNUC__)
   __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
 #endif /* __GNUC__ */
+  uint32_t tickstart;
 
   if ((pData == NULL) || (Size == 0UL))
   {
     return  HAL_ERROR;
   }
 
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
   /* Process Locked */
   __HAL_LOCK(hi2s);
 
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
+  /* Init tickstart for timeout management*/
+  tickstart = HAL_GetTick();
 
   /* Set state and reset error code */
   hi2s->State       = HAL_I2S_STATE_BUSY_RX;
@@ -965,13 +974,13 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
   while (hi2s->RxXferCount > 0UL)
   {
     /* Wait until RXP flag is set */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, Timeout) != HAL_OK)
+    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXP, SET, tickstart, Timeout) != HAL_OK)
     {
       /* Set the error code */
       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
       hi2s->State = HAL_I2S_STATE_READY;
       __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
+      return HAL_TIMEOUT;
     }
 
     if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
@@ -1026,7 +1035,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
   * @retval HAL status
   */
 
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
                                             uint16_t Size, uint32_t Timeout)
 {
   uint32_t tmp_TxXferCount;
@@ -1038,17 +1047,16 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
   __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->RXDR));
 #endif /* __GNUC__ */
 
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
   /* Process Locked */
   __HAL_LOCK(hi2s);
 
@@ -1057,7 +1065,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
 
   hi2s->TxXferSize  = Size;
   hi2s->TxXferCount = Size;
-  hi2s->pTxBuffPtr  = pTxData;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pTxData;
   hi2s->RxXferSize  = Size;
   hi2s->RxXferCount = Size;
   hi2s->pRxBuffPtr  = pRxData;
@@ -1086,7 +1094,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
       if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
       {
         /* Transmit data in 32 Bit mode */
-        hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
+        hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
         hi2s->pTxBuffPtr += 2;
         tmp_TxXferCount--;
       }
@@ -1094,9 +1102,9 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
       {
         /* Transmit data in 16 Bit mode */
 #if defined (__GNUC__)
-        *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
+        *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
 #else
-        *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
+        *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
 #endif /* __GNUC__ */
 
         hi2s->pTxBuffPtr++;
@@ -1153,7 +1161,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
       SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
       hi2s->State = HAL_I2S_STATE_READY;
       __HAL_UNLOCK(hi2s);
-      return HAL_ERROR;
+      return HAL_TIMEOUT;
     }
   }
 
@@ -1176,26 +1184,25 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
   *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
 {
   if ((pData == NULL) || (Size == 0UL))
   {
     return  HAL_ERROR;
   }
 
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
   if (hi2s->State != HAL_I2S_STATE_READY)
   {
-    __HAL_UNLOCK(hi2s);
     return HAL_BUSY;
   }
 
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
   /* Set state and reset error code */
   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr  = (uint16_t *)pData;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pData;
   hi2s->TxXferSize  = Size;
   hi2s->TxXferCount = Size;
 
@@ -1260,15 +1267,14 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
     return  HAL_ERROR;
   }
 
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
   if (hi2s->State != HAL_I2S_STATE_READY)
   {
-    __HAL_UNLOCK(hi2s);
     return HAL_BUSY;
   }
 
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
   /* Set state and reset error code */
   hi2s->State       = HAL_I2S_STATE_BUSY_RX;
   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
@@ -1328,25 +1334,24 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
   *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
                                                uint16_t Size)
 {
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-
   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
   /* Process Locked */
   __HAL_LOCK(hi2s);
 
-  hi2s->pTxBuffPtr = pTxData;
-  hi2s->pRxBuffPtr = pRxData;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pTxData;
+  hi2s->pRxBuffPtr  = pRxData;
 
   hi2s->TxXferSize  = Size;
   hi2s->TxXferCount = Size;
@@ -1357,7 +1362,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t
   hi2s->State     = HAL_I2S_STATE_BUSY_TX_RX;
 
 
-    /* Set the function for IT treatment */
+  /* Set the function for IT treatment */
   if ((hi2s->Init.DataFormat == I2S_DATAFORMAT_24B) || (hi2s->Init.DataFormat == I2S_DATAFORMAT_32B))
   {
     hi2s->TxISR = I2S_Transmit_32Bit_IT;
@@ -1369,7 +1374,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t
     hi2s->RxISR = I2S_Receive_16Bit_IT;
   }
 
-    /* Check if the I2S is already enabled */
+  /* Check if the I2S is already enabled */
   if ((hi2s->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
   {
     /* Enable I2S peripheral */
@@ -1407,26 +1412,27 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t
   *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size)
 {
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
   if ((pData == NULL) || (Size == 0UL))
   {
     return  HAL_ERROR;
   }
 
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
   if (hi2s->State != HAL_I2S_STATE_READY)
   {
-    __HAL_UNLOCK(hi2s);
     return HAL_BUSY;
   }
 
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
   /* Set state and reset error code */
   hi2s->State       = HAL_I2S_STATE_BUSY_TX;
   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
-  hi2s->pTxBuffPtr  = pData;
+  hi2s->pTxBuffPtr  = (const uint16_t *)pData;
   hi2s->TxXferSize  = Size;
   hi2s->TxXferCount = Size;
 
@@ -1445,14 +1451,16 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
 
   /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
+  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
+                                 hi2s->TxXferCount))
   {
     /* Update I2S error code */
     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
     hi2s->State = HAL_I2S_STATE_READY;
 
     __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
+    errorcode = HAL_ERROR;
+    return errorcode;
   }
 
   /* Check if the I2S Tx request is already enabled */
@@ -1473,7 +1481,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
 
   __HAL_UNLOCK(hi2s);
-  return HAL_OK;
+  return errorcode;
 }
 
 /**
@@ -1492,20 +1500,21 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   */
 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
 {
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
   if ((pData == NULL) || (Size == 0UL))
   {
     return HAL_ERROR;
   }
 
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
   if (hi2s->State != HAL_I2S_STATE_READY)
   {
-    __HAL_UNLOCK(hi2s);
     return HAL_BUSY;
   }
 
+  /* Process Locked */
+  __HAL_LOCK(hi2s);
+
   /* Set state and reset error code */
   hi2s->State       = HAL_I2S_STATE_BUSY_RX;
   hi2s->ErrorCode   = HAL_I2S_ERROR_NONE;
@@ -1529,14 +1538,15 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
 
   /* Enable the Rx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
+                                 hi2s->RxXferCount))
   {
     /* Update I2S error code */
     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
     hi2s->State = HAL_I2S_STATE_READY;
-
+    errorcode = HAL_ERROR;
     __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
+    return errorcode;
   }
 
   /* Check if the I2S Rx request is already enabled */
@@ -1557,7 +1567,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
 
   __HAL_UNLOCK(hi2s);
-  return HAL_OK;
+  return errorcode;
 }
 
 /**
@@ -1575,24 +1585,26 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   *         between Master and Slave(example: audio streaming).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
                                                 uint16_t Size)
 {
-  if (hi2s->State != HAL_I2S_STATE_READY)
-  {
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
+  HAL_StatusTypeDef errorcode = HAL_OK;
+
 
   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
+  if (hi2s->State != HAL_I2S_STATE_READY)
+  {
+    return HAL_BUSY;
+  }
+
   /* Process Locked */
   __HAL_LOCK(hi2s);
 
-  hi2s->pTxBuffPtr = pTxData;
+  hi2s->pTxBuffPtr = (const uint16_t *)pTxData;
   hi2s->pRxBuffPtr = pRxData;
 
   hi2s->TxXferSize  = Size;
@@ -1614,16 +1626,17 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
 
   /* Set the I2S Rx DMA error callback */
   hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-
   /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR, hi2s->TxXferSize))
+  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->TXDR,
+                                 hi2s->TxXferCount))
   {
     /* Update I2S error code */
     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
     hi2s->State = HAL_I2S_STATE_READY;
 
     __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
+    errorcode = HAL_ERROR;
+    return errorcode;
   }
 
   /* Check if the I2S Tx request is already enabled */
@@ -1633,15 +1646,16 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
     SET_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
   }
 
-    /* Enable the Rx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize))
+  /* Enable the Rx DMA Stream/Channel */
+  if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->RXDR, (uint32_t)hi2s->pRxBuffPtr,
+                                 hi2s->RxXferCount))
   {
     /* Update I2S error code */
     SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
     hi2s->State = HAL_I2S_STATE_READY;
-
+    errorcode = HAL_ERROR;
     __HAL_UNLOCK(hi2s);
-    return HAL_ERROR;
+    return errorcode;
   }
 
   /* Check if the I2S Rx request is already enabled */
@@ -1662,7 +1676,7 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
   SET_BIT(hi2s->Instance->CR1, SPI_CR1_CSTART);
 
   __HAL_UNLOCK(hi2s);
-  return HAL_OK;
+  return errorcode;
 }
 
 /**
@@ -1917,8 +1931,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
     /* I2S Underrun error interrupt occurred --------------------------------*/
     if (HAL_IS_BIT_SET(trigger, I2S_FLAG_UDR))
     {
-      /* Disable TXP and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
+      /* Disable TXP, RXP and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
 
       /* Clear Underrun flag */
       __HAL_I2S_CLEAR_UDRFLAG(hi2s);
@@ -1939,8 +1953,8 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
     /* I2S Overrun error interrupt occurred -------------------------------------*/
     if (HAL_IS_BIT_SET(trigger, I2S_FLAG_OVR))
     {
-      /* Disable RXP and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXP | I2S_IT_ERR));
+      /* Disable TXP, RXP and ERR interrupt */
+      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_RXP | I2S_IT_ERR));
 
       /* Clear Overrun flag */
       __HAL_I2S_CLEAR_OVRFLAG(hi2s);
@@ -2099,7 +2113,7 @@ __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
   *         the configuration information for I2S module
   * @retval HAL state
   */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
+HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s)
 {
   return hi2s->State;
 }
@@ -2110,7 +2124,7 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
   *         the configuration information for I2S module
   * @retval I2S Error Code
   */
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
+uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s)
 {
   return hi2s->ErrorCode;
 }
@@ -2118,7 +2132,13 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
   * @}
   */
 
+/**
+  * @}
+  */
 
+/** @addtogroup I2S_Private_Functions
+  * @{
+  */
 /**
   * @brief  DMA I2S transmit process complete callback
   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
@@ -2127,7 +2147,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
   */
 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* if DMA is configured in DMA_NORMAL Mode */
   if (hdma->Init.Mode == DMA_NORMAL)
@@ -2154,7 +2175,8 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Call user Tx half complete callback */
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
@@ -2172,7 +2194,8 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* if DMA is configured in DMA_NORMAL Mode */
   if (hdma->Init.Mode == DMA_NORMAL)
@@ -2198,7 +2221,8 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Call user Rx half complete callback */
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
@@ -2218,6 +2242,21 @@ static void I2SEx_DMATxRxCplt(DMA_HandleTypeDef *hdma)
 {
   I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
+  /* if DMA is configured in DMA_NORMAL Mode */
+  if (hdma->Init.Mode == DMA_NORMAL)
+  {
+    /* Disable Tx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_TXDMAEN);
+    hi2s->TxXferCount = (uint16_t) 0UL;
+
+    /* Disable Rx DMA Request */
+    CLEAR_BIT(hi2s->Instance->CFG1, SPI_CFG1_RXDMAEN);
+    hi2s->RxXferCount = (uint16_t)0UL;
+
+    /* Updated HAL State */
+    hi2s->State = HAL_I2S_STATE_READY;
+  }
+
   /* Call user TxRx complete callback */
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
   hi2s->TxRxCpltCallback(hi2s);
@@ -2252,7 +2291,8 @@ static void I2SEx_DMATxRxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void I2S_DMAError(DMA_HandleTypeDef *hdma)
 {
-  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable Rx and Tx DMA Request */
   CLEAR_BIT(hi2s->Instance->CFG1, (SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN));
@@ -2283,9 +2323,9 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
 #if defined (__GNUC__)
   __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hi2s->Instance->TXDR));
 
-  *ptxdr_16bits = *((uint16_t *)hi2s->pTxBuffPtr);
+  *ptxdr_16bits = *((const uint16_t *)hi2s->pTxBuffPtr);
 #else
-  *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((uint16_t *)hi2s->pTxBuffPtr);
+  *((__IO uint16_t *)&hi2s->Instance->TXDR) = *((const uint16_t *)hi2s->pTxBuffPtr);
 #endif /* __GNUC__ */
   hi2s->pTxBuffPtr++;
   hi2s->TxXferCount--;
@@ -2295,16 +2335,17 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
     /* Disable TXP and ERR interrupt */
     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
 
-    if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+    if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
     {
       hi2s->State = HAL_I2S_STATE_READY;
-    }
-    /* Call user Tx complete callback */
+
+      /* Call user Tx complete callback */
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
-    hi2s->TxCpltCallback(hi2s);
+      hi2s->TxCpltCallback(hi2s);
 #else
-    HAL_I2S_TxCpltCallback(hi2s);
+      HAL_I2S_TxCpltCallback(hi2s);
 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+    }
   }
 }
 
@@ -2317,7 +2358,7 @@ static void I2S_Transmit_16Bit_IT(I2S_HandleTypeDef *hi2s)
 static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
 {
   /* Transmit data */
-  hi2s->Instance->TXDR = *((uint32_t *)hi2s->pTxBuffPtr);
+  hi2s->Instance->TXDR = *((const uint32_t *)hi2s->pTxBuffPtr);
   hi2s->pTxBuffPtr += 2;
   hi2s->TxXferCount--;
 
@@ -2326,16 +2367,17 @@ static void I2S_Transmit_32Bit_IT(I2S_HandleTypeDef *hi2s)
     /* Disable TXP and ERR interrupt */
     __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXP | I2S_IT_ERR));
 
-    if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) ||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
+    if ((hi2s->Init.Mode == I2S_MODE_SLAVE_TX) || (hi2s->Init.Mode == I2S_MODE_MASTER_TX))
     {
       hi2s->State = HAL_I2S_STATE_READY;
-    }
-    /* Call user Tx complete callback */
+
+      /* Call user Tx complete callback */
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
-    hi2s->TxCpltCallback(hi2s);
+      hi2s->TxCpltCallback(hi2s);
 #else
-    HAL_I2S_TxCpltCallback(hi2s);
+      HAL_I2S_TxCpltCallback(hi2s);
 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
+    }
   }
 }
 
@@ -2451,22 +2493,19 @@ static void I2S_Receive_32Bit_IT(I2S_HandleTypeDef *hi2s)
   *         the configuration information for I2S module
   * @param  Flag Flag checked
   * @param  State Value of the flag expected
+  * @param  Tickstart Tick start value
   * @param  Timeout Duration of the timeout
   * @retval HAL status
   */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout)
+static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
+                                                       uint32_t Tickstart, uint32_t Timeout)
 {
-  uint32_t tickstart;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
   /* Wait until flag is set to status*/
   while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
   {
     if (Timeout != HAL_MAX_DELAY)
     {
-      if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0UL))
+      if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0UL))
       {
         /* Set the I2S State ready */
         hi2s->State = HAL_I2S_STATE_READY;
@@ -2495,4 +2534,3 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s,
 
 #endif /* HAL_I2S_MODULE_ENABLED */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.h
index 66762f450a..407bf2ccb3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -102,7 +101,7 @@ typedef struct __I2S_HandleTypeDef
 
   I2S_InitTypeDef            Init;                 /*!< I2S communication parameters */
 
-  uint16_t                   *pTxBuffPtr;          /*!< Pointer to I2S Tx transfer buffer */
+  const uint16_t             *pTxBuffPtr;          /*!< Pointer to I2S Tx transfer buffer */
 
   __IO uint16_t              TxXferSize;           /*!< I2S Tx transfer size */
 
@@ -122,7 +121,7 @@ typedef struct __I2S_HandleTypeDef
   void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
 
   void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
-  
+
   DMA_HandleTypeDef          *hdmatx;              /*!< I2S Tx DMA handle parameters */
 
   DMA_HandleTypeDef          *hdmarx;              /*!< I2S Rx DMA handle parameters */
@@ -324,12 +323,12 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
 /** @defgroup I2S_Flags_Definition I2S Flags Definition
   * @{
   */
-#define I2S_FLAG_RXP                     SPI_SR_RXP       /* I2S status flag : Rx-Packet available flag                 */
-#define I2S_FLAG_TXP                     SPI_SR_TXP       /* I2S status flag : Tx-Packet space available flag           */
-#define I2S_FLAG_DXP                     SPI_SR_DXP       /* I2S status flag : Dx-Packet space available flag           */
-#define I2S_FLAG_UDR                     SPI_SR_UDR       /* I2S Error flag  : Underrun flag                            */
-#define I2S_FLAG_OVR                     SPI_SR_OVR       /* I2S Error flag  : Overrun flag                             */
-#define I2S_FLAG_FRE                     SPI_SR_TIFRE     /* I2S Error flag  : TI mode frame format error flag          */
+#define I2S_FLAG_RXP                     SPI_SR_RXP       /* I2S status flag : Rx-Packet available flag              */
+#define I2S_FLAG_TXP                     SPI_SR_TXP       /* I2S status flag : Tx-Packet space available flag        */
+#define I2S_FLAG_DXP                     SPI_SR_DXP       /* I2S status flag : Dx-Packet space available flag        */
+#define I2S_FLAG_UDR                     SPI_SR_UDR       /* I2S Error flag  : Underrun flag                         */
+#define I2S_FLAG_OVR                     SPI_SR_OVR       /* I2S Error flag  : Overrun flag                          */
+#define I2S_FLAG_FRE                     SPI_SR_TIFRE     /* I2S Error flag  : TI mode frame format error flag       */
 
 #define I2S_FLAG_MASK                    (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_DXP |SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
 /**
@@ -357,7 +356,7 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
                                                                   } while(0)
 #else
 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif
+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 
 /** @brief  Enable the specified SPI peripheral (in I2S mode).
   * @param  __HANDLE__ specifies the I2S Handle.
@@ -415,7 +414,8 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
   *            @arg I2S_IT_ERR : Error interrupt enable
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
+                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Check whether the specified I2S flag is set or not.
   * @param  __HANDLE__ specifies the I2S Handle.
@@ -469,7 +469,8 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
+                                           pI2S_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
@@ -481,24 +482,24 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca
   */
 /* I/O operation functions  ***************************************************/
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
                                             uint16_t Size, uint32_t Timeout);
 
 /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
                                                uint16_t Size);
 
 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
 
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
-                                               uint16_t Size);
+HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, const uint16_t *pTxData, uint16_t *pRxData,
+                                                uint16_t Size);
 
 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
@@ -520,8 +521,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
   * @{
   */
 /* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
+HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s);
+uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s);
 /**
   * @}
   */
@@ -541,6 +542,15 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
   * @}
   */
 
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2S_Private_Functions I2S Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_i2S.c file */
+/**
+  * @}
+  */
+
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup I2S_Private_Macros I2S Private Macros
   * @{
@@ -557,7 +567,9 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
   *            @arg I2S_FLAG_FRE : TI mode frame format error flag
   * @retval SET or RESET.
   */
-#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
+#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
+                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK))\
+                                                  ? SET : RESET)
 
 /** @brief  Check whether the specified SPI Interrupt is set or not.
   * @param  __IER__  copy of I2S IER register.
@@ -571,7 +583,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
   *            @arg I2S_IT_ERR : Error interrupt enable
   * @retval SET or RESET.
   */
-#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__)      ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__)      ((((__IER__)\
+                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks if I2S Mode parameter is in allowed range.
   * @param  __MODE__ specifies the I2S Mode.
@@ -592,9 +605,9 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
 #define IS_I2S_SLAVE(__MODE__)                      (((__MODE__) == I2S_MODE_SLAVE_TX)                  || \
                                                      ((__MODE__) == I2S_MODE_SLAVE_RX)                  || \
                                                      ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
-                                                     
+
 #define IS_I2S_FULLDUPLEX(__MODE__)                 (((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX)         || \
-                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))                                                  
+                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
 
 #define IS_I2S_STANDARD(__STANDARD__)               (((__STANDARD__) == I2S_STANDARD_PHILIPS)            || \
                                                      ((__STANDARD__) == I2S_STANDARD_MSB)                || \
@@ -612,7 +625,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
 
 #define IS_I2S_AUDIO_FREQ(__FREQ__)                ((((__FREQ__) >= I2S_AUDIOFREQ_8K)                    && \
                                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K))                 || \
-                                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
+                                                    ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
 
 #define IS_I2S_CPOL(__CPOL__)                       (((__CPOL__) == I2S_CPOL_LOW)                        || \
                                                      ((__CPOL__) == I2S_CPOL_HIGH))
@@ -648,4 +661,3 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
 
 #endif /* STM32H7xx_HAL_I2S_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.c
index dad1c58a96..171dcf7191 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.c
@@ -5,21 +5,20 @@
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of I2S extension peripheral:
-  *           + Extension features Functions 
+  *           + Extension features Functions
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
-  
+
 /**
   ******************************************************************************
                       ===== I2S FULL DUPLEX FEATURE =====
@@ -30,4 +29,3 @@
 
 
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.h
index 0f745077e4..231781d34e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2s_ex.h
@@ -6,17 +6,16 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
-  
+
 /**
   ******************************************************************************
                       ===== I2S FULL DUPLEX FEATURE =====
@@ -25,4 +24,3 @@
   */
 
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c
index 865e9c8164..124d7fe3f3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c
@@ -11,6 +11,17 @@
   *           + Peripheral State and Errors functions
   *           + Peripheral Control functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -114,8 +125,8 @@
     allows the user to configure dynamically the driver callbacks.
 
     [..]
-    Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback.
-    Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks:
+    Use Function HAL_IRDA_RegisterCallback() to register a user callback.
+    Function HAL_IRDA_RegisterCallback() allows to register following callbacks:
     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
     (+) TxCpltCallback            : Tx Complete Callback.
     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
@@ -130,9 +141,9 @@
     and a pointer to the user callback function.
 
     [..]
-    Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
@@ -147,13 +158,13 @@
     (+) MspDeInitCallback         : IRDA MspDeInit.
 
     [..]
-    By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback().
+    By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback().
     Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init()
-    and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit()
+    reset to the legacy weak functions in the HAL_IRDA_Init()
+    and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
     [..]
@@ -162,27 +173,16 @@
     in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user)
     MspInit/DeInit callbacks can be used during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit()
-    or @ref HAL_IRDA_Init() function.
+    using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit()
+    or HAL_IRDA_Init() function.
 
     [..]
     When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -462,7 +462,9 @@ __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User IRDA Callback
-  *         To be used instead of the weak predefined callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+  *         to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
   * @param  hirda irda handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -491,8 +493,6 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hirda);
 
   if (hirda->gState == HAL_IRDA_STATE_READY)
   {
@@ -577,15 +577,14 @@ HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
   return status;
 }
 
 /**
   * @brief  Unregister an IRDA callback
   *         IRDA callback is redirected to the weak predefined callback
+  * @note   The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+  *         to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
   * @param  hirda irda handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -605,9 +604,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hirda);
-
   if (HAL_IRDA_STATE_READY == hirda->gState)
   {
     switch (CallbackID)
@@ -693,9 +689,6 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
   return status;
 }
 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
@@ -801,10 +794,10 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
   * @param Timeout Specify timeout value.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
   uint32_t tickstart;
 
   /* Check that a Tx process is not already ongoing */
@@ -831,7 +824,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
     if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
     {
       pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */
+      pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */
     }
     else
     {
@@ -980,7 +973,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
   * @param Size Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
 {
   /* Check that a Tx process is not already ongoing */
   if (hirda->gState == HAL_IRDA_STATE_READY)
@@ -1052,8 +1045,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
     /* Process Unlocked */
     __HAL_UNLOCK(hirda);
 
-    /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    if (hirda->Init.Parity != IRDA_PARITY_NONE)
+    {
+      /* Enable the IRDA Parity Error and Data Register not empty Interrupts */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      /* Enable the IRDA Data Register not empty Interrupts */
+      SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
 
     /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1077,7 +1078,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
   * @param Size Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size)
 {
   /* Check that a Tx process is not already ongoing */
   if (hirda->gState == HAL_IRDA_STATE_READY)
@@ -1194,8 +1195,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData
       /* Process Unlocked */
       __HAL_UNLOCK(hirda);
 
-      /* Enable the UART Parity Error Interrupt */
-      SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+      if (hirda->Init.Parity != IRDA_PARITY_NONE)
+      {
+        /* Enable the UART Parity Error Interrupt */
+        SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+      }
 
       /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
       SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1287,7 +1291,10 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
     __HAL_IRDA_CLEAR_OREFLAG(hirda);
 
     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    if (hirda->Init.Parity != IRDA_PARITY_NONE)
+    {
+      SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
+    }
     SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the IRDA DMA Rx request */
@@ -2178,7 +2185,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda)
   *                the configuration information for the specified IRDA module.
   * @retval HAL state
   */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda)
 {
   /* Return IRDA handle state */
   uint32_t temp1;
@@ -2195,7 +2202,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
   *               the configuration information for the specified IRDA module.
   * @retval IRDA Error Code
   */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
+uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda)
 {
   return hirda->ErrorCode;
 }
@@ -2285,28 +2292,30 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
   {
     case IRDA_CLOCKSOURCE_D2PCLK1:
       pclk = HAL_RCC_GetPCLK1Freq();
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
       break;
     case IRDA_CLOCKSOURCE_D2PCLK2:
       pclk = HAL_RCC_GetPCLK2Freq();
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
       break;
     case IRDA_CLOCKSOURCE_PLL2Q:
       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll2_clocks.PLL2_Q_Frequency,
+                                              hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
       break;
     case IRDA_CLOCKSOURCE_PLL3Q:
       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pll3_clocks.PLL3_Q_Frequency, hirda->Init.BaudRate,
+                                              hirda->Init.ClockPrescaler));
       break;
     case IRDA_CLOCKSOURCE_CSI:
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(CSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
       break;
     case IRDA_CLOCKSOURCE_HSI:
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
       break;
     case IRDA_CLOCKSOURCE_LSE:
-      tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
+      tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
       break;
     default:
       ret = HAL_ERROR;
@@ -2316,7 +2325,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
   /* USARTDIV must be greater than or equal to 0d16 */
   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
   {
-    hirda->Instance->BRR = tmpreg;
+    hirda->Instance->BRR = (uint16_t)tmpreg;
   }
   else
   {
@@ -2374,11 +2383,12 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda)
 }
 
 /**
-  * @brief  Handle IRDA Communication Timeout.
+  * @brief  Handle IRDA Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *               the configuration information for the specified IRDA module.
   * @param  Flag Specifies the IRDA flag to check.
-  * @param  Status Flag status (SET or RESET)
+  * @param  Status The actual Flag status (SET or RESET)
   * @param  Tickstart Tick start value
   * @param  Timeout Timeout duration
   * @retval HAL status
@@ -2427,7 +2437,6 @@ static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
   hirda->gState = HAL_IRDA_STATE_READY;
 }
 
-
 /**
   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
   * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
@@ -2779,7 +2788,7 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
   */
 static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
 {
-  uint16_t *tmp;
+  const uint16_t *tmp;
 
   /* Check that a Tx process is ongoing */
   if (hirda->gState == HAL_IRDA_STATE_BUSY_TX)
@@ -2796,7 +2805,7 @@ static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
     {
       if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE))
       {
-        tmp = (uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
+        tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */
         hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
         hirda->pTxBuffPtr += 2U;
       }
@@ -2904,4 +2913,4 @@ static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h
index 869f840e13..67546df1c7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -126,7 +125,7 @@ typedef enum
   IRDA_CLOCKSOURCE_D2PCLK1    = 0x11U,    /*!< Domain2 PCLK1 clock source */
   IRDA_CLOCKSOURCE_D2PCLK2    = 0x12U,    /*!< Domain2 PCLK2 clock source */
   IRDA_CLOCKSOURCE_PLL2Q      = 0x14U,    /*!< PLL2Q clock source         */
-  IRDA_CLOCKSOURCE_PLL3Q      = 0x18U,    /*!< PCLK2 clock source         */
+  IRDA_CLOCKSOURCE_PLL3Q      = 0x18U,    /*!< PLL3Q clock source         */
   IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
   IRDA_CLOCKSOURCE_CSI        = 0x08U,    /*!< CSI clock source           */
   IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
@@ -146,7 +145,7 @@ typedef struct
 
   IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
 
-  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
+  const uint8_t            *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
 
   uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
 
@@ -830,11 +829,11 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
   */
 
 /* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
 HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
@@ -868,8 +867,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
   */
 
 /* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda);
+uint32_t              HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda);
 
 /**
   * @}
@@ -893,4 +892,3 @@ uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
 
 #endif /* STM32H7xx_HAL_IRDA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda_ex.h
index c1a2f2072f..a7a1ea310d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -647,4 +646,3 @@ extern "C" {
 
 #endif /* STM32H7xx_HAL_IRDA_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c
index 85548ac40d..2ec2829876 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c
@@ -8,6 +8,17 @@
   *           + Initialization and Start functions
   *           + IO operation functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### IWDG Generic features #####
@@ -87,18 +98,6 @@
           the reload register
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -122,11 +121,13 @@
 /* Status register needs up to 5 LSI clock periods divided by the clock
    prescaler to be updated. The number of LSI clock periods is upper-rounded to
    6 for the timeout value calculation.
-   The timeout value is also calculated using the highest prescaler (256) and
+   The timeout value is calculated using the highest prescaler (256) and
    the LSI_VALUE constant. The value of this constant can be changed by the user
    to take into account possible LSI clock period variations.
-   The timeout value is multiplied by 1000 to be converted in milliseconds. */
-#define HAL_IWDG_DEFAULT_TIMEOUT        ((6UL * 256UL * 1000UL) / LSI_VALUE)
+   The timeout value is multiplied by 1000 to be converted in milliseconds.
+   LSI startup time is also considered here by adding LSI_STARTUP_TIME
+   converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT        (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL))
 #define IWDG_KERNEL_UPDATE_FLAGS        (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU)
 /**
   * @}
@@ -280,5 +281,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h
index 93d30256cb..895c33b914 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -236,5 +235,3 @@ HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
 #endif
 
 #endif /* STM32H7xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c
index ce873e28a9..d83327162b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c
@@ -16,6 +16,17 @@
   *           + IRQ handler management
   *           + Peripheral State and Error functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -203,17 +214,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -4197,4 +4197,3 @@ static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h
index 16176c3459..0e3ccf8cc5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -290,7 +289,7 @@ typedef  void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8
   * @brief JPEG Flags definition
   * @{
   */
-#define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is bellow its threshold flag */
+#define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is below its threshold flag */
 #define JPEG_FLAG_IFNFF    ((uint32_t)JPEG_SR_IFNFF)  /*!< Input FIFO Not Full Flag, a data can be written */
 #define JPEG_FLAG_OFTF     ((uint32_t)JPEG_SR_OFTF)   /*!< Output FIFO is not empty and has reach its threshold */
 #define JPEG_FLAG_OFNEF    ((uint32_t)JPEG_SR_OFNEF)  /*!< Output FIFO is not empty, a data is available  */
@@ -358,7 +357,7 @@ typedef  void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8
   * @param  __HANDLE__ specifies the JPEG handle.
   * @param  __FLAG__  specifies the flag to check
   *         This parameter can be one of the following values:
-  *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is bellow its threshold flag
+  *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is below its threshold flag
   *         @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
   *         @arg JPEG_FLAG_OFTF  : The output FIFO is not empty and has reach its threshold
   *         @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
@@ -652,4 +651,3 @@ uint32_t               HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
 
 #endif /* STM32H7xx_HAL_JPEG_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c
index 5c396663dc..eb49bb0c7f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c
@@ -11,6 +11,17 @@
   *           + Reading operation functions.
   *           + Peripheral State functions.
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -96,13 +107,13 @@
   The compilation define  USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
   [..]
-  Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
-  @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  Use Function HAL_LPTIM_RegisterCallback() to register a callback.
+  HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
   the Callback ID and a pointer to the user callback function.
   [..]
-  Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
+  Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the
   default weak function.
-  @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
   and the Callback ID.
   [..]
   These functions allow to register/unregister following callbacks:
@@ -120,7 +131,7 @@
   [..]
   By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
   all interrupt callbacks are set to the corresponding weak functions:
-  examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
+  examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback().
 
   [..]
   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
@@ -134,7 +145,7 @@
   in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+  using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
 
   [..]
   When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
@@ -143,17 +154,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -188,7 +188,7 @@
 #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag);
 
 /* Exported functions --------------------------------------------------------*/
 
@@ -235,8 +235,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
 
   assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source));
   assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler));
-  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) 
-   || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
   {
     assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity));
     assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime));
@@ -279,8 +279,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
   /* Get the LPTIMx CFGR value */
   tmpcfgr = hlptim->Instance->CFGR;
 
-  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) 
-   || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
   {
     tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT));
   }
@@ -310,8 +310,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
   }
 
   /* Configure LPTIM external clock polarity and digital filter */
-  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) 
-   || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
+  if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM)
+      || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
   {
     tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity |
                 hlptim->Init.UltraLowPowerClock.SampleTime);
@@ -343,10 +343,10 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
   {
     if (hlptim->Instance == LPTIM3)
     {
-      /* Check LPTIM3 Input1 source */
+      /* Check LPTIM Input1 source */
       assert_param(IS_LPTIM_INPUT1_SOURCE(hlptim->Instance, hlptim->Init.Input1Source));
 
-      /* Configure LPTIM3 Input1 source */
+      /* Configure LPTIM Input1 source */
       hlptim->Instance->CFGR2 = hlptim->Init.Input1Source;
     }
   }
@@ -469,7 +469,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the LPTIM PWM generation.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @param  Pulse Specifies the compare value.
   *         This parameter must be a value between 0x0000 and 0xFFFF.
   * @retval HAL status
@@ -517,7 +517,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -534,7 +534,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
 
-  /* Set the LPTIM state */
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_BUSY;
 
   /* Disable the Peripheral */
@@ -545,7 +545,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
     return HAL_TIMEOUT;
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -556,7 +556,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the LPTIM PWM generation in interrupt mode.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF
+  *         This parameter must be a value between 0x0001 and 0xFFFF
   * @param  Pulse Specifies the compare value.
   *         This parameter must be a value between 0x0000 and 0xFFFF
   * @retval HAL status
@@ -634,7 +634,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -651,7 +651,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
 
-  /* Set the LPTIM state */
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_BUSY;
 
   /* Disable the Peripheral */
@@ -681,7 +681,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -692,7 +692,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the LPTIM One pulse generation.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @param  Pulse Specifies the compare value.
   *         This parameter must be a value between 0x0000 and 0xFFFF.
   * @retval HAL status
@@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
   /* Start timer in single (one shot) mode */
   __HAL_LPTIM_START_SINGLE(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -768,7 +768,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
     return HAL_TIMEOUT;
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -779,7 +779,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the LPTIM One pulse generation in interrupt mode.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @param  Pulse Specifies the compare value.
   *         This parameter must be a value between 0x0000 and 0xFFFF.
   * @retval HAL status
@@ -857,7 +857,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
   /* Start timer in single (one shot) mode */
   __HAL_LPTIM_START_SINGLE(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -877,6 +877,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   /* Set the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_BUSY;
 
+
   /* Disable the Peripheral */
   __HAL_LPTIM_DISABLE(hlptim);
 
@@ -904,7 +905,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -915,7 +916,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the LPTIM in Set once mode.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @param  Pulse Specifies the compare value.
   *         This parameter must be a value between 0x0000 and 0xFFFF.
   * @retval HAL status
@@ -963,7 +964,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
   /* Start timer in single (one shot) mode */
   __HAL_LPTIM_START_SINGLE(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -991,7 +992,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
     return HAL_TIMEOUT;
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1080,7 +1081,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
   /* Start timer in single (one shot) mode */
   __HAL_LPTIM_START_SINGLE(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1127,7 +1128,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
     __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG);
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1138,7 +1139,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the Encoder interface.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1188,7 +1189,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1219,7 +1220,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
   /* Reset ENC bit to disable the encoder interface */
   hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1298,7 +1299,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1335,7 +1336,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   /* Disable "switch to up direction" interrupt */
   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1348,7 +1349,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   *         trigger event will reset the counter and the timer restarts.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @param  Timeout Specifies the TimeOut value to reset the counter.
   *         This parameter must be a value between 0x0000 and 0xFFFF.
   * @retval HAL status
@@ -1396,7 +1397,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1427,7 +1428,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
   /* Reset TIMOUT bit to enable the timeout function */
   hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1440,7 +1441,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
   *         trigger event will reset the counter and the timer restarts.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @param  Timeout Specifies the TimeOut value to reset the counter.
   *         This parameter must be a value between 0x0000 and 0xFFFF.
   * @retval HAL status
@@ -1502,7 +1503,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1536,7 +1537,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   /* Disable Compare match interrupt */
   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1547,7 +1548,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the Counter mode.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1587,7 +1588,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1615,7 +1616,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
     return HAL_TIMEOUT;
   }
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1626,7 +1627,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
   * @brief  Start the Counter mode in interrupt mode.
   * @param  hlptim LPTIM handle
   * @param  Period Specifies the Autoreload value.
-  *         This parameter must be a value between 0x0000 and 0xFFFF.
+  *         This parameter must be a value between 0x0001 and 0xFFFF.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period)
@@ -1683,7 +1684,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
   /* Start timer in continuous mode */
   __HAL_LPTIM_START_CONTINUOUS(hlptim);
 
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1716,7 +1717,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
 
   /* Disable Autoreload match interrupt */
   __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
-  /* Change the TIM state*/
+  /* Change the LPTIM state */
   hlptim->State = HAL_LPTIM_STATE_READY;
 
   /* Return function status */
@@ -1747,7 +1748,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
   * @param  hlptim LPTIM handle
   * @retval Counter value.
   */
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
+uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim)
 {
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1760,7 +1761,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
   * @param  hlptim LPTIM handle
   * @retval Autoreload value.
   */
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
+uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim)
 {
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -1773,7 +1774,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
   * @param  hlptim LPTIM handle
   * @retval Compare value.
   */
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
+uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim)
 {
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(hlptim->Instance));
@@ -2068,9 +2069,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hlptim);
-
   if (hlptim->State == HAL_LPTIM_STATE_READY)
   {
     switch (CallbackID)
@@ -2141,9 +2139,6 @@ HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef        *hlptim,
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hlptim);
-
   return status;
 }
 
@@ -2169,47 +2164,53 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlpti
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hlptim);
-
   if (hlptim->State == HAL_LPTIM_STATE_READY)
   {
     switch (CallbackID)
     {
       case HAL_LPTIM_MSPINIT_CB_ID :
-        hlptim->MspInitCallback = HAL_LPTIM_MspInit;                          /* Legacy weak MspInit Callback */
+        /* Legacy weak MspInit Callback */
+        hlptim->MspInitCallback = HAL_LPTIM_MspInit;
         break;
 
       case HAL_LPTIM_MSPDEINIT_CB_ID :
-        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;                       /* Legacy weak Msp DeInit Callback */
+        /* Legacy weak Msp DeInit Callback */
+        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
         break;
 
       case HAL_LPTIM_COMPARE_MATCH_CB_ID :
-        hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;         /* Legacy weak Compare match Callback */
+        /* Legacy weak Compare match Callback */
+        hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
         break;
 
       case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
-        hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;   /* Legacy weak Auto-reload match Callback */
+        /* Legacy weak Auto-reload match Callback */
+        hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
         break;
 
       case HAL_LPTIM_TRIGGER_CB_ID :
-        hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;                   /* Legacy weak External trigger event detection Callback */
+        /* Legacy weak External trigger event detection Callback */
+        hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
         break;
 
       case HAL_LPTIM_COMPARE_WRITE_CB_ID :
-        hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;         /* Legacy weak Compare register write complete Callback */
+        /* Legacy weak Compare register write complete Callback */
+        hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
         break;
 
       case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
-        hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;   /* Legacy weak Auto-reload register write complete Callback */
+        /* Legacy weak Auto-reload register write complete Callback */
+        hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
         break;
 
       case HAL_LPTIM_DIRECTION_UP_CB_ID :
-        hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;           /* Legacy weak Up-counting direction change Callback */
+        /* Legacy weak Up-counting direction change Callback */
+        hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
         break;
 
       case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
-        hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;       /* Legacy weak Down-counting direction change Callback */
+        /* Legacy weak Down-counting direction change Callback */
+        hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
         break;
 
       default :
@@ -2223,11 +2224,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlpti
     switch (CallbackID)
     {
       case HAL_LPTIM_MSPINIT_CB_ID :
-        hlptim->MspInitCallback = HAL_LPTIM_MspInit;                           /* Legacy weak MspInit Callback */
+        /* Legacy weak MspInit Callback */
+        hlptim->MspInitCallback = HAL_LPTIM_MspInit;
         break;
 
       case HAL_LPTIM_MSPDEINIT_CB_ID :
-        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;                        /* Legacy weak Msp DeInit Callback */
+        /* Legacy weak Msp DeInit Callback */
+        hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
         break;
 
       default :
@@ -2242,9 +2245,6 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlpti
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hlptim);
-
   return status;
 }
 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@@ -2272,7 +2272,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef        *hlpti
   * @param  hlptim LPTIM handle
   * @retval HAL state
   */
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim)
 {
   /* Return LPTIM handle state */
   return hlptim->State;
@@ -2302,13 +2302,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
 static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
 {
   /* Reset the LPTIM callback to the legacy weak callbacks */
-  lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;    /* Compare match Callback                       */
-  lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback                   */
-  lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;         /* External trigger event detection Callback    */
-  lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;    /* Compare register write complete Callback     */
-  lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
-  lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;     /* Up-counting direction change Callback        */
-  lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;   /* Down-counting direction change Callback      */
+  lptim->CompareMatchCallback    = HAL_LPTIM_CompareMatchCallback;
+  lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+  lptim->TriggerCallback         = HAL_LPTIM_TriggerCallback;
+  lptim->CompareWriteCallback    = HAL_LPTIM_CompareWriteCallback;
+  lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+  lptim->DirectionUpCallback     = HAL_LPTIM_DirectionUpCallback;
+  lptim->DirectionDownCallback   = HAL_LPTIM_DirectionDownCallback;
 }
 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
 
@@ -2319,7 +2319,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
   * @param  flag   The lptim flag
   * @retval HAL status
   */
-static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
+static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag)
 {
   HAL_StatusTypeDef result = HAL_OK;
   uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
@@ -2351,9 +2351,12 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
   uint32_t tmpCFGR;
   uint32_t tmpCMP;
   uint32_t tmpARR;
+  uint32_t primask_bit;
   uint32_t tmpCFGR2;
 
-  __disable_irq();
+  /* Enter critical section */
+  primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1) ;
 
   /*********** Save LPTIM Config ***********/
   /* Save LPTIM source clock */
@@ -2519,7 +2522,8 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
   hlptim->Instance->CFGR = tmpCFGR;
   hlptim->Instance->CFGR2 = tmpCFGR2;
 
-  __enable_irq();
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
 }
 /**
   * @}
@@ -2534,5 +2538,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h
index 7275614e9a..59517aa1ce 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -96,30 +95,30 @@ typedef struct
   */
 typedef struct
 {
-  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
+  LPTIM_ClockConfigTypeDef     Clock;             /*!< Specifies the clock parameters */
 
-  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
+  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
 
-  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
+  LPTIM_TriggerConfigTypeDef   Trigger;           /*!< Specifies the Trigger parameters */
 
-  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
-                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */
+  uint32_t                     OutputPolarity;    /*!< Specifies the Output polarity.
+                                                  This parameter can be a value of @ref LPTIM_Output_Polarity */
 
-  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
-                                                    values is done immediately or after the end of current period.
-                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */
+  uint32_t                     UpdateMode;        /*!< Specifies whether the update of the autoreload and the compare
+                                                  values is done immediately or after the end of current period.
+                                                  This parameter can be a value of @ref LPTIM_Updating_Mode */
 
-  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
-                                                    or each external event.
-                                                    This parameter can be a value of @ref LPTIM_Counter_Source */
+  uint32_t                     CounterSource;     /*!< Specifies whether the counter is incremented each internal event
+                                                  or each external event.
+                                                  This parameter can be a value of @ref LPTIM_Counter_Source */
 
-  uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
-                                                    This parameter can be a value of @ref LPTIM_Input1_Source */
+  uint32_t                     Input1Source;      /*!< Specifies source selected for input1 (GPIO or comparator output).
+                                                  This parameter can be a value of @ref LPTIM_Input1_Source */
 
-  uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
-                                                    Note: This parameter is used only for encoder feature so is used only
-                                                    for LPTIM1 instance.
-                                                    This parameter can be a value of @ref LPTIM_Input2_Source */
+  uint32_t                     Input2Source;      /*!< Specifies source selected for input2 (GPIO or comparator output).
+                                                  Note: This parameter is used only for encoder feature so is used only
+                                                  for LPTIM1 instance.
+                                                  This parameter can be a value of @ref LPTIM_Input2_Source */
 } LPTIM_InitTypeDef;
 
 /**
@@ -437,6 +436,7 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   * @brief  Write the passed parameter in the Autoreload register.
   * @param  __HANDLE__ LPTIM handle
   * @param  __VALUE__ Autoreload value
+  *         This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF.
   * @retval None
   * @note   The ARR register can only be modified when the LPTIM instance is enabled.
   */
@@ -620,9 +620,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
   * @{
   */
 /* Reading operation functions ************************************************/
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim);
+uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim);
 /**
   * @}
   */
@@ -658,7 +658,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_
   * @{
   */
 /* Peripheral State functions  ************************************************/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim);
 /**
   * @}
   */
@@ -751,11 +751,10 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
 #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
                                                  ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
 
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFUL)
-
 #define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
 
-#define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFFUL)
+#define IS_LPTIM_PERIOD(__PERIOD__)             ((0x00000001UL <= (__PERIOD__)) &&\
+                                                 ((__PERIOD__) <= 0x0000FFFFUL))
 
 #define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
 
@@ -808,5 +807,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
 #endif
 
 #endif /* STM32H7xx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.c
index 0258304e1e..80fe3ad953 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State and Errors functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -146,17 +157,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -178,6 +178,13 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+/** @defgroup LTDC_Private_Define LTDC Private Define
+  * @{
+  */
+#define LTDC_TIMEOUT_VALUE ((uint32_t)100U)  /* 100ms */
+/**
+  * @}
+  */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -211,7 +218,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
   */
 HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
 {
-  uint32_t tmp, tmp1;
+  uint32_t tmp;
+  uint32_t tmp1;
 
   /* Check the LTDC peripheral state */
   if (hltdc == NULL)
@@ -320,6 +328,44 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc)
 
 HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc)
 {
+  uint32_t tickstart;
+
+  /* Check the LTDC peripheral state */
+  if (hltdc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check function parameters */
+  assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance));
+
+  /* Disable LTDC Layer 1 */
+  __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1);
+
+#if defined(LTDC_Layer2_BASE)
+  /* Disable LTDC Layer 2 */
+  __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2);
+#endif /* LTDC_Layer2_BASE */
+
+  /* Reload during vertical blanking period */
+  __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait for VSYNC Interrupt */
+  while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U)
+  {
+    /* Check for the Timeout */
+    if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE)
+    {
+      break;
+    }
+  }
+
+  /* Disable LTDC  */
+  __HAL_LTDC_DISABLE(hltdc);
+
 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
   if (hltdc->MspDeInitCallback == NULL)
   {
@@ -391,7 +437,8 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc)
   * @param pCallback pointer to the Callback function
   * @retval status
   */
-HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+                                            pLTDC_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -473,7 +520,7 @@ HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_
 
 /**
   * @brief  Unregister an LTDC Callback
-  *         LTDC callabck is redirected to the weak predefined callback
+  *         LTDC callback is redirected to the weak predefined callback
   * @param hltdc ltdc handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -508,7 +555,7 @@ HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTD
         break;
 
       case HAL_LTDC_MSPINIT_CB_ID :
-        hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback     */
+        hltdc->MspInitCallback = HAL_LTDC_MspInit;                  /* Legcay weak MspInit Callback  */
         break;
 
       case HAL_LTDC_MSPDEINIT_CB_ID :
@@ -887,11 +934,13 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT
   {
     if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44)
     {
-      tmp  = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+      tmp  = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
     }
     else
     {
-      tmp  = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
+      tmp  = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \
+              ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U));
     }
 
     pcolorlut++;
@@ -1345,12 +1394,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
 }
 
 /**
-  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
-  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
-  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
-  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
-  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
-  *         configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+  *         that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+  *         layer for which we want to read and display on screen only a portion 320x240 taken in the center
+  *         of the buffer.
+  *         The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous
+  *         call to HAL_LTDC_ConfigLayer().
+  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+  *         pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
   * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
   *                            the configuration information for the LTDC.
   * @param  LinePitchInPixels  New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
@@ -1504,7 +1555,8 @@ HAL_StatusTypeDef  HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp
   *                    LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+                                                uint32_t LayerIdx)
 {
   /* Check the parameters */
   assert_param(IS_LTDC_LAYER(LayerIdx));
@@ -1553,7 +1605,8 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_
   *                   LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
   * @retval  HAL status
   */
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+                                                  uint32_t LayerIdx)
 {
   LTDC_LayerCfgTypeDef *pLayerCfg;
 
@@ -1607,7 +1660,8 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin
   *                         LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1)
   * @retval  HAL status
   */
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+                                                      uint32_t LayerIdx)
 {
   LTDC_LayerCfgTypeDef *pLayerCfg;
 
@@ -1774,12 +1828,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32
 }
 
 /**
-  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
-  *         larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
-  *         want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
-  *         will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
-  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
-  *         configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
+  * @brief  Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width
+  *         that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to
+  *         layer for which we want to read and display on screen only a portion 320x240 taken in the center
+  *         of the buffer.
+  *         The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by
+  *         previous call to HAL_LTDC_ConfigLayer().
+  * @note   This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default
+  *         pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
   *         Variant of the function HAL_LTDC_SetPitch without immediate reload.
   * @param  hltdc              pointer to a LTDC_HandleTypeDef structure that contains
   *                            the configuration information for the LTDC.
@@ -2082,7 +2138,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
   /* Configure the horizontal start and stop position */
   tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U);
   LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS);
-  LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
+  LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \
+                                         ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp);
 
   /* Configure the vertical start and stop position */
   tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U);
@@ -2097,7 +2154,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
   tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U);
   tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U);
   tmp2 = (pLayerCfg->Alpha0 << 24U);
-  LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA);
+  LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED |
+                                         LTDC_LxDCCR_DCALPHA);
   LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2);
 
   /* Specifies the constant alpha value */
@@ -2134,7 +2192,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
 
   /* Configure the color frame buffer pitch in byte */
   LTDC_LAYER(hltdc, LayerIdx)->CFBLR  &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP);
-  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 7U));
+  LTDC_LAYER(hltdc, LayerIdx)->CFBLR  = (((pLayerCfg->ImageWidth * tmp) << 16U) |
+                                         (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp)  + 7U));
   /* Configure the frame buffer line number */
   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  &= ~(LTDC_LxCFBLNR_CFBLNBR);
   LTDC_LAYER(hltdc, LayerIdx)->CFBLNR  = (pLayerCfg->ImageHeight);
@@ -2160,4 +2219,3 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.h
index 3785b57ed3..d5b4a665b3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -80,28 +79,36 @@ typedef struct
                                                       This parameter can be one of value of @ref LTDC_PC_POLARITY */
 
   uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.
-                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = 0x000 and Max_Data = 0xFFF. */
 
   uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.
-                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = 0x000 and Max_Data = 0x7FF. */
 
   uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.
-                                                      This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
 
   uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.
-                                                      This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
 
   uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.
-                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
 
   uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.
-                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
 
   uint32_t            TotalWidth;                /*!< configures the total width.
-                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
 
   uint32_t            TotalHeigh;                /*!< configures the total height.
-                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
+                                                      This parameter must be a number between
+                                                      Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
 
   LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */
 } LTDC_InitTypeDef;
@@ -112,25 +119,31 @@ typedef struct
 typedef struct
 {
   uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.
-                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
 
   uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.
-                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0xFFF. */
 
   uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.
-                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
 
   uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.
-                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x7FF. */
 
   uint32_t PixelFormat;                /*!< Specifies the pixel format.
                                             This parameter can be one of value of @ref LTDC_Pixelformat */
 
   uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.
-                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
 
   uint32_t Alpha0;                     /*!< Configures the default alpha value.
-                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x00 and Max_Data = 0xFF. */
 
   uint32_t BlendingFactor1;            /*!< Select the blending factor 1.
                                             This parameter can be one of value of @ref LTDC_BlendingFactor1 */
@@ -141,10 +154,12 @@ typedef struct
   uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */
 
   uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.
-                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x0000 and Max_Data = 0x1FFF. */
 
   uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.
-                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
+                                            This parameter must be a number between
+                                            Min_Data = 0x000 and Max_Data = 0x7FF. */
 
   LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */
 } LTDC_LayerCfgTypeDef;
@@ -323,14 +338,14 @@ typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer
 /** @defgroup LTDC_Pixelformat LTDC Pixel format
   * @{
   */
-#define LTDC_PIXEL_FORMAT_ARGB8888        0x00000000U   /*!< ARGB8888 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_RGB888          0x00000001U   /*!< RGB888 LTDC pixel format   */
-#define LTDC_PIXEL_FORMAT_RGB565          0x00000002U   /*!< RGB565 LTDC pixel format   */
-#define LTDC_PIXEL_FORMAT_ARGB1555        0x00000003U   /*!< ARGB1555 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_ARGB4444        0x00000004U   /*!< ARGB4444 LTDC pixel format */
-#define LTDC_PIXEL_FORMAT_L8              0x00000005U   /*!< L8 LTDC pixel format       */
-#define LTDC_PIXEL_FORMAT_AL44            0x00000006U   /*!< AL44 LTDC pixel format     */
-#define LTDC_PIXEL_FORMAT_AL88            0x00000007U   /*!< AL88 LTDC pixel format     */
+#define LTDC_PIXEL_FORMAT_ARGB8888        0x00000000U   /*!< ARGB8888 LTDC pixel format             */
+#define LTDC_PIXEL_FORMAT_RGB888          0x00000001U   /*!< RGB888 LTDC pixel format               */
+#define LTDC_PIXEL_FORMAT_RGB565          0x00000002U   /*!< RGB565 LTDC pixel format               */
+#define LTDC_PIXEL_FORMAT_ARGB1555        0x00000003U   /*!< ARGB1555 LTDC pixel format             */
+#define LTDC_PIXEL_FORMAT_ARGB4444        0x00000004U   /*!< ARGB4444 LTDC pixel format             */
+#define LTDC_PIXEL_FORMAT_L8              0x00000005U   /*!< L8 LTDC pixel format                   */
+#define LTDC_PIXEL_FORMAT_AL44            0x00000006U   /*!< AL44 LTDC pixel format                 */
+#define LTDC_PIXEL_FORMAT_AL88            0x00000007U   /*!< AL88 LTDC pixel format                 */
 /**
   * @}
   */
@@ -400,7 +415,7 @@ typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer
   * @retval None
   */
 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
                                                       (__HANDLE__)->State = HAL_LTDC_STATE_RESET;     \
                                                       (__HANDLE__)->MspInitCallback = NULL;           \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \
@@ -430,7 +445,8 @@ typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer
   *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
   * @retval None.
   */
-#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+                                                         |= (uint32_t)LTDC_LxCR_LEN)
 
 /**
   * @brief  Disable the LTDC Layer.
@@ -439,7 +455,8 @@ typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer
   *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
   * @retval None.
   */
-#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\
+                                                         &= ~(uint32_t)LTDC_LxCR_LEN)
 
 /**
   * @brief  Reload immediately all LTDC Layers.
@@ -545,7 +562,8 @@ void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID,
+                                            pLTDC_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
 
@@ -583,9 +601,12 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t
 HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
 HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
 HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
-HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
-HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg,
+                                                uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize,
+                                                  uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0,
+                                                      uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
@@ -621,12 +642,18 @@ uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
 /** @defgroup LTDC_Private_Macros LTDC Private Macros
   * @{
   */
-#define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
+#define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(\
+                                                                               ((uint32_t)((__HANDLE__)->Instance))\
+                                                                               + 0x84U + (0x80U*(__LAYER__)))))
 #define IS_LTDC_LAYER(__LAYER__)                       ((__LAYER__) < MAX_LAYER)
-#define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
-#define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
-#define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))
-#define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))
+#define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL)\
+                                                        || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
+#define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL)\
+                                                        || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
+#define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL)\
+                                                        || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))
+#define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\
+                                                        || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))
 #define IS_LTDC_HSYNC(__HSYNC__)                       ((__HSYNC__)  <= LTDC_HORIZONTALSYNC)
 #define IS_LTDC_VSYNC(__VSYNC__)                       ((__VSYNC__)  <= LTDC_VERTICALSYNC)
 #define IS_LTDC_AHBP(__AHBP__)                         ((__AHBP__)   <= LTDC_HORIZONTALSYNC)
@@ -642,10 +669,14 @@ uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
                                                         ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
 #define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
                                                         ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
-#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)         (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
-                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
-                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
-                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)         (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || \
+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
 #define IS_LTDC_ALPHA(__ALPHA__)                       ((__ALPHA__) <= LTDC_ALPHA)
 #define IS_LTDC_HCONFIGST(__HCONFIGST__)               ((__HCONFIGST__) <= LTDC_STARTPOSITION)
 #define IS_LTDC_HCONFIGSP(__HCONFIGSP__)               ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
@@ -655,7 +686,8 @@ uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
 #define IS_LTDC_CFBLL(__CFBLL__)                       ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
 #define IS_LTDC_CFBLNBR(__CFBLNBR__)                   ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
 #define IS_LTDC_LIPOS(__LIPOS__)                       ((__LIPOS__) <= 0x7FFU)
-#define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
+#define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \
+                                                        ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
 /**
   * @}
   */
@@ -685,4 +717,3 @@ uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
 
 #endif /* STM32H7xx_HAL_LTDC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.c
index d53d698299..2ffdb1d992 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -75,21 +74,26 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc
   /* The following polarity is inverted:
                      LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
 
+#if !defined(POLARITIES_INVERSION_UPDATED)
   /* Note 1 : Code in line w/ Current LTDC specification */
-  hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+  hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \
+                            DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
   hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
   hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
-
+#else
   /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
-  /* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
-     hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
-     hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
+  hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
+  hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
+  hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29;
+#endif /* POLARITIES_INVERSION_UPDATED */
 
   /* Retrieve vertical timing parameters from DSI */
   hltdc->Init.VerticalSync       = VidCfg->VerticalSyncActive - 1U;
   hltdc->Init.AccumulatedVBP     = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
-  hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
-  hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
+  hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+                                   VidCfg->VerticalActive - 1U;
+  hltdc->Init.TotalHeigh         = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \
+                                   VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
 
   return HAL_OK;
 }
@@ -113,16 +117,18 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
                      LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
                      LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
 
+#if !defined(POLARITIES_INVERSION_UPDATED)
   /* Note 1 : Code in line w/ Current LTDC specification */
-  hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
+  hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \
+                            DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
   hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
   hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
-
+#else
   /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
-  /* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
-     hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
-     hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
-
+  hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
+  hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
+  hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29;
+#endif /* POLARITIES_INVERSION_UPDATED */
   return HAL_OK;
 }
 
@@ -146,4 +152,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.h
index f95a18c09c..15e9adf7b5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ltdc_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -82,5 +81,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD
 #endif
 
 #endif /* STM32H7xx_HAL_LTDC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c
index 834ffeb11e..dc7b722acf 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -112,18 +123,6 @@
 
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -143,18 +142,29 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Define MDIOS Private Define
+  * @{
+  */
 #define MDIOS_PORT_ADDRESS_SHIFT        ((uint32_t)8)
 #define  MDIOS_ALL_REG_FLAG             ((uint32_t)0xFFFFFFFFU)
 #define  MDIOS_ALL_ERRORS_FLAG          ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
 
 #define MDIOS_DIN_BASE_ADDR             (MDIOS_BASE + 0x100U)
 #define MDIOS_DOUT_BASE_ADDR            (MDIOS_BASE + 0x180U)
-
+/**
+  * @}
+  */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
+  * @{
+  */
 static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios);
+/**
+  * @}
+  */
 #endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
 /* Private functions ---------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
@@ -435,7 +445,7 @@ HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MD
 
 /**
   * @brief  Unregister an MDIOS Callback
-  *         MDIOS callabck is redirected to the weak predefined callback
+  *         MDIOS callback is redirected to the weak predefined callback
   * @param hmdios mdios handle
   * @param CallbackID ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -932,6 +942,9 @@ HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
   */
 
 #if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
+/** @addtogroup MDIOS_Private_Functions
+  * @{
+  */
 static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
 {
   /* Init the MDIOS Callback settings */
@@ -940,11 +953,10 @@ static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
   hmdios->ErrorCallback      = HAL_MDIOS_ErrorCallback;       /* Legacy weak ErrorCallback */
   hmdios->WakeUpCallback     = HAL_MDIOS_WakeUpCallback;        /* Legacy weak WakeUpCallback   */
 }
-#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
-
 /**
   * @}
   */
+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
 #endif /* HAL_MDIOS_MODULE_ENABLED */
 /**
   * @}
@@ -954,4 +966,3 @@ static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.h
index f4954b47be..50c61f41d1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -607,4 +606,3 @@ HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
 
 #endif /* STM32H7xx_HAL_MDIOS_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c
index 1ce7664b28..089d9fbb1d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c
@@ -7,6 +7,17 @@
   *           + Initialization/de-initialization functions
   *           + I/O operation functions
   *           + Peripheral State and errors functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -132,19 +143,7 @@
 
     [..]
 
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
+  @endverbatim
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -1898,4 +1897,3 @@ static void MDMA_Init(MDMA_HandleTypeDef *hmdma)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h
index 2e5f8e1111..a39cc0d755 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -867,4 +866,3 @@ uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
 
 #endif /* STM32H7xx_HAL_MDMA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c
index 07ec0b24de..199b4592c0 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + MMC card Control functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -53,7 +64,7 @@
     SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer).
     This function provide the following operations:
 
-    (#) Initialize the SDMMC peripheral interface with defaullt configuration.
+    (#) Initialize the SDMMC peripheral interface with default configuration.
         The initialization process is done at 400KHz. You can change or adapt
         this frequency by adjusting the "ClockDiv" field.
         The MMC Card frequency (SDMMC_CK) is computed as follows:
@@ -177,7 +188,7 @@
     The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
 
-    Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback,
+    Use Functions HAL_MMC_RegisterCallback() to register a user callback,
     it allows to register following callbacks:
       (+) TxCpltCallback : callback when a transmission transfer is completed.
       (+) RxCpltCallback : callback when a reception transfer is completed.
@@ -192,7 +203,7 @@
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
 
-    Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default
+    Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default
     weak (surcharged) function. It allows to reset following callbacks:
       (+) TxCpltCallback : callback when a transmission transfer is completed.
       (+) RxCpltCallback : callback when a reception transfer is completed.
@@ -206,12 +217,12 @@
       (+) MspDeInitCallback  : MMC MspDeInit.
     This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-    By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
+    By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET
     all callbacks are reset to the corresponding legacy weak (surcharged) functions.
     Exception done for MspInit and MspDeInit callbacks that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init
-    and @ref  HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit
+    reset to the legacy weak (surcharged) functions in the HAL_MMC_Init
+    and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
     Callbacks can be registered/unregistered in READY state only.
@@ -219,8 +230,8 @@
     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
     during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit
-    or @ref HAL_MMC_Init function.
+    using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit
+    or HAL_MMC_Init function.
 
     When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registering feature is not available
@@ -228,17 +239,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -261,7 +261,7 @@
   * @{
   */
 #if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
-#define MMC_VOLTAGE_RANGE               MMC_LOW_VOLTAGE_RANGE
+#define MMC_VOLTAGE_RANGE               EMMC_LOW_VOLTAGE_RANGE
 
 #define MMC_EXT_CSD_PWR_CL_26_INDEX     201
 #define MMC_EXT_CSD_PWR_CL_52_INDEX     200
@@ -271,7 +271,7 @@
 #define MMC_EXT_CSD_PWR_CL_52_POS       0
 #define MMC_EXT_CSD_PWR_CL_DDR_52_POS   16
 #else
-#define MMC_VOLTAGE_RANGE               MMC_HIGH_VOLTAGE_RANGE
+#define MMC_VOLTAGE_RANGE               EMMC_HIGH_VOLTAGE_RANGE
 
 #define MMC_EXT_CSD_PWR_CL_26_INDEX     203
 #define MMC_EXT_CSD_PWR_CL_52_INDEX     202
@@ -280,10 +280,15 @@
 #define MMC_EXT_CSD_PWR_CL_26_POS       24
 #define MMC_EXT_CSD_PWR_CL_52_POS       16
 #define MMC_EXT_CSD_PWR_CL_DDR_52_POS   24
-#endif
+#endif /* (VDD_VALUE) && (VDD_VALUE <= 1950U)*/
+
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX 216
+#define MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS   0
+#define MMC_EXT_CSD_S_A_TIMEOUT_INDEX             217
+#define MMC_EXT_CSD_S_A_TIMEOUT_POS               8
 
 /* Frequencies used in the driver for clock divider calculation */
-#define MMC_INIT_FREQ                   400000U   /* Initalization phase : 400 kHz max */
+#define MMC_INIT_FREQ                   400000U   /* Initialization phase : 400 kHz max */
 #define MMC_HIGH_SPEED_FREQ             52000000U /* High speed phase : 52 MHz max */
 /**
   * @}
@@ -378,7 +383,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
 #else
     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
     HAL_MMC_MspInit(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
   }
 
   hmmc->State = HAL_MMC_STATE_BUSY;
@@ -451,8 +456,15 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc)
 
   /* wait 74 Cycles: required power up waiting time before starting
      the MMC initialization sequence */
-  sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
-  HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  if (Init.ClockDiv != 0U)
+  {
+    sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  }
+
+  if (sdmmc_clk != 0U)
+  {
+    HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  }
 
   /* Identify card operating voltage */
   errorstate = MMC_PowerON(hmmc);
@@ -518,7 +530,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
 #else
   /* De-Initialize the MSP layer */
   HAL_MMC_MspDeInit(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
 
   hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
   hmmc->State = HAL_MMC_STATE_RESET;
@@ -589,12 +601,15 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
-                                     uint32_t NumberOfBlocks, uint32_t Timeout)
+                                     uint32_t NumberOfBlocks,
+                                     uint32_t Timeout)
 {
   SDMMC_DataInitTypeDef config;
   uint32_t errorstate;
   uint32_t tickstart = HAL_GetTick();
-  uint32_t count, data, dataremaining;
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
   uint32_t add = BlockAdd;
   uint8_t *tempbuff = pData;
 
@@ -615,7 +630,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
     }
 
     /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
-    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
+         & 0x000000FFU) != 0x0U)
     {
       if ((NumberOfBlocks % 8U) != 0U)
       {
@@ -781,15 +797,17 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
   * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
                                       uint32_t NumberOfBlocks, uint32_t Timeout)
 {
   SDMMC_DataInitTypeDef config;
   uint32_t errorstate;
   uint32_t tickstart = HAL_GetTick();
-  uint32_t count, data, dataremaining;
+  uint32_t count;
+  uint32_t data;
+  uint32_t dataremaining;
   uint32_t add = BlockAdd;
-  uint8_t *tempbuff = pData;
+  const uint8_t *tempbuff = pData;
 
   if (NULL == pData)
   {
@@ -975,8 +993,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
   * @param  NumberOfBlocks: Number of blocks to read.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
-                                        uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                        uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
   uint32_t errorstate;
@@ -1088,7 +1106,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
   * @param  NumberOfBlocks: Number of blocks to write
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
                                          uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -1202,8 +1220,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
   * @param  NumberOfBlocks: Number of blocks to read.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
-                                         uint32_t BlockAdd, uint32_t NumberOfBlocks)
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                         uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
   uint32_t errorstate;
@@ -1317,7 +1335,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
   * @param  NumberOfBlocks: Number of blocks to write
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData,
                                           uint32_t BlockAdd, uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -1452,7 +1470,8 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
     }
 
     /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */
-    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U)
+    if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS)
+         & 0x000000FFU) != 0x0U)
     {
       if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U))
       {
@@ -1576,7 +1595,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
           hmmc->ErrorCallback(hmmc);
 #else
           HAL_MMC_ErrorCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
         }
       }
 
@@ -1590,7 +1609,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->TxCpltCallback(hmmc);
 #else
         HAL_MMC_TxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
       if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
       {
@@ -1598,7 +1617,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->RxCpltCallback(hmmc);
 #else
         HAL_MMC_RxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
     }
     else if ((context & MMC_CONTEXT_IT) != 0U)
@@ -1614,7 +1633,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
           hmmc->ErrorCallback(hmmc);
 #else
           HAL_MMC_ErrorCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
         }
       }
 
@@ -1628,7 +1647,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->RxCpltCallback(hmmc);
 #else
         HAL_MMC_RxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
       else
       {
@@ -1636,7 +1655,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->TxCpltCallback(hmmc);
 #else
         HAL_MMC_TxCpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
     }
     else
@@ -1730,7 +1749,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->Write_DMADblBuf1CpltCallback(hmmc);
 #else
         HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
       else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
       {
@@ -1738,7 +1757,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->Read_DMADblBuf1CpltCallback(hmmc);
 #else
         HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
     }
     else /* MMC_DMA_BUFFER1 */
@@ -1750,7 +1769,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->Write_DMADblBuf0CpltCallback(hmmc);
 #else
         HAL_MMCEx_Write_DMADoubleBuf0CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
       else /* MMC_CONTEXT_READ_MULTIPLE_BLOCK */
       {
@@ -1758,7 +1777,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
         hmmc->Read_DMADblBuf0CpltCallback(hmmc);
 #else
         HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
       }
     }
   }
@@ -1854,6 +1873,9 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
 /**
   * @brief  Register a User MMC Callback
   *         To be used instead of the weak (surcharged) predefined callback
+  * @note   The HAL_MMC_RegisterCallback() may be called before HAL_MMC_Init() in 
+  *         HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID 
+  *         and HAL_MMC_MSP_DEINIT_CB_ID.
   * @param hmmc : MMC handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -1882,9 +1904,6 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hmmc);
-
   if (hmmc->State == HAL_MMC_STATE_READY)
   {
     switch (CallbackId)
@@ -1953,14 +1972,15 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hmmc);
   return status;
 }
 
 /**
   * @brief  Unregister a User MMC Callback
   *         MMC Callback is redirected to the weak (surcharged) predefined callback
+  * @note   The HAL_MMC_UnRegisterCallback() may be called before HAL_MMC_Init() in 
+  *         HAL_MMC_STATE_RESET to register callbacks for HAL_MMC_MSP_INIT_CB_ID 
+  *         and HAL_MMC_MSP_DEINIT_CB_ID.
   * @param hmmc : MMC handle
   * @param CallbackId : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -1980,9 +2000,6 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hmmc);
-
   if (hmmc->State == HAL_MMC_STATE_READY)
   {
     switch (CallbackId)
@@ -2051,11 +2068,9 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hmmc);
   return status;
 }
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -2285,7 +2300,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC
 
     /* Configure the MMC DPSM (Data Path State Machine) */
     config.DataTimeOut   = SDMMC_DATATIMEOUT;
-    config.DataLength    = 512;
+    config.DataLength    = 512U;
     config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
     config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
     config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
@@ -2681,35 +2696,90 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
   */
 HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
 {
-  HAL_MMC_CardStateTypeDef CardState;
+  uint32_t error_code;
+  uint32_t tickstart;
 
-  /* DIsable All interrupts */
-  __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
-                       SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
-
-  /* Clear All flags */
-  __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
-
-  /* If IDMA Context, disable Internal DMA */
-  hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
-  hmmc->State = HAL_MMC_STATE_READY;
-
-  /* Initialize the MMC operation */
-  hmmc->Context = MMC_CONTEXT_NONE;
-
-  CardState = HAL_MMC_GetCardState(hmmc);
-  if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
+  if (hmmc->State == HAL_MMC_STATE_BUSY)
   {
+    /* DIsable All interrupts */
+    __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                         SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+    __SDMMC_CMDTRANS_DISABLE(hmmc->Instance);
+
+    /*we will send the CMD12 in all cases in order to stop the data transfers*/
+    /*In case the data transfer just finished , the external memory will not respond and will return HAL_MMC_ERROR_CMD_RSP_TIMEOUT*/
+    /*In case the data transfer aborted , the external memory will respond and will return HAL_MMC_ERROR_NONE*/
+    /*Other scenario will return HAL_ERROR*/
+
     hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
-  }
-  if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
-  {
-    return HAL_ERROR;
+    error_code = hmmc->ErrorCode;
+    if ((error_code != HAL_MMC_ERROR_NONE) && (error_code != HAL_MMC_ERROR_CMD_RSP_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+
+    tickstart = HAL_GetTick();
+    if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+    {
+      if (hmmc->ErrorCode == HAL_MMC_ERROR_NONE)
+      {
+         while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+        {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+              hmmc->State = HAL_MMC_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+        }
+      }
+
+      if (hmmc->ErrorCode == HAL_MMC_ERROR_CMD_RSP_TIMEOUT)
+      {
+        while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND))
+        {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+              hmmc->State = HAL_MMC_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+        }
+      }
+    }
+    else if ((hmmc->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+    {
+      while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+      {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hmmc->ErrorCode = HAL_MMC_ERROR_TIMEOUT;
+              hmmc->State = HAL_MMC_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+      }
+    }
+    else
+    {
+      /* Nothing to do*/
+    }
+
+    /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear the appropriate flags that will be set depending of the abort/non abort of the memory */
+    /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared and will result in next SDMMC read/write operation to fail */
+
+    /*SDMMC ready for clear data flags*/
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+    __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+      /* If IDMA Context, disable Internal DMA */
+    hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Initialize the MMC operation */
+    hmmc->Context = MMC_CONTEXT_NONE;
   }
   return HAL_OK;
 }
-
 /**
   * @brief  Abort the current transfer and disable the MMC (IT mode).
   * @param  hmmc: pointer to a MMC_HandleTypeDef structure that contains
@@ -2747,7 +2817,7 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
     hmmc->AbortCpltCallback(hmmc);
 #else
     HAL_MMC_AbortCallback(hmmc);
-#endif
+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
   }
 
   return HAL_OK;
@@ -2905,7 +2975,9 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT
   */
 HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
 {
-  uint32_t errorstate, response = 0U, count;
+  uint32_t errorstate;
+  uint32_t response = 0U;
+  uint32_t count;
   uint32_t tickstart = HAL_GetTick();
 
   /* Check the state of the driver */
@@ -3014,7 +3086,10 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc)
   */
 HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode)
 {
-  uint32_t srt, errorstate, response = 0U, count;
+  uint32_t srt;
+  uint32_t errorstate;
+  uint32_t response = 0U;
+  uint32_t count;
 
   /* Check the erase type value is correct */
   assert_param(IS_MMC_SRT_TYPE(SRTMode));
@@ -3137,6 +3212,343 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui
   }
 }
 
+/**
+  * @brief  Switch the device from Standby State to Sleep State.
+  * @param  hmmc pointer to MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate,
+           sleep_timeout,
+           timeout,
+           count,
+           response = 0U  ;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+    errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+      count = SDMMC_MAX_TRIAL;
+      do
+      {
+        errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+        if (errorstate != HAL_MMC_ERROR_NONE)
+        {
+          break;
+        }
+
+        /* Get command response */
+        response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+        count--;
+      } while (((response & 0x100U) == 0U) && (count != 0U));
+
+      /* Check the status after the switch command execution */
+      if (count == 0U)
+      {
+        errorstate = SDMMC_ERROR_TIMEOUT;
+      }
+      else if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        /* Check the bit SWITCH_ERROR of the device status */
+        if ((response & 0x80U) != 0U)
+        {
+          errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+        }
+        else
+        {
+          /* Set the power-off notification to sleep notification : Ext_CSD[34] = 4 */
+          errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220400U));
+          if (errorstate == HAL_MMC_ERROR_NONE)
+          {
+            /* Field SLEEP_NOTIFICATION_TIME [216] */
+            sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_INDEX / 4)] >>
+                              MMC_EXT_CSD_SLEEP_NOTIFICATION_TIME_POS) & 0x000000FFU);
+
+            /* Sleep/Awake Timeout = 10us * 2^SLEEP_NOTIFICATION_TIME */
+            /* In HAL, the tick interrupt occurs each ms */
+            if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+            {
+              sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+            }
+            timeout = (((1UL << sleep_timeout) / 100U) + 1U);
+
+            /* Wait that the device is ready by checking the D0 line */
+            while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+            {
+              if ((HAL_GetTick() - tickstart) >= timeout)
+              {
+                errorstate = SDMMC_ERROR_TIMEOUT;
+              }
+            }
+
+            /* Clear the flag corresponding to end D0 bus line */
+            __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+            if (errorstate == HAL_MMC_ERROR_NONE)
+            {
+              /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+              count = SDMMC_MAX_TRIAL;
+              do
+              {
+                errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
+                                                 (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+                if (errorstate != HAL_MMC_ERROR_NONE)
+                {
+                  break;
+                }
+
+                /* Get command response */
+                response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+                count--;
+              } while (((response & 0x100U) == 0U) && (count != 0U));
+
+              /* Check the status after the switch command execution */
+              if (count == 0U)
+              {
+                errorstate = SDMMC_ERROR_TIMEOUT;
+              }
+              else if (errorstate == HAL_MMC_ERROR_NONE)
+              {
+                /* Check the bit SWITCH_ERROR of the device status */
+                if ((response & 0x80U) != 0U)
+                {
+                  errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+                }
+                else
+                {
+                  /* Switch the device in stand-by mode */
+                  (void)SDMMC_CmdSelDesel(hmmc->Instance, 0U);
+
+                  /* Field S_A_TIEMOUT [217] */
+                  sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >>
+                                    MMC_EXT_CSD_S_A_TIMEOUT_POS) & 0x000000FFU);
+
+                  /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
+                  /* In HAL, the tick interrupt occurs each ms */
+                  if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+                  {
+                    sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+                  }
+                  timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
+
+                  if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+                  {
+                    /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */
+                    errorstate = SDMMC_CmdSleepMmc(hmmc->Instance,
+                                                   ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U)));
+                    if (errorstate == HAL_MMC_ERROR_NONE)
+                    {
+                      /* Wait that the device is ready by checking the D0 line */
+                      while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+                      {
+                        if ((HAL_GetTick() - tickstart) >= timeout)
+                        {
+                          errorstate = SDMMC_ERROR_TIMEOUT;
+                        }
+                      }
+
+                      /* Clear the flag corresponding to end D0 bus line */
+                      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+                    }
+                  }
+                  else
+                  {
+                    errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+                  }
+                }
+              }
+              else
+              {
+                /* Nothing to do */
+              }
+            }
+          }
+        }
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Switch the device from Sleep State to Standby State.
+  * @param  hmmc pointer to MMC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc)
+{
+  uint32_t errorstate;
+  uint32_t sleep_timeout;
+  uint32_t timeout;
+  uint32_t count;
+  uint32_t response = 0U;
+  uint32_t tickstart = HAL_GetTick();
+
+  /* Check the state of the driver */
+  if (hmmc->State == HAL_MMC_STATE_READY)
+  {
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_BUSY;
+
+    /* Field S_A_TIEMOUT [217] */
+    sleep_timeout = ((hmmc->Ext_CSD[(MMC_EXT_CSD_S_A_TIMEOUT_INDEX / 4)] >> MMC_EXT_CSD_S_A_TIMEOUT_POS) &
+                     0x000000FFU);
+
+    /* Sleep/Awake Timeout = 100ns * 2^S_A_TIMEOUT */
+    /* In HAL, the tick interrupt occurs each ms */
+    if ((sleep_timeout == 0U) || (sleep_timeout > 0x17U))
+    {
+      sleep_timeout = 0x17U; /* Max register value defined is 0x17 */
+    }
+    timeout = (((1UL << sleep_timeout) / 10000U) + 1U);
+
+    /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and AWAKE as argument */
+    errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+    if (errorstate == HAL_MMC_ERROR_NONE)
+    {
+      /* Wait that the device is ready by checking the D0 line */
+      while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE))
+      {
+        if ((HAL_GetTick() - tickstart) >= timeout)
+        {
+          errorstate = SDMMC_ERROR_TIMEOUT;
+        }
+      }
+
+      /* Clear the flag corresponding to end D0 bus line */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END);
+
+      if (errorstate == HAL_MMC_ERROR_NONE)
+      {
+        if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_STANDBY)
+        {
+          /* Switch the device in transfer mode */
+          errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (hmmc->MmcCard.RelCardAdd << 16U));
+          if (errorstate == HAL_MMC_ERROR_NONE)
+          {
+            if (HAL_MMC_GetCardState(hmmc) == HAL_MMC_CARD_TRANSFER)
+            {
+              /* Set the power-off notification to powered-on : Ext_CSD[34] = 1 */
+              errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03220100U));
+              if (errorstate == HAL_MMC_ERROR_NONE)
+              {
+                /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+                count = SDMMC_MAX_TRIAL;
+                do
+                {
+                  errorstate = SDMMC_CmdSendStatus(hmmc->Instance,
+                                                   (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+                  if (errorstate != HAL_MMC_ERROR_NONE)
+                  {
+                    break;
+                  }
+
+                  /* Get command response */
+                  response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+                  count--;
+                } while (((response & 0x100U) == 0U) && (count != 0U));
+
+                /* Check the status after the switch command execution */
+                if (count == 0U)
+                {
+                  errorstate = SDMMC_ERROR_TIMEOUT;
+                }
+                else if (errorstate == HAL_MMC_ERROR_NONE)
+                {
+                  /* Check the bit SWITCH_ERROR of the device status */
+                  if ((response & 0x80U) != 0U)
+                  {
+                    errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+                  }
+                }
+                else
+                {
+                  /* NOthing to do */
+                }
+              }
+            }
+            else
+            {
+              errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+            }
+          }
+        }
+        else
+        {
+          errorstate = SDMMC_ERROR_REQUEST_NOT_APPLICABLE;
+        }
+      }
+    }
+
+    /* Change State */
+    hmmc->State = HAL_MMC_STATE_READY;
+
+    /* Manage errors */
+    if (errorstate != HAL_MMC_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+      hmmc->ErrorCode |= errorstate;
+
+      if (errorstate != HAL_MMC_ERROR_TIMEOUT)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    else
+    {
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
 /**
   * @}
   */
@@ -3267,7 +3679,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
 static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
 {
   __IO uint32_t count = 0U;
-  uint32_t response = 0U, validvoltage = 0U;
+  uint32_t response = 0U;
+  uint32_t validvoltage = 0U;
   uint32_t errorstate;
 
   /* CMD0: GO_IDLE_STATE */
@@ -3376,7 +3789,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
 
   /* Configure the MMC DPSM (Data Path State Machine) */
   config.DataTimeOut   = SDMMC_DATATIMEOUT;
-  config.DataLength    = 512;
+  config.DataLength    = 512U;
   config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
   config.TransferDir   = SDMMC_TRANSFER_DIR_TO_SDMMC;
   config.TransferMode  = SDMMC_TRANSFER_MODE_BLOCK;
@@ -3395,7 +3808,8 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
   }
 
   /* Poll on SDMMC flags */
-  while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+  while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT |
+                             SDMMC_FLAG_DATAEND))
   {
     if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
     {
@@ -3476,7 +3890,8 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel
   */
 static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
 {
-  uint32_t count, data;
+  uint32_t count;
+  uint32_t data;
   uint8_t *tmp;
 
   tmp = hmmc->pRxBuffPtr;
@@ -3510,8 +3925,9 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc)
   */
 static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
 {
-  uint32_t count, data;
-  uint8_t *tmp;
+  uint32_t count;
+  uint32_t data;
+  const uint8_t *tmp;
 
   tmp = hmmc->pTxBuffPtr;
 
@@ -3545,7 +3961,8 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc)
 static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
 {
   uint32_t errorstate = HAL_MMC_ERROR_NONE;
-  uint32_t response = 0U, count;
+  uint32_t response = 0U;
+  uint32_t count;
   uint32_t sdmmc_clk;
   SDMMC_InitTypeDef Init;
 
@@ -3613,13 +4030,21 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
         {
           /* High Speed Clock should be less or equal to 52MHz*/
           sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC);
+
           if (sdmmc_clk == 0U)
           {
             errorstate = SDMMC_ERROR_INVALID_PARAMETER;
           }
           else
           {
-            Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ);
+            if (sdmmc_clk <= MMC_HIGH_SPEED_FREQ)
+            {
+              Init.ClockDiv = 0;
+            }
+            else
+            {
+              Init.ClockDiv = (sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ)) + 1U;
+            }
             (void)SDMMC_Init(hmmc->Instance, Init);
 
             SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED);
@@ -3649,7 +4074,8 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state)
 static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state)
 {
   uint32_t errorstate = HAL_MMC_ERROR_NONE;
-  uint32_t response = 0U, count;
+  uint32_t response = 0U;
+  uint32_t count;
 
   if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) && (state == DISABLE))
   {
@@ -3758,7 +4184,8 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3
   uint32_t count;
   uint32_t response = 0U;
   uint32_t errorstate = HAL_MMC_ERROR_NONE;
-  uint32_t power_class, supported_pwr_class;
+  uint32_t power_class;
+  uint32_t supported_pwr_class;
 
   if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
   {
@@ -3922,5 +4349,3 @@ __weak void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h
index db25542b36..ed4e5e5ade 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -64,15 +63,18 @@ typedef enum
   */
 typedef uint32_t HAL_MMC_CardStateTypeDef;
 
-#define HAL_MMC_CARD_READY          0x00000001U  /*!< Card state is ready                     */
-#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
-#define HAL_MMC_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */
-#define HAL_MMC_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */
-#define HAL_MMC_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */
-#define HAL_MMC_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */
-#define HAL_MMC_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */
-#define HAL_MMC_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */
-#define HAL_MMC_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */
+#define HAL_MMC_CARD_IDLE           0x00000000U  /*!< Card is in idle state (can't be checked by CMD13)           */
+#define HAL_MMC_CARD_READY          0x00000001U  /*!< Card state is ready (can't be checked by CMD13)             */
+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state (can't be checked by CMD13) */
+#define HAL_MMC_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                                    */
+#define HAL_MMC_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state                                   */
+#define HAL_MMC_CARD_SENDING        0x00000005U  /*!< Card is sending an operation                                */
+#define HAL_MMC_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information                     */
+#define HAL_MMC_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state                                */
+#define HAL_MMC_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                                        */
+#define HAL_MMC_CARD_BUSTEST        0x00000009U  /*!< Card is in bus test state                                   */
+#define HAL_MMC_CARD_SLEEP          0x0000000AU  /*!< Card is in sleep state (can't be checked by CMD13)          */
+#define HAL_MMC_CARD_ERROR          0x000000FFU  /*!< Card response Error (can't be checked by CMD13)             */
 /**
   * @}
   */
@@ -119,7 +121,7 @@ typedef struct
 
   HAL_LockTypeDef              Lock;             /*!< MMC locking object                   */
 
-  uint8_t                      *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */
+  const uint8_t                      *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */
 
   uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                 */
 
@@ -342,9 +344,9 @@ typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc);
 #define MMC_HIGH_VOLTAGE_RANGE         0x80FF8000U  /*!< High voltage in byte mode    */
 #define MMC_DUAL_VOLTAGE_RANGE         0x80FF8080U  /*!< Dual voltage in byte mode    */
 #define MMC_LOW_VOLTAGE_RANGE          0x80000080U  /*!< Low voltage in byte mode     */
-#define eMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< High voltage in sector mode  */
-#define eMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< Dual voltage in sector mode  */
-#define eMMC_LOW_VOLTAGE_RANGE         0xC0000080U  /*!< Low voltage in sector mode   */
+#define EMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< High voltage in sector mode  */
+#define EMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< Dual voltage in sector mode  */
+#define EMMC_LOW_VOLTAGE_RANGE         0xC0000080U  /*!< Low voltage in sector mode   */
 #define MMC_INVALID_VOLTAGE_RANGE      0x0001FF01U
 /**
   * @}
@@ -645,19 +647,20 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
   */
 /* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
-                                     uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks,
+                                     uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
                                       uint32_t NumberOfBlocks, uint32_t Timeout);
 HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
 /* Non-Blocking mode: IT */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
                                         uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
                                          uint32_t NumberOfBlocks);
 /* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
                                          uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, const uint8_t *pData, uint32_t BlockAdd,
                                           uint32_t NumberOfBlocks);
 
 void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
@@ -729,6 +732,14 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui
   * @}
   */
 
+/** @defgroup MMC_Exported_Functions_Group8 Peripheral Sleep management
+  * @{
+  */
+HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_AwakeDevice(MMC_HandleTypeDef *hmmc);
+/**
+  * @}
+  */
 /* Private types -------------------------------------------------------------*/
 /** @defgroup MMC_Private_Types MMC Private Types
   * @{
@@ -812,5 +823,3 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui
 
 
 #endif /* STM32H7xx_HAL_MMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c
index f392a54243..10acaf3610 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c
@@ -7,6 +7,17 @@
   *          functionalities of the Secure Digital (MMC) peripheral:
   *           + Extended features functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -20,17 +31,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -351,5 +351,3 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h
index 256f986729..215749583f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -111,5 +110,3 @@ void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);
 
 
 #endif /* STM32H7xx_HAL_MMCEx_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c
index 1b59059c3f..87c492d0f1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c
@@ -6,6 +6,17 @@
   *          This file provides a generic firmware to drive NAND memories mounted
   *          as external device.
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                          ##### How to use this driver #####
@@ -58,25 +69,25 @@
       The compilation define  USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
       allows the user to configure dynamically the driver callbacks.
 
-      Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
+      Use Functions HAL_NAND_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
         (+) MspInitCallback    : NAND MspInit.
         (+) MspDeInitCallback  : NAND MspDeInit.
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
-      Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
+      Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
         (+) MspInitCallback    : NAND MspInit.
         (+) MspDeInitCallback  : NAND MspDeInit.
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-      By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
-      and @ref  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
+      reset to the legacy weak (overridden) functions in the HAL_NAND_Init
+      and  HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
       Callbacks can be registered/unregistered in READY state only.
@@ -84,26 +95,15 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
-      or @ref HAL_NAND_Init function.
+      using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
+      or HAL_NAND_Init function.
 
       When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak (overridden) callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -516,8 +516,8 @@ HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC
   * @param  NumPageToRead  number of pages to read from block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
-                                        uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                        uint8_t *pBuffer, uint32_t NumPageToRead)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -674,8 +674,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT
   * @param  NumPageToRead  number of pages to read from block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
-                                         uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                         uint16_t *pBuffer, uint32_t NumPageToRead)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -842,8 +842,8 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address
   * @param  NumPageToWrite   number of pages to write to block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
-                                         uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                         const uint8_t *pBuffer, uint32_t NumPageToWrite)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -851,7 +851,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
   uint32_t numpageswritten = 0U;
   uint32_t nandaddress;
   uint32_t nbpages = NumPageToWrite;
-  uint8_t *buff = pBuffer;
+  const uint8_t *buff = pBuffer;
 
   /* Check the NAND controller state */
   if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -995,8 +995,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address
   * @param  NumPageToWrite   number of pages to write to block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
-                                          uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                          const uint16_t *pBuffer, uint32_t NumPageToWrite)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -1004,7 +1004,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
   uint32_t numpageswritten = 0U;
   uint32_t nandaddress;
   uint32_t nbpages = NumPageToWrite;
-  uint16_t *buff = pBuffer;
+  const uint16_t *buff = pBuffer;
 
   /* Check the NAND controller state */
   if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1159,8 +1159,8 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres
   * @param  NumSpareAreaToRead Number of spare area to read
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
-                                             uint32_t NumSpareAreaToRead)
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                             uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -1324,7 +1324,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add
   * @param  NumSpareAreaToRead Number of spare area to read
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
                                               uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
 {
   uint32_t index;
@@ -1489,8 +1489,8 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad
   * @param  NumSpareAreaTowrite   number of spare areas to write to block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
-                                              uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                              const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -1499,7 +1499,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
   uint32_t nandaddress;
   uint32_t columnaddress;
   uint32_t nbspare = NumSpareAreaTowrite;
-  uint8_t *buff = pBuffer;
+  const uint8_t *buff = pBuffer;
 
   /* Check the NAND controller state */
   if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1652,8 +1652,8 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad
   * @param  NumSpareAreaTowrite   number of spare areas to write to block
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
-                                               uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                               const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
 {
   uint32_t index;
   uint32_t tickstart;
@@ -1662,7 +1662,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
   uint32_t nandaddress;
   uint32_t columnaddress;
   uint32_t nbspare = NumSpareAreaTowrite;
-  uint16_t *buff = pBuffer;
+  const uint16_t *buff = pBuffer;
 
   /* Check the NAND controller state */
   if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1813,7 +1813,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A
   * @param  pAddress  pointer to NAND address structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
 {
   uint32_t deviceaddress;
 
@@ -1869,7 +1869,7 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
   *           - NAND_VALID_ADDRESS: When the new address is valid address
   *           - NAND_INVALID_ADDRESS: When the new address is invalid address
   */
-uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
+uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
 {
   uint32_t status = NAND_VALID_ADDRESS;
 
@@ -1900,7 +1900,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA
 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User NAND Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hnand : NAND handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -1920,9 +1920,6 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hnand);
-
   if (hnand->State == HAL_NAND_STATE_READY)
   {
     switch (CallbackId)
@@ -1964,14 +1961,12 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hnand);
   return status;
 }
 
 /**
   * @brief  Unregister a User NAND Callback
-  *         NAND Callback is redirected to the weak (surcharged) predefined callback
+  *         NAND Callback is redirected to the weak predefined callback
   * @param hnand : NAND handle
   * @param CallbackId : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -1984,9 +1979,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hnand);
-
   if (hnand->State == HAL_NAND_STATE_READY)
   {
     switch (CallbackId)
@@ -2028,8 +2020,6 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hnand);
   return status;
 }
 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
@@ -2180,7 +2170,7 @@ HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
   *                the configuration information for NAND module.
   * @retval HAL state
   */
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
 {
   return hnand->State;
 }
@@ -2191,7 +2181,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
   *                the configuration information for NAND module.
   * @retval NAND status
   */
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
+uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
 {
   uint32_t data;
   uint32_t deviceaddress;
@@ -2239,5 +2229,3 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
   * @}
   */
 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h
index 3141ec9490..7290893bd4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -105,9 +104,8 @@ typedef struct
   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
                                               parameter is mandatory for some NAND parts after the read
                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
-                                              Example: Toshiba THTH58BYG3S0HBAI6.
                                               This parameter could be ENABLE or DISABLE
-                                              Please check the Read Mode sequnece in the NAND device datasheet */
+                                              Please check the Read Mode sequence in the NAND device datasheet */
 } NAND_DeviceConfigTypeDef;
 
 /**
@@ -127,7 +125,7 @@ typedef struct
 
   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 
-  NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
+  NAND_DeviceConfigTypeDef       Config;     /*!< NAND physical characteristic information structure    */
 
 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
   void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand);               /*!< NAND Msp Init callback              */
@@ -215,27 +213,27 @@ void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 /* IO operation functions  ****************************************************/
 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 
-HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
-                                         uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
-                                          uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                         uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                          const uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
                                               uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
-                                               uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                               const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 
-HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
-                                          uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
-                                           uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                          uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                           const uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
                                                uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
-                                                uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
+                                                const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 
-HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress);
 
-uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+uint32_t           HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 
 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 /* NAND callback registering/unregistering */
@@ -265,8 +263,8 @@ HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
   * @{
   */
 /* NAND State functions *******************************************************/
-HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand);
+uint32_t              HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand);
 /**
   * @}
   */
@@ -324,8 +322,10 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
   * @retval NAND Raw address value
   */
 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
-                                                 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \
-                                                 ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+                                                 (((__ADDRESS__)->Block + \
+                                                   (((__ADDRESS__)->Plane) * \
+                                                    ((__HANDLE__)->Config.PlaneSize))) * \
+                                                  ((__HANDLE__)->Config.BlockSize)))
 
 /**
   * @brief  NAND memory Column address computation.
@@ -374,5 +374,3 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 #endif
 
 #endif /* STM32H7xx_HAL_NAND_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c
index 1fab108671..71a7669b41 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c
@@ -6,6 +6,17 @@
   *          This file provides a generic firmware to drive NOR memories mounted
   *          as external device.
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -55,25 +66,25 @@
       The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
       allows the user to configure dynamically the driver callbacks.
 
-      Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+      Use Functions HAL_NOR_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
         (+) MspInitCallback    : NOR MspInit.
         (+) MspDeInitCallback  : NOR MspDeInit.
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
-      Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
+      Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
         (+) MspInitCallback    : NOR MspInit.
         (+) MspDeInitCallback  : NOR MspDeInit.
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-      By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
-      and @ref  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+      reset to the legacy weak (overridden) functions in the HAL_NOR_Init
+      and  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
       Callbacks can be registered/unregistered in READY state only.
@@ -81,26 +92,15 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
-      or @ref HAL_NOR_Init function.
+      using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit
+      or HAL_NOR_Init function.
 
       When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak (overridden) callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -126,6 +126,11 @@
   */
 
 /* Constants to define address to set to write a command */
+#define NOR_CMD_ADDRESS_FIRST_BYTE            (uint16_t)0x0AAA
+#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE        (uint16_t)0x00AA
+#define NOR_CMD_ADDRESS_SECOND_BYTE           (uint16_t)0x0555
+#define NOR_CMD_ADDRESS_THIRD_BYTE            (uint16_t)0x0AAA
+
 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
 #define NOR_CMD_ADDRESS_FIRST_CFI             (uint16_t)0x0055
 #define NOR_CMD_ADDRESS_SECOND                (uint16_t)0x02AA
@@ -229,6 +234,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
                                FMC_NORSRAM_TimingTypeDef *ExtTiming)
 {
   uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the NOR handle parameter */
   if (hnor == NULL)
@@ -262,7 +268,8 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
   (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
 
   /* Initialize NOR extended mode timing Interface */
-  (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+  (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming,
+                                         hnor->Init.NSBank, hnor->Init.ExtendedMode);
 
   /* Enable the NORSRAM device */
   __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
@@ -301,11 +308,32 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
     deviceaddress = NOR_MEMORY_ADRESS4;
   }
 
-  /* Get the value of the command set */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-  hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+  if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE)
+  {
+    (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
 
-  return HAL_NOR_ReturnToReadMode(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_PROTECTED;
+  }
+  else
+  {
+    /* Get the value of the command set */
+    if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+                NOR_CMD_DATA_CFI);
+    }
+    else
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    }
+
+    hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+    status = HAL_NOR_ReturnToReadMode(hnor);
+  }
+
+  return status;
 }
 
 /**
@@ -428,7 +456,11 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
   {
     return HAL_BUSY;
   }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hnor);
@@ -457,9 +489,22 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
     /* Send read ID command */
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_AUTO_SELECT);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_AUTO_SELECT);
+      }
     }
     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
     {
@@ -515,7 +560,11 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
   {
     return HAL_BUSY;
   }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hnor);
@@ -589,7 +638,11 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
   {
     return HAL_BUSY;
   }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hnor);
@@ -618,9 +671,22 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
     /* Send read data command */
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_READ_RESET);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_READ_RESET);
+      }
     }
     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
     {
@@ -699,9 +765,21 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
     /* Send program data command */
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_PROGRAM);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+      }
     }
     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
     {
@@ -758,7 +836,11 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
   {
     return HAL_BUSY;
   }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hnor);
@@ -787,9 +869,22 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
     /* Send read data command */
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_READ_RESET);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_READ_RESET);
+      }
     }
     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
     {
@@ -882,10 +977,20 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
 
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      /* Issue unlock command sequence */
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        /* Issue unlock command sequence */
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+      }
+      else
+      {
+        /* Issue unlock command sequence */
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      }
       /* Write Buffer Load Command */
       NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
       NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
@@ -985,14 +1090,26 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
     /* Send block erase command sequence */
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+      }
       NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
     }
     else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
@@ -1070,15 +1187,28 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
     /* Send NOR chip erase command sequence */
     if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
     {
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
-                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+      if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE),
+                  NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE),
+                  NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+      }
+      else
+      {
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+                  NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+        NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH),
+                  NOR_CMD_DATA_CHIP_ERASE);
+      }
     }
     else
     {
@@ -1118,7 +1248,11 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
   {
     return HAL_BUSY;
   }
-  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  else if (state == HAL_NOR_STATE_PROTECTED)
+  {
+    return HAL_ERROR;
+  }
+  else if (state == HAL_NOR_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hnor);
@@ -1145,8 +1279,15 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
     }
 
     /* Send read CFI query command */
-    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
-
+    if (uwNORMemoryDataWidth == NOR_MEMORY_8B)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE),
+                NOR_CMD_DATA_CFI);
+    }
+    else
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    }
     /* read the NOR CFI information */
     pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
     pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
@@ -1170,7 +1311,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User NOR Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hnor : NOR handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -1190,9 +1331,6 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hnor);
-
   state = hnor->State;
   if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
   {
@@ -1216,14 +1354,12 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hnor);
   return status;
 }
 
 /**
   * @brief  Unregister a User NOR Callback
-  *         NOR Callback is redirected to the weak (surcharged) predefined callback
+  *         NOR Callback is redirected to the weak predefined callback
   * @param hnor : NOR handle
   * @param CallbackId : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -1236,9 +1372,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca
   HAL_StatusTypeDef status = HAL_OK;
   HAL_NOR_StateTypeDef state;
 
-  /* Process locked */
-  __HAL_LOCK(hnor);
-
   state = hnor->State;
   if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
   {
@@ -1262,8 +1395,6 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hnor);
   return status;
 }
 #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
@@ -1380,7 +1511,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
   *                the configuration information for NOR module.
   * @retval NOR controller state
   */
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
+HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor)
 {
   return hnor->State;
 }
@@ -1509,5 +1640,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
   * @}
   */
 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h
index d614cb0666..de0494b6cc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -234,7 +233,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
   */
 
 /* NOR State functions ********************************************************/
-HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StateTypeDef  HAL_NOR_GetState(const NOR_HandleTypeDef *hnor);
 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 /**
   * @}
@@ -323,5 +322,3 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
 #endif
 
 #endif /* STM32H7xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.c
index 5ebf16ea3b..688ff3e7af 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.c
@@ -2,24 +2,32 @@
   ******************************************************************************
   * @file    stm32h7xx_hal_opamp.c
   * @author  MCD Application Team
-  * @brief   OPAMP HAL module driver. 
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the operational amplifier(s) peripheral: 
-  *           + OPAMP configuration
-  *           + OPAMP calibration
-  *          Thanks to
+  * @brief   OPAMP HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the operational amplifier(s) peripheral:
   *           + Initialization and de-initialization functions
   *           + IO operation functions
   *           + Peripheral Control functions
   *           + Peripheral State functions
-  *         
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
 ================================================================================
           ##### OPAMP Peripheral Features #####
 ================================================================================
-           
+
   [..] The device integrates 2 operational amplifiers OPAMP1 & OPAMP2
-       
+
        (#) The OPAMP(s) provides several exclusive running modes.
        (++) Standalone mode
        (++) Programmable Gain Amplifier (PGA) modes
@@ -27,36 +35,36 @@
 
        (#) Each OPAMP(s) can be configured in normal and high speed mode.
 
-       (#) The OPAMP(s) provide(s) calibration capabilities.  
+       (#) The OPAMP(s) provide(s) calibration capabilities.
        (++) Calibration aims at correcting some offset for running mode.
-       (++) The OPAMP uses either factory calibration settings OR user defined 
+       (++) The OPAMP uses either factory calibration settings OR user defined
            calibration (trimming) settings (i.e. trimming mode).
-       (++) The user defined settings can be figured out using self calibration 
+       (++) The user defined settings can be figured out using self calibration
            handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
        (++) HAL_OPAMP_SelfCalibrate:
-       (+++) Runs automatically the calibration in 2 steps. 
+       (+++) Runs automatically the calibration in 2 steps.
             (90% of VDDA for NMOS transistors, 10% of VDDA for PMOS transistors).
-            (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is 
+            (As OPAMP is Rail-to-rail input/output, these 2 steps calibration is
              appropriate and enough in most cases).
        (+++) Runs automatically the calibration.
        (+++) Enables the user trimming mode
-       (+++) Updates the init structure with trimming values with fresh calibration 
-            results. 
-            The user may store the calibration results for larger 
-            (ex monitoring the trimming as a function of temperature 
+       (+++) Updates the init structure with trimming values with fresh calibration
+            results.
+            The user may store the calibration results for larger
+            (ex monitoring the trimming as a function of temperature
             for instance)
        (+++) HAL_OPAMPEx_SelfCalibrateAll
             runs calibration of all OPAMPs in parallel to save search time.
-                    
-       (#) Running mode: Standalone mode 
+
+       (#) Running mode: Standalone mode
        (++) Gain is set externally (gain depends on external loads).
        (++) Follower mode also possible externally by connecting the inverting input to
            the output.
-       
+
        (#) Running mode: Follower mode
        (++) No Inverting Input is connected.
-       
-       (#) Running mode: Programmable Gain Amplifier (PGA) mode 
+
+       (#) Running mode: Programmable Gain Amplifier (PGA) mode
            (Resistor feedback output)
        (#) The OPAMP(s) output(s) can be internally connected to resistor feedback
            output.
@@ -64,7 +72,7 @@
 
       (##) Gain of x2, x4, x8 or x16 for non inverting mode with:
       (+++) VREF- referenced.
-      (+++) Filtering on VINM0, VREF- referenced. 
+      (+++) Filtering on VINM0, VREF- referenced.
       (+++) VINM0 node for bias voltage and VINP0 for input signal.
       (+++) VINM0 node for bias voltage and VINP0 for input signal, VINM1 node for filtering.
 
@@ -72,16 +80,16 @@
       (+++) VINM0 node for input signal and VINP0 for bias.
       (+++) VINM0 node for input signal and VINP0 for bias voltage, VINM1 node for filtering.
 
-       (#) The OPAMPs inverting input can be selected according to the Reference Manual 
+       (#) The OPAMPs inverting input can be selected according to the Reference Manual
            "OPAMP functional description" chapter.
 
-       (#) The OPAMPs non inverting input can be selected according to the Reference Manual 
+       (#) The OPAMPs non inverting input can be selected according to the Reference Manual
            "OPAMP functional description" chapter.
 
 
             ##### How to use this driver #####
 ================================================================================
-  [..] 
+  [..]
 
     *** High speed / normal power mode ***
     ============================================
@@ -95,7 +103,7 @@
     ============================================
     [..]  To run the OPAMP calibration self calibration:
 
-      (#) Start calibration using HAL_OPAMP_SelfCalibrate. 
+      (#) Start calibration using HAL_OPAMP_SelfCalibrate.
            Store the calibration results.
 
     *** Running mode ***
@@ -105,29 +113,29 @@
 
       (#) Fill in the HAL_OPAMP_MspInit() to
       (++) Enable the OPAMP Peripheral clock using macro __HAL_RCC_OPAMP_CLK_ENABLE()
-      (++) Configure the OPAMP input AND output in analog mode using 
+      (++) Configure the OPAMP input AND output in analog mode using
            HAL_GPIO_Init() to map the OPAMP output to the GPIO pin.
 
       (#) Registrate Callbacks
       (++) The compilation define  USE_HAL_OPAMP_REGISTER_CALLBACKS when set to 1
            allows the user to configure dynamically the driver callbacks.
 
-      (++) Use Functions @ref HAL_OPAMP_RegisterCallback() to register a user callback,
+      (++) Use Functions HAL_OPAMP_RegisterCallback() to register a user callback,
            it allows to register following callbacks:
-      (+++) MspInitCallback         : OPAMP MspInit.  
+      (+++) MspInitCallback         : OPAMP MspInit.
       (+++) MspDeInitCallback       : OPAMP MspDeInit.
            This function takes as parameters the HAL peripheral handle, the Callback ID
            and a pointer to the user callback function.
 
-      (++) Use function @ref HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
-           weak (surcharged) function. It allows to reset following callbacks:
-      (+++) MspInitCallback         : OPAMP MspInit.  
+      (++) Use function HAL_OPAMP_UnRegisterCallback() to reset a callback to the default
+           weak (overridden) function. It allows to reset following callbacks:
+      (+++) MspInitCallback         : OPAMP MspInit.
       (+++) MspDeInitCallback       : OPAMP MspDeInit.
       (+++) All Callbacks
       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
       (++) Select the mode
       (++) Select the inverting input
-      (++) Select the non-inverting input 
+      (++) Select the non-inverting input
       (++) If PGA mode is enabled, Select if inverting input is connected.
       (++) Select either factory or user defined trimming mode.
       (++) If the user-defined trimming mode is enabled, select PMOS & NMOS trimming values
@@ -138,7 +146,7 @@
       (#) Disable the OPAMP using HAL_OPAMP_Stop() function.
 
       (#) Lock the OPAMP in running mode using HAL_OPAMP_Lock() function.
-          Caution: On STM32H7, HAL OPAMP lock is software lock only (not 
+          Caution: On STM32H7, HAL OPAMP lock is software lock only (not
           hardware lock as on some other STM32 devices)
 
       (#) If needed, unlock the OPAMP using HAL_OPAMPEx_Unlock() function.
@@ -152,8 +160,8 @@
       (#) Configure the OPAMP using HAL_OPAMP_Init() function:
       (++) As in configure case, select first the parameters you wish to modify.
 
-      (#) Change from high speed mode to normal power mode (& vice versa) requires  
-          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init(). 
+      (#) Change from high speed mode to normal power mode (& vice versa) requires
+          first HAL_OPAMP_DeInit() (force OPAMP OFF) and then HAL_OPAMP_Init().
           In other words, of OPAMP is ON, HAL_OPAMP_Init can NOT change power mode
           alone.
 
@@ -193,23 +201,11 @@
     |                 |        |   COMP1_INN7 if       |                     |
     |                 |        |  connected internally |                     |
     |-----------------|--------|-----------------------|---------------------|
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal.h"
-    
+
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
@@ -228,7 +224,7 @@
   * @{
   */
 
-/* CSR register reset value */ 
+/* CSR register reset value */
 #define OPAMP_CSR_RESET_VALUE             0x00000000U
 
 /* CSR Init masks */
@@ -238,14 +234,14 @@
 
 
 #define OPAMP_CSR_INIT_MASK_FOLLOWER (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL| OPAMP_CSR_VPSEL \
-                                    | OPAMP_CSR_USERTRIM)                                   
+                                    | OPAMP_CSR_USERTRIM)
 
 
 #define OPAMP_CSR_INIT_MASK_STANDALONE (OPAMP_CSR_OPAHSM | OPAMP_CSR_VMSEL | OPAMP_CSR_VPSEL  \
                                        | OPAMP_CSR_VMSEL | OPAMP_CSR_USERTRIM)
 /**
   * @}
-  */ 
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -255,14 +251,14 @@
   * @{
   */
 
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
+/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
  *
 @verbatim
   ==============================================================================
               ##### Initialization and de-initialization functions #####
   ==============================================================================
- 
+
 @endverbatim
   * @{
   */
@@ -276,7 +272,7 @@
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
-{ 
+{
   HAL_StatusTypeDef status = HAL_OK;
   uint32_t updateotrlpotr;
 
@@ -289,7 +285,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
   {
     return HAL_ERROR;
-  }  
+  }
   else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
   {
     return HAL_ERROR;
@@ -298,15 +294,15 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
   {
     /* Check the parameter */
     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-       
+
     /* Set OPAMP parameters */
     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
     assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
     assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
-    
+
 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
     if(hopamp->State == HAL_OPAMP_STATE_RESET)
-    {  
+    {
       if(hopamp->MspInitCallback == NULL)
       {
         hopamp->MspInitCallback               = HAL_OPAMP_MspInit;
@@ -318,14 +314,14 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
       assert_param(IS_OPAMP_INVERTING_INPUT_STANDALONE(hopamp->Init.InvertingInput));
     }
 
-    if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)      
+    if ((hopamp->Init.Mode) == OPAMP_PGA_MODE)
     {
       assert_param(IS_OPAMP_PGA_GAIN(hopamp->Init.PgaGain));
       assert_param(IS_OPAMP_PGACONNECT(hopamp->Init.PgaConnect));
     }
-    
 
-    assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming)); 
+
+    assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
 
     if ((hopamp->Init.UserTrimming) == OPAMP_TRIMMING_USER)
     {
@@ -340,7 +336,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
         assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNHighSpeed));
       }
     }
-     
+
     if(hopamp->State == HAL_OPAMP_STATE_RESET)
     {
       /* Allocate lock resource and initialize it */
@@ -348,15 +344,15 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
     }
 
 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
-    hopamp->MspInitCallback(hopamp);    
-#else    
+    hopamp->MspInitCallback(hopamp);
+#else
     /* Call MSP init function */
     HAL_OPAMP_MspInit(hopamp);
 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
 
     /* Set operating mode */
     CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALON);
-    /* In PGA mode InvertingInput is Not Applicable  */                                          
+    /* In PGA mode InvertingInput is Not Applicable  */
     if (hopamp->Init.Mode == OPAMP_PGA_MODE)
     {
       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_PGA, \
@@ -367,7 +363,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
                                         hopamp->Init.NonInvertingInput | \
                                         hopamp->Init.UserTrimming);
     }
-    
+
     if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
     {
   /* In Follower mode InvertingInput is Not Applicable  */
@@ -375,9 +371,9 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
                                               hopamp->Init.PowerMode | \
                                               hopamp->Init.Mode | \
                                               hopamp->Init.NonInvertingInput | \
-                                              hopamp->Init.UserTrimming);     
-    }     
-    
+                                              hopamp->Init.UserTrimming);
+    }
+
     if (hopamp->Init.Mode == OPAMP_STANDALONE_MODE)
     {
       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_INIT_MASK_STANDALONE, \
@@ -386,8 +382,8 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
                                         hopamp->Init.InvertingInput    | \
                                         hopamp->Init.NonInvertingInput | \
                                         hopamp->Init.UserTrimming);
-    } 
-    
+    }
+
     if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
     {
       /* Set power mode and associated calibration parameters */
@@ -398,7 +394,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
         /* transistors differential pair high (PMOS) and low (NMOS) for     */
         /* normal mode.                                                     */
         updateotrlpotr = (((hopamp->Init.TrimmingValueP) << (OPAMP_INPUT_NONINVERTING)) \
-                         | (hopamp->Init.TrimmingValueN)); 
+                         | (hopamp->Init.TrimmingValueN));
         MODIFY_REG(hopamp->Instance->OTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
       }
       else
@@ -407,11 +403,11 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
         /* transistors differential pair high (PMOS) and low (NMOS) for     */
         /* high speed mode.                                                     */
         updateotrlpotr = (((hopamp->Init.TrimmingValuePHighSpeed) << (OPAMP_INPUT_NONINVERTING)) \
-                         | (hopamp->Init.TrimmingValueNHighSpeed)); 
-        MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);     
+                         | (hopamp->Init.TrimmingValueNHighSpeed));
+        MODIFY_REG(hopamp->Instance->HSOTR, OPAMP_OTR_TRIMOFFSETN | OPAMP_OTR_TRIMOFFSETP, updateotrlpotr);
       }
-    } 
-   
+    }
+
     /* Update the OPAMP state*/
     if (hopamp->State == HAL_OPAMP_STATE_RESET)
     {
@@ -424,7 +420,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
 }
 
 /**
-  * @brief  DeInitialize the OPAMP peripheral 
+  * @brief  DeInitialize the OPAMP peripheral
   * @note   Deinitialization can be performed if the OPAMP configuration is locked.
   *         (the lock is SW in H7)
   * @param  hopamp OPAMP handle
@@ -433,7 +429,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Check the OPAMP handle allocation */
   /* DeInit not allowed if calibration is on going */
   if(hopamp == NULL)
@@ -452,7 +448,7 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
     /* Set OPAMP_CSR register to reset value */
     WRITE_REG(hopamp->Instance->CSR, OPAMP_CSR_RESET_VALUE);
 
-    /* DeInit the low level hardware */   
+    /* DeInit the low level hardware */
 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
     if(hopamp->MspDeInitCallback == NULL)
     {
@@ -465,7 +461,7 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
 
     /* Update the OPAMP state*/
-    hopamp->State = HAL_OPAMP_STATE_RESET;   
+    hopamp->State = HAL_OPAMP_STATE_RESET;
     /* Process unlocked */
     __HAL_UNLOCK(hopamp);
 
@@ -509,13 +505,13 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
   */
 
 
-/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions 
- *  @brief   IO operation functions 
+/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions
+ *  @brief   IO operation functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                         ##### IO operation functions #####
- =============================================================================== 
+ ===============================================================================
     [..]
     This subsection provides a set of functions allowing to manage the OPAMP
     start, stop and calibration actions.
@@ -530,9 +526,9 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
-{ 
+{
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   /* Check the OPAMP handle allocation */
   /* Check if OPAMP locked */
   if(hopamp == NULL)
@@ -542,39 +538,39 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
   else if(hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
   {
     status = HAL_ERROR;
-  }    
+  }
   else
   {
     /* Check the parameter */
     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    
+
     if(hopamp->State == HAL_OPAMP_STATE_READY)
     {
       /* Enable the selected opamp */
       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
 
-      /* Update the OPAMP state*/     
+      /* Update the OPAMP state*/
       /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
-      hopamp->State = HAL_OPAMP_STATE_BUSY;   
+      hopamp->State = HAL_OPAMP_STATE_BUSY;
     }
     else
     {
       status = HAL_ERROR;
     }
-    
+
    }
   return status;
 }
 
 /**
-  * @brief  Stop the OPAMP. 
+  * @brief  Stop the OPAMP.
   * @param  hopamp OPAMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
-{ 
+{
   HAL_StatusTypeDef status = HAL_OK;
-    
+
   /* Check the OPAMP handle allocation */
   /* Check if OPAMP locked */
   /* Check if OPAMP calibration ongoing */
@@ -586,7 +582,7 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
   {
     status = HAL_ERROR;
   }
-  else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) 
+  else if(hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
   {
     status = HAL_ERROR;
   }
@@ -598,9 +594,9 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
     if(hopamp->State == HAL_OPAMP_STATE_BUSY)
     {
       /* Disable the selected opamp */
-      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN); 
-    
-      /* Update the OPAMP state*/     
+      CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
+
+      /* Update the OPAMP state*/
       /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
       hopamp->State = HAL_OPAMP_STATE_READY;
     }
@@ -623,17 +619,17 @@ HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
-{ 
+{
 
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   uint32_t trimmingvaluen;
   uint32_t trimmingvaluep;
   uint32_t delta;
   uint32_t opampmode;
-  
+
   __IO uint32_t* tmp_opamp_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or HSOTR */
-    
+
   /* Check the OPAMP handle allocation */
   /* Check if OPAMP locked */
   if(hopamp == NULL)
@@ -646,7 +642,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
   }
   else
   {
-  
+
     /* Check if OPAMP in calibration mode and calibration not yet enable */
     if(hopamp->State ==  HAL_OPAMP_STATE_READY)
     {
@@ -655,12 +651,12 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
       assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
 
       opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_VMSEL);
-      
-      /* Use of standalone mode */ 
-      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE); 
+
+      /* Use of standalone mode */
+      MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_VMSEL, OPAMP_STANDALONE_MODE);
       /*  user trimming values are used for offset calibration */
       SET_BIT(hopamp->Instance->CSR, OPAMP_CSR_USERTRIM);
-      
+
       /* Select trimming settings depending on power mode */
       if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
       {
@@ -673,7 +669,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
         tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
       }
 
-       
+
       /* Enable calibration */
       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
 
@@ -685,25 +681,25 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
 
       /* Enable the selected opamp */
       SET_BIT (hopamp->Instance->CSR, OPAMP_CSR_OPAMPxEN);
-      
-      /* Init trimming counter */    
+
+      /* Init trimming counter */
       /* Medium value */
       trimmingvaluen = 16U;
       delta = 8U;
-           
+
       while (delta != 0U)
       {
         /* Set candidate trimming */
         /* OPAMP_POWERMODE_NORMAL */
         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
-  
-        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ 
+
+        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
         /* Offset trim time: during calibration, minimum time needed between */
         /* two steps to have 1 mV accuracy */
         HAL_Delay(OPAMP_TRIMMING_DELAY);
-     
-        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) 
-        { 
+
+        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
+        {
           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
           trimmingvaluen += delta;
         }
@@ -712,22 +708,22 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
           /* OPAMP_CSR_CALOUT is LOW try lower trimming */
           trimmingvaluen -= delta;
         }
-        /* Divide range by 2 to continue dichotomy sweep */       
+        /* Divide range by 2 to continue dichotomy sweep */
         delta >>= 1;
       }
 
       /* Still need to check if right calibration is current value or one step below */
       /* Indeed the first value that causes the OUTCAL bit to change from 1  to 0  */
-    
+
       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETN, trimmingvaluen);
-           
-      /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ 
+
+      /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
       /* Offset trim time: during calibration, minimum time needed between */
       /* two steps to have 1 mV accuracy */
       HAL_Delay(OPAMP_TRIMMING_DELAY);
-      
+
       if ((READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)) != 0U)
-      { 
+      {
         /* Trimming value is actually one value more */
         trimmingvaluen++;
         /* Set right trimming */
@@ -736,25 +732,25 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
 
       /* 2nd calibration - P */
       MODIFY_REG(hopamp->Instance->CSR, OPAMP_CSR_CALSEL, OPAMP_VREF_10VDDA);
-      
-      /* Init trimming counter */    
+
+      /* Init trimming counter */
       /* Medium value */
-      trimmingvaluep = 16U; 
+      trimmingvaluep = 16U;
       delta = 8U;
-      
+
       while (delta != 0U)
       {
         /* Set candidate trimming */
         /* OPAMP_POWERMODE_NORMAL */
         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
 
-        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ 
+        /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
         /* Offset trim time: during calibration, minimum time needed between */
         /* two steps to have 1 mV accuracy */
         HAL_Delay(OPAMP_TRIMMING_DELAY);
 
-        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U) 
-        { 
+        if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT)!= 0U)
+        {
           /* OPAMP_CSR_CALOUT is HIGH try higher trimming */
           trimmingvaluep += delta;
         }
@@ -763,28 +759,28 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
           /* OPAMP_CSR_CALOUT  is LOW try lower trimming */
           trimmingvaluep -= delta;
         }
-        
+
         /* Divide range by 2 to continue dichotomy sweep */
         delta >>= 1U;
       }
-      
+
       /* Still need to check if right calibration is current value or one step below */
       /* Indeed the first value that causes the OUTCAL bit to change from 1 to 0  */
       /* Set candidate trimming */
       MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
 
-      /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */ 
+      /* OFFTRIMmax delay 2 ms as per datasheet (electrical characteristics */
       /* Offset trim time: during calibration, minimum time needed between */
       /* two steps to have 1 mV accuracy */
       HAL_Delay(OPAMP_TRIMMING_DELAY);
-      
-      if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U) 
+
+      if (READ_BIT(hopamp->Instance->CSR, OPAMP_CSR_CALOUT) != 0U)
       {
         /* Trimming value is actually one value more */
         trimmingvaluep++;
         MODIFY_REG(*tmp_opamp_reg_trimming, OPAMP_OTR_TRIMOFFSETP, (trimmingvaluep<<OPAMP_INPUT_NONINVERTING));
       }
-      
+
       /* Disable calibration & set normal mode (operating mode) */
       CLEAR_BIT (hopamp->Instance->CSR, OPAMP_CSR_CALON);
 
@@ -793,11 +789,11 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
 
       /* Set operating mode back */
       CLEAR_BIT(hopamp->Instance->CSR, OPAMP_CSR_FORCEVP);
-                 
+
       /* Self calibration is successful  */
       /* Store calibration(user trimming) results in init structure. */
 
-      /* Set user trimming mode */  
+      /* Set user trimming mode */
       hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
 
       /* Affect calibration parameters depending on mode normal/high speed */
@@ -821,9 +817,9 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
 
     else
     {
-      /* OPAMP can not be calibrated from this mode */ 
+      /* OPAMP can not be calibrated from this mode */
       status = HAL_ERROR;
-    }   
+    }
   }
   return status;
 }
@@ -832,15 +828,15 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
   * @}
   */
 
-/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
+/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief   Peripheral Control functions
  *
-@verbatim   
+@verbatim
  ===============================================================================
                       ##### Peripheral Control functions #####
- =============================================================================== 
+ ===============================================================================
     [..]
-    This subsection provides a set of functions allowing to control the OPAMP data 
+    This subsection provides a set of functions allowing to control the OPAMP data
     transfers.
 
 
@@ -851,8 +847,8 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  Lock the selected OPAMP configuration.
-  * @note   On STM32H7, HAL OPAMP lock is software lock only (in 
-  *         contrast of hardware lock available on some other STM32 
+  * @note   On STM32H7, HAL OPAMP lock is software lock only (in
+  *         contrast of hardware lock available on some other STM32
   *         devices)
   * @param  hopamp OPAMP handle
   * @retval HAL status
@@ -863,13 +859,13 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
 
   /* Check the OPAMP handle allocation */
   /* Check if OPAMP locked */
-  /* OPAMP can be locked when enabled and running in normal mode */ 
+  /* OPAMP can be locked when enabled and running in normal mode */
   /*   It is meaningless otherwise */
   if(hopamp == NULL)
   {
     status = HAL_ERROR;
   }
-  
+
   else if(hopamp->State != HAL_OPAMP_STATE_BUSY)
   {
     status = HAL_ERROR;
@@ -878,29 +874,29 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
   {
     /* Check the parameter */
     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    
+
    /* OPAMP state changed to locked */
     hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
-  }  
-  return status; 
+  }
+  return status;
 }
 
 /**
   * @brief  Return the OPAMP factory trimming value.
-  * @note            On STM32H7 OPAMP, user can retrieve factory trimming if 
+  * @note            On STM32H7 OPAMP, user can retrieve factory trimming if
   *                  OPAMP has never been set to user trimming before.
-  *                  Therefore, this function must be called when OPAMP init  
-  *                  parameter "UserTrimming" is set to trimming factory, 
-  *                  and before OPAMP  calibration (function 
+  *                  Therefore, this function must be called when OPAMP init
+  *                  parameter "UserTrimming" is set to trimming factory,
+  *                  and before OPAMP  calibration (function
   *                  "HAL_OPAMP_SelfCalibrate()").
-  *                  Otherwise, factory trimming value cannot be retrieved and 
+  *                  Otherwise, factory trimming value cannot be retrieved and
   *                  error status is returned.
   * @param  hopamp  OPAMP handle
   * @param  trimmingoffset  Trimming offset (P or N)
   *         This parameter must be a value of @ref OPAMP_FactoryTrimming
-  * @note   Calibration parameter retrieved is corresponding to the mode 
-  *         specified in OPAMP init structure (mode normal or high-speed). 
-  *         To retrieve calibration parameters for both modes, repeat this 
+  * @note   Calibration parameter retrieved is corresponding to the mode
+  *         specified in OPAMP init structure (mode normal or high-speed).
+  *         To retrieve calibration parameters for both modes, repeat this
   *         function after OPAMP init structure accordingly updated.
   * @retval Trimming value (P or N): range: 0->31
   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
@@ -910,23 +906,23 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop
 {
   HAL_OPAMP_TrimmingValueTypeDef trimmingvalue;
   __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  
+
   /* Check the OPAMP handle allocation */
   /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
   if(hopamp == NULL)
   {
     return OPAMP_FACTORYTRIMMING_DUMMY;
   }
-  
+
   if(hopamp->State == HAL_OPAMP_STATE_READY)
   {
     /* Check the parameter */
     assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
     assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
     assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-    
+
     /* Check the trimming mode */
-    if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= 0U) 
+    if (READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_USERTRIM)!= 0U)
     {
       /* This function must called when OPAMP init parameter "UserTrimming"   */
       /* is set to trimming factory, and before OPAMP calibration (function   */
@@ -945,8 +941,8 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop
       else
       {
         tmp_opamp_reg_trimming = &hopamp->Instance->HSOTR;
-      }      
-    
+      }
+
       /* Get factory trimming  */
       if (trimmingoffset == OPAMP_FACTORYTRIMMING_P)
       {
@@ -964,69 +960,26 @@ HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hop
   {
     return OPAMP_FACTORYTRIMMING_DUMMY;
   }
-  
+
   return trimmingvalue;
 }
 
-/**
-  * @}
-  */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- =============================================================================== 
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the OPAMP handle state.
-  * @param  hopamp  OPAMP handle
-  * @retval HAL state
-  */
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
-{
-  /* Check the OPAMP handle allocation */
-  if(hopamp == NULL)
-  {
-    return HAL_OPAMP_STATE_RESET;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
- /* Return OPAMP handle state */
-  return hopamp->State;
-}
-
-/**
-  * @}
-  */
-
 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User OPAMP Callback
-  *         To be used instead of the weak (surcharged) predefined callback 
+  *         To be used instead of the weak (overridden) predefined callback
   * @param hopamp  OPAMP handle
   * @param CallbackId  ID of the callback to be registered
   *        This parameter can be one of the following values:
-  *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID       OPAMP MspInit callback ID 
-  *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID     OPAMP MspDeInit callback ID  
+  *          @arg @ref HAL_OPAMP_MSPINIT_CB_ID       OPAMP MspInit callback ID
+  *          @arg @ref HAL_OPAMP_MSPDEINIT_CB_ID     OPAMP MspDeInit callback ID
   * @param pCallback  pointer to the Callback function
   * @retval status
   */
 HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  
+
   if(pCallback == NULL)
   {
     return HAL_ERROR;
@@ -1034,7 +987,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O
 
   /* Process locked */
   __HAL_LOCK(hopamp);
-  
+
   if(hopamp->State == HAL_OPAMP_STATE_READY)
   {
     switch (CallbackId)
@@ -1080,7 +1033,7 @@ HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_O
 
 /**
   * @brief  Unregister a User OPAMP Callback
-  *         OPAMP Callback is redirected to the weak (surcharged) predefined callback 
+  *         OPAMP Callback is redirected to the weak (overridden) predefined callback
   * @param hopamp  OPAMP handle
   * @param CallbackId  ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -1095,11 +1048,11 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL
 
   /* Process locked */
   __HAL_LOCK(hopamp);
-  
+
   if(hopamp->State == HAL_OPAMP_STATE_READY)
   {
     switch (CallbackId)
-    {     
+    {
     case HAL_OPAMP_MSPINIT_CB_ID :
       hopamp->MspInitCallback = HAL_OPAMP_MspInit;
       break;
@@ -1144,13 +1097,53 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL
 }
 
 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-  /**
-  * @}
-  */ 
-  
+
 /**
   * @}
-  */  
+  */
+
+
+/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the OPAMP handle state.
+  * @param  hopamp  OPAMP handle
+  * @retval HAL state
+  */
+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
+{
+  /* Check the OPAMP handle allocation */
+  if(hopamp == NULL)
+  {
+    return HAL_OPAMP_STATE_RESET;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
+
+  /* Return OPAMP handle state */
+  return hopamp->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
 #endif /* HAL_OPAMP_MODULE_ENABLED */
 /**
   * @}
@@ -1160,4 +1153,3 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.h
index 006ff5ab75..60c75ca109 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -146,10 +145,6 @@ void (* MspDeInitCallback)              (struct __OPAMP_HandleTypeDef *hopamp);
 
 typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
 
-/**
-  * @}
-  */
-
 #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
 /**
   * @brief  HAL OPAMP Callback ID enumeration definition
@@ -166,7 +161,9 @@ typedef enum
   */
 typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
-    
+/**
+  * @}
+  */
     
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
@@ -455,4 +452,3 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
 
 #endif /* STM32H7xx_HAL_OPAMP_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.c
index f53006fe10..8eedb6789a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.c
@@ -4,22 +4,20 @@
   * @author  MCD Application Team
   * @brief   Extended OPAMP HAL module driver.
   *          This file provides firmware functions to manage the following
-  *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
-  *          peripheral:
+  *          functionalities of the operational amplifier(s) peripheral:
   *           + Extended Initialization and de-initialization functions
   *           + Extended Peripheral Control functions
-  *         
+  *
   @verbatim
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -432,4 +430,4 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
   */
 
 #endif /* HAL_OPAMP_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.h
index 855ebc45cb..a08d563b26 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_opamp_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -80,4 +79,3 @@ HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
 
 #endif /* STM32H7xx_HAL_OPAMP_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c
index 69cb96ecb1..a38e06b301 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c
@@ -15,6 +15,17 @@
               + Errors management and abort functionality
               + IO manager configuration
 
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -41,7 +52,7 @@
      and the CS boundary using the HAL_OSPI_Init() function.
     [..]
      When using Hyperbus, configure the RW recovery time, the access time,
-     the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+     the write latency and the latency mode using the HAL_OSPI_HyperbusCfg()
      function.
 
     *** Indirect functional mode ***
@@ -109,25 +120,32 @@
     ====================================
     [..]
      Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_OSPI_MspInit() function :
-     (+) MDMA settings for write operation : 
-         (++) The DestinationInc should be MDMA_DEST_INC_DISABLE  
+     (+) MDMA settings for write operation :
+         (++) The DestinationInc should be MDMA_DEST_INC_DISABLE
          (++) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
-         (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) 
+         (++) The SourceDataSize must be a value of @ref MDMA Source data size
+              (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
               aligned with @ref MDMA_Source_increment_mode .
-         (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) 
-     (+) MDMA settings for read operation : 
-         (++) The SourceInc should be MDMA_SRC_INC_DISABLE  
-         (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
-         (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
-         (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+         (++) The DestDataSize must be a value of @ref MDMA Destination data size
+              (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+     (+) MDMA settings for read operation :
+         (++) The SourceInc should be MDMA_SRC_INC_DISABLE
+         (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode
+         (Except the MDMA_DEST_INC_DOUBLEWORD).
+         (++) The SourceDataSize must be a value of @ref MDMA Source data size
+              (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
+         (++) The DestDataSize must be a value of @ref MDMA Destination data size
+              (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
               aligned with @ref MDMA_Destination_increment_mode.
      (+) The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi.
     [..]
-     In case of wrong MDMA setting 
-     (+) For write operation : 
-         (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA().
-     (+) For read operation : 
-         (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA().
+     In case of wrong MDMA setting
+     (+) For write operation :
+         (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled
+              by the HAL_OSPI_Transmit_DMA().
+     (+) For read operation :
+         (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled
+              by the HAL_OSPI_Receive_DMA().
 
     *** Memory-mapped functional mode ***
     =====================================
@@ -203,7 +221,7 @@
 
     [..]
      Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
-     weak (surcharged) function. It allows to reset following callbacks:
+     weak (overridden) function. It allows to reset following callbacks:
      (+) ErrorCallback : callback when error occurs.
      (+) AbortCpltCallback : callback when abort is completed.
      (+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -221,9 +239,9 @@
 
     [..]
      By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
-     all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+     all callbacks are reset to the corresponding legacy weak (overridden) functions.
      Exception done for MspInit and MspDeInit callbacks that are respectively
-     reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+     reset to the legacy weak (overridden) functions in the HAL_OSPI_Init()
      and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
      If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
@@ -240,21 +258,10 @@
     [..]
      When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
-     and weak (surcharged) callbacks are used.
+     and weak (overridden) callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -300,13 +307,14 @@
 /* Private variables ---------------------------------------------------------*/
 
 /* Private function prototypes -----------------------------------------------*/
-static void              OSPI_DMACplt                  (MDMA_HandleTypeDef *hmdma);
-static void              OSPI_DMAError                 (MDMA_HandleTypeDef *hmdma);
-static void              OSPI_DMAAbortCplt             (MDMA_HandleTypeDef *hmdma);
-static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, 
+static void              OSPI_DMACplt(MDMA_HandleTypeDef *hmdma);
+static void              OSPI_DMAError(MDMA_HandleTypeDef *hmdma);
+static void              OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma);
+static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State,
                                                         uint32_t Tickstart, uint32_t Timeout);
-static HAL_StatusTypeDef OSPI_ConfigCmd                (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
-static HAL_StatusTypeDef OSPIM_GetConfig               (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
+static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
+static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg);
+static void OSPI_DMAAbortOnError(MDMA_HandleTypeDef *hmdma);
 /**
   @endcond
   */
@@ -339,7 +347,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig               (uint8_t instance_nb, OSP
   * @param  hospi : OSPI handle
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
+HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi)
 {
   HAL_StatusTypeDef status = HAL_OK;
   uint32_t tickstart = HAL_GetTick();
@@ -353,21 +361,20 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
   else
   {
     /* Check the parameters of the initialization structure */
-    assert_param(IS_OSPI_FIFO_THRESHOLD (hospi->Init.FifoThreshold));
-    assert_param(IS_OSPI_DUALQUAD_MODE  (hospi->Init.DualQuad));
-    assert_param(IS_OSPI_MEMORY_TYPE    (hospi->Init.MemoryType));
-    assert_param(IS_OSPI_DEVICE_SIZE    (hospi->Init.DeviceSize));
-    assert_param(IS_OSPI_CS_HIGH_TIME   (hospi->Init.ChipSelectHighTime));
-    assert_param(IS_OSPI_FREE_RUN_CLK   (hospi->Init.FreeRunningClock));
-    assert_param(IS_OSPI_CLOCK_MODE     (hospi->Init.ClockMode));
-    assert_param(IS_OSPI_WRAP_SIZE      (hospi->Init.WrapSize));
-    assert_param(IS_OSPI_CLK_PRESCALER  (hospi->Init.ClockPrescaler));
+    assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold));
+    assert_param(IS_OSPI_DUALQUAD_MODE(hospi->Init.DualQuad));
+    assert_param(IS_OSPI_MEMORY_TYPE(hospi->Init.MemoryType));
+    assert_param(IS_OSPI_DEVICE_SIZE(hospi->Init.DeviceSize));
+    assert_param(IS_OSPI_CS_HIGH_TIME(hospi->Init.ChipSelectHighTime));
+    assert_param(IS_OSPI_FREE_RUN_CLK(hospi->Init.FreeRunningClock));
+    assert_param(IS_OSPI_CLOCK_MODE(hospi->Init.ClockMode));
+    assert_param(IS_OSPI_WRAP_SIZE(hospi->Init.WrapSize));
+    assert_param(IS_OSPI_CLK_PRESCALER(hospi->Init.ClockPrescaler));
     assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting));
-    assert_param(IS_OSPI_DHQC           (hospi->Init.DelayHoldQuarterCycle));
-    assert_param(IS_OSPI_CS_BOUNDARY    (hospi->Init.ChipSelectBoundary));
-    assert_param(IS_OSPI_CKCSHT         (hospi->Init.ClkChipSelectHighTime));
-    assert_param(IS_OSPI_DLYBYP         (hospi->Init.DelayBlockBypass));
-    assert_param(IS_OSPI_MAXTRAN        (hospi->Init.MaxTran));
+    assert_param(IS_OSPI_DHQC(hospi->Init.DelayHoldQuarterCycle));
+    assert_param(IS_OSPI_CS_BOUNDARY(hospi->Init.ChipSelectBoundary));
+    assert_param(IS_OSPI_DLYBYP(hospi->Init.DelayBlockBypass));
+    assert_param(IS_OSPI_MAXTRAN(hospi->Init.MaxTran));
 
     /* Initialize error code */
     hospi->ErrorCode = HAL_OSPI_ERROR_NONE;
@@ -388,7 +395,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
       hospi->StatusMatchCallback   = HAL_OSPI_StatusMatchCallback;
       hospi->TimeOutCallback       = HAL_OSPI_TimeOutCallback;
 
-      if(hospi->MspInitCallback == NULL)
+      if (hospi->MspInitCallback == NULL)
       {
         hospi->MspInitCallback = HAL_OSPI_MspInit;
       }
@@ -403,13 +410,13 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
       /* Configure the default timeout for the OSPI memory access */
       (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
 
-      /* Configure memory type, device size, chip select high time, clocked chip select high time, delay block bypass, free running clock, clock mode */
+      /* Configure memory type, device size, chip select high time, delay block bypass,
+         free running clock, clock mode */
       MODIFY_REG(hospi->Instance->DCR1,
-                 (OCTOSPI_DCR1_MTYP   | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_CKCSHT |
-                  OCTOSPI_DCR1_DLYBYP | OCTOSPI_DCR1_FRCK    | OCTOSPI_DCR1_CKMODE),
+                 (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP |
+                  OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE),
                  (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) |
                   ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) |
-                  (hospi->Init.ClkChipSelectHighTime << OCTOSPI_DCR1_CKCSHT_Pos) |
                   hospi->Init.DelayBlockBypass | hospi->Init.ClockMode));
 
       /* Configure wrap size */
@@ -431,15 +438,15 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi)
       if (status == HAL_OK)
       {
         /* Configure clock prescaler */
-        MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, 
-                  ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
+        MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER,
+                   ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos));
 
         /* Configure Dual Quad mode */
         MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad);
 
         /* Configure sample shifting and delay hold quarter cycle */
         MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC),
-                  (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
+                   (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle));
 
         /* Enable OctoSPI */
         __HAL_OSPI_ENABLE(hospi);
@@ -499,27 +506,27 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi)
   }
   else
   {
-     /* Disable OctoSPI */
-     __HAL_OSPI_DISABLE(hospi);
+    /* Disable OctoSPI */
+    __HAL_OSPI_DISABLE(hospi);
 
-     /* Disable free running clock if needed : must be done after OSPI disable */
-     CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
+    /* Disable free running clock if needed : must be done after OSPI disable */
+    CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK);
 
 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
-     if(hospi->MspDeInitCallback == NULL)
-     {
-       hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
-     }
+    if (hospi->MspDeInitCallback == NULL)
+    {
+      hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+    }
 
-     /* DeInit the low level hardware */
-     hospi->MspDeInitCallback(hospi);
+    /* DeInit the low level hardware */
+    hospi->MspDeInitCallback(hospi);
 #else
-     /* De-initialize the low-level hardware */
-     HAL_OSPI_MspDeInit(hospi);
+    /* De-initialize the low-level hardware */
+    HAL_OSPI_MspDeInit(hospi);
 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
 
-     /* Reset the driver state */
-     hospi->State = HAL_OSPI_STATE_RESET;
+    /* Reset the driver state */
+    hospi->State = HAL_OSPI_STATE_RESET;
   }
 
   return status;
@@ -611,7 +618,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
     hospi->FifoThresholdCallback(hospi);
 #else
     HAL_OSPI_FifoThresholdCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
   }
   /* OctoSPI transfer complete interrupt occurred ----------------------------*/
   else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U))
@@ -625,7 +632,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
         hospi->pBuffPtr++;
         hospi->XferCount--;
       }
-      else if(hospi->XferCount == 0U)
+      else if (hospi->XferCount == 0U)
       {
         /* Clear flag */
         hospi->Instance->FCR = HAL_OSPI_FLAG_TC;
@@ -641,7 +648,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
         hospi->RxCpltCallback(hospi);
 #else
         HAL_OSPI_RxCpltCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
       }
       else
       {
@@ -666,7 +673,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
         hospi->TxCpltCallback(hospi);
 #else
         HAL_OSPI_TxCpltCallback(hospi);
-#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 
+#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
       }
       else if (currentstate == HAL_OSPI_STATE_BUSY_CMD)
       {
@@ -772,7 +779,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi)
       hospi->ErrorCallback(hospi);
 #else
       HAL_OSPI_ErrorCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ 
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
     }
   }
   /* OctoSPI timeout interrupt occurred --------------------------------------*/
@@ -818,21 +825,21 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp
   assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
   if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
   {
-    assert_param(IS_OSPI_INSTRUCTION_SIZE    (cmd->InstructionSize));
+    assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
     assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
   }
 
   assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
   if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
   {
-    assert_param(IS_OSPI_ADDRESS_SIZE    (cmd->AddressSize));
+    assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
     assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
   }
 
   assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
   if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
   {
-    assert_param(IS_OSPI_ALT_BYTES_SIZE    (cmd->AlternateBytesSize));
+    assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
     assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
   }
 
@@ -841,21 +848,21 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp
   {
     if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG)
     {
-      assert_param(IS_OSPI_NUMBER_DATA  (cmd->NbData));
+      assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
     }
     assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
-    assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
+    assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
   }
 
-  assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+  assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
   assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
 
   /* Check the state of the driver */
   state = hospi->State;
   if (((state == HAL_OSPI_STATE_READY)         && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) ||
-      ((state == HAL_OSPI_STATE_READ_CMD_CFG)  && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) 
-                                                || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
-      ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)  || 
+      ((state == HAL_OSPI_STATE_READ_CMD_CFG)  && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG)
+                                                   || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) ||
+      ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG)  ||
                                                    (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))))
   {
     /* Wait till busy flag is reset */
@@ -949,33 +956,33 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd
   assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode));
   if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE)
   {
-    assert_param(IS_OSPI_INSTRUCTION_SIZE    (cmd->InstructionSize));
+    assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize));
     assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode));
   }
 
   assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode));
   if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE)
   {
-    assert_param(IS_OSPI_ADDRESS_SIZE    (cmd->AddressSize));
+    assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
     assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode));
   }
 
   assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode));
   if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE)
   {
-    assert_param(IS_OSPI_ALT_BYTES_SIZE    (cmd->AlternateBytesSize));
+    assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize));
     assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode));
   }
 
   assert_param(IS_OSPI_DATA_MODE(cmd->DataMode));
   if (cmd->DataMode != HAL_OSPI_DATA_NONE)
   {
-    assert_param(IS_OSPI_NUMBER_DATA  (cmd->NbData));
+    assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
     assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode));
-    assert_param(IS_OSPI_DUMMY_CYCLES (cmd->DummyCycles));
+    assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles));
   }
 
-  assert_param(IS_OSPI_DQS_MODE (cmd->DQSMode));
+  assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
   assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode));
 
   /* Check the state of the driver */
@@ -999,7 +1006,7 @@ HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmd
       if (status == HAL_OK)
       {
         /* Update the state */
-          hospi->State = HAL_OSPI_STATE_BUSY_CMD;
+        hospi->State = HAL_OSPI_STATE_BUSY_CMD;
 
         /* Enable the transfer complete and transfer error interrupts */
         __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE);
@@ -1030,10 +1037,10 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC
   uint32_t tickstart = HAL_GetTick();
 
   /* Check the parameters of the hyperbus configuration structure */
-  assert_param(IS_OSPI_RW_RECOVERY_TIME  (cfg->RWRecoveryTime));
-  assert_param(IS_OSPI_ACCESS_TIME       (cfg->AccessTime));
+  assert_param(IS_OSPI_RW_RECOVERY_TIME(cfg->RWRecoveryTime));
+  assert_param(IS_OSPI_ACCESS_TIME(cfg->AccessTime));
   assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency));
-  assert_param(IS_OSPI_LATENCY_MODE      (cfg->LatencyMode));
+  assert_param(IS_OSPI_LATENCY_MODE(cfg->LatencyMode));
 
   /* Check the state of the driver */
   state = hospi->State;
@@ -1077,9 +1084,9 @@ HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusC
 
   /* Check the parameters of the hyperbus command structure */
   assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace));
-  assert_param(IS_OSPI_ADDRESS_SIZE (cmd->AddressSize));
-  assert_param(IS_OSPI_NUMBER_DATA  (cmd->NbData));
-  assert_param(IS_OSPI_DQS_MODE     (cmd->DQSMode));
+  assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize));
+  assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData));
+  assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode));
 
   /* Check the state of the driver */
   if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS))
@@ -1263,7 +1270,7 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui
         *hospi->pBuffPtr = *((__IO uint8_t *)data_reg);
         hospi->pBuffPtr++;
         hospi->XferCount--;
-      } while(hospi->XferCount > 0U);
+      } while (hospi->XferCount > 0U);
 
       if (status == HAL_OK)
       {
@@ -1461,23 +1468,24 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat
         /* Clear the MDMA abort callback */
         hospi->hmdma->XferAbortCallback = NULL;
 
-        /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment to disable */
-        MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) ,MDMA_DEST_INC_DISABLE);
-        
+        /* In Transmit mode , the MDMA destination is the OSPI DR register : Force the MDMA Destination Increment
+           to disable */
+        MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_DISABLE);
+
         /* Update MDMA configuration with the correct SourceInc field for Write operation */
         if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_BYTE)
         {
-          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_BYTE);
+          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_BYTE);
         }
         else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_HALFWORD)
         {
-          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_HALFWORD);
+          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_HALFWORD);
         }
         else if (hospi->hmdma->Init.SourceDataSize == MDMA_SRC_DATASIZE_WORD)
         {
-          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_WORD);
+          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_WORD);
         }
-        else   
+        else
         {
           /* in case of incorrect source data size */
           hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
@@ -1485,17 +1493,19 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat
         }
 
         /* Enable the transmit MDMA Channel */
-        if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK)
-          {
-            /* Enable the transfer error interrupt */
-            __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
-            
-            /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
-          }
-          else
-          {
-            status = HAL_ERROR;
-            hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
+        if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize, 1) == \
+            HAL_OK)
+        {
+          /* Enable the transfer error interrupt */
+          __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
+
+          /* Enable the DMA transfer by setting the DMAEN bit  */
+          SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
+        }
+        else
+        {
+          status = HAL_ERROR;
+          hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
           hospi->State = HAL_OSPI_STATE_READY;
         }
       }
@@ -1528,7 +1538,6 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData
   uint32_t data_size = hospi->Instance->DLR + 1U;
   uint32_t addr_reg = hospi->Instance->AR;
   uint32_t ir_reg = hospi->Instance->IR;
-
   /* Check the data pointer allocation */
   if (pData == NULL)
   {
@@ -1564,31 +1573,32 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData
         /* Clear the DMA abort callback */
         hospi->hmdma->XferAbortCallback = NULL;
 
-/* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
-      MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS) , MDMA_SRC_INC_DISABLE);
-      
-      /* Update MDMA configuration with the correct DestinationInc field for read operation */
-      if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
-      {
-        MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_BYTE);
-      }
-      else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
-      {
-        MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_HALFWORD);
-      }
-      else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
-      {
-        MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS) , MDMA_DEST_INC_WORD);
-      }
-      else 
-      {
-       /* in case of incorrect destination data size */
-        hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
-        status = HAL_ERROR;
-      }   
+        /* In Receive mode , the MDMA source is the OSPI DR register : Force the MDMA Source Increment to disable */
+        MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_SINC | MDMA_CTCR_SINCOS), MDMA_SRC_INC_DISABLE);
+
+        /* Update MDMA configuration with the correct DestinationInc field for read operation */
+        if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_BYTE)
+        {
+          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_BYTE);
+        }
+        else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_HALFWORD)
+        {
+          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_HALFWORD);
+        }
+        else if (hospi->hmdma->Init.DestDataSize == MDMA_DEST_DATASIZE_WORD)
+        {
+          MODIFY_REG(hospi->hmdma->Instance->CTCR, (MDMA_CTCR_DINC | MDMA_CTCR_DINCOS), MDMA_DEST_INC_WORD);
+        }
+        else
+        {
+          /* in case of incorrect destination data size */
+          hospi->ErrorCode |= HAL_OSPI_ERROR_DMA;
+          status = HAL_ERROR;
+        }
 
         /* Enable the transmit MDMA Channel */
-        if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == HAL_OK)
+        if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize, 1) == \
+            HAL_OK)
         {
           /* Enable the transfer error interrupt */
           __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE);
@@ -1610,7 +1620,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData
             }
           }
 
-          /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/
+          /* Enable the DMA transfer by setting the DMAEN bit  */
+          SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
         }
         else
         {
@@ -1650,10 +1661,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli
 #endif /* USE_FULL_ASSERT */
 
   /* Check the parameters of the autopolling configuration structure */
-  assert_param(IS_OSPI_MATCH_MODE       (cfg->MatchMode));
-  assert_param(IS_OSPI_AUTOMATIC_STOP   (cfg->AutomaticStop));
-  assert_param(IS_OSPI_INTERVAL         (cfg->Interval));
-  assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
+  assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+  assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+  assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
 
   /* Check the state */
   if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE))
@@ -1664,10 +1675,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli
     if (status == HAL_OK)
     {
       /* Configure registers */
-      WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
-      WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
-      WRITE_REG (hospi->Instance->PIR,   cfg->Interval);
-      MODIFY_REG(hospi->Instance->CR,    (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+      WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+      WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+      WRITE_REG(hospi->Instance->PIR,   cfg->Interval);
+      MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
                  (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
 
       /* Trig the transfer by re-writing address or instruction register */
@@ -1728,10 +1739,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo
 #endif /* USE_FULL_ASSERT */
 
   /* Check the parameters of the autopolling configuration structure */
-  assert_param(IS_OSPI_MATCH_MODE       (cfg->MatchMode));
-  assert_param(IS_OSPI_AUTOMATIC_STOP   (cfg->AutomaticStop));
-  assert_param(IS_OSPI_INTERVAL         (cfg->Interval));
-  assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg+1U));
+  assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode));
+  assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
+  assert_param(IS_OSPI_INTERVAL(cfg->Interval));
+  assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U));
 
   /* Check the state */
   if (hospi->State == HAL_OSPI_STATE_CMD_CFG)
@@ -1742,10 +1753,10 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo
     if (status == HAL_OK)
     {
       /* Configure registers */
-      WRITE_REG (hospi->Instance->PSMAR, cfg->Match);
-      WRITE_REG (hospi->Instance->PSMKR, cfg->Mask);
-      WRITE_REG (hospi->Instance->PIR,   cfg->Interval);
-      MODIFY_REG(hospi->Instance->CR,    (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
+      WRITE_REG(hospi->Instance->PSMAR, cfg->Match);
+      WRITE_REG(hospi->Instance->PSMKR, cfg->Mask);
+      WRITE_REG(hospi->Instance->PIR,   cfg->Interval);
+      MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE),
                  (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING));
 
       /* Clear flags related to interrupt */
@@ -1920,7 +1931,7 @@ __weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
   * @param  hospi : OSPI handle
   * @retval None
   */
- __weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
+__weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hospi);
@@ -1993,7 +2004,7 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
 /**
   * @brief  Register a User OSPI Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hospi : OSPI handle
   * @param CallbackID : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -2017,77 +2028,77 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(pCallback == NULL)
+  if (pCallback == NULL)
   {
     /* Update the error code */
     hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
     return HAL_ERROR;
   }
 
-  if(hospi->State == HAL_OSPI_STATE_READY)
+  if (hospi->State == HAL_OSPI_STATE_READY)
   {
     switch (CallbackID)
     {
-    case  HAL_OSPI_ERROR_CB_ID :
-      hospi->ErrorCallback = pCallback;
-      break;
-    case HAL_OSPI_ABORT_CB_ID :
-      hospi->AbortCpltCallback = pCallback;
-      break;
-    case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
-      hospi->FifoThresholdCallback = pCallback;
-      break;
-    case HAL_OSPI_CMD_CPLT_CB_ID :
-      hospi->CmdCpltCallback = pCallback;
-      break;
-    case HAL_OSPI_RX_CPLT_CB_ID :
-      hospi->RxCpltCallback = pCallback;
-      break;
-    case HAL_OSPI_TX_CPLT_CB_ID :
-      hospi->TxCpltCallback = pCallback;
-      break;
-    case HAL_OSPI_RX_HALF_CPLT_CB_ID :
-      hospi->RxHalfCpltCallback = pCallback;
-      break;
-    case HAL_OSPI_TX_HALF_CPLT_CB_ID :
-      hospi->TxHalfCpltCallback = pCallback;
-      break;
-    case HAL_OSPI_STATUS_MATCH_CB_ID :
-      hospi->StatusMatchCallback = pCallback;
-      break;
-    case HAL_OSPI_TIMEOUT_CB_ID :
-      hospi->TimeOutCallback = pCallback;
-      break;
-    case HAL_OSPI_MSP_INIT_CB_ID :
-      hospi->MspInitCallback = pCallback;
-      break;
-    case HAL_OSPI_MSP_DEINIT_CB_ID :
-      hospi->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
+      case  HAL_OSPI_ERROR_CB_ID :
+        hospi->ErrorCallback = pCallback;
+        break;
+      case HAL_OSPI_ABORT_CB_ID :
+        hospi->AbortCpltCallback = pCallback;
+        break;
+      case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+        hospi->FifoThresholdCallback = pCallback;
+        break;
+      case HAL_OSPI_CMD_CPLT_CB_ID :
+        hospi->CmdCpltCallback = pCallback;
+        break;
+      case HAL_OSPI_RX_CPLT_CB_ID :
+        hospi->RxCpltCallback = pCallback;
+        break;
+      case HAL_OSPI_TX_CPLT_CB_ID :
+        hospi->TxCpltCallback = pCallback;
+        break;
+      case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+        hospi->RxHalfCpltCallback = pCallback;
+        break;
+      case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+        hospi->TxHalfCpltCallback = pCallback;
+        break;
+      case HAL_OSPI_STATUS_MATCH_CB_ID :
+        hospi->StatusMatchCallback = pCallback;
+        break;
+      case HAL_OSPI_TIMEOUT_CB_ID :
+        hospi->TimeOutCallback = pCallback;
+        break;
+      case HAL_OSPI_MSP_INIT_CB_ID :
+        hospi->MspInitCallback = pCallback;
+        break;
+      case HAL_OSPI_MSP_DEINIT_CB_ID :
+        hospi->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else if (hospi->State == HAL_OSPI_STATE_RESET)
   {
     switch (CallbackID)
     {
-    case HAL_OSPI_MSP_INIT_CB_ID :
-      hospi->MspInitCallback = pCallback;
-      break;
-    case HAL_OSPI_MSP_DEINIT_CB_ID :
-      hospi->MspDeInitCallback = pCallback;
-      break;
-    default :
-      /* Update the error code */
-      hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
+      case HAL_OSPI_MSP_INIT_CB_ID :
+        hospi->MspInitCallback = pCallback;
+        break;
+      case HAL_OSPI_MSP_DEINIT_CB_ID :
+        hospi->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else
@@ -2103,7 +2114,7 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_
 
 /**
   * @brief  Unregister a User OSPI Callback
-  *         OSPI Callback is redirected to the weak (surcharged) predefined callback
+  *         OSPI Callback is redirected to the weak predefined callback
   * @param hospi : OSPI handle
   * @param CallbackID : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -2121,74 +2132,74 @@ HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_
   *          @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID     OSPI MspDeInit callback ID
   * @retval status
   */
-HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(hospi->State == HAL_OSPI_STATE_READY)
+  if (hospi->State == HAL_OSPI_STATE_READY)
   {
     switch (CallbackID)
     {
-    case  HAL_OSPI_ERROR_CB_ID :
-      hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
-      break;
-    case HAL_OSPI_ABORT_CB_ID :
-      hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
-      break;
-    case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
-      hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
-      break;
-    case HAL_OSPI_CMD_CPLT_CB_ID :
-      hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
-      break;
-    case HAL_OSPI_RX_CPLT_CB_ID :
-      hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
-      break;
-    case HAL_OSPI_TX_CPLT_CB_ID :
-      hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
-      break;
-    case HAL_OSPI_RX_HALF_CPLT_CB_ID :
-      hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
-      break;
-    case HAL_OSPI_TX_HALF_CPLT_CB_ID :
-      hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
-      break;
-    case HAL_OSPI_STATUS_MATCH_CB_ID :
-      hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
-      break;
-    case HAL_OSPI_TIMEOUT_CB_ID :
-      hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
-      break;
-    case HAL_OSPI_MSP_INIT_CB_ID :
-      hospi->MspInitCallback = HAL_OSPI_MspInit;
-      break;
-    case HAL_OSPI_MSP_DEINIT_CB_ID :
-      hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
+      case  HAL_OSPI_ERROR_CB_ID :
+        hospi->ErrorCallback = HAL_OSPI_ErrorCallback;
+        break;
+      case HAL_OSPI_ABORT_CB_ID :
+        hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback;
+        break;
+      case HAL_OSPI_FIFO_THRESHOLD_CB_ID :
+        hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback;
+        break;
+      case HAL_OSPI_CMD_CPLT_CB_ID :
+        hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback;
+        break;
+      case HAL_OSPI_RX_CPLT_CB_ID :
+        hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback;
+        break;
+      case HAL_OSPI_TX_CPLT_CB_ID :
+        hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback;
+        break;
+      case HAL_OSPI_RX_HALF_CPLT_CB_ID :
+        hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback;
+        break;
+      case HAL_OSPI_TX_HALF_CPLT_CB_ID :
+        hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback;
+        break;
+      case HAL_OSPI_STATUS_MATCH_CB_ID :
+        hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback;
+        break;
+      case HAL_OSPI_TIMEOUT_CB_ID :
+        hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback;
+        break;
+      case HAL_OSPI_MSP_INIT_CB_ID :
+        hospi->MspInitCallback = HAL_OSPI_MspInit;
+        break;
+      case HAL_OSPI_MSP_DEINIT_CB_ID :
+        hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else if (hospi->State == HAL_OSPI_STATE_RESET)
   {
     switch (CallbackID)
     {
-    case HAL_OSPI_MSP_INIT_CB_ID :
-      hospi->MspInitCallback = HAL_OSPI_MspInit;
-      break;
-    case HAL_OSPI_MSP_DEINIT_CB_ID :
-      hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
-      break;
-    default :
-      /* Update the error code */
-      hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status =  HAL_ERROR;
-      break;
+      case HAL_OSPI_MSP_INIT_CB_ID :
+        hospi->MspInitCallback = HAL_OSPI_MspInit;
+        break;
+      case HAL_OSPI_MSP_DEINIT_CB_ID :
+        hospi->MspDeInitCallback = HAL_OSPI_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
     }
   }
   else
@@ -2227,10 +2238,10 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS
   */
 
 /**
-* @brief  Abort the current transmission.
-* @param  hospi : OSPI handle
-* @retval HAL status
-*/
+  * @brief  Abort the current transmission.
+  * @param  hospi : OSPI handle
+  * @retval HAL status
+  */
 HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
 {
   HAL_StatusTypeDef status = HAL_OK;
@@ -2295,10 +2306,10 @@ HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi)
 }
 
 /**
-* @brief  Abort the current transmission (non-blocking function)
-* @param  hospi : OSPI handle
-* @retval HAL status
-*/
+  * @brief  Abort the current transmission (non-blocking function)
+  * @param  hospi : OSPI handle
+  * @retval HAL status
+  */
 HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
 {
   HAL_StatusTypeDef status = HAL_OK;
@@ -2332,7 +2343,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi)
         hospi->AbortCpltCallback(hospi);
 #else
         HAL_OSPI_AbortCpltCallback(hospi);
-#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ 
+#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
       }
     }
     else
@@ -2388,7 +2399,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t
     hospi->Init.FifoThreshold = Threshold;
 
     /* Configure new fifo threshold */
-    MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold-1U) << OCTOSPI_CR_FTHRES_Pos));
+    MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos));
 
   }
   else
@@ -2405,7 +2416,7 @@ HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t
   * @param  hospi : OSPI handle.
   * @retval Fifo threshold
   */
-uint32_t HAL_OSPI_GetFifoThreshold(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi)
 {
   return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U);
 }
@@ -2422,11 +2433,11 @@ HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeou
 }
 
 /**
-* @brief  Return the OSPI error code.
-* @param  hospi : OSPI handle
-* @retval OSPI Error Code
-*/
-uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
+  * @brief  Return the OSPI error code.
+  * @param  hospi : OSPI handle
+  * @retval OSPI Error Code
+  */
+uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi)
 {
   return hospi->ErrorCode;
 }
@@ -2436,7 +2447,7 @@ uint32_t HAL_OSPI_GetError(OSPI_HandleTypeDef *hospi)
   * @param  hospi : OSPI handle
   * @retval HAL state
   */
-uint32_t HAL_OSPI_GetState(OSPI_HandleTypeDef *hospi)
+uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi)
 {
   /* Return OSPI handle state */
   return hospi->State;
@@ -2502,7 +2513,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
   /**************** Get current configuration of the instances ****************/
   for (index = 0U; index < OSPI_NB_INSTANCE; index++)
   {
-    if (OSPIM_GetConfig(index+1U, &(IOM_cfg[index])) != HAL_OK)
+    if (OSPIM_GetConfig(index + 1U, &(IOM_cfg[index])) != HAL_OK)
     {
       status = HAL_ERROR;
       hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM;
@@ -2524,7 +2535,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
     }
 
     /***************** Deactivation of previous configuration *****************/
-    CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+    CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
     if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
     {
       /* De-multiplexing should be performed */
@@ -2532,18 +2543,20 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
 
       if (other_instance == 1U)
       {
-        SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC);
+        SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKSRC);
         if (IOM_cfg[other_instance].DQSPort != 0U)
         {
-          SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC);
+          SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSSRC);
         }
         if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
         {
-          SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1);
+          SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], \
+                  OCTOSPIM_PCR_IOLSRC_1);
         }
         if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
         {
-          SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1);
+          SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], \
+                  OCTOSPIM_PCR_IOHSRC_1);
         }
       }
     }
@@ -2551,18 +2564,18 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
     {
       if (IOM_cfg[instance].ClkPort != 0U)
       {
-        CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+        CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
         if (IOM_cfg[instance].DQSPort != 0U)
         {
-          CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+          CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
         }
         if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
         {
-          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
+          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN);
         }
         if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
         {
-          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
+          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN);
         }
       }
     }
@@ -2572,9 +2585,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
         (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) ||
         (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
     {
-      if ((cfg->ClkPort   == IOM_cfg[other_instance].ClkPort)   && 
+      if ((cfg->ClkPort   == IOM_cfg[other_instance].ClkPort)   &&
           (cfg->DQSPort    == IOM_cfg[other_instance].DQSPort)  &&
-          (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && 
+          (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) &&
           (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort))
       {
         /* Multiplexing should be performed */
@@ -2582,28 +2595,28 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
       }
       else
       {
-        CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN);
+        CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN);
         if (IOM_cfg[other_instance].DQSPort != 0U)
         {
-          CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN);
+          CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN);
         }
-        CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN);
+        CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN);
         if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE)
         {
-          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)],
+          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
                     OCTOSPIM_PCR_IOLEN);
         }
         if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE)
         {
-          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)],
+          CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
                     OCTOSPIM_PCR_IOHEN);
         }
       }
     }
 
     /******************** Activation of new configuration *********************/
-        MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
-                  (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
+    MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC),
+               (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos)));
 
     if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos))
     {
@@ -2612,84 +2625,84 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
 
     if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U)
     {
-      MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
+      MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN);
       if (cfg->DQSPort != 0U)
       {
-        MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
+        MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN);
       }
 
       if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN);
       }
       else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN);
       }
       else
       {
-         /* Nothing to do */
+        /* Nothing to do */
       }
 
       if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0));
       }
       else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0));
       }
       else
       {
-         /* Nothing to do */
+        /* Nothing to do */
       }
     }
     else
     {
-      MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), 
-                (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
+      MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC),
+                 (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos)));
       if (cfg->DQSPort != 0U)
       {
-        MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), 
-                  (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
+        MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC),
+                   (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos)));
       }
 
       if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
-                  (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+                   (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
       }
       else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
-                  (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+                   (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
       }
       else
       {
-         /* Nothing to do */
+        /* Nothing to do */
       }
 
       if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
-                  (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U))));
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC),
+                   (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U))));
       }
       else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE)
       {
-        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], 
-                  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
-                  (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U))));
+        MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)],
+                   (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC),
+                   (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U))));
       }
       else
       {
-         /* Nothing to do */
+        /* Nothing to do */
       }
     }
 
@@ -2722,7 +2735,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *
   */
 static void OSPI_DMACplt(MDMA_HandleTypeDef *hmdma)
 {
-  OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+  OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
   hospi->XferCount = 0;
 
   /* Disable the DMA transfer on the OctoSPI side */
@@ -2742,19 +2755,58 @@ static void OSPI_DMACplt(MDMA_HandleTypeDef *hmdma)
   */
 static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma)
 {
-  OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+  OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
   hospi->XferCount = 0;
   hospi->ErrorCode = HAL_OSPI_ERROR_DMA;
 
   /* Disable the DMA transfer on the OctoSPI side */
   CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN);
 
-  /* Abort the OctoSPI */
-  if (HAL_OSPI_Abort_IT(hospi) != HAL_OK)
-  {
-    /* Disable the interrupts */
-    __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
+  /* Disable all interrupts */
+  __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE);
 
+  /* Update state */
+  hospi->State = HAL_OSPI_STATE_ABORT;
+
+  /* Disable the DMA transfer on the DMA side */
+  hospi->hmdma->XferAbortCallback = OSPI_DMAAbortOnError;
+  if (HAL_MDMA_Abort_IT(hospi->hmdma) != HAL_OK)
+  {
+    /* Update state */
+    hospi->State = HAL_OSPI_STATE_READY;
+
+    /* Error callback */
+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
+    hospi->ErrorCallback(hospi);
+#else
+    HAL_OSPI_ErrorCallback(hospi);
+#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
+  }
+}
+
+/**
+  * @brief  DMA OSPI abort complete callback.
+  * @param  hdma : DMA handle
+  * @retval None
+  */
+static void OSPI_DMAAbortOnError(MDMA_HandleTypeDef *hmdma)
+{
+  OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
+
+  /* DMA abort called by OctoSPI abort */
+  if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET)
+  {
+    /* Clear transfer complete flag */
+    __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC);
+
+    /* Enable the transfer complete interrupts */
+    __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC);
+
+    /* Perform an abort of the OctoSPI */
+    SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT);
+  }
+  else
+  {
     /* Update state */
     hospi->State = HAL_OSPI_STATE_READY;
 
@@ -2774,7 +2826,7 @@ static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma)
   */
 static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
 {
-  OSPI_HandleTypeDef* hospi = ( OSPI_HandleTypeDef* )(hmdma->Parent);
+  OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hmdma->Parent);
   hospi->XferCount = 0;
 
   /* Check the state */
@@ -2833,12 +2885,12 @@ static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hosp
                                                         FlagStatus State, uint32_t Tickstart, uint32_t Timeout)
 {
   /* Wait until flag is in expected state */
-  while((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
+  while ((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State)
   {
     /* Check for the Timeout */
     if (Timeout != HAL_MAX_DELAY)
     {
-      if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
       {
         hospi->State     = HAL_OSPI_STATE_ERROR;
         hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT;
@@ -2861,7 +2913,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
   HAL_StatusTypeDef status = HAL_OK;
   __IO uint32_t *ccr_reg;
   __IO uint32_t *tcr_reg;
-  __IO uint32_t *ir_reg; 
+  __IO uint32_t *ir_reg;
   __IO uint32_t *abr_reg;
 
   /* Re-initialize the value of the functional mode */
@@ -2905,7 +2957,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
 
     /* Configure the CCR register with alternate bytes communication parameters */
     MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE),
-                           (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
+               (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize));
   }
 
   /* Configure the TCR register with the number of dummy cycles */
@@ -2932,9 +2984,9 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE  | OCTOSPI_CCR_IDTR  | OCTOSPI_CCR_ISIZE  |
                                 OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
                                 OCTOSPI_CCR_DMODE  | OCTOSPI_CCR_DDTR),
-                               (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
-                                cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize     |
-                                cmd->DataMode        | cmd->DataDtrMode));
+                   (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+                    cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize     |
+                    cmd->DataMode        | cmd->DataDtrMode));
       }
       else
       {
@@ -2943,8 +2995,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
         /* Configure the CCR register with all communication parameters */
         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE  | OCTOSPI_CCR_IDTR  | OCTOSPI_CCR_ISIZE  |
                                 OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
-                               (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
-                                cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize));
+                   (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+                    cmd->AddressMode     | cmd->AddressDtrMode     | cmd->AddressSize));
 
         /* The DHQC bit is linked with DDTR bit which should be activated */
         if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
@@ -2969,8 +3021,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
         /* Configure the CCR register with all communication parameters */
         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE |
                                 OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR),
-                               (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
-                                cmd->DataMode        | cmd->DataDtrMode));
+                   (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize |
+                    cmd->DataMode        | cmd->DataDtrMode));
       }
       else
       {
@@ -2978,7 +3030,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
 
         /* Configure the CCR register with all communication parameters */
         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE),
-                               (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
+                   (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize));
 
         /* The DHQC bit is linked with DDTR bit which should be activated */
         if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) &&
@@ -3004,8 +3056,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
         /* Configure the CCR register with all communication parameters */
         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE |
                                 OCTOSPI_CCR_DMODE  | OCTOSPI_CCR_DDTR),
-                               (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize     |
-                                cmd->DataMode    | cmd->DataDtrMode));
+                   (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | cmd->DataMode |
+                    cmd->DataDtrMode));
       }
       else
       {
@@ -3013,7 +3065,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
 
         /* Configure the CCR register with all communication parameters */
         MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE),
-                               (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
+                   (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize));
       }
 
       /* Configure the AR register with the instruction value */
@@ -3040,7 +3092,7 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC
 static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  uint32_t reg; 
+  uint32_t reg;
   uint32_t value = 0U;
   uint32_t index;
 
@@ -3062,8 +3114,8 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
     {
       if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U)
       {
-        value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC 
-               | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
+        value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC
+                 | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1);
       }
       else
       {
@@ -3082,7 +3134,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
         if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC))
         {
           /* The clock correspond to the instance passed as parameter */
-          cfg->ClkPort = index+1U;
+          cfg->ClkPort = index + 1U;
         }
       }
 
@@ -3092,7 +3144,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
         if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC))
         {
           /* The DQS correspond to the instance passed as parameter */
-          cfg->DQSPort = index+1U;
+          cfg->DQSPort = index + 1U;
         }
       }
 
@@ -3102,7 +3154,7 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
         if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC))
         {
           /* The nCS correspond to the instance passed as parameter */
-          cfg->NCSPort = index+1U;
+          cfg->NCSPort = index + 1U;
         }
       }
 
@@ -3114,11 +3166,11 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
           /* The IO Low correspond to the instance passed as parameter */
           if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U)
           {
-            cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
+            cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
           }
           else
           {
-            cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
+            cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
           }
         }
       }
@@ -3131,11 +3183,11 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
           /* The IO High correspond to the instance passed as parameter */
           if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U)
           {
-            cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index+1U));
+            cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index + 1U));
           }
           else
           {
-            cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index+1U));
+            cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index + 1U));
           }
         }
       }
@@ -3165,5 +3217,3 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *
   */
 
 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h
index 6d7471ffc3..6f96b60996 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,7 +21,7 @@
 #define STM32H7xx_HAL_OSPI_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -81,9 +80,6 @@ typedef struct
   uint32_t ChipSelectBoundary;        /*!< It enables the transaction boundary feature and
                                            defines the boundary of bytes to release the chip select.
                                            This parameter can be a value between 0 and 31 */
-  uint32_t ClkChipSelectHighTime;     /*!< It defines the number of clocks provided on the CLK/nCLK pins when
-                                           the chip select is set to high at the end of a transaction.
-                                           This parameter can be a value between 0 and 7 */
   uint32_t DelayBlockBypass;          /*!< It enables the delay block bypass, so the sampling is not affected
                                            by the delay block.
                                            This parameter can be a value of @ref OSPI_DelayBlockBypass */
@@ -94,7 +90,7 @@ typedef struct
   uint32_t Refresh;                   /*!< It enables the refresh rate feature. The chip select is released every
                                            Refresh+1 clock cycles.
                                            This parameter can be a value between 0 and 0xFFFFFFFF */
-}OSPI_InitTypeDef;
+} OSPI_InitTypeDef;
 
 /**
   * @brief  HAL OSPI Handle Structure definition
@@ -115,21 +111,21 @@ typedef struct
   __IO uint32_t              ErrorCode;     /*!< Error code in case of HAL driver internal error  */
   uint32_t                   Timeout;       /*!< Timeout used for the OSPI external device access */
 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
-  void (* ErrorCallback)        (struct __OSPI_HandleTypeDef *hospi);
-  void (* AbortCpltCallback)    (struct __OSPI_HandleTypeDef *hospi);
+  void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
   void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
-  void (* CmdCpltCallback)      (struct __OSPI_HandleTypeDef *hospi);
-  void (* RxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);
-  void (* TxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);
-  void (* RxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);
-  void (* TxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);
-  void (* StatusMatchCallback)  (struct __OSPI_HandleTypeDef *hospi);
-  void (* TimeOutCallback)      (struct __OSPI_HandleTypeDef *hospi);
+  void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi);
 
-  void (* MspInitCallback)      (struct __OSPI_HandleTypeDef *hospi);
-  void (* MspDeInitCallback)    (struct __OSPI_HandleTypeDef *hospi);
+  void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi);
+  void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi);
 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
-}OSPI_HandleTypeDef;
+} OSPI_HandleTypeDef;
 
 /**
   * @brief  HAL OSPI Regular Command Structure definition
@@ -180,7 +176,7 @@ typedef struct
                                            This parameter can be a value of @ref OSPI_DQSMode */
   uint32_t SIOOMode;                  /*!< It enables or not the SIOO mode.
                                            This parameter can be a value of @ref OSPI_SIOOMode */
-}OSPI_RegularCmdTypeDef;
+} OSPI_RegularCmdTypeDef;
 
 /**
   * @brief  HAL OSPI Hyperbus Configuration Structure definition
@@ -195,7 +191,7 @@ typedef struct
                                       This parameter can be a value of @ref OSPI_WriteZeroLatency */
   uint32_t LatencyMode;          /*!< It configures the latency mode.
                                       This parameter can be a value of @ref OSPI_LatencyMode */
-}OSPI_HyperbusCfgTypeDef;
+} OSPI_HyperbusCfgTypeDef;
 
 /**
   * @brief  HAL OSPI Hyperbus Command Structure definition
@@ -214,7 +210,7 @@ typedef struct
                                   In case of autopolling mode, this parameter can be any value between 1 and 4 */
   uint32_t DQSMode;          /*!< It enables or not the data strobe management.
                                   This parameter can be a value of @ref OSPI_DQSMode */
-}OSPI_HyperbusCmdTypeDef;
+} OSPI_HyperbusCmdTypeDef;
 
 /**
   * @brief  HAL OSPI Auto Polling mode configuration structure definition
@@ -231,7 +227,7 @@ typedef struct
                                     This parameter can be a value of @ref OSPI_AutomaticStop */
   uint32_t Interval;           /*!< Specifies the number of clock cycles between two read during automatic polling phases.
                                     This parameter can be any value between 0 and 0xFFFF */
-}OSPI_AutoPollingTypeDef;
+} OSPI_AutoPollingTypeDef;
 
 /**
   * @brief  HAL OSPI Memory Mapped mode configuration structure definition
@@ -242,7 +238,7 @@ typedef struct
                                     This parameter can be a value of @ref OSPI_TimeOutActivation */
   uint32_t TimeOutPeriod;      /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
                                     This parameter can be any value between 0 and 0xFFFF */
-}OSPI_MemoryMappedTypeDef;
+} OSPI_MemoryMappedTypeDef;
 
 /**
   * @brief HAL OSPI IO Manager Configuration structure definition
@@ -259,10 +255,10 @@ typedef struct
                                         This parameter can be a value of @ref OSPIM_IOPort */
   uint32_t IOHighPort;             /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.
                                         This parameter can be a value of @ref OSPIM_IOPort */
-  uint32_t Req2AckTime;            /*!< It indicates the minimum switching duration (in number of clock cycles) expected 
+  uint32_t Req2AckTime;            /*!< It indicates the minimum switching duration (in number of clock cycles) expected
                                         if some signals are multiplexed in the OSPI IO Manager with the other OSPI.
                                         This parameter can be a value between 1 and 256 */
-}OSPIM_CfgTypeDef;
+} OSPIM_CfgTypeDef;
 
 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
 /**
@@ -283,7 +279,7 @@ typedef enum
 
   HAL_OSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< OSPI MspInit Callback ID          */
   HAL_OSPI_MSP_DEINIT_CB_ID     = 0x0BU   /*!< OSPI MspDeInit Callback ID        */
-}HAL_OSPI_CallbackIDTypeDef;
+} HAL_OSPI_CallbackIDTypeDef;
 
 /**
   * @brief  HAL OSPI Callback pointer definition
@@ -794,10 +790,10 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
 /** @addtogroup OSPI_Exported_Functions_Group1
   * @{
   */
-HAL_StatusTypeDef     HAL_OSPI_Init                 (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_MspInit              (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef     HAL_OSPI_DeInit               (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_MspDeInit            (OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef     HAL_OSPI_Init(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef     HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi);
 
 /**
   * @}
@@ -808,7 +804,7 @@ void                  HAL_OSPI_MspDeInit            (OSPI_HandleTypeDef *hospi);
   * @{
   */
 /* OSPI IRQ handler function */
-void                  HAL_OSPI_IRQHandler           (OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi);
 
 /* OSPI command configuration functions */
 HAL_StatusTypeDef     HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
@@ -829,25 +825,25 @@ HAL_StatusTypeDef     HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoP
 HAL_StatusTypeDef     HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
 
 /* OSPI memory-mapped mode functions */
-HAL_StatusTypeDef     HAL_OSPI_MemoryMapped         (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
+HAL_StatusTypeDef     HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
 
 /* Callback functions in non-blocking modes ***********************************/
-void                  HAL_OSPI_ErrorCallback        (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_AbortCpltCallback    (OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi);
 void                  HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
 
 /* OSPI indirect mode functions */
-void                  HAL_OSPI_CmdCpltCallback      (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_RxCpltCallback       (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_TxCpltCallback       (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_RxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);
-void                  HAL_OSPI_TxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi);
 
 /* OSPI status flag polling mode functions */
-void                  HAL_OSPI_StatusMatchCallback  (OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi);
 
 /* OSPI memory-mapped mode functions */
-void                  HAL_OSPI_TimeOutCallback      (OSPI_HandleTypeDef *hospi);
+void                  HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi);
 
 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
 /* OSPI callback registering/unregistering */
@@ -863,13 +859,13 @@ HAL_StatusTypeDef     HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL
 /** @addtogroup OSPI_Exported_Functions_Group3
   * @{
   */
-HAL_StatusTypeDef     HAL_OSPI_Abort                (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef     HAL_OSPI_Abort_IT             (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef     HAL_OSPI_SetFifoThreshold     (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
-uint32_t              HAL_OSPI_GetFifoThreshold     (OSPI_HandleTypeDef *hospi);
-HAL_StatusTypeDef     HAL_OSPI_SetTimeout           (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
-uint32_t              HAL_OSPI_GetError             (OSPI_HandleTypeDef *hospi);
-uint32_t              HAL_OSPI_GetState             (OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef     HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef     HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef     HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold);
+uint32_t              HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi);
+HAL_StatusTypeDef     HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout);
+uint32_t              HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi);
+uint32_t              HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi);
 
 /**
   * @}
@@ -1028,8 +1024,6 @@ HAL_StatusTypeDef     HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD
 
 #define IS_OSPI_CS_BOUNDARY(BOUNDARY)      ((BOUNDARY) <= 31U)
 
-#define IS_OSPI_CKCSHT(CLK_NB)             ((CLK_NB) <= 7U)
-
 #define IS_OSPI_DLYBYP(MODE)               (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
                                             ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
 
@@ -1079,5 +1073,3 @@ HAL_StatusTypeDef     HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeD
 #endif
 
 #endif /* STM32H7xx_HAL_OSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c
index 2b3fd1bd5b..af78206b19 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c
@@ -9,6 +9,17 @@
   *           + Region setting/enable functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -58,11 +69,11 @@
 
      The compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS, when set to 1,
      allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_OTFDEC_RegisterCallback()
+     Use Functions HAL_OTFDEC_RegisterCallback()
      to register an interrupt callback.
     [..]
 
-     Function @ref HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
+     Function HAL_OTFDEC_RegisterCallback() allows to register following callbacks:
        (+) ErrorCallback                  : OTFDEC error callback
        (+) MspInitCallback                : OTFDEC Msp Init callback
        (+) MspDeInitCallback              : OTFDEC Msp DeInit callback
@@ -70,11 +81,11 @@
      and a pointer to the user callback function.
     [..]
 
-     Use function @ref HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
+     Use function HAL_OTFDEC_UnRegisterCallback to reset a callback to the default
      weak function.
     [..]
 
-     @ref HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+    HAL_OTFDEC_UnRegisterCallback takes as parameters the HAL peripheral handle,
      and the Callback ID.
      This function allows to reset following callbacks:
        (+) ErrorCallback                  : OTFDEC error callback
@@ -82,27 +93,27 @@
        (+) MspDeInitCallback              : OTFDEC Msp DeInit callback
      [..]
 
-     By default, after the @ref HAL_OTFDEC_Init() and when the state is @ref HAL_OTFDEC_STATE_RESET
+     By default, after the HAL_OTFDEC_Init() and when the state is HAL_OTFDEC_STATE_RESET
      all callbacks are set to the corresponding weak functions:
-     example @ref HAL_OTFDEC_ErrorCallback().
+     example HAL_OTFDEC_ErrorCallback().
      Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit() only when
+     reset to the legacy weak functions in the HAL_OTFDEC_Init()HAL_OTFDEC_DeInit() only when
      these callbacks are null (not registered beforehand).
     [..]
 
-     If MspInit or MspDeInit are not null, the @ref HAL_OTFDEC_Init()/ @ref HAL_OTFDEC_DeInit()
+     If MspInit or MspDeInit are not null, the HAL_OTFDEC_Init()/HAL_OTFDEC_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
      [..]
 
-     Callbacks can be registered/unregistered in @ref HAL_OTFDEC_STATE_READY state only.
+     Callbacks can be registered/unregistered in HAL_OTFDEC_STATE_READY state only.
      Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_OTFDEC_STATE_READY or @ref HAL_OTFDEC_STATE_RESET state,
+     in HAL_OTFDEC_STATE_READY or HAL_OTFDEC_STATE_RESET state,
      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
     [..]
 
      Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_OTFDEC_RegisterCallback() before calling @ref HAL_OTFDEC_DeInit()
-     or @ref HAL_OTFDEC_Init() function.
+     using HAL_OTFDEC_RegisterCallback() before calling HAL_OTFDEC_DeInit()
+     or HAL_OTFDEC_Init() function.
      [..]
 
      When the compilation flag USE_HAL_OTFDEC_REGISTER_CALLBACKS is set to 0 or
@@ -111,17 +122,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -148,16 +148,14 @@
 /* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
 
-
-
- /* Exported functions --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
 /** @addtogroup OTFDEC_Exported_Functions
   * @{
   */
 
 /** @defgroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions.
- *
+  *  @brief    Initialization and Configuration functions.
+  *
 @verbatim
   ==============================================================================
               ##### Initialization and de-initialization functions #####
@@ -176,7 +174,7 @@
 HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
 {
   /* Check the OTFDEC handle allocation */
-  if(hotfdec == NULL)
+  if (hotfdec == NULL)
   {
     return HAL_ERROR;
   }
@@ -184,7 +182,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
   /* Check the parameters */
   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
 
-  if(hotfdec->State == HAL_OTFDEC_STATE_RESET)
+  if (hotfdec->State == HAL_OTFDEC_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     __HAL_UNLOCK(hotfdec);
@@ -222,7 +220,7 @@ HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec)
 HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec)
 {
   /* Check the OTFDEC handle allocation */
-  if(hotfdec == NULL)
+  if (hotfdec == NULL)
   {
     return HAL_ERROR;
   }
@@ -305,7 +303,7 @@ __weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec)
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, 
+HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
                                               pOTFDEC_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
@@ -457,8 +455,8 @@ HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, H
   */
 
 /** @defgroup OTFDEC_Exported_Functions_Group2  OTFDEC IRQ handler management
- *  @brief   OTFDEC IRQ handler.
- *
+  *  @brief   OTFDEC IRQ handler.
+  *
 @verbatim
   ==============================================================================
                 ##### OTFDEC IRQ handler management #####
@@ -482,17 +480,17 @@ void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec)
   isr_reg = READ_REG(hotfdec->Instance->ISR);
   if ((isr_reg & OTFDEC_ISR_SEIF) == OTFDEC_ISR_SEIF)
   {
-    SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_SEIF );
+    SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_SEIF);
     hotfdec->ErrorCode |= HAL_OTFDEC_SECURITY_ERROR;
   }
   if ((isr_reg & OTFDEC_ISR_XONEIF) == OTFDEC_ISR_XONEIF)
   {
-    SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF );
+    SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_XONEIF);
     hotfdec->ErrorCode |= HAL_OTFDEC_EXECUTE_ERROR;
   }
   if ((isr_reg & OTFDEC_ISR_KEIF) == OTFDEC_ISR_KEIF)
   {
-    SET_BIT( hotfdec->Instance->ICR, OTFDEC_ICR_KEIF );
+    SET_BIT(hotfdec->Instance->ICR, OTFDEC_ICR_KEIF);
     hotfdec->ErrorCode |= HAL_OTFDEC_KEY_ERROR;
   }
 
@@ -527,8 +525,8 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
 
 
 /** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   Peripheral control functions.
- *
+  *  @brief   Peripheral control functions.
+  *
 @verbatim
   ==============================================================================
                       ##### Peripheral Control functions #####
@@ -550,7 +548,7 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec)
   */
 HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -560,10 +558,10 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32
   /* Take Lock */
   __HAL_LOCK(hotfdec);
 
-  address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+  address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
   region = (OTFDEC_Region_TypeDef *)address;
 
-  SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK );
+  SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_KEYLOCK);
 
   /* Release Lock */
   __HAL_UNLOCK(hotfdec);
@@ -584,7 +582,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32
   */
 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -600,26 +598,26 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_
     /* Take Lock */
     __HAL_LOCK(hotfdec);
 
-    address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+    address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
     region = (OTFDEC_Region_TypeDef *)address;
 
     /* Set Key */
-    WRITE_REG( region->REG_KEYR0, pKey[0]);
+    WRITE_REG(region->REG_KEYR0, pKey[0]);
 
     __DSB();
     __ISB();
 
-    WRITE_REG( region->REG_KEYR1, pKey[1]);
+    WRITE_REG(region->REG_KEYR1, pKey[1]);
 
     __DSB();
     __ISB();
 
-    WRITE_REG( region->REG_KEYR2, pKey[2]);
+    WRITE_REG(region->REG_KEYR2, pKey[2]);
 
     __DSB();
     __ISB();
 
-    WRITE_REG( region->REG_KEYR3, pKey[3]);
+    WRITE_REG(region->REG_KEYR3, pKey[3]);
 
     /* Compute theoretically expected CRC and compare it with that reported by the peripheral */
     if (HAL_OTFDEC_KeyCRCComputation(pKey) != HAL_OTFDEC_RegionGetKeyCRC(hotfdec, RegionIndex))
@@ -645,19 +643,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_
   *         the configuration information for OTFDEC module
   * @param  RegionIndex index of region the mode of which is set
   * @param  mode This parameter can be only:
-  *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY            
+  *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY
                         Only instruction accesses are decrypted
-  *           @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY                    
+  *           @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY
                         Only data accesses are decrypted
-  *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES         
+  *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES
                         All read accesses are decrypted (instruction or data)
-  *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER 
+  *           @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER
                         Only instruction accesses are decrypted with proprietary cipher activated
   * @retval HAL state
   */
 HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -668,7 +666,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32
   /* Take Lock */
   __HAL_LOCK(hotfdec);
 
-  address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+  address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
   region = (OTFDEC_Region_TypeDef *)address;
 
   /* Set mode */
@@ -694,10 +692,10 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32
   *          @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE       OTFDEC region configuration is locked
   * @retval HAL state
   */
-HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, 
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
                                           OTFDEC_RegionConfigTypeDef *Config, uint32_t lock)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -715,30 +713,30 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_
     /* Take Lock */
     __HAL_LOCK(hotfdec);
 
-    address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+    address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
     region = (OTFDEC_Region_TypeDef *)address;
 
     /* Set Nonce */
-    WRITE_REG( region->REG_NONCER0, Config->Nonce[0]);
+    WRITE_REG(region->REG_NONCER0, Config->Nonce[0]);
 
-    WRITE_REG( region->REG_NONCER1, Config->Nonce[1]);
+    WRITE_REG(region->REG_NONCER1, Config->Nonce[1]);
 
     /* Write region protected area start and end addresses */
-    WRITE_REG( region->REG_START_ADDR, Config->StartAddress);
+    WRITE_REG(region->REG_START_ADDR, Config->StartAddress);
 
-    WRITE_REG( region->REG_END_ADDR, Config->EndAddress);
+    WRITE_REG(region->REG_END_ADDR, Config->EndAddress);
 
     /* Write Version */
-    MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, 
-	          (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos );
+    MODIFY_REG(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION,
+               (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos);
 
     /* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */
-    SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+    SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
 
     /* Lock the region configuration according to lock parameter value */
     if (lock == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
     {
-      SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
+      SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE);
     }
 
     /* Release Lock */
@@ -764,7 +762,7 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
   uint32_t  j;
   uint32_t  keyval;
   uint32_t  k;
-  uint32_t * temp = pKey;
+  uint32_t *temp = pKey;
 
   for (j = 0U; j < 4U; j++)
   {
@@ -782,15 +780,15 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
     crc = 0;
     for (i = 0; i < (uint8_t)32; i++)
     {
-      k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31-i))&((uint8_t)0xF)))) & 1U;
+      k = ((((uint32_t)crc >> 7) ^ ((keyval >> ((uint8_t)31 - i)) & ((uint8_t)0xF)))) & 1U;
       crc <<= 1;
       if (k != 0U)
       {
         crc ^= crc7_poly;
-       }
+      }
     }
 
-    crc^=(uint8_t)0x55;
+    crc ^= (uint8_t)0x55;
   }
 
   return (uint32_t) crc;
@@ -807,7 +805,7 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey)
   */
 HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -817,19 +815,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_
   /* Take Lock */
   __HAL_LOCK(hotfdec);
 
-  address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+  address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
   region = (OTFDEC_Region_TypeDef *)address;
 
-  if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+  if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
   {
     /* Configuration is locked, REG_EN bit can't be modified */
     __HAL_UNLOCK(hotfdec);
 
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
 
   /* Enable region processing */
-  SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+  SET_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
 
   /* Release Lock */
   __HAL_UNLOCK(hotfdec);
@@ -848,7 +846,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_
   */
 HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -858,19 +856,19 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32
   /* Take Lock */
   __HAL_LOCK(hotfdec);
 
-  address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+  address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
   region = (OTFDEC_Region_TypeDef *)address;
 
-  if (READ_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
+  if (READ_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_LOCK_ENABLE) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)
   {
     /* Configuration is locked, REG_EN bit can't be modified */
     __HAL_UNLOCK(hotfdec);
 
-     return HAL_ERROR;
+    return HAL_ERROR;
   }
 
   /* Disable region processing */
-  CLEAR_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
+  CLEAR_BIT(region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE);
 
   /* Release Lock */
   __HAL_UNLOCK(hotfdec);
@@ -884,8 +882,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32
   */
 
 /** @defgroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
- *  @brief   Peripheral State functions.
- *
+  *  @brief   Peripheral State functions.
+  *
 @verbatim
   ==============================================================================
                       ##### Peripheral State functions #####
@@ -918,7 +916,7 @@ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec)
   */
 uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
   uint32_t keycrc;
 
@@ -926,10 +924,10 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi
   assert_param(IS_OTFDEC_ALL_INSTANCE(hotfdec->Instance));
   assert_param(IS_OTFDEC_REGIONINDEX(RegionIndex));
 
-  address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+  address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
   region = (OTFDEC_Region_TypeDef *)address;
 
-  keycrc = (READ_REG( region->REG_CONFIGR )) & OTFDEC_REG_CONFIGR_KEYCRC;
+  keycrc = (READ_REG(region->REG_CONFIGR)) & OTFDEC_REG_CONFIGR_KEYCRC;
 
   keycrc >>= OTFDEC_REG_CONFIGR_KEYCRC_Pos;
 
@@ -947,7 +945,7 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi
 HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
                                              OTFDEC_RegionConfigTypeDef *Config)
 {
-  OTFDEC_Region_TypeDef * region;
+  OTFDEC_Region_TypeDef *region;
   uint32_t address;
 
   /* Check the parameters */
@@ -963,7 +961,7 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
     /* Take Lock */
     __HAL_LOCK(hotfdec);
 
-    address =   (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
+    address = (uint32_t)(hotfdec->Instance) + 0x20U + (0x30U * RegionIndex);
     region = (OTFDEC_Region_TypeDef *)address;
 
     /* Read Nonce */
@@ -975,8 +973,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
     Config->EndAddress = READ_REG(region->REG_END_ADDR);
 
     /* Read Version */
-    Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & 
-	                             OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
+    Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) &
+                                 OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos;
 
     /* Release Lock */
     __HAL_UNLOCK(hotfdec);
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h
index 3a49ef2ac0..bfdfb0b456 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,7 +21,7 @@
 #define STM32H7xx_HAL_OTFDEC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -61,7 +60,7 @@ typedef struct
 
   uint16_t          Version;         /*!< OTFDEC region firmware version */
 
-}OTFDEC_RegionConfigTypeDef;
+} OTFDEC_RegionConfigTypeDef;
 
 /**
   * @}
@@ -79,7 +78,7 @@ typedef enum
   HAL_OTFDEC_STATE_RESET             = 0x00U,  /*!< OTFDEC not yet initialized or disabled */
   HAL_OTFDEC_STATE_READY             = 0x01U,  /*!< OTFDEC initialized and ready for use   */
   HAL_OTFDEC_STATE_BUSY              = 0x02U,  /*!< OTFDEC internal processing is ongoing  */
-}HAL_OTFDEC_StateTypeDef;
+} HAL_OTFDEC_StateTypeDef;
 
 /**
   * @brief OTFDEC handle structure definition
@@ -106,7 +105,7 @@ typedef struct
   void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */
 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
 
-}OTFDEC_HandleTypeDef;
+} OTFDEC_HandleTypeDef;
 
 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
 /**
@@ -267,7 +266,7 @@ typedef  void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po
   */
 #define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
 
-  /** @brief  Check whether the specified combination of OTFDEC interrupt flags is set or not.
+/** @brief  Check whether the specified combination of OTFDEC interrupt flags is set or not.
   * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
   *         the configuration information for OTFDEC module
   * @param  __FLAG__ mask on combination of interrupts flags
@@ -279,7 +278,7 @@ typedef  void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po
   *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts flags
   *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts flag
   *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts flags
- * @retval The state of __FLAG__ (TRUE or FALSE).
+  * @retval The state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
 
@@ -319,7 +318,7 @@ void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec);
 #if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
 /* Callbacks Register/UnRegister functions  ***********************************/
 HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
-                                           pOTFDEC_CallbackTypeDef pCallback);
+                                              pOTFDEC_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
 /**
@@ -342,7 +341,7 @@ void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec);
 HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
 HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);
 HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);
-HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, 
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex,
                                           OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
 uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);
 HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
@@ -423,10 +422,11 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
   * @param __MODE__ OTFDEC region operating mode parameter.
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */
-#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY)    || \
-                                                  ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY)           || \
-                                                  ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
-                                                  ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
+#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) \
+  (((__MODE__)== OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY)    || \
+   ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY)           || \
+   ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
+   ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
 
 /**
   * @brief Verify the OTFDEC region index.
@@ -474,6 +474,3 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint
 #endif
 
 #endif /* STM32H7xx_HAL_OTFDEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c
index e577f400c0..221cdfc082 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
@@ -41,17 +52,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -122,7 +122,6 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
   */
 HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
 {
-  USB_OTG_GlobalTypeDef *USBx;
   uint8_t i;
 
   /* Check the PCD handle allocation */
@@ -134,8 +133,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
   /* Check the parameters */
   assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
 
-  USBx = hpcd->Instance;
-
   if (hpcd->State == HAL_PCD_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
@@ -171,12 +168,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
 
   hpcd->State = HAL_PCD_STATE_BUSY;
 
-  /* Disable DMA mode for FS instance */
-  if ((USBx->CID & (0x1U << 8)) == 0U)
-  {
-    hpcd->Init.dma_enable = 0U;
-  }
-
   /* Disable the Interrupts */
   __HAL_PCD_DISABLE(hpcd);
 
@@ -187,8 +178,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
     return HAL_ERROR;
   }
 
-  /* Force Device Mode*/
-  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
+  /* Force Device Mode */
+  if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
+  {
+    hpcd->State = HAL_PCD_STATE_ERROR;
+    return HAL_ERROR;
+  }
 
   /* Init endpoints structures */
   for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@@ -224,7 +219,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
 
   hpcd->USB_Address = 0U;
   hpcd->State = HAL_PCD_STATE_READY;
-  
+
   /* Activate LPM */
   if (hpcd->Init.lpm_enable == 1U)
   {
@@ -318,7 +313,7 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
   * @param  pCallback pointer to the Callback function
@@ -422,7 +417,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
 
 /**
   * @brief  Unregister an USB PCD Callback
-  *         USB PCD callabck is redirected to the weak predefined callback
+  *         USB PCD callback is redirected to the weak predefined callback
   * @param  hpcd USB PCD handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -432,7 +427,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
   *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
   *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
   *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
-  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
   *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
   *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
   * @retval HAL status
@@ -721,7 +716,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
 
 /**
   * @brief  Unregister the USB PCD Iso OUT incomplete Callback
-  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
+  *         USB PCD Iso OUT incomplete Callback is redirected
+  *         to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
   * @param  hpcd PCD handle
   * @retval HAL status
   */
@@ -795,7 +791,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
 
 /**
   * @brief  Unregister the USB PCD Iso IN incomplete Callback
-  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
+  *         USB PCD Iso IN incomplete Callback is redirected
+  *         to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
   * @param  hpcd PCD handle
   * @retval HAL status
   */
@@ -1002,8 +999,8 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
 
   __HAL_LOCK(hpcd);
 
-  if ((hpcd->Init.battery_charging_enable == 1U) &&
-      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
+      (hpcd->Init.battery_charging_enable == 1U))
   {
     /* Enable USB Transceiver */
     USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
@@ -1031,8 +1028,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
 
   (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);
 
-  if ((hpcd->Init.battery_charging_enable == 1U) &&
-      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
+      (hpcd->Init.battery_charging_enable == 1U))
   {
     /* Disable USB Transceiver */
     USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -1053,9 +1050,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
 {
   USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t i, ep_intr, epint, epnum;
-  uint32_t fifoemptymsk, temp;
   USB_OTG_EPTypeDef *ep;
+  uint32_t i;
+  uint32_t ep_intr;
+  uint32_t epint;
+  uint32_t epnum;
+  uint32_t fifoemptymsk;
+  uint32_t RegVal;
 
   /* ensure that we are in device mode */
   if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@@ -1066,6 +1067,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
       return;
     }
 
+    /* store current frame number */
+    hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos;
+
     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
     {
       /* incorrect mode, acknowledge the interrupt */
@@ -1077,30 +1081,31 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
     {
       USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
 
-      temp = USBx->GRXSTSP;
+      RegVal = USBx->GRXSTSP;
 
-      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
+      ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM];
 
-      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
+      if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)
       {
-        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
+        if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U)
         {
           (void)USB_ReadPacket(USBx, ep->xfer_buff,
-                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
+                               (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4));
 
-          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
+          ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
         }
       }
-      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)
+      else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT)
       {
         (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);
-        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
+        ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4;
       }
       else
       {
         /* ... */
       }
+
       USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
     }
 
@@ -1135,6 +1140,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
             CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
           }
 
+          /* Clear OUT Endpoint disable interrupt */
+          if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD)
+          {
+            if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF)
+            {
+              USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
+            }
+
+            ep = &hpcd->OUT_ep[epnum];
+
+            if (ep->is_iso_incomplete == 1U)
+            {
+              ep->is_iso_incomplete = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+              hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+              HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+            }
+
+            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD);
+          }
+
           /* Clear Status Phase Received interrupt */
           if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
           {
@@ -1204,6 +1233,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
           }
           if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
           {
+            (void)USB_FlushTxFifo(USBx, epnum);
+
+            ep = &hpcd->IN_ep[epnum];
+
+            if (ep->is_iso_incomplete == 1U)
+            {
+              ep->is_iso_incomplete = 0U;
+
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+              hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#else
+              HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+            }
+
             CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
           }
           if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
@@ -1294,7 +1338,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
       {
         USBx_INEP(i)->DIEPINT = 0xFB7FU;
         USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-        USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;
         USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
         USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
         USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;
@@ -1366,18 +1409,37 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
     }
 
+    /* Handle Global OUT NAK effective Interrupt */
+    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF))
+    {
+      USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM;
+
+      for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+      {
+        if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U)
+        {
+          /* Abort current transaction and disable the EP */
+          (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum);
+        }
+      }
+    }
+
     /* Handle Incomplete ISO IN Interrupt */
     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
     {
-      /* Keep application checking the corresponding Iso IN endpoint
-      causing the incomplete Interrupt */
-      epnum = 0U;
+      for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+      {
+        RegVal = USBx_INEP(epnum)->DIEPCTL;
 
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
-#else
-      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+        if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) &&
+            ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA))
+        {
+          hpcd->IN_ep[epnum].is_iso_incomplete = 1U;
+
+          /* Abort current transaction and disable the EP */
+          (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U));
+        }
+      }
 
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
     }
@@ -1385,15 +1447,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
     /* Handle Incomplete ISO OUT Interrupt */
     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
     {
-      /* Keep application checking the corresponding Iso OUT endpoint
-      causing the incomplete Interrupt */
-      epnum = 0U;
+      for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++)
+      {
+        RegVal = USBx_OUTEP(epnum)->DOEPCTL;
 
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
-#else
-      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+        if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) &&
+            ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) &&
+            ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U)))
+        {
+          hpcd->OUT_ep[epnum].is_iso_incomplete = 1U;
+
+          USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM;
+
+          if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U)
+          {
+            USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
+            break;
+          }
+        }
+      }
 
       __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
     }
@@ -1413,9 +1485,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
     /* Handle Disconnection event Interrupt */
     if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
     {
-      temp = hpcd->Instance->GOTGINT;
+      RegVal = hpcd->Instance->GOTGINT;
 
-      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
+      if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
       {
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
         hpcd->DisconnectCallback(hpcd);
@@ -1423,7 +1495,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
         HAL_PCD_DisconnectCallback(hpcd);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
       }
-      hpcd->Instance->GOTGINT |= temp;
+      hpcd->Instance->GOTGINT |= RegVal;
     }
   }
 }
@@ -1632,8 +1704,8 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
 
   __HAL_LOCK(hpcd);
 
-  if ((hpcd->Init.battery_charging_enable == 1U) &&
-      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
+      (hpcd->Init.battery_charging_enable == 1U))
   {
     /* Enable USB Transceiver */
     USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
@@ -1656,8 +1728,8 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
   __HAL_LOCK(hpcd);
   (void)USB_DevDisconnect(hpcd->Instance);
 
-  if ((hpcd->Init.battery_charging_enable == 1U) &&
-      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
+  if (((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) != 0U) &&
+      (hpcd->Init.battery_charging_enable == 1U))
   {
     /* Disable USB Transceiver */
     USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -1717,6 +1789,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
     /* Assign a Tx FIFO */
     ep->tx_fifo_num = ep->num;
   }
+
   /* Set initial data PID. */
   if (ep_type == EP_TYPE_BULK)
   {
@@ -1750,7 +1823,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
     ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
     ep->is_in = 0U;
   }
-  ep->num   = ep_addr & EP_ADDR_MSK;
+  ep->num = ep_addr & EP_ADDR_MSK;
 
   __HAL_LOCK(hpcd);
   (void)USB_DeactivateEndpoint(hpcd->Instance, ep);
@@ -1785,14 +1858,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
     ep->dma_addr = (uint32_t)pBuf;
   }
 
-  if ((ep_addr & EP_ADDR_MSK) == 0U)
-  {
-    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
-  }
-  else
-  {
-    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
-  }
+  (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
 
   return HAL_OK;
 }
@@ -1803,7 +1869,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
   * @param  ep_addr endpoint address
   * @retval Data Size
   */
-uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr)
 {
   return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;
 }
@@ -1833,14 +1899,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
     ep->dma_addr = (uint32_t)pBuf;
   }
 
-  if ((ep_addr & EP_ADDR_MSK) == 0U)
-  {
-    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
-  }
-  else
-  {
-    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
-  }
+  (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);
 
   return HAL_OK;
 }
@@ -1924,6 +1983,32 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
   return HAL_OK;
 }
 
+/**
+   * @brief  Abort an USB EP transaction.
+   * @param  hpcd PCD handle
+   * @param  ep_addr endpoint address
+   * @retval HAL status
+   */
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
+{
+  HAL_StatusTypeDef ret;
+  PCD_EPTypeDef *ep;
+
+  if ((0x80U & ep_addr) == 0x80U)
+  {
+    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
+  }
+  else
+  {
+    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
+  }
+
+  /* Stop Xfer */
+  ret = USB_EPStopXfer(hpcd->Instance, ep);
+
+  return ret;
+}
+
 /**
   * @brief  Flush an endpoint
   * @param  hpcd PCD handle
@@ -1992,11 +2077,40 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
   * @param  hpcd PCD handle
   * @retval HAL state
   */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd)
 {
   return hpcd->State;
 }
 
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+/**
+  * @brief  Set the USB Device high speed test mode.
+  * @param  hpcd PCD handle
+  * @param  testmode USB Device high speed test mode
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode)
+{
+  const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  uint32_t USBx_BASE = (uint32_t)USBx;
+
+  switch (testmode)
+  {
+    case TEST_J:
+    case TEST_K:
+    case TEST_SE0_NAK:
+    case TEST_PACKET:
+    case TEST_FORCE_EN:
+      USBx_DEVICE->DCTL |= (uint32_t)testmode << 4;
+      break;
+
+    default:
+      break;
+  }
+
+  return HAL_OK;
+}
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 /**
   * @}
   */
@@ -2078,9 +2192,10 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
   */
 static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
 {
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  USB_OTG_EPTypeDef *ep;
+  const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
   uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
 
   if (hpcd->Init.dma_enable == 1U)
@@ -2108,18 +2223,24 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
       }
       else
       {
-        /* out data packet received over EP0 */
-        hpcd->OUT_ep[epnum].xfer_count =
-          hpcd->OUT_ep[epnum].maxpacket -
-          (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+        ep = &hpcd->OUT_ep[epnum];
 
-        hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+        /* out data packet received over EP */
+        ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
 
-        if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
+        if (epnum == 0U)
         {
-          /* this is ZLP, so prepare EP0 for next setup */
-          (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+          if (ep->xfer_len == 0U)
+          {
+            /* this is ZLP, so prepare EP0 for next setup */
+            (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
+          }
+          else
+          {
+            ep->xfer_buff += ep->xfer_count;
+          }
         }
+
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
         hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
 #else
@@ -2183,9 +2304,9 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint
   */
 static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
 {
-  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+  const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
   uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
 
   if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
@@ -2224,5 +2345,3 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h
index 7236566114..f1fe87fbd4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -107,6 +106,7 @@ typedef struct
   uint32_t                Setup[12];   /*!< Setup packet buffer               */
   PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */
   uint32_t                BESL;
+  uint32_t                FrameNumber; /*!< Store Current Frame number        */
 
 
   uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .
@@ -190,20 +190,24 @@ typedef struct
   *  @brief macros to handle interrupts and specific clock configurations
   * @{
   */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 #define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
 #define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
 
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+  ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__))
 #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
 
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \
+  *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
 
-#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)       *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \
+  *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
 
-#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)         *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
-
-#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)      ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \
+  ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)
 
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
 #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
@@ -270,12 +274,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType
   * @}
   */
 
-HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
-                                           HAL_PCD_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID,
                                            pPCD_CallbackTypeDef pCallback);
 
-HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
-                                             HAL_PCD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
 
 HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
                                                        pPCD_DataOutStageCallbackTypeDef pCallback);
@@ -297,14 +299,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
 
 HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
 
-HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
-                                              pPCD_BcdCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
 
-HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
-                                              pPCD_LpmCallbackTypeDef pCallback);
-
+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
 /**
@@ -343,24 +341,21 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
 HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                  uint16_t ep_mps, uint8_t ep_type);
-
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
 HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                     uint8_t *pBuf, uint32_t len);
-
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
-                                      uint8_t *pBuf, uint32_t len);
-
-
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
 HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
 HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
 HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
+HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode);
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
-uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr);
 /**
   * @}
   */
@@ -369,7 +364,7 @@ uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr
 /** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
   * @{
   */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
 /**
   * @}
   */
@@ -401,27 +396,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
 #if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 #ifndef USB_OTG_DOEPINT_OTEPSPR
 #define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_OTEPSPR */
 
 #ifndef USB_OTG_DOEPMSK_OTEPSPRM
 #define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */
 
 #ifndef USB_OTG_DOEPINT_NAK
 #define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_NAK */
 
 #ifndef USB_OTG_DOEPMSK_NAKM
 #define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NAKM */
 
 #ifndef USB_OTG_DOEPINT_STPKTRX
 #define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */
-#endif
+#endif /* defined USB_OTG_DOEPINT_STPKTRX */
 
 #ifndef USB_OTG_DOEPMSK_NYETM
 #define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */
-#endif
+#endif /* defined USB_OTG_DOEPMSK_NYETM */
 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 /* Private macros ------------------------------------------------------------*/
@@ -447,5 +442,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
 #endif
 
 #endif /* STM32H7xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c
index 5debbe016d..1d4bfe902d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c
@@ -10,13 +10,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -164,26 +163,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
   /* Enable DCD : Data Contact Detect */
   USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
 
-  /* Wait Detect flag or a timeout is happen*/
-  while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
-  {
-    /* Check for the Timeout */
-    if ((HAL_GetTick() - tickstart) > 1000U)
-    {
-#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
-#else
-      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
-#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  /* Wait for Min DCD Timeout */
+  HAL_Delay(300U);
 
-      return;
-    }
-  }
-
-  /* Right response got */
-  HAL_Delay(200U);
-
-  /* Check Detect flag*/
+  /* Check Detect flag */
   if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
   {
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
@@ -193,11 +176,11 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
   }
 
-  /*Primary detection: checks if connected to Standard Downstream Port
+  /* Primary detection: checks if connected to Standard Downstream Port
   (without charging capability) */
-  USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
+  USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN;
   HAL_Delay(50U);
-  USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
+  USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
   HAL_Delay(50U);
 
   if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
@@ -213,9 +196,9 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
   {
     /* start secondary detection to check connection to Charging Downstream
     Port or Dedicated Charging Port */
-    USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
+    USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
     HAL_Delay(50U);
-    USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
+    USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
     HAL_Delay(50U);
 
     if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
@@ -229,7 +212,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
     }
     else
     {
-      /* case Charging Downstream Port  */
+      /* case Charging Downstream Port */
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
       hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
 #else
@@ -241,11 +224,23 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
   /* Battery Charging capability discovery finished */
   (void)HAL_PCDEx_DeActivateBCD(hpcd);
 
+  /* Check for the Timeout, else start USB Device */
+  if ((HAL_GetTick() - tickstart) > 1000U)
+  {
 #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
-  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+    hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
 #else
-  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
+  else
+  {
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+    hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#else
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+  }
 }
 
 /**
@@ -344,5 +339,3 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.h
index babeda7751..9cfa0125e6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -23,7 +22,7 @@
 
 #ifdef __cplusplus
 extern "C" {
-#endif
+#endif /* __cplusplus */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
@@ -83,9 +82,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
 
 #ifdef __cplusplus
 }
-#endif
+#endif /* __cplusplus */
 
 
 #endif /* STM32H7xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.c
index 19f0a69362..7824ebb05d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.c
@@ -9,6 +9,17 @@
   *           + IO operation functions
   *           + Peripheral State and Errors functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -42,7 +53,6 @@
     (#) Initialize the PSSI registers by calling the @ref HAL_PSSI_Init(), configure also the low level Hardware
         (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_PSSI_MspInit(&hpssi) API.
 
-
     (#) For PSSI IO operations, two operation modes are available within this driver :
 
     *** Polling mode IO operation ***
@@ -131,18 +141,6 @@
        (@) You can refer to the PSSI HAL driver header file for more useful macros
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -180,17 +178,26 @@
   * @{
   */
 /* Private functions to handle DMA transfer */
+#if defined(HAL_DMA_MODULE_ENABLED)
 void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 void PSSI_DMAError(DMA_HandleTypeDef *hdma);
 void PSSI_DMAAbort(DMA_HandleTypeDef *hdma);
-
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
 /* Private functions to handle IT transfer */
 static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode);
 
+
+/* Private functions for PSSI transfer IRQ handler */
+
+
 /* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
+                                                       uint32_t Timeout, uint32_t Tickstart);
+
+/* Private functions to centralize the enable/disable of Interrupts */
+
 
 /**
   * @}
@@ -203,8 +210,8 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi
   */
 
 /** @defgroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
+  *  @brief    Initialization and Configuration functions
+  *
 @verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
@@ -257,6 +264,7 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
     /* Allocate lock resource and initialize it */
     hpssi->Lock = HAL_UNLOCKED;
 
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     /* Init the PSSI Callback settings */
     hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
     hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback; /* Legacy weak RxCpltCallback */
@@ -270,7 +278,10 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
 
     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
     hpssi->MspInitCallback(hpssi);
-
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_PSSI_MspInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
   }
 
   hpssi->State = HAL_PSSI_STATE_BUSY;
@@ -281,8 +292,9 @@ HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi)
   /*---------------------------- PSSIx CR Configuration ----------------------*/
   /* Configure PSSIx: Control Signal and Bus Width*/
 
-  MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DERDYCFG|PSSI_CR_EDM|PSSI_CR_DEPOL|PSSI_CR_RDYPOL,
-             hpssi->Init.ControlSignal|hpssi->Init.DataEnablePolarity|hpssi->Init.ReadyPolarity|hpssi->Init.BusWidth);
+  MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DERDYCFG | PSSI_CR_EDM | PSSI_CR_DEPOL | PSSI_CR_RDYPOL,
+             hpssi->Init.ControlSignal | hpssi->Init.DataEnablePolarity |
+             hpssi->Init.ReadyPolarity | hpssi->Init.BusWidth);
 
   hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
   hpssi->State = HAL_PSSI_STATE_READY;
@@ -312,6 +324,7 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
   /* Disable the PSSI Peripheral Clock */
   HAL_PSSI_DISABLE(hpssi);
 
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
   if (hpssi->MspDeInitCallback == NULL)
   {
     hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit; /* Legacy weak MspDeInit  */
@@ -319,6 +332,10 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi)
 
   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
   hpssi->MspDeInitCallback(hpssi);
+#else
+  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
+  HAL_PSSI_MspDeInit(hpssi);
+#endif /*USE_HAL_PSSI_REGISTER_CALLBACKS*/
 
   hpssi->ErrorCode = HAL_PSSI_ERROR_NONE;
   hpssi->State = HAL_PSSI_STATE_RESET;
@@ -346,7 +363,7 @@ __weak void HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi)
 }
 
 /**
-  * @brief DeInitialize the PSSI MSP.
+  * @brief De-Initialize the PSSI MSP.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
   *                the configuration information for the specified PSSI.
   * @retval None
@@ -356,14 +373,18 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hpssi);
 
-  /* NOTE : This function should not be modified, when the callback is needed,
+  /* NOTE : This function should not be modified; when the callback is needed,
             the HAL_PSSI_MspDeInit can be implemented in the user file
    */
 }
 
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User PSSI Callback
   *         To be used instead of the weak predefined callback
+  * @note   The HAL_PSSI_RegisterCallback() may be called before HAL_PSSI_Init() in
+  *         HAL_PSSI_STATE_RESET to register callbacks for HAL_PSSI_MSPINIT_CB_ID
+  *         and HAL_PSSI_MSPDEINIT_CB_ID.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
   *                the configuration information for the specified PSSI.
   * @param  CallbackID ID of the callback to be registered
@@ -377,7 +398,8 @@ __weak void HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi)
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
+                                            pPSSI_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -388,8 +410,6 @@ HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hpssi);
 
   if (HAL_PSSI_STATE_READY == hpssi->State)
   {
@@ -458,14 +478,15 @@ HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hpssi);
   return status;
 }
 
 /**
   * @brief  Unregister an PSSI Callback
   *         PSSI callback is redirected to the weak predefined callback
+  * @note   The HAL_PSSI_UnRegisterCallback() may be called before HAL_PSSI_Init() in
+  *         HAL_PSSI_STATE_RESET to un-register callbacks for HAL_PSSI_MSPINIT_CB_ID
+  *         and HAL_PSSI_MSPDEINIT_CB_ID.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
   *                the configuration information for the specified PSSI.
   * @param  CallbackID ID of the callback to be unregistered
@@ -482,35 +503,32 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hpssi);
-
   if (HAL_PSSI_STATE_READY == hpssi->State)
   {
     switch (CallbackID)
     {
       case HAL_PSSI_TX_COMPLETE_CB_ID :
-        hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback; /* Legacy weak TxCpltCallback */
+        hpssi->TxCpltCallback = HAL_PSSI_TxCpltCallback;             /* Legacy weak TxCpltCallback     */
         break;
 
       case HAL_PSSI_RX_COMPLETE_CB_ID :
-        hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback;   /* Legacy weak RxCpltCallback  */
+        hpssi->RxCpltCallback = HAL_PSSI_RxCpltCallback;             /* Legacy weak RxCpltCallback     */
         break;
 
       case HAL_PSSI_ERROR_CB_ID :
-        hpssi->ErrorCallback = HAL_PSSI_ErrorCallback;               /* Legacy weak ErrorCallback        */
+        hpssi->ErrorCallback = HAL_PSSI_ErrorCallback;               /* Legacy weak ErrorCallback      */
         break;
 
       case HAL_PSSI_ABORT_CB_ID :
-        hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
+        hpssi->AbortCpltCallback = HAL_PSSI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback  */
         break;
 
       case HAL_PSSI_MSPINIT_CB_ID :
-        hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit              */
+        hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit            */
         break;
 
       case HAL_PSSI_MSPDEINIT_CB_ID :
-        hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit            */
+        hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit          */
         break;
 
       default :
@@ -527,11 +545,11 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS
     switch (CallbackID)
     {
       case HAL_PSSI_MSPINIT_CB_ID :
-        hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit              */
+        hpssi->MspInitCallback = HAL_PSSI_MspInit;                   /* Legacy weak MspInit            */
         break;
 
       case HAL_PSSI_MSPDEINIT_CB_ID :
-        hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit            */
+        hpssi->MspDeInitCallback = HAL_PSSI_MspDeInit;               /* Legacy weak MspDeInit          */
         break;
 
       default :
@@ -552,19 +570,18 @@ HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSS
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hpssi);
   return status;
 }
 
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
 /** @defgroup PSSI_Exported_Functions_Group2 Input and Output operation functions
- *  @brief   Data transfers functions
- *
+  *  @brief   Data transfers functions
+  *
 @verbatim
  ===============================================================================
                       ##### IO operation functions #####
@@ -614,13 +631,9 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
   uint32_t tickstart;
   uint32_t  transfer_size = Size;
 
-#if defined (__GNUC__)
-  __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
-#endif /* __GNUC__ */
-
   if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
-      ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
-      ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
+      ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
+      ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
   {
     hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
     return HAL_ERROR;
@@ -637,10 +650,13 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
     HAL_PSSI_DISABLE(hpssi);
 
     /* Configure transfer parameters */
-    hpssi->Instance->CR |= PSSI_CR_OUTEN_OUTPUT |
-      ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL);
+    MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+              (PSSI_CR_OUTEN_OUTPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL)));
+
+#if defined(HAL_DMA_MODULE_ENABLED)
     /* DMA Disable */
     hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
     /* Enable the selected PSSI peripheral */
     HAL_PSSI_ENABLE(hpssi);
@@ -673,6 +689,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
     else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
     {
       uint16_t *pbuffer = (uint16_t *)pData;
+      __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
+
       while (transfer_size > 0U)
       {
         /* Init tickstart for timeout management*/
@@ -687,16 +705,11 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
           return HAL_ERROR;
         }
         /* Write data to DR */
-#if defined (__GNUC__)
-        *pdr_16bits = *pbuffer;
-#else
-        *(__IO uint16_t *)((uint32_t)(&hpssi->Instance->DR)) = *pbuffer;
-#endif /* __GNUC__ */
+        *dr = *pbuffer;
 
         /* Increment Buffer pointer */
         pbuffer++;
         transfer_size -= 2U;
-
       }
     }
     else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
@@ -722,7 +735,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
         pbuffer++;
         transfer_size -= 4U;
       }
-
     }
     else
     {
@@ -758,7 +770,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, u
   }
 }
 
-
 /**
   * @brief  Receives an amount of data in blocking mode.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -772,13 +783,10 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
 {
   uint32_t tickstart;
   uint32_t  transfer_size = Size;
-#if defined (__GNUC__)
-  __IO uint16_t *pdr_16bits = (__IO uint16_t *)(&(hpssi->Instance->DR));
-#endif /* __GNUC__ */
 
   if (((hpssi->Init.DataWidth == HAL_PSSI_8BITS) && (hpssi->Init.BusWidth != HAL_PSSI_8LINES)) ||
-      ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size%2U) != 0U)) ||
-      ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size%4U) != 0U)))
+      ((hpssi->Init.DataWidth == HAL_PSSI_16BITS) && ((Size % 2U) != 0U)) ||
+      ((hpssi->Init.DataWidth == HAL_PSSI_32BITS) && ((Size % 4U) != 0U)))
   {
     hpssi->ErrorCode = HAL_PSSI_ERROR_NOT_SUPPORTED;
     return HAL_ERROR;
@@ -795,11 +803,13 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
     /* Disable the selected PSSI peripheral */
     HAL_PSSI_DISABLE(hpssi);
     /* Configure transfer parameters */
-    hpssi->Instance->CR |= PSSI_CR_OUTEN_INPUT |((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE)?0U:PSSI_CR_CKPOL);
-
+    MODIFY_REG(hpssi->Instance->CR, (PSSI_CR_OUTEN | PSSI_CR_CKPOL),
+              (PSSI_CR_OUTEN_INPUT | ((hpssi->Init.ClockPolarity == HAL_PSSI_FALLING_EDGE) ? 0U : PSSI_CR_CKPOL)));
 
+#if defined(HAL_DMA_MODULE_ENABLED)
     /* DMA Disable */
     hpssi->Instance->CR &= PSSI_CR_DMA_DISABLE;
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
     /* Enable the selected PSSI peripheral */
     HAL_PSSI_ENABLE(hpssi);
@@ -829,6 +839,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
     else if (hpssi->Init.DataWidth == HAL_PSSI_16BITS)
     {
       uint16_t *pbuffer = (uint16_t *)pData;
+      __IO uint16_t *dr = (__IO uint16_t *)(&hpssi->Instance->DR);
 
       while (transfer_size > 0U)
       {
@@ -845,15 +856,9 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
         }
 
         /* Read data from DR */
-#if defined (__GNUC__)
-        *pbuffer = *pdr_16bits;
-#else
-        *pbuffer = *(__IO uint16_t *)((uint32_t)&hpssi->Instance->DR);
-#endif /* __GNUC__ */
-
+        *pbuffer = *dr;
         pbuffer++;
         transfer_size -= 2U;
-
       }
     }
     else if (hpssi->Init.DataWidth == HAL_PSSI_32BITS)
@@ -878,7 +883,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
         *pbuffer = *(__IO uint32_t *)(&hpssi->Instance->DR);
         pbuffer++;
         transfer_size -= 4U;
-
       }
     }
     else
@@ -899,7 +903,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
       return HAL_ERROR;
     }
 
-
     hpssi->State = HAL_PSSI_STATE_READY;
 
     /* Process Unlocked */
@@ -913,6 +916,7 @@ HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, ui
   }
 }
 
+#if defined(HAL_DMA_MODULE_ENABLED)
 /**
   * @brief  Transmit an amount of data in non-blocking mode with DMA
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -956,15 +960,17 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
       {
 
         /* Configure BusWidth */
-        if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+        if (hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
         {
-          MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
-                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+                     PSSI_CR_DMA_ENABLE | PSSI_CR_OUTEN_OUTPUT |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
         }
         else
         {
-          MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
-                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?0U:PSSI_CR_CKPOL));
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+                     PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth | PSSI_CR_OUTEN_OUTPUT |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? 0U : PSSI_CR_CKPOL));
         }
 
         /* Set the PSSI DMA transfer complete callback */
@@ -978,7 +984,8 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
         hpssi->hdmatx->XferAbortCallback = NULL;
 
         /* Enable the DMA  */
-        dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR, hpssi->XferSize);
+        dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmatx, (uint32_t)pData, (uint32_t)&hpssi->Instance->DR,
+                                         hpssi->XferSize);
       }
       else
       {
@@ -996,8 +1003,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
 
       if (dmaxferstatus == HAL_OK)
       {
-
-
         /* Update XferCount value */
         hpssi->XferCount -= hpssi->XferSize;
 
@@ -1042,7 +1047,6 @@ HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDa
 
       HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
     }
-
     return HAL_OK;
   }
   else
@@ -1092,17 +1096,17 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
     {
       if (hpssi->hdmarx != NULL)
       {
-
         /* Configure BusWidth */
-        if( hpssi->hdmatx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
+        if (hpssi->hdmarx->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
         {
-          MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE |
-                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL, PSSI_CR_DMA_ENABLE |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
         }
         else
         {
-          MODIFY_REG(hpssi->Instance->CR,PSSI_CR_DMAEN|PSSI_CR_OUTEN|PSSI_CR_CKPOL,PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
-                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE)?PSSI_CR_CKPOL:0U));
+          MODIFY_REG(hpssi->Instance->CR, PSSI_CR_DMAEN | PSSI_CR_OUTEN | PSSI_CR_CKPOL,
+                     PSSI_CR_DMA_ENABLE | hpssi->Init.BusWidth |
+                     ((hpssi->Init.ClockPolarity == HAL_PSSI_RISING_EDGE) ? PSSI_CR_CKPOL : 0U));
         }
 
         /* Set the PSSI DMA transfer complete callback */
@@ -1116,7 +1120,8 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
         hpssi->hdmarx->XferAbortCallback = NULL;
 
         /* Enable the DMA  */
-        dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData, hpssi->XferSize);
+        dmaxferstatus = HAL_DMA_Start_IT(hpssi->hdmarx, (uint32_t)&hpssi->Instance->DR, (uint32_t)pData,
+                                         hpssi->XferSize);
       }
       else
       {
@@ -1167,7 +1172,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
     }
     else
     {
-
       /* Process Unlocked */
       __HAL_UNLOCK(hpssi);
 
@@ -1183,8 +1187,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
   }
 }
 
-
-
 /**
   * @brief  Abort a DMA process communication with Interrupt.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1193,7 +1195,6 @@ HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pDat
   */
 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
 {
-
   /* Process Locked */
   __HAL_LOCK(hpssi);
 
@@ -1208,7 +1209,6 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
   {
     if (hpssi->State == HAL_PSSI_STATE_BUSY_TX)
     {
-
       hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
 
       if (hpssi->hdmatx != NULL)
@@ -1224,12 +1224,10 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
           hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
         }
       }
-
     }
     /* Abort DMA RX transfer if any */
     else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
     {
-
       hpssi->Instance->CR &= ~PSSI_CR_DMAEN;
 
       if (hpssi->hdmarx != NULL)
@@ -1248,12 +1246,16 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
     }
     else
     {
+
       /* Call the error callback */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
       hpssi->ErrorCallback(hpssi);
+#else
+      HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
     }
   }
 
-
   /* Process Unlocked */
   __HAL_UNLOCK(hpssi);
 
@@ -1263,16 +1265,16 @@ HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi)
   HAL_PSSI_ENABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
 
   return HAL_OK;
-
 }
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
 /**
   * @}
   */
 
-/** @defgroup PSSI_Exported_Functions_Group3 IRQ Handler and Callbacks
- * @{
- */
+/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
 
 /**
   * @brief  This function handles PSSI event interrupt request.
@@ -1286,13 +1288,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
   if (HAL_PSSI_GET_FLAG(hpssi, PSSI_FLAG_OVR_MIS) != 0U)
   {
     /* Reset handle parameters */
-
     hpssi->XferCount     = 0U;
 
     /* Disable all interrupts */
     HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
 
-
+#if defined(HAL_DMA_MODULE_ENABLED)
     /* Abort DMA TX transfer if any */
     if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
     {
@@ -1319,7 +1320,6 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
             hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
           }
         }
-
       }
       /* Abort DMA RX transfer if any */
       else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
@@ -1348,10 +1348,15 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
       }
       else
       {
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
         /* Call the corresponding callback to inform upper layer of the error */
         hpssi->ErrorCallback(hpssi);
+#else
+        HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
       }
     }
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
     /* If state is an abort treatment on going, don't change state */
     if (hpssi->State == HAL_PSSI_STATE_ABORT)
@@ -1361,9 +1366,12 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
       /* Process Unlocked */
       __HAL_UNLOCK(hpssi);
 
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
       /* Call the corresponding callback to inform upper layer of End of Transfer */
       hpssi->AbortCpltCallback(hpssi);
-
+#else
+      HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
     }
     else
     {
@@ -1372,15 +1380,16 @@ void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi)
       /* Process Unlocked */
       __HAL_UNLOCK(hpssi);
 
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
       /* Call the corresponding callback to inform upper layer of End of Transfer */
       hpssi->ErrorCallback(hpssi);
-
+#else
+      HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
     }
-
   }
 }
 
-
 /**
   * @brief   Tx Transfer complete callback.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1413,7 +1422,6 @@ __weak void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi)
    */
 }
 
-
 /**
   * @brief  PSSI error callback.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
@@ -1450,9 +1458,9 @@ __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
   * @}
   */
 
-/** @defgroup PSSI_Exported_Functions_Group4 Peripheral State, Mode and Error functions
- *  @brief   Peripheral State, Mode and Error functions
- *
+/** @defgroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
+  *  @brief   Peripheral State, Mode and Error functions
+  *
 @verbatim
  ===============================================================================
             ##### Peripheral State, Mode and Error functions #####
@@ -1471,20 +1479,19 @@ __weak void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi)
   *                the configuration information for the specified PSSI.
   * @retval HAL state
   */
-HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi)
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi)
 {
   /* Return PSSI handle state */
   return hpssi->State;
 }
 
-
 /**
-* @brief  Return the PSSI error code.
+  * @brief  Return the PSSI error code.
   * @param  hpssi Pointer to a PSSI_HandleTypeDef structure that contains
   *              the configuration information for the specified PSSI.
-* @retval PSSI Error Code
-*/
-uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
+  * @retval PSSI Error Code
+  */
+uint32_t HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi)
 {
   return hpssi->ErrorCode;
 }
@@ -1509,9 +1516,7 @@ uint32_t HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi)
   */
 static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
 {
-
   /* Reset handle parameters */
-
   hpssi->XferCount     = 0U;
 
   /* Set new error code */
@@ -1520,7 +1525,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
   /* Disable all interrupts */
   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
 
-
+#if defined(HAL_DMA_MODULE_ENABLED)
   /* Abort DMA TX transfer if any */
   if ((hpssi->Instance->CR & PSSI_CR_DMAEN) == PSSI_CR_DMAEN)
   {
@@ -1544,7 +1549,6 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
           hpssi->hdmatx->XferAbortCallback(hpssi->hdmatx);
         }
       }
-
     }
     /* Abort DMA RX transfer if any */
     else if (hpssi->State == HAL_PSSI_STATE_BUSY_RX)
@@ -1573,6 +1577,7 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
       /*Nothing to do*/
     }
   }
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
   /* If state is an abort treatment on going, don't change state */
   if (hpssi->State == HAL_PSSI_STATE_ABORT)
@@ -1583,9 +1588,11 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
     __HAL_UNLOCK(hpssi);
 
     /* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->AbortCpltCallback(hpssi);
-
+#else
+    HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
   else
   {
@@ -1596,11 +1603,15 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
     __HAL_UNLOCK(hpssi);
 
     /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->ErrorCallback(hpssi);
-
+#else
+    HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
 }
 
+#if defined(HAL_DMA_MODULE_ENABLED)
 /**
   * @brief  DMA PSSI slave transmit process complete callback.
   * @param  hdma DMA handle
@@ -1608,11 +1619,11 @@ static void PSSI_Error(PSSI_HandleTypeDef *hpssi, uint32_t ErrorCode)
   */
 void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   uint32_t tmperror;
 
-
   /* Disable Interrupts */
   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
 
@@ -1634,12 +1645,12 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
     __HAL_UNLOCK(hpssi);
 
     /* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->TxCpltCallback(hpssi);
-
+#else
+    HAL_PSSI_TxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
-
-
 }
 
 /**
@@ -1649,11 +1660,11 @@ void PSSI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
   */
 void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   uint32_t tmperror;
 
-
   /* Disable Interrupts */
   HAL_PSSI_DISABLE_IT(hpssi, PSSI_FLAG_OVR_RIS);
 
@@ -1675,11 +1686,12 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
     __HAL_UNLOCK(hpssi);
 
     /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->RxCpltCallback(hpssi);
-
+#else
+    HAL_PSSI_RxCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
-
-
 }
 
 /**
@@ -1690,7 +1702,8 @@ void PSSI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   */
 void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
 {
-  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   /* Reset AbortCpltCallback */
   hpssi->hdmatx->XferAbortCallback = NULL;
@@ -1702,16 +1715,23 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
     hpssi->State = HAL_PSSI_STATE_READY;
 
     /* Call the corresponding callback to inform upper layer of End of Transfer */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->AbortCpltCallback(hpssi);
-
+#else
+    HAL_PSSI_AbortCpltCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
   else
   {
     /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->ErrorCallback(hpssi);
+#else
+    HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
 }
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
 /**
   * @brief  This function handles PSSI Communication Timeout.
@@ -1723,7 +1743,8 @@ void PSSI_DMAAbort(DMA_HandleTypeDef *hdma)
   * @param  Tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi, uint32_t Flag, FlagStatus Status,
+                                                       uint32_t Timeout, uint32_t Tickstart)
 {
   while ((HAL_PSSI_GET_STATUS(hpssi, Flag) & Flag) == (uint32_t)Status)
   {
@@ -1744,13 +1765,15 @@ static HAL_StatusTypeDef PSSI_WaitOnStatusUntilTimeout(PSSI_HandleTypeDef *hpssi
   }
   return HAL_OK;
 }
+
+#if defined(HAL_DMA_MODULE_ENABLED)
 void PSSI_DMAError(DMA_HandleTypeDef *hdma)
 {
-  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
+  /* Derogation MISRAC2012-Rule-11.5 */
+  PSSI_HandleTypeDef *hpssi = (PSSI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent);
 
   uint32_t tmperror;
 
-
   /* Disable the selected PSSI peripheral */
   HAL_PSSI_DISABLE(hpssi);
 
@@ -1774,12 +1797,14 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma)
     __HAL_UNLOCK(hpssi);
 
     /* Call the corresponding callback to inform upper layer of End of Transfer */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
     hpssi->ErrorCallback(hpssi);
-
+#else
+    HAL_PSSI_ErrorCallback(hpssi);
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
   }
-
 }
-
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
 
 /**
@@ -1794,5 +1819,3 @@ void PSSI_DMAError(DMA_HandleTypeDef *hdma)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h
index cd5023447f..0fde68c4ca 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -32,6 +31,12 @@ extern "C" {
   * @{
   */
 #if defined(PSSI)
+
+#ifndef USE_HAL_PSSI_REGISTER_CALLBACKS
+/* For backward compatibility, if USE_HAL_PSSI_REGISTER_CALLBACKS not defined, define it to 1*/
+#define USE_HAL_PSSI_REGISTER_CALLBACKS 0U
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
 /** @addtogroup PSSI PSSI
   * @brief PSSI HAL module driver
   * @{
@@ -48,12 +53,18 @@ extern "C" {
   */
 typedef struct
 {
-  uint32_t  DataWidth;          /* !< Configures the parallel bus width 8 lines or 16 lines */
-  uint32_t  BusWidth;           /* !< Configures the parallel bus width 8 lines or 16 lines */
-  uint32_t  ControlSignal;      /* !< Configures Data enable and Data ready */
-  uint32_t  ClockPolarity;      /* !< Configures the PSSI Input Clock polarity */
-  uint32_t  DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
-  uint32_t  ReadyPolarity;      /* !< Configures the PSSI Ready polarity */
+  uint32_t  DataWidth;          /* !< Configures the data width.
+                                      This parameter can be a value of @ref PSSI_DATA_WIDTH. */
+  uint32_t  BusWidth;           /* !< Configures the parallel bus width.
+                                      This parameter can be a value of @ref PSSI_BUS_WIDTH. */
+  uint32_t  ControlSignal;      /* !< Configures Data enable and Data ready.
+                                      This parameter can be a value of @ref ControlSignal_Configuration. */
+  uint32_t  ClockPolarity;      /* !< Configures the PSSI Input Clock polarity.
+                                      This parameter can be a value of @ref Clock_Polarity. */
+  uint32_t  DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity.
+                                      This parameter can be a value of @ref Data_Enable_Polarity. */
+  uint32_t  ReadyPolarity;      /* !< Configures the PSSI Ready polarity.
+                                      This parameter can be a value of @ref Ready_Polarity. */
 
 } PSSI_InitTypeDef;
 
@@ -77,16 +88,23 @@ typedef enum
 /**
   * @brief  PSSI handle Structure definition
   */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
 typedef struct __PSSI_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
 {
   PSSI_TypeDef         *Instance;    /*!< PSSI register base address.    */
   PSSI_InitTypeDef      Init;        /*!< PSSI Initialization Structure. */
   uint32_t             *pBuffPtr;    /*!< PSSI Data buffer.              */
   uint32_t              XferCount;   /*!< PSSI transfer count            */
   uint32_t              XferSize;    /*!< PSSI  transfer size            */
+#if defined(HAL_DMA_MODULE_ENABLED)
   DMA_HandleTypeDef    *hdmatx;      /*!< PSSI Tx DMA Handle parameters  */
   DMA_HandleTypeDef    *hdmarx;      /*!< PSSI Rx DMA Handle parameters  */
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
   void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
   void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
   void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi);     /*!< PSSI transfer complete callback. */
@@ -94,6 +112,7 @@ typedef struct __PSSI_HandleTypeDef
 
   void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi);   /*!< PSSI Msp Init callback.          */
   void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback.        */
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
 
   HAL_LockTypeDef             Lock;                               /*!< PSSI lock.                       */
   __IO HAL_PSSI_StateTypeDef State;                               /*!< PSSI transfer state.             */
@@ -101,15 +120,12 @@ typedef struct __PSSI_HandleTypeDef
 
 } PSSI_HandleTypeDef;
 
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
 /**
   * @brief  HAL PSSI Callback pointer definition
   */
 typedef  void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi);  /*!< Pointer to a PSSI common callback function */
 
-/**
-  * @}
-  */
 /**
   * @brief  HAL PSSI Callback ID enumeration definition
   */
@@ -124,6 +140,11 @@ typedef enum
   HAL_PSSI_MSPDEINIT_CB_ID   = 0x06U  /*!< PSSI Msp DeInit callback ID             */
 
 } HAL_PSSI_CallbackIDTypeDef;
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
 
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup PSSI_Exported_Constants PSSI Exported Constants
@@ -139,8 +160,9 @@ typedef enum
 #define HAL_PSSI_ERROR_OVER_RUN         0x00000004U /*!< FIFO Over-run  error    */
 #define HAL_PSSI_ERROR_DMA              0x00000008U /*!< Dma     error           */
 #define HAL_PSSI_ERROR_TIMEOUT          0x00000010U /*!< Timeout error           */
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
 #define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error  */
-
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
 
 /**
   * @}
@@ -175,7 +197,7 @@ typedef enum
   * @}
   */
 
-/** @defgroup PSSI_ControlSignal Configuration
+/** @defgroup ControlSignal_Configuration ControlSignal Configuration
   * @{
   */
 #define HAL_PSSI_DE_RDY_DISABLE           (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */
@@ -192,7 +214,7 @@ typedef enum
   */
 
 
-/** @defgroup PSSI_Data_Enable_Polarity Data Enable Polarity
+/** @defgroup Data_Enable_Polarity Data Enable Polarity
   * @{
   */
 #define HAL_PSSI_DEPOL_ACTIVE_LOW         0x0U            /*!< Active Low */
@@ -200,7 +222,7 @@ typedef enum
 /**
   * @}
   */
-/** @defgroup PSSI_Reday_Polarity Reday Polarity
+/** @defgroup Ready_Polarity Ready Polarity
   * @{
   */
 #define HAL_PSSI_RDYPOL_ACTIVE_LOW        0x0U            /*!< Active Low */
@@ -209,13 +231,11 @@ typedef enum
   * @}
   */
 
-/** @defgroup PSSI_Clock_Polarity Clock Polarity
+/** @defgroup Clock_Polarity Clock Polarity
   * @{
   */
 #define HAL_PSSI_FALLING_EDGE             0x0U            /*!< Fallling Edge */
 #define HAL_PSSI_RISING_EDGE              0x1U            /*!< Rising Edge */
-
-
 /**
   * @}
   */
@@ -232,12 +252,12 @@ typedef enum
 #define PSSI_CR_OUTEN_OUTPUT        PSSI_CR_OUTEN    /*!< Output Mode     */
 
 #define PSSI_CR_DMA_ENABLE          PSSI_CR_DMAEN    /*!< DMA Mode Enable */
-#define PSSI_CR_DMA_DISABLE         (~PSSI_CR_DMAEN) /*!< DMA Mode Disable */
+#define PSSI_CR_DMA_DISABLE         (~PSSI_CR_DMAEN) /*!< DMA Mode Disable*/
 
 #define PSSI_CR_16BITS              PSSI_CR_EDM      /*!< 16 Lines Mode   */
 #define PSSI_CR_8BITS               (~PSSI_CR_EDM)   /*!< 8 Lines Mode    */
 
-#define PSSI_FLAG_RTT1B             PSSI_SR_RTT1B    /*!< 1 Byte Fifo Flag*/
+#define PSSI_FLAG_RTT1B             PSSI_SR_RTT1B    /*!< 1 Byte Fifo Flag */
 #define PSSI_FLAG_RTT4B             PSSI_SR_RTT4B    /*!< 4 Bytes Fifo Flag*/
 
 
@@ -271,12 +291,15 @@ typedef enum
   * @param  __HANDLE__ specifies the PSSI handle.
   * @retval None
   */
-
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
 #define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
                                                       (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
                                                       (__HANDLE__)->MspInitCallback = NULL;       \
                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                      }while(0)
+#else
+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PSSI_STATE_RESET)
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
 
 
 /**
@@ -358,6 +381,7 @@ typedef enum
   */
 #define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
 
+
 /**
   * @brief  Check whether the PSSI Control signal is valid.
   * @param  __CONTROL__ Control signals configuration
@@ -372,6 +396,9 @@ typedef enum
                                              ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE        ) || \
                                              ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE         ) || \
                                              ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE   ))
+
+
+
 /**
   * @brief  Check whether the PSSI Bus Width is valid.
   * @param  __BUSWIDTH__ PSSI Bush width
@@ -382,6 +409,7 @@ typedef enum
                                         ((__BUSWIDTH__) == HAL_PSSI_16LINES   ))
 
 /**
+
   * @brief  Check whether the PSSI Clock Polarity is valid.
   * @param  __CLOCKPOL__ PSSI Clock Polarity
   * @retval Valid or not.
@@ -389,6 +417,8 @@ typedef enum
 
 #define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE   ) || \
                                               ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE    ))
+
+
 /**
   * @brief  Check whether the PSSI Data Enable Polarity is valid.
   * @param  __DEPOL__ PSSI DE Polarity
@@ -397,6 +427,7 @@ typedef enum
 
 #define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW    ) || \
                                         ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH   ))
+
 /**
   * @brief  Check whether the PSSI Ready Polarity is valid.
   * @param  __RDYPOL__ PSSI RDY Polarity
@@ -404,18 +435,19 @@ typedef enum
   */
 
 #define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW   ) || \
-                                         ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))
+                                          ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))
+
 /**
   * @}
   */
 
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup PSSI_Exported_Functions
+/** @addtogroup PSSI_Exported_Functions PSSI Exported Functions
   * @{
   */
 
-/** @addtogroup PSSI_Exported_Functions_Group1
+/** @addtogroup PSSI_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 
@@ -425,56 +457,61 @@ HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
 void              HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
 void              HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
 /* Callbacks Register/UnRegister functions  ***********************************/
-
-HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback);
+#if (USE_HAL_PSSI_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID,
+                                            pPSSI_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
-
+#endif /* USE_HAL_PSSI_REGISTER_CALLBACKS */
 
 /**
   * @}
   */
 
-/** @addtogroup PSSI_Exported_Functions_Group2
+
+/** @addtogroup PSSI_Exported_Functions_Group2 Input and Output operation functions
   * @{
   */
 
 /* IO operation functions *******************************************************/
 HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+#if defined(HAL_DMA_MODULE_ENABLED)
 HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
 HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
 HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
-void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
+#endif /*HAL_DMA_MODULE_ENABLED*/
 
 /**
   * @}
   */
 
-/** @addtogroup PSSI_Exported_Functions_Group3
+/** @addtogroup PSSI_Exported_Functions_Group3 Peripheral State and Error functions
   * @{
   */
 
+/* Peripheral State functions ***************************************************/
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(const PSSI_HandleTypeDef *hpssi);
+uint32_t              HAL_PSSI_GetError(const PSSI_HandleTypeDef *hpssi);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+  * @{
+  */
+
+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
 void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
 void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
 void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
 void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
 
-
 /**
   * @}
   */
 
-/** @addtogroup PSSI_Exported_Functions_Group4
-  * @{
-  */
 
-/* Peripheral State functions ***************************************************/
-HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
-uint32_t               HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
-
-/**
-  * @}
-  */
 
 /**
   * @}
@@ -502,5 +539,3 @@ uint32_t               HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
 
 #endif /* STM32H7xx_HAL_PSSI_H */
 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c
index 0de6bb2a19..4621780374 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c
@@ -8,6 +8,17 @@
   *           + Initialization and de-initialization functions.
   *           + Peripheral Control functions.
   *           + Interrupt Handling functions.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### PWR peripheral overview #####
@@ -129,18 +140,6 @@
       (+) __HAL_PWR_CLEAR_FLAG()            : Clear the PWR pending flags.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -568,6 +567,9 @@ void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
   assert_param (IS_PWR_REGULATOR (Regulator));
   assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(Regulator);
+
   /* Clear SLEEPDEEP bit of Cortex System Control Register */
   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 
@@ -872,4 +874,3 @@ __weak void HAL_PWR_PVDCallback (void)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.h
index 9dbf404ae1..91a905409f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -808,4 +807,3 @@ void HAL_PWR_DisableSEVOnPend   (void);
 
 #endif /* STM32H7xx_HAL_PWR_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c
index aaa58099c7..4b1a86e7c5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c
@@ -6,6 +6,17 @@
   *          This file provides firmware functions to manage the following
   *          functionalities of PWR extension peripheral:
   *           + Peripheral Extended features functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -136,18 +147,6 @@
        AVD interrupt request.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -2059,8 +2058,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
         /* PWR PVD interrupt user callback */
         HAL_PWR_PVDCallback ();
 
-        /* Clear PWR EXTI D1/CD pending bit */
-        __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+        if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
+        {
+          /* Clear PWR EXTI D1/CD pending bit */
+          __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
+        }
       }
     }
 #if defined (DUAL_CORE)
@@ -2072,8 +2074,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
         /* PWR PVD interrupt user callback */
         HAL_PWR_PVDCallback ();
 
-        /* Clear PWR EXTI D2 pending bit */
-        __HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
+        if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
+        {
+          /* Clear PWR EXTI D2 pending bit */
+          __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
+        }
       }
     }
 #endif /* defined (DUAL_CORE) */
@@ -2092,8 +2097,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
         /* PWR AVD interrupt user callback */
         HAL_PWREx_AVDCallback ();
 
-        /* Clear PWR EXTI D1/CD pending bit */
-        __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+        if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
+        {
+          /* Clear PWR EXTI D1/CD pending bit */
+          __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
+        }
       }
     }
 #if defined (DUAL_CORE)
@@ -2105,8 +2113,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
         /* PWR AVD interrupt user callback */
         HAL_PWREx_AVDCallback ();
 
-        /* Clear PWR EXTI D2 pending bit */
-        __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+        if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
+        {
+          /* Clear PWR EXTI D2 pending bit */
+          __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
+        }
       }
     }
 #endif /* defined (DUAL_CORE) */
@@ -2141,4 +2152,3 @@ __weak void HAL_PWREx_AVDCallback (void)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h
index 12f557a170..61c76092cd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -788,4 +787,3 @@ void HAL_PWREx_AVDCallback        (void);
 
 #endif /* STM32H7xx_HAL_PWR_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c
index 12214968cb..fc0a6036cf 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c
@@ -14,6 +14,17 @@
   *           + Errors management and abort functionality
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -93,16 +104,16 @@
       (#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function :
          (++) MDMA settings for write operation :
           (+) The DestinationInc should be MDMA_DEST_INC_DISABLE
-          (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
-          (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
-              aligned with @ref MDMA_Source_increment_mode .
-          (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+          (+) The SourceInc must be a value of MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD).
+          (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD)
+              aligned with MDMA_Source_increment_mode .
+          (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
          (++) MDMA settings for read operation :
           (+) The SourceInc should be MDMA_SRC_INC_DISABLE
-          (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
-          (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
-          (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
-              aligned with @ref MDMA_Destination_increment_mode.
+          (+) The DestinationInc must be a value of MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD).
+          (+) The SourceDataSize must be a value of MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) .
+          (+) The DestDataSize must be a value of MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD)
+              aligned with MDMA_Destination_increment_mode.
          (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Quadspi.
       (#)In case of wrong MDMA setting
         (++) For write operation :
@@ -132,7 +143,7 @@
     =================================================
     [..]
       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
-      (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
+      (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and
           flushes the fifo :
          (++) In polling mode, the output of the function is done when the transfer
               complete bit is set and the busy bit cleared.
@@ -154,7 +165,7 @@
       The compilation define  USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1
       allows the user to configure dynamically the driver callbacks.
 
-      Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback,
+      Use Functions HAL_QSPI_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
         (+) ErrorCallback : callback when error occurs.
         (+) AbortCpltCallback : callback when abort is completed.
@@ -169,8 +180,8 @@
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
-      Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
+      Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
         (+) ErrorCallback : callback when error occurs.
         (+) AbortCpltCallback : callback when abort is completed.
         (+) FifoThresholdCallback : callback when the fifo threshold is reached.
@@ -183,12 +194,12 @@
         (+) MspDeInitCallback  : QSPI MspDeInit.
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-      By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init
-      and @ref  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit
+      reset to the legacy weak (overridden) functions in the HAL_QSPI_Init
+      and  HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
       Callbacks can be registered/unregistered in READY state only.
@@ -196,12 +207,12 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit
-      or @ref HAL_QSPI_Init function.
+      using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit
+      or HAL_QSPI_Init function.
 
       When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak (overridden) callbacks are used.
 
     *** Workarounds linked to Silicon Limitation ***
     ====================================================
@@ -211,17 +222,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -300,7 +300,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
 /**
   * @brief Initialize the QSPI mode according to the specified parameters
   *        in the QSPI_InitTypeDef and initialize the associated handle.
-  * @param hqspi : QSPI handle
+  * @param hqspi QSPI handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@@ -394,7 +394,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief De-Initialize the QSPI peripheral.
-  * @param hqspi : QSPI handle
+  * @param hqspi QSPI handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -432,7 +432,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief Initialize the QSPI MSP.
-  * @param hqspi : QSPI handle
+  * @param hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -447,7 +447,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief DeInitialize the QSPI MSP.
-  * @param hqspi : QSPI handle
+  * @param hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -486,7 +486,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief Handle QSPI interrupt request.
-  * @param hqspi : QSPI handle
+  * @param hqspi QSPI handle
   * @retval None
   */
 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -775,9 +775,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief Set the command configuration.
-  * @param hqspi : QSPI handle
+  * @param hqspi QSPI handle
   * @param cmd : structure that contains the command configuration information
-  * @param Timeout : Timeout duration
+  * @param Timeout Timeout duration
   * @note   This function is used only in Indirect Read or Write Modes
   * @retval HAL status
   */
@@ -865,8 +865,8 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe
 
 /**
   * @brief Set the command configuration in interrupt mode.
-  * @param hqspi : QSPI handle
-  * @param cmd : structure that contains the command configuration information
+  * @param hqspi QSPI handle
+  * @param cmd structure that contains the command configuration information
   * @note   This function is used only in Indirect Read or Write Modes
   * @retval HAL status
   */
@@ -964,11 +964,10 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp
 
 /**
   * @brief Transmit an amount of data in blocking mode.
-  * @param hqspi : QSPI handle
-  * @param pData : pointer to data buffer
-  * @param Timeout : Timeout duration
+  * @param hqspi QSPI handle
+  * @param pData pointer to data buffer
+  * @param Timeout Timeout duration
   * @note   This function is used only in Indirect Write Mode
-  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
@@ -1048,9 +1047,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
 
 /**
   * @brief Receive an amount of data in blocking mode.
-  * @param hqspi : QSPI handle
-  * @param pData : pointer to data buffer
-  * @param Timeout : Timeout duration
+  * @param hqspi QSPI handle
+  * @param pData pointer to data buffer
+  * @param Timeout Timeout duration
   * @note   This function is used only in Indirect Read Mode
   * @retval HAL status
   */
@@ -1134,8 +1133,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
 
 /**
   * @brief  Send an amount of data in non-blocking mode with interrupt.
-  * @param  hqspi : QSPI handle
-  * @param  pData : pointer to data buffer
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
   * @note   This function is used only in Indirect Write Mode
   * @retval HAL status
   */
@@ -1194,8 +1193,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData
 
 /**
   * @brief  Receive an amount of data in non-blocking mode with interrupt.
-  * @param  hqspi : QSPI handle
-  * @param  pData : pointer to data buffer
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
   * @note   This function is used only in Indirect Read Mode
   * @retval HAL status
   */
@@ -1258,8 +1257,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
 
 /**
   * @brief  Send an amount of data in non-blocking mode with DMA.
-  * @param  hqspi : QSPI handle
-  * @param  pData : pointer to data buffer
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer
   * @note   This function is used only in Indirect Write Mode
   * @retval HAL status
   */
@@ -1371,8 +1370,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat
 
 /**
   * @brief  Receive an amount of data in non-blocking mode with DMA.
-  * @param  hqspi : QSPI handle
-  * @param  pData : pointer to data buffer.
+  * @param  hqspi QSPI handle
+  * @param  pData pointer to data buffer.
   * @note   This function is used only in Indirect Read Mode
   * @retval HAL status
   */
@@ -1486,10 +1485,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData
 
 /**
   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
-  * @param  hqspi : QSPI handle
-  * @param  cmd : structure that contains the command configuration information.
-  * @param  cfg : structure that contains the polling configuration information.
-  * @param  Timeout : Timeout duration
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the polling configuration information.
+  * @param  Timeout Timeout duration
   * @note   This function is used only in Automatic Polling Mode
   * @retval HAL status
   */
@@ -1587,9 +1586,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy
 
 /**
   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
-  * @param  hqspi : QSPI handle
-  * @param  cmd : structure that contains the command configuration information.
-  * @param  cfg : structure that contains the polling configuration information.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the polling configuration information.
   * @note   This function is used only in Automatic Polling Mode
   * @retval HAL status
   */
@@ -1691,9 +1690,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman
 
 /**
   * @brief  Configure the Memory Mapped mode.
-  * @param  hqspi : QSPI handle
-  * @param  cmd : structure that contains the command configuration information.
-  * @param  cfg : structure that contains the memory mapped configuration information.
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information.
+  * @param  cfg structure that contains the memory mapped configuration information.
   * @note   This function is used only in Memory mapped Mode
   * @retval HAL status
   */
@@ -1780,7 +1779,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT
 
 /**
   * @brief  Transfer Error callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1795,7 +1794,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  Abort completed callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1810,7 +1809,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  Command completed callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1825,7 +1824,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  Rx Transfer completed callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1840,7 +1839,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  Tx Transfer completed callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1856,7 +1855,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  FIFO Threshold callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1871,7 +1870,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  Status Match callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1886,7 +1885,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
 
 /**
   * @brief  Timeout callback.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval None
   */
 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -1901,9 +1900,9 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User QSPI Callback
-  *         To be used instead of the weak (surcharged) predefined callback
-  * @param hqspi : QSPI handle
-  * @param CallbackId : ID of the callback to be registered
+  *         To be used to override the weak predefined callback
+  * @param hqspi QSPI handle
+  * @param CallbackId ID of the callback to be registered
   *        This parameter can be one of the following values:
   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
@@ -1915,7 +1914,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
   *          @arg @ref HAL_QSPI_TIMEOUT_CB_ID        QSPI Timeout Callback ID
   *          @arg @ref HAL_QSPI_MSP_INIT_CB_ID       QSPI MspInit callback ID
   *          @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID     QSPI MspDeInit callback ID
-  * @param pCallback : pointer to the Callback function
+  * @param pCallback pointer to the Callback function
   * @retval status
   */
 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback)
@@ -2007,9 +2006,9 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI
 
 /**
   * @brief  Unregister a User QSPI Callback
-  *         QSPI Callback is redirected to the weak (surcharged) predefined callback
-  * @param hqspi : QSPI handle
-  * @param CallbackId : ID of the callback to be unregistered
+  *         QSPI Callback is redirected to the weak predefined callback
+  * @param hqspi QSPI handle
+  * @param CallbackId ID of the callback to be unregistered
   *        This parameter can be one of the following values:
   *          @arg @ref HAL_QSPI_ERROR_CB_ID          QSPI Error Callback ID
   *          @arg @ref HAL_QSPI_ABORT_CB_ID          QSPI Abort Callback ID
@@ -2128,10 +2127,10 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS
 
 /**
   * @brief  Return the QSPI handle state.
-  * @param  hqspi : QSPI handle
+  * @param  hqspi QSPI handle
   * @retval HAL state
   */
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi)
 {
   /* Return QSPI handle state */
   return hqspi->State;
@@ -2139,17 +2138,17 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
 
 /**
 * @brief  Return the QSPI error code.
-* @param  hqspi : QSPI handle
+* @param  hqspi QSPI handle
 * @retval QSPI Error Code
 */
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi)
 {
   return hqspi->ErrorCode;
 }
 
 /**
 * @brief  Abort the current transmission.
-* @param  hqspi : QSPI handle
+* @param  hqspi QSPI handle
 * @retval HAL status
 */
 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -2177,25 +2176,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
       }
     }
 
-    /* Configure QSPI: CR register with Abort request */
-    SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
-
-    /* Wait until TC flag is set to go back in idle state */
-    status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
-
-    if (status == HAL_OK)
+    if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
     {
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+      /* Configure QSPI: CR register with Abort request */
+      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      
+      /* Wait until TC flag is set to go back in idle state */
+      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
+      
+      if (status == HAL_OK)
+      {
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+        
+        /* Wait until BUSY flag is reset */
+        status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+      }
 
-      /* Wait until BUSY flag is reset */
-      status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
+      if (status == HAL_OK)
+      {
+        /* Reset functional mode configuration to indirect write mode by default */
+        CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
+        
+        /* Update state */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
     }
-
-    if (status == HAL_OK)
+    else
     {
-      /* Reset functional mode configuration to indirect write mode by default */
-      CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE);
-
       /* Update state */
       hqspi->State = HAL_QSPI_STATE_READY;
     }
@@ -2206,7 +2213,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
 
 /**
 * @brief  Abort the current transmission (non-blocking function)
-* @param  hqspi : QSPI handle
+* @param  hqspi QSPI handle
 * @retval HAL status
 */
 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -2248,22 +2255,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
     }
     else
     {
-      /* Clear interrupt */
-      __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
-
-      /* Enable the QSPI Transfer Complete Interrupt */
-      __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
-
-      /* Configure QSPI: CR register with Abort request */
-      SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET)
+      {
+        /* Clear interrupt */
+        __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
+        
+        /* Enable the QSPI Transfer Complete Interrupt */
+        __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
+        
+        /* Configure QSPI: CR register with Abort request */
+        SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
+      }    
+      else
+      {
+        /* Change state of QSPI */
+        hqspi->State = HAL_QSPI_STATE_READY;
+      }
     }
   }
   return status;
 }
 
 /** @brief Set QSPI timeout.
-  * @param  hqspi : QSPI handle.
-  * @param  Timeout : Timeout for the QSPI memory access.
+  * @param  hqspi QSPI handle.
+  * @param  Timeout Timeout for the QSPI memory access.
   * @retval None
   */
 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2272,8 +2287,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
 }
 
 /** @brief Set QSPI Fifo threshold.
-  * @param  hqspi : QSPI handle.
-  * @param  Threshold : Threshold of the Fifo (value between 1 and 16).
+  * @param  hqspi QSPI handle.
+  * @param  Threshold Threshold of the Fifo (value between 1 and 16).
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2305,17 +2320,17 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t
 }
 
 /** @brief Get QSPI Fifo threshold.
-  * @param  hqspi : QSPI handle.
+  * @param  hqspi QSPI handle.
   * @retval Fifo threshold (value between 1 and 16)
   */
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi)
 {
   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
 }
 
 /** @brief  Set FlashID.
-  * @param  hqspi : QSPI handle.
-  * @param  FlashID : Index of the flash memory to be accessed.
+  * @param  hqspi QSPI handle.
+  * @param  FlashID Index of the flash memory to be accessed.
   *                   This parameter can be a value of @ref QSPI_Flash_Select.
   * @note   The FlashID is ignored when dual flash mode is enabled.
   * @retval HAL status
@@ -2364,7 +2379,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI
 
 /**
   * @brief  DMA QSPI receive process complete callback.
-  * @param  hmdma : MDMA handle
+  * @param  hmdma MDMA handle
   * @retval None
   */
 static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
@@ -2378,7 +2393,7 @@ static void QSPI_DMARxCplt(MDMA_HandleTypeDef *hmdma)
 
 /**
   * @brief  DMA QSPI transmit process complete callback.
-  * @param  hmdma : MDMA handle
+  * @param  hmdma MDMA handle
   * @retval None
   */
 static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
@@ -2392,7 +2407,7 @@ static void QSPI_DMATxCplt(MDMA_HandleTypeDef *hmdma)
 
 /**
   * @brief  DMA QSPI communication error callback.
-  * @param  hmdma : MDMA handle
+  * @param  hmdma MDMA handle
   * @retval None
   */
 static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
@@ -2414,7 +2429,7 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma)
 
 /**
   * @brief  MDMA QSPI abort complete callback.
-  * @param  hmdma : MDMA handle
+  * @param  hmdma MDMA handle
   * @retval None
   */
 static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
@@ -2453,11 +2468,11 @@ static void QSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma)
 
 /**
   * @brief  Wait for a flag state until timeout.
-  * @param  hqspi : QSPI handle
-  * @param  Flag : Flag checked
-  * @param  State : Value of the flag expected
-  * @param  Tickstart : Tick start value
-  * @param  Timeout : Duration of the timeout
+  * @param  hqspi QSPI handle
+  * @param  Flag Flag checked
+  * @param  State Value of the flag expected
+  * @param  Tickstart Tick start value
+  * @param  Timeout Duration of the timeout
   * @retval HAL status
   */
 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2483,9 +2498,9 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp
 
 /**
   * @brief  Configure the communication registers.
-  * @param  hqspi : QSPI handle
-  * @param  cmd : structure that contains the command configuration information
-  * @param  FunctionalMode : functional mode to configured
+  * @param  hqspi QSPI handle
+  * @param  cmd structure that contains the command configuration information
+  * @param  FunctionalMode functional mode to configured
   *           This parameter can be one of the following values:
   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
@@ -2649,5 +2664,3 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin
   */
 
 #endif /* defined(QUADSPI) */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.h
index 4379cbe39d..98b2c5cf19 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -453,7 +452,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
   * @{
   */
 /** @brief Reset QSPI handle state.
-  * @param  __HANDLE__ : QSPI handle.
+  * @param  __HANDLE__ QSPI handle.
   * @retval None
   */
 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
@@ -467,20 +466,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
 #endif
 
 /** @brief  Enable the QSPI peripheral.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
+  * @param  __HANDLE__ specifies the QSPI Handle.
   * @retval None
   */
 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
 
 /** @brief  Disable the QSPI peripheral.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
+  * @param  __HANDLE__ specifies the QSPI Handle.
   * @retval None
   */
 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
 
 /** @brief  Enable the specified QSPI interrupt.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
-  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to enable.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
   *            @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -493,8 +492,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
 
 
 /** @brief  Disable the specified QSPI interrupt.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
-  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to disable.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
   *            @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -506,8 +505,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
 
 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
-  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to check.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __INTERRUPT__ specifies the QSPI interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
   *            @arg QSPI_IT_SM: QSPI Status match interrupt
@@ -520,8 +519,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
 
 /**
   * @brief  Check whether the selected QSPI flag is set or not.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
-  * @param  __FLAG__ : specifies the QSPI flag to check.
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __FLAG__ specifies the QSPI flag to check.
   *          This parameter can be one of the following values:
   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
@@ -534,8 +533,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
 
 /** @brief  Clears the specified QSPI's flag status.
-  * @param  __HANDLE__ : specifies the QSPI Handle.
-  * @param  __FLAG__ : specifies the QSPI clear register flag that needs to be set
+  * @param  __HANDLE__ specifies the QSPI Handle.
+  * @param  __FLAG__ specifies the QSPI clear register flag that needs to be set
   *          This parameter can be one of the following values:
   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
   *            @arg QSPI_FLAG_SM: QSPI Status match flag
@@ -618,13 +617,13 @@ HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi,
   * @{
   */
 /* Peripheral Control and State functions  ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
-uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (const QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError        (const QSPI_HandleTypeDef *hqspi);
 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
-uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
 HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
 /**
   * @}
@@ -736,12 +735,10 @@ HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint3
   * @}
   */
 
-#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
+#endif /* defined(QUADSPI) */
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* STM32H7xx_HAL_QSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c
index 54491f939c..29152064d1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c
@@ -9,6 +9,17 @@
   *           + Monitoring operation functions
   *           + Error information functions
   *           + State and error functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -17,7 +28,7 @@
    (#) Enable and latch error information through HAL_RAMECC_Init().
 
    (#) For a given Monitor, enable and disable interrupt through
-       HAL_RAMECC_EnableNotifiaction().
+       HAL_RAMECC_EnableNotification().
        To enable a notification for a given RAMECC instance, use global
        interrupts.
        To enable a notification for only RAMECC monitor, use monitor interrupts.
@@ -33,11 +44,12 @@
      *** Interrupt mode ***
      ======================
     [..]
-          (+) Use HAL_RAMECC_EnableNotifiaction() to enable interrupts for a
+          (+) Use HAL_RAMECC_EnableNotification() to enable interrupts for a
               given error.
           (+) Configure the RAMECC interrupt priority using
               HAL_NVIC_SetPriority().
           (+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ().
+          (+) Start RAMECC latch failing information using HAL_RAMECC_StartMonitor().
 
      *** Failing information ***
      ======================
@@ -68,19 +80,32 @@
                                     flag.
       (+) __HAL_RAMECC_CLEAR_FLAG : Clear the current RAMECC Monitor selected
                                     flag.
+
+    ##### Callback registration #####
+    ==================================
+    [..]
+      (#) The compilation define USE_HAL_RAMECC_REGISTER_CALLBACKS when set to 1
+          allows the user to configure dynamically the driver callback.
+
+    [..]
+      (#) Use Function HAL_RAMECC_RegisterCallback() to register a user callback.
+      (#) Function HAL_RAMECC_RegisterCallback() allows to register following callback:
+         (+) RAMECCErrorCode        : RAMECC error code detection.
+      (#) This function takes as parameters the HAL peripheral handle 
+          and a pointer to the user callback function.
+
+    [..]
+      (#) Use function HAL_RAMECC_UnRegisterCallback() to reset a callback to the default
+          weak function.
+      (#) HAL_RAMECC_UnRegisterCallback() takes as parameters the HAL peripheral handle.
+      (#) This function allows to reset following callback:
+          (+) RAMECCErrorCode        : RAMECC error code detection.
+    [..]
+      (#) When The compilation define USE_HAL_RAMECC_REGISTER_CALLBACKS is set to 0 or
+          not defined, the callback registration feature is not available
+          and weak callbacks are used.
+ 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -132,7 +157,7 @@
   *                  Monitor.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the RAMECC peripheral handle */
   if (hramecc == NULL)
@@ -163,6 +188,9 @@ HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
   /* Initialise the RAMECC error code */
   hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
 
+  /* Initialise the RAMECC error detected code */
+  hramecc->RAMECCErrorCode = HAL_RAMECC_NO_ERROR;
+
   /* Update the RAMECC state */
   hramecc->State = HAL_RAMECC_STATE_READY;
 
@@ -170,7 +198,6 @@ HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
   return HAL_OK;
 }
 
-
 /**
   * @brief  DeInitializes the RAMECC peripheral.
   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -178,7 +205,7 @@ HAL_StatusTypeDef HAL_RAMECC_Init (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the RAMECC peripheral handle */
   if (hramecc == NULL)
@@ -203,21 +230,23 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
   /* Clear RAMECC monitor flags */
   __HAL_RAMECC_CLEAR_FLAG (hramecc, RAMECC_FLAGS_ALL);
 
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
   /* Clean callback */
   hramecc->DetectErrorCallback = NULL;
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
 
-  /* Initialise the RAMECC error code */
+  /* Initialize the RAMECC error code */
   hramecc->ErrorCode = HAL_RAMECC_ERROR_NONE;
 
+  /* Initialize the RAMECC error detected code */
+  hramecc->RAMECCErrorCode = HAL_RAMECC_NO_ERROR;
+
   /* Change RAMECC peripheral state */
   hramecc->State = HAL_RAMECC_STATE_RESET;
 
   /* Return HAL status */
   return HAL_OK;
 }
-/**
-  * @}
-  */
 
 /**
   * @}
@@ -246,7 +275,7 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -276,7 +305,6 @@ HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
   return HAL_OK;
 }
 
-
 /**
   * @brief  Stop the RAMECC latching error information.
   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -284,7 +312,7 @@ HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -314,7 +342,6 @@ HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
   return HAL_OK;
 }
 
-
 /**
   * @brief  Enable the RAMECC error interrupts.
   * @param  hramecc        Pointer to a RAMECC_HandleTypeDef structure that
@@ -323,7 +350,7 @@ HAL_StatusTypeDef HAL_RAMECC_StopMonitor (RAMECC_HandleTypeDef *hramecc)
   * @param  Notifications  Select the notification.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
+HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -354,7 +381,6 @@ HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc,
   return HAL_OK;
 }
 
-
 /**
   * @brief  Disable the RAMECC error interrupts.
   * @param  hramecc        Pointer to a RAMECC_HandleTypeDef structure that
@@ -363,7 +389,7 @@ HAL_StatusTypeDef HAL_RAMECC_EnableNotification (RAMECC_HandleTypeDef *hramecc,
   * @param  Notifications  Select the notification.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
+HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -394,7 +420,31 @@ HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc,
   return HAL_OK;
 }
 
+/**
+  * @}
+  */
 
+/** @addtogroup RAMECC_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+               ##### Handle Interrupt and Callbacks Functions  #####
+ ===============================================================================
+    [..]
+      This section provides functions to handle RAMECC interrupts and
+      Register / UnRegister the different callbacks.
+    [..]
+      The HAL_RAMECC_IRQHandler() function allows the user to handle the active RAMECC
+      interrupt request.
+      The HAL_RAMECC_RegisterCallback() function allows the user to register the selected
+      RAMECC callbacks.
+      The HAL_RAMECC_UnRegisterCallback() function allows the user to unregister the
+      selected RAMECC callbacks.
+@endverbatim
+  * @{
+  */
+
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register callbacks.
   * @param  hramecc    Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -438,7 +488,6 @@ HAL_StatusTypeDef HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, vo
   return status;
 }
 
-
 /**
   * @brief  UnRegister callbacks.
   * @param  hramecc    Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -446,7 +495,7 @@ HAL_StatusTypeDef HAL_RAMECC_RegisterCallback (RAMECC_HandleTypeDef *hramecc, vo
   *                    Monitor.
   * @retval HAL status.
   */
-HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
+HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -454,7 +503,7 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
 
   /* Check RAMECC state */
-  if(hramecc->State == HAL_RAMECC_STATE_READY)
+  if (hramecc->State == HAL_RAMECC_STATE_READY)
   {
     hramecc->DetectErrorCallback = NULL;
   }
@@ -470,7 +519,7 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
   /* Return HAL status */
   return status;
 }
-
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
 
 /**
   * @brief  Handles RAMECC interrupt request.
@@ -479,11 +528,11 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval None.
   */
-void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
+void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc)
 {
   uint32_t ier_reg = ((RAMECC_TypeDef *)((uint32_t)hramecc->Instance & 0xFFFFFF00U))->IER;
   uint32_t cr_reg = hramecc->Instance->CR >> 1U;
-  uint32_t sr_reg = hramecc->Instance->SR << 1U;
+  uint32_t sr_reg = hramecc->Instance->SR;
 
   /* Update global interrupt variables */
   if ((ier_reg & RAMECC_IER_GIE) == RAMECC_IER_GIE)
@@ -491,19 +540,55 @@ void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
     ier_reg = RAMECC_IT_GLOBAL_ALL;
   }
 
+  /* Store the ECC Single error detected */
+  if ((sr_reg & RAMECC_SR_SEDCF) == RAMECC_SR_SEDCF)
+  {
+    hramecc->RAMECCErrorCode |= HAL_RAMECC_SINGLEERROR_DETECTED;
+  }
+
+  /* Store the ECC double error detected */
+  if ((sr_reg & (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U)
+  {
+    hramecc->RAMECCErrorCode |= HAL_RAMECC_DOUBLEERROR_DETECTED;
+  }
+
   /* Clear active flags */
-  __HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & sr_reg) >> 1U));
+  __HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & (sr_reg << 1U)) >> 1U));
 
   /* Check if a valid double error callback is registered */
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
+  /* Check if a valid error callback is registered */
   if (hramecc->DetectErrorCallback != NULL)
   {
     /* Error detection callback */
     hramecc->DetectErrorCallback(hramecc);
   }
+#else
+  HAL_RAMECC_DetectErrorCallback(hramecc);
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
 }
 
+/**
+  * @brief  RAMECC error detection callback.
+  * @param  hramecc : Pointer to a RAMECC_HandleTypeDef structure that contains
+  *                   the configuration information for the specified RAMECC.
+  * @retval None.
+  */
+__weak void HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hramecc);
 
-/** @addtogroup RAMECC_Exported_Functions_Group3
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_RAMECC_DetectDoubleErrorCallback can be implemented in
+            the user file.                                                    */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RAMECC_Exported_Functions_Group4
   *
 @verbatim
  ===============================================================================
@@ -528,7 +613,7 @@ void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval Failing address offset.
   */
-uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -537,7 +622,6 @@ uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
   return hramecc->Instance->FAR;
 }
 
-
 /**
   * @brief  Return the RAMECC data low.
   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -545,7 +629,7 @@ uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval Failing data low.
   */
-uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -554,7 +638,6 @@ uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
   return hramecc->Instance->FDRL;
 }
 
-
 /**
   * @brief  Return the RAMECC data high.
   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -562,7 +645,7 @@ uint32_t HAL_RAMECC_GetFailingDataLow (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval Failing data high.
   */
-uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -571,7 +654,6 @@ uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
   return hramecc->Instance->FDRH;
 }
 
-
 /**
   * @brief  Return the RAMECC Hamming bits injected.
   * @param  hramecc  Pointer to a RAMECC_HandleTypeDef structure that contains
@@ -579,7 +661,7 @@ uint32_t HAL_RAMECC_GetFailingDataHigh (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval Hamming bits injected.
   */
-uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -595,7 +677,7 @@ uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval State of bit (1 or 0).
   */
-uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -611,7 +693,7 @@ uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc)
   *                  Monitor.
   * @retval State of bit (1 or 0).
   */
-uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc)
 {
   /* Check the parameters */
   assert_param (IS_RAMECC_MONITOR_ALL_INSTANCE (hramecc->Instance));
@@ -619,12 +701,12 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
   /* Return the state of DEDF | DEBWDF flags */
   return ((READ_BIT(hramecc->Instance->SR, (RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)) != 0U) ? 1UL : 0UL);
 }
+
 /**
   * @}
   */
 
-
-/** @addtogroup RAMECC_Exported_Functions_Group4
+/** @addtogroup RAMECC_Exported_Functions_Group5
   *
 @verbatim
  ===============================================================================
@@ -638,6 +720,8 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
     state.
     The HAL_RAMECC_GetError() function allows to Get the RAMECC peripheral error
     code.
+    The HAL_RAMECC_GetRAMECCError() function allows to Get the RAMECC error code
+	detected.
 
 @endverbatim
   * @{
@@ -650,7 +734,7 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc)
   *                         specified RAMECC instance.
   * @retval RAMECC state.
   */
-HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
+HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc)
 {
   /* Return the RAMECC state */
   return hramecc->State;
@@ -663,16 +747,29 @@ HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc)
   *                         specified RAMECC instance.
   * @retval RAMECC error code.
   */
-uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
+uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc)
 {
   /* Return the RAMECC error code */
   return hramecc->ErrorCode;
 }
+
+/**
+  * @brief  Get the RAMECC error code detected.
+  * @param  hramecc       : Pointer to a RAMECC_HandleTypeDef structure that
+  *                         contains the configuration information for the
+  *                         specified RAMECC instance.
+  * @retval RAMECC error code detected.
+  */
+uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc)
+{
+  /* Return the RAMECC error code detected*/
+  return hramecc->RAMECCErrorCode;
+}
+
 /**
   * @}
   */
 #endif /* HAL_RAMECC_MODULE_ENABLED */
-
 /**
   * @}
   */
@@ -680,13 +777,3 @@ uint32_t HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc)
 /**
   * @}
   */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h
index 1046ca85ee..f9444ebc87 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -58,13 +57,19 @@ typedef enum
 /**
   * @brief  RAMECC handle Structure definition
   */
-
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
 typedef struct __RAMECC_HandleTypeDef
+#else
+typedef struct
+#endif  /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
 {
-  RAMECC_MonitorTypeDef           *Instance;                                                            /*!< Register base address        */
-  __IO HAL_RAMECC_StateTypeDef    State;                                                                /*!< RAMECC state                 */
-  __IO uint32_t                   ErrorCode;                                                            /*!< RAMECC Error Code            */
-  void                            (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc);     /*!< RAMECC error detect callback */
+  RAMECC_MonitorTypeDef           *Instance;                                                         /*!< Register base address        */
+  __IO HAL_RAMECC_StateTypeDef    State;                                                             /*!< RAMECC state                 */
+  __IO uint32_t                   ErrorCode;                                                         /*!< RAMECC Error Code            */
+  __IO uint32_t                   RAMECCErrorCode;                                                   /*!< RAMECC Detected Error Code   */
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
+  void                            (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc);  /*!< RAMECC Error Detect callback */
+#endif  /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
 }RAMECC_HandleTypeDef;
 
 /**
@@ -73,14 +78,29 @@ typedef struct __RAMECC_HandleTypeDef
 
 
 /* Exported constants --------------------------------------------------------*/
-
+/** @defgroup RAMECC_Exported_Constants RAMECC Exported Constants
+  * @{
+  */
 /** @defgroup RAMECC_Error_Codes RAMECC Error Codes
   * @{
   */
 #define HAL_RAMECC_ERROR_NONE              0x00000000U  /*!< RAMECC No Error         */
 #define HAL_RAMECC_ERROR_TIMEOUT           0x00000001U  /*!< RAMECC Timeout Error    */
 #define HAL_RAMECC_ERROR_BUSY              0x00000002U  /*!< RAMECC Busy Error       */
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
 #define HAL_RAMECC_ERROR_INVALID_CALLBACK  0x00000003U  /*!< Invalid Callback error  */
+#endif  /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup RAMECC_Error_Codes RAMECC Error Detected Codes
+  * @{
+  */
+#define HAL_RAMECC_NO_ERROR                           0x00000000U  /*!< RAMECC No Error Detected                      */
+#define HAL_RAMECC_SINGLEERROR_DETECTED               0x00000001U  /*!< RAMECC Single Error Detected                  */
+#define HAL_RAMECC_DOUBLEERROR_DETECTED               0x00000002U  /*!< RAMECC Double Error Detected                  */
 /**
   * @}
   */
@@ -114,6 +134,9 @@ typedef struct __RAMECC_HandleTypeDef
 #define RAMECC_FLAG_DOUBLEERR_W            RAMECC_SR_DEBWDF
 #define RAMECC_FLAGS_ALL                   (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)
 
+/**
+  * @}
+  */
 /**
   * @}
   */
@@ -131,15 +154,15 @@ typedef struct __RAMECC_HandleTypeDef
   * @param  __HANDLE__   : RAMECC handle.
   * @param  __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
   *        This parameter can be one of the following values:
-  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
-  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
-  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
+  *           @arg RAMECC_IT_GLOBAL_ENABLE         : Global interrupt enable mask.
+  *           @arg RAMECC_IT_GLOBAL_SINGLEERR_R    : Global ECC single error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DOUBLEERR_R    : Global ECC double error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DOUBLEERR_W    : Global ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_ALL            : All Global ECC interrupts enable mask.
+  *           @arg RAMECC_IT_MONITOR_SINGLEERR_R   : Monitor ECC single error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DOUBLEERR_R   : Monitor ECC double error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DOUBLEERR_W   : Monitor ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_ALL           : All Monitor ECC interrupts enable mask.
   * @retval None
   */
 #define __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( \
@@ -155,15 +178,15 @@ typedef struct __RAMECC_HandleTypeDef
   * @param  __HANDLE__   : RAMECC handle.
   * @param  __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.
   *        This parameter can be one of the following values:
-  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
-  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
-  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
+  *           @arg RAMECC_IT_GLOBAL_ENABLE         : Global interrupt enable mask.
+  *           @arg RAMECC_IT_GLOBAL_SINGLEERR_R    : Global ECC single error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DOUBLEERR_R    : Global ECC double error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DOUBLEERR_W    : Global ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_ALL            : All Global ECC interrupts enable mask.
+  *           @arg RAMECC_IT_MONITOR_SINGLEERR_R   : Monitor ECC single error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DOUBLEERR_R   : Monitor ECC double error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DOUBLEERR_W   : Monitor ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_ALL           : All Monitor ECC interrupts enable mask.
   * @retval None
   */
 #define __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ( \
@@ -179,15 +202,15 @@ typedef struct __RAMECC_HandleTypeDef
   * @param  __HANDLE__    : Specifies the RAMECC Handle.
   * @param  __INTERRUPT__ : Specifies the RAMECC interrupt source to check.
   *          This parameter can be one of the following values:
-  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
-  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
-  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
-  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
-  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
+  *           @arg RAMECC_IT_GLOBAL_ENABLE         : Global interrupt enable mask.
+  *           @arg RAMECC_IT_GLOBAL_SINGLEERR_R    : Global ECC single error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DOUBLEERR_R    : Global ECC double error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DOUBLEERR_W    : Global ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_ALL            : All Global ECC interrupts enable mask.
+  *           @arg RAMECC_IT_MONITOR_SINGLEERR_R   : Monitor ECC single error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DOUBLEERR_R   : Monitor ECC double error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DOUBLEERR_W   : Monitor ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_ALL           : All Monitor ECC interrupts enable mask.
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
 #define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (  \
@@ -200,10 +223,10 @@ typedef struct __RAMECC_HandleTypeDef
   * @param  __HANDLE__   : RAMECC handle.
   * @param  __FLAG__     : specifies the flag to clear.
   *          This parameter can be any combination of the following values:
-  *            @arg RAMECC_FLAG_SEDCF  : RAMECC instance ECC single error detected and corrected flag.
-  *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.
-  *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
-  *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.
+  *            @arg RAMECC_FLAG_SINGLEERR_R  : RAMECC instance ECC single error detected and corrected flag.
+  *            @arg RAMECC_FLAG_DOUBLEERR_R  : RAMECC instance ECC double error detected flag.
+  *            @arg RAMECC_FLAG_DOUBLEERR_W  : RAMECC instance ECC double error on byte write (BW) detected flag.
+  *            @arg RAMECC_FLAGS_ALL         : RAMECC instance all flag.
   * @retval The state of __FLAG__ (SET or RESET).
   */
 #define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
@@ -214,10 +237,10 @@ typedef struct __RAMECC_HandleTypeDef
   * @param  __HANDLE__   : RAMECC handle.
   * @param  __FLAG__     : specifies the flag to clear.
   *          This parameter can be any combination of the following values:
-  *            @arg RAMECC_FLAG_SEDCF  : RAMECC instance ECC single error detected and corrected flag.
-  *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.
-  *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
-  *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.
+  *            @arg RAMECC_FLAG_SINGLEERR_R  : RAMECC instance ECC single error detected and corrected flag.
+  *            @arg RAMECC_FLAG_DOUBLEERR_R  : RAMECC instance ECC double error detected flag.
+  *            @arg RAMECC_FLAG_DOUBLEERR_W  : RAMECC instance ECC double error on byte write (BW) detected flag.
+  *            @arg RAMECC_FLAGS_ALL         : RAMECC instance all flag.
   * @retval None.
   */
 #define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
@@ -243,8 +266,8 @@ typedef struct __RAMECC_HandleTypeDef
   * @brief    Initialization and de-initialization functions
   * @{
   */
-HAL_StatusTypeDef HAL_RAMECC_Init   (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc);
 /**
   * @}
   */
@@ -253,37 +276,50 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
   * @brief    monitoring operation functions
   * @{
   */
-HAL_StatusTypeDef HAL_RAMECC_StartMonitor        (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_StopMonitor         (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_EnableNotification  (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
-HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
-void              HAL_RAMECC_IRQHandler          (RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_RegisterCallback    (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
-HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback  (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
+HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
+
 /**
   * @}
   */
 
-/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions
-  * @brief    Error information functions
+/** @defgroup RAMECC_Exported_Functions_Group3 handle Interrupt and Callbacks Functions
+  * @brief    handle Interrupt and Callbacks Functions
   * @{
   */
-uint32_t HAL_RAMECC_GetFailingAddress        (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetFailingDataLow        (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetFailingDataHigh       (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetHammingErrorCode      (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc);
+void              HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc);
+void              HAL_RAMECC_DetectErrorCallback(RAMECC_HandleTypeDef *hramecc);
+#if (USE_HAL_RAMECC_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
+HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc);
+#endif /* USE_HAL_RAMECC_REGISTER_CALLBACKS */
 /**
   * @}
   */
 
-/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions
+/** @defgroup RAMECC_Exported_Functions_Group4 Error information functions
   * @brief    Error information functions
   * @{
   */
-HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);
-uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_IsECCSingleErrorDetected(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_IsECCDoubleErrorDetected(RAMECC_HandleTypeDef *hramecc);
+/**
+  * @}
+  */
+
+/** @defgroup RAMECC_Exported_Functions_Group5 State and Error Functions
+  * @brief    State and Error Functions
+  * @{
+  */
+HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetError(RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetRAMECCError(RAMECC_HandleTypeDef *hramecc);
 /**
   * @}
   */
@@ -325,10 +361,6 @@ uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
   * @}
   */
 
-/** @defgroup RAMECC_FLAG RAMECC Monitor flags
-  * @{
-  */
-
 /* Private functions ---------------------------------------------------------*/
 /** @defgroup RAMECC_Private_Functions RAMECC Private Functions
   * @brief    RAMECC private  functions
@@ -342,10 +374,6 @@ uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
   * @}
   */
 
-/**
-  * @}
-  */
-
 /**
   * @}
   */
@@ -354,5 +382,3 @@ uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
 #endif
 
 #endif /* STM32H7xx_HAL_RAMECC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c
index b5e93c78b9..8c987ac8ef 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c
@@ -54,14 +54,12 @@
  ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -191,15 +189,15 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
 {
   uint32_t tickstart;
 
-        /* Increasing the CPU frequency */
-  if(FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
+  /* Increasing the CPU frequency */
+  if (FLASH_LATENCY_DEFAULT  > __HAL_FLASH_GET_LATENCY())
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
     {
       return HAL_ERROR;
     }
@@ -233,7 +231,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   SystemD2Clock = HSI_VALUE;
 
   /* Adapt Systick interrupt period */
-  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  if (HAL_InitTick(uwTickPrio) != HAL_OK)
   {
     return HAL_ERROR;
   }
@@ -254,8 +252,8 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   tickstart = HAL_GetTick();
 
   /* Reset CSION, CSIKERON, HSEON, HSI48ON, HSECSSON, HSIDIV bits */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON  \
-  | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON  \
+            | RCC_CR_HSI48ON | RCC_CR_CSSHSEON);
 
   /* Wait till HSE is disabled */
   while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
@@ -332,25 +330,25 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
 #endif
 
   /* Reset PLLCKSELR register to default value */
-  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+  RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
 
   /* Reset PLLCFGR register to default value */
   WRITE_REG(RCC->PLLCFGR, 0x01FF0000U);
 
   /* Reset PLL1DIVR register to default value */
-  WRITE_REG(RCC->PLL1DIVR,0x01010280U);
+  WRITE_REG(RCC->PLL1DIVR, 0x01010280U);
 
   /* Reset PLL1FRACR register */
   CLEAR_REG(RCC->PLL1FRACR);
 
   /* Reset PLL2DIVR register to default value */
-  WRITE_REG(RCC->PLL2DIVR,0x01010280U);
+  WRITE_REG(RCC->PLL2DIVR, 0x01010280U);
 
   /* Reset PLL2FRACR register */
   CLEAR_REG(RCC->PLL2FRACR);
 
   /* Reset PLL3DIVR register to default value */
-  WRITE_REG(RCC->PLL3DIVR,0x01010280U);
+  WRITE_REG(RCC->PLL3DIVR, 0x01010280U);
 
   /* Reset PLL3FRACR register */
   CLEAR_REG(RCC->PLL3FRACR);
@@ -367,25 +365,25 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_REG(RCC->CIER);
 
   /* Clear all interrupts flags */
-  WRITE_REG(RCC->CICR,0xFFFFFFFFU);
+  WRITE_REG(RCC->CICR, 0xFFFFFFFFU);
 
   /* Reset all RSR flags */
   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
 
-      /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (FLASH_LATENCY_DEFAULT  < __HAL_FLASH_GET_LATENCY())
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT);
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
+    if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT)
     {
       return HAL_ERROR;
     }
 
-}
+  }
 
   return HAL_OK;
 }
@@ -409,8 +407,8 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
   uint32_t tickstart;
   uint32_t temp1_pllckcfg, temp2_pllckcfg;
 
-    /* Check Null pointer */
-  if(RCC_OscInitStruct == NULL)
+  /* Check Null pointer */
+  if (RCC_OscInitStruct == NULL)
   {
     return HAL_ERROR;
   }
@@ -418,7 +416,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
   /* Check the parameters */
   assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
   /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
@@ -426,9 +424,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
     /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
+    if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
     {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
       {
         return HAL_ERROR;
       }
@@ -439,15 +437,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 
       /* Check the HSE State */
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
       {
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
 
         /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
         {
-          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -459,9 +457,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till HSE is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
         {
-          if((uint32_t) (HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -470,7 +468,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     }
   }
   /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
@@ -479,16 +477,30 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     /* When the HSI is used as system clock it will not be disabled */
     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
-    if((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
+    if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
     {
       /* When HSI is used as system clock it will not be disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
       {
         return HAL_ERROR;
       }
-      /* Otherwise, just the calibration is allowed */
+      /* Otherwise, only HSI division and calibration are allowed */
       else
       {
+        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2, HSIDIV4, or HSIDIV8) */
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        {
+          if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
         /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
         __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
       }
@@ -497,18 +509,18 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     else
     {
       /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
       {
-     /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
+        /* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
         __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
 
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
 
         /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
         {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -526,9 +538,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till HSI is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
         {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -537,7 +549,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     }
   }
   /*----------------------------- CSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
   {
     /* Check the parameters */
     assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
@@ -546,10 +558,10 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     /* When the CSI is used as system clock it will not disabled */
     const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
     const uint32_t temp_pllckselr = RCC->PLLCKSELR;
-    if((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
+    if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
     {
       /* When CSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
+      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
       {
         return HAL_ERROR;
       }
@@ -563,7 +575,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     else
     {
       /* Check the CSI State */
-      if((RCC_OscInitStruct->CSIState)!= RCC_CSI_OFF)
+      if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
       {
         /* Enable the Internal High Speed oscillator (CSI). */
         __HAL_RCC_CSI_ENABLE();
@@ -572,9 +584,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till CSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
         {
-          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -592,9 +604,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till CSI is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
         {
-          if((HAL_GetTick() - tickstart ) > CSI_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -603,13 +615,13 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     }
   }
   /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
 
     /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
     {
       /* Enable the Internal Low Speed oscillator (LSI). */
       __HAL_RCC_LSI_ENABLE();
@@ -618,9 +630,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       tickstart = HAL_GetTick();
 
       /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
       {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }
@@ -635,9 +647,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       tickstart = HAL_GetTick();
 
       /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
       {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }
@@ -646,13 +658,13 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
   }
 
   /*------------------------------ HSI48 Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
 
     /* Check the HSI48 State */
-    if((RCC_OscInitStruct->HSI48State)!= RCC_HSI48_OFF)
+    if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
     {
       /* Enable the Internal Low Speed oscillator (HSI48). */
       __HAL_RCC_HSI48_ENABLE();
@@ -661,9 +673,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       tickstart = HAL_GetTick();
 
       /* Wait till HSI48 is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
       {
-        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }
@@ -678,9 +690,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       tickstart = HAL_GetTick();
 
       /* Wait till HSI48 is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
       {
-        if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE)
+        if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }
@@ -688,7 +700,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     }
   }
   /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
   {
     /* Check the parameters */
     assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
@@ -699,9 +711,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     /* Wait for Backup domain Write protection disable */
     tickstart = HAL_GetTick();
 
-    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
     {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }
@@ -710,15 +722,15 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
     /* Set the new LSE configuration -----------------------------------------*/
     __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
     /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
     {
       /* Get Start Tick*/
       tickstart = HAL_GetTick();
 
       /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
       {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }
@@ -730,9 +742,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       tickstart = HAL_GetTick();
 
       /* Wait till LSE is disabled */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
+      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
       {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
         {
           return HAL_TIMEOUT;
         }
@@ -745,9 +757,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
   if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
   {
     /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
     {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
       {
         /* Check the parameters */
         assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
@@ -767,9 +779,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
         {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -783,11 +795,11 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
                              RCC_OscInitStruct->PLL.PLLQ,
                              RCC_OscInitStruct->PLL.PLLR);
 
-         /* Disable PLLFRACN . */
-         __HAL_RCC_PLLFRACN_DISABLE();
+        /* Disable PLLFRACN . */
+        __HAL_RCC_PLLFRACN_DISABLE();
 
-         /* Configure PLL PLL1FRACN */
-         __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+        /* Configure PLL PLL1FRACN */
+        __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
 
         /* Select PLL1 input reference frequency range: VCI */
         __HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
@@ -796,16 +808,16 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         __HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
 
         /* Enable PLL System Clock output. */
-         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
 
         /* Enable PLL1Q Clock output. */
-         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
         /* Enable PLL1R  Clock output. */
-         __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
 
         /* Enable PLL1FRACN . */
-         __HAL_RCC_PLLFRACN_ENABLE();
+        __HAL_RCC_PLLFRACN_ENABLE();
 
         /* Enable the main PLL. */
         __HAL_RCC_PLL_ENABLE();
@@ -814,9 +826,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
         {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -831,9 +843,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
         tickstart = HAL_GetTick();
 
         /* Wait till PLL is disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
         {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
           {
             return HAL_TIMEOUT;
           }
@@ -845,16 +857,37 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruc
       /* Do not return HAL_ERROR if request repeats the current configuration */
       temp1_pllckcfg = RCC->PLLCKSELR;
       temp2_pllckcfg = RCC->PLL1DIVR;
-      if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
-	 (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-         ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
-         (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
-         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
-         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
-         ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
+      if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+          (READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+          ((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
+          (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
+          ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
       {
         return HAL_ERROR;
       }
+      else
+      {
+        /* Check if only fractional part needs to be updated  */
+        temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
+        if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
+        {
+          assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
+          /* Disable PLL1FRACEN */
+          __HAL_RCC_PLLFRACN_DISABLE();
+          /* Get Start Tick*/
+          tickstart = HAL_GetTick();
+          /* Wait at least 2 CK_REF (PLL input source divided by M) period to make sure next latched value will be taken into account. */
+          while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
+          {
+          }
+          /* Configure PLL1 PLL1FRACN */
+          __HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
+          /* Enable PLL1FRACEN to latch new value. */
+          __HAL_RCC_PLLFRACN_ENABLE();
+        }
+      }
     }
   }
   return HAL_OK;
@@ -892,8 +925,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   uint32_t tickstart;
   uint32_t common_system_clock;
 
-   /* Check Null pointer */
-  if(RCC_ClkInitStruct == NULL)
+  /* Check Null pointer */
+  if (RCC_ClkInitStruct == NULL)
   {
     return HAL_ERROR;
   }
@@ -907,14 +940,14 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
     (HCLK) and the supply voltage of the device. */
 
   /* Increasing the CPU frequency */
-  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  if (FLatency > __HAL_FLASH_GET_LATENCY())
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
     {
       return HAL_ERROR;
     }
@@ -923,16 +956,16 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 
   /* Increasing the BUS frequency divider */
   /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
   {
 #if defined (RCC_D1CFGR_D1PPRE)
-    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
     {
       assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
     }
 #else
-    if((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+    if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
     {
       assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
       MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
@@ -941,33 +974,33 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   }
 
   /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
   {
 #if defined (RCC_D2CFGR_D2PPRE1)
-    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
     {
       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
     }
 #else
-    if((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+    if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
     {
       assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
-  }
-#endif
     }
+#endif
+  }
   /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
   {
 #if defined(RCC_D2CFGR_D2PPRE2)
-    if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
     {
       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
       MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
     }
 #else
-     if((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+    if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
     {
       assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
       MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
@@ -976,35 +1009,35 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   }
 
   /*-------------------------- D3PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
   {
 #if defined(RCC_D3CFGR_D3PPRE)
-    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
     {
       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
-      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
     }
 #else
-    if((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+    if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
     {
       assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
-      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
+      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
     }
 #endif
   }
 
-   /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
   {
 #if defined (RCC_D1CFGR_HPRE)
-    if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->D1CFGR & RCC_D1CFGR_HPRE))
     {
       /* Set the new HCLK clock divider */
       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
     }
 #else
-        if((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
     {
       /* Set the new HCLK clock divider */
       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
@@ -1013,80 +1046,80 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 #endif
   }
 
-    /*------------------------- SYSCLK Configuration -------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-    {
-      assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
-      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+  /*------------------------- SYSCLK Configuration -------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
 #if defined(RCC_D1CFGR_D1CPRE)
-      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
+    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
 #else
-      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
+    MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
 #endif
-      /* HSE is selected as System Clock Source */
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    /* HSE is selected as System Clock Source */
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
       {
-        /* Check the HSE ready flag */
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
-        {
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
-      /* PLL is selected as System Clock Source */
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    }
+    /* PLL is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
       {
-        /* Check the PLL ready flag */
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
-        {
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
-      /* CSI is selected as System Clock Source */
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+    }
+    /* CSI is selected as System Clock Source */
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
+    {
+      /* Check the PLL ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
       {
-        /* Check the PLL ready flag */
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
-        {
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
-      /* HSI is selected as System Clock Source */
-      else
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
       {
-        /* Check the HSI ready flag */
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
-        {
-          return HAL_ERROR;
-        }
+        return HAL_ERROR;
       }
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+    }
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
 
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() !=  (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
+    /* Get Start Tick*/
+    tickstart = HAL_GetTick();
 
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
     }
 
-    /* Decreasing the BUS frequency divider */
-   /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  }
+
+  /* Decreasing the BUS frequency divider */
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
   {
 #if defined(RCC_D1CFGR_HPRE)
-    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
+    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_HPRE))
     {
       /* Set the new HCLK clock divider */
       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
       MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
     }
 #else
-    if((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
+    if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
     {
       /* Set the new HCLK clock divider */
       assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
@@ -1096,102 +1129,102 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   }
 
   /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  if (FLatency < __HAL_FLASH_GET_LATENCY())
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     __HAL_FLASH_SET_LATENCY(FLatency);
 
     /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    if (__HAL_FLASH_GET_LATENCY() != FLatency)
     {
       return HAL_ERROR;
     }
- }
+  }
 
   /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
- {
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
+  {
 #if defined(RCC_D1CFGR_D1PPRE)
-   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
-   {
-     assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
-     MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
-   }
+    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE))
+    {
+      assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
 #else
-   if((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
-   {
-     assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
-     MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
-   }
+    if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
+    {
+      assert_param(IS_RCC_CDPCLK1(RCC_ClkInitStruct->APB3CLKDivider));
+      MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
+    }
 #endif
- }
+  }
 
   /*-------------------------- PCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- {
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
 #if defined(RCC_D2CFGR_D2PPRE1)
-   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
-   {
-     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
-     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
-   }
+    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
 #else
-   if((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
-   {
-     assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
-     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
-   }
+    if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
+    {
+      assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
+    }
 #endif
- }
+  }
 
   /*-------------------------- PCLK2 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- {
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
 #if defined (RCC_D2CFGR_D2PPRE2)
-   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
-   {
-     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
-     MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
-   }
+    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
 #else
-   if((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
-   {
-     assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
-     MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
-   }
+    if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
+    {
+      assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
+      MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
+    }
 #endif
- }
+  }
 
   /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/
- if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
- {
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
+  {
 #if defined(RCC_D3CFGR_D3PPRE)
-   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
-   {
-     assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
-     MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
-   }
+    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE))
+    {
+      assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider));
+    }
 #else
-   if((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
-   {
-     assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
-     MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
-   }
+    if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
+    {
+      assert_param(IS_RCC_SRDPCLK1(RCC_ClkInitStruct->APB4CLKDivider));
+      MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
+    }
 #endif
- }
+  }
 
   /* Update the SystemCoreClock global variable */
 #if defined(RCC_D1CFGR_D1CPRE)
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
 #else
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
 #endif
 
 #if defined(RCC_D1CFGR_HPRE)
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 #else
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
 #endif
 
 #if defined(DUAL_CORE) && defined(CORE_CM4)
@@ -1201,7 +1234,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
 #endif /* DUAL_CORE && CORE_CM4 */
 
   /* Configure the source of time base considering new system clocks settings*/
-  halstatus = HAL_InitTick (uwTickPrio);
+  halstatus = HAL_InitTick(uwTickPrio);
 
   return halstatus;
 }
@@ -1210,7 +1243,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, ui
   * @}
   */
 
-/** @defgroup RCC_Group2 Peripheral Control functions
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
  *  @brief   RCC clocks control functions
  *
 @verbatim
@@ -1257,7 +1290,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
   assert_param(IS_RCC_MCO(RCC_MCOx));
   assert_param(IS_RCC_MCODIV(RCC_MCODiv));
   /* RCC_MCO1 */
-  if(RCC_MCOx == RCC_MCO1)
+  if (RCC_MCOx == RCC_MCO1)
   {
     assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
 
@@ -1362,78 +1395,78 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
 
   switch (RCC->CFGR & RCC_CFGR_SWS)
   {
-  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
 
-   if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
       {
-        sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
+        sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
       }
       else
       {
         sysclockfreq = (uint32_t) HSI_VALUE;
       }
 
-    break;
+      break;
 
-  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
-    sysclockfreq = CSI_VALUE;
-    break;
+    case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+      sysclockfreq = CSI_VALUE;
+      break;
 
-  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    sysclockfreq = HSE_VALUE;
-    break;
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+      sysclockfreq = HSE_VALUE;
+      break;
 
-  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+    case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
 
-    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
-    SYSCLK = PLL_VCO / PLLR
-    */
-    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
-    pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
-    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLR
+      */
+      pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+      pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4)  ;
+      pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
+      fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
 
-    if (pllm != 0U)
-    {
-      switch (pllsource)
+      if (pllm != 0U)
       {
-      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
-
-       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        switch (pllsource)
         {
-          hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+          case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+
+            if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+            {
+              hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+              pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            }
+            else
+            {
+              pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            }
+            break;
+
+          case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            break;
+
+          case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+            pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            break;
+
+          default:
+            pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+            break;
         }
-        else
-        {
-          pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        }
-        break;
-
-      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
-        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        break;
-
-      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-        pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        break;
-
-      default:
-        pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-        break;
+        pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
+        sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
       }
-      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
-      sysclockfreq =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
-    }
-    else
-    {
-      sysclockfreq = 0U;
-    }
-    break;
+      else
+      {
+        sysclockfreq = 0U;
+      }
+      break;
 
-  default:
-    sysclockfreq = CSI_VALUE;
-    break;
+    default:
+      sysclockfreq = CSI_VALUE;
+      break;
   }
 
   return sysclockfreq;
@@ -1451,18 +1484,18 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
-uint32_t common_system_clock;
+  uint32_t common_system_clock;
 
 #if defined(RCC_D1CFGR_D1CPRE)
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
 #else
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
 #endif
 
 #if defined(RCC_D1CFGR_HPRE)
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 #else
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
 #endif
 
 #if defined(DUAL_CORE) && defined(CORE_CM4)
@@ -1485,16 +1518,16 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
 {
 #if defined (RCC_D2CFGR_D2PPRE1)
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)>> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
 #else
- /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1)>> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
 #endif
 }
 
 
 /**
-  * @brief  Returns the PCLK2 frequency
+  * @brief  Returns the D2 PCLK2 frequency
   * @note   Each time PCLK2 changes, this function must be called to update the
   *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency
@@ -1503,9 +1536,9 @@ uint32_t HAL_RCC_GetPCLK2Freq(void)
 {
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
 #if defined(RCC_D2CFGR_D2PPRE2)
-  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)>> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU));
 #else
-  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2)>> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
+  return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU));
 #endif
 }
 
@@ -1520,19 +1553,19 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
   /* Set all possible values for the Oscillator type parameter ---------------*/
   RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_CSI | \
-                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI| RCC_OSCILLATORTYPE_HSI48;
+                                      RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48;
 
   /* Get the HSE configuration -----------------------------------------------*/
 #if defined(RCC_CR_HSEEXT)
-  if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
+  if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == RCC_CR_HSEBYP)
   {
     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
   }
-  else if((RCC->CR &(RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
+  else if ((RCC->CR & (RCC_CR_HSEBYP | RCC_CR_HSEEXT)) == (RCC_CR_HSEBYP | RCC_CR_HSEEXT))
   {
     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS_DIGITAL;
   }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
   {
     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
   }
@@ -1541,11 +1574,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
   }
 #else
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
   {
     RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
   }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
   {
     RCC_OscInitStruct->HSEState = RCC_HSE_ON;
   }
@@ -1555,8 +1588,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   }
 #endif /* RCC_CR_HSEEXT */
 
-   /* Get the CSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_CSION) == RCC_CR_CSION)
+  /* Get the CSI configuration -----------------------------------------------*/
+  if ((RCC->CR & RCC_CR_CSION) == RCC_CR_CSION)
   {
     RCC_OscInitStruct->CSIState = RCC_CSI_ON;
   }
@@ -1566,7 +1599,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   }
 
 #if defined(RCC_VER_X)
-  if(HAL_GetREVID() <= REV_ID_Y)
+  if (HAL_GetREVID() <= REV_ID_Y)
   {
     RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
   }
@@ -1575,11 +1608,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
   }
 #else
- RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
 #endif /*RCC_VER_X*/
 
   /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
   {
     RCC_OscInitStruct->HSIState = RCC_HSI_ON;
   }
@@ -1589,7 +1622,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   }
 
 #if defined(RCC_VER_X)
-  if(HAL_GetREVID() <= REV_ID_Y)
+  if (HAL_GetREVID() <= REV_ID_Y)
   {
     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
   }
@@ -1598,20 +1631,20 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
   }
 #else
-    RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
 #endif /*RCC_VER_X*/
 
   /* Get the LSE configuration -----------------------------------------------*/
 #if defined(RCC_BDCR_LSEEXT)
-  if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
+  if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == RCC_BDCR_LSEBYP)
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
   }
-  else if((RCC->BDCR &(RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP|RCC_BDCR_LSEEXT))
+  else if ((RCC->BDCR & (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT)) == (RCC_BDCR_LSEBYP | RCC_BDCR_LSEEXT))
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS_DIGITAL;
   }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
   }
@@ -1620,11 +1653,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
   }
 #else
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
   }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
   {
     RCC_OscInitStruct->LSEState = RCC_LSE_ON;
   }
@@ -1635,7 +1668,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
 #endif /* RCC_BDCR_LSEEXT */
 
   /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
   {
     RCC_OscInitStruct->LSIState = RCC_LSI_ON;
   }
@@ -1645,7 +1678,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   }
 
   /* Get the HSI48 configuration ---------------------------------------------*/
-  if((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
+  if ((RCC->CR & RCC_CR_HSI48ON) == RCC_CR_HSI48ON)
   {
     RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
   }
@@ -1655,7 +1688,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
   }
 
   /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
   {
     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
   }
@@ -1664,11 +1697,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
     RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
   }
   RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> RCC_PLLCKSELR_DIVM1_Pos);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos)+ 1U;
-  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos)+ 1U;
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos)+ 1U;
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos)+ 1U;
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1U;
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1U;
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1U;
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1U;
   RCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1RGE));
   RCC_OscInitStruct->PLL.PLLVCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL1VCOSEL) >> RCC_PLLCFGR_PLL1VCOSEL_Pos);
   RCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos));
@@ -1741,10 +1774,10 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pF
 void HAL_RCC_NMI_IRQHandler(void)
 {
   /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  if (__HAL_RCC_GET_IT(RCC_IT_CSS))
   {
     /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CCSCallback();
+    HAL_RCC_CSSCallback();
 
     /* Clear RCC CSS pending bit */
     __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
@@ -1755,10 +1788,10 @@ void HAL_RCC_NMI_IRQHandler(void)
   * @brief  RCC Clock Security System interrupt callback
   * @retval none
   */
-__weak void HAL_RCC_CCSCallback(void)
+__weak void HAL_RCC_CSSCallback(void)
 {
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RCC_CCSCallback could be implemented in the user file
+            the HAL_RCC_CSSCallback could be implemented in the user file
    */
 }
 
@@ -1779,4 +1812,3 @@ __weak void HAL_RCC_CCSCallback(void)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h
index 6a589ee132..1626c6d050 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h
@@ -6,14 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -22,7 +20,7 @@
 #define STM32H7xx_HAL_RCC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -57,9 +55,9 @@ typedef struct
                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */
 
   uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 4 and Max_Data = 512 
+                            This parameter must be a number between Min_Data = 4 and Max_Data = 512
                             or between Min_Data = 8 and Max_Data = 420(*)
-                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */                        
+                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */
 
   uint32_t PLLP;       /*!< PLLP: Division factor for system clock.
                             This parameter must be a number between Min_Data = 2 and Max_Data = 128
@@ -78,7 +76,7 @@ typedef struct
   uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for
                         PLL1 VCO It should be a value between 0 and 8191                              */
 
-}RCC_PLLInitTypeDef;
+} RCC_PLLInitTypeDef;
 
 /**
   * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition
@@ -104,7 +102,7 @@ typedef struct
   uint32_t LSIState;             /*!< The new state of the LSI.
                                       This parameter can be a value of @ref RCC_LSI_Config                        */
 
- uint32_t HSI48State;            /*!< The new state of the HSI48.
+  uint32_t HSI48State;            /*!< The new state of the HSI48.
                                       This parameter can be a value of @ref RCC_HSI48_Config                      */
 
   uint32_t CSIState;             /*!< The new state of the CSI.
@@ -116,7 +114,7 @@ typedef struct
 
   RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
 
-}RCC_OscInitTypeDef;
+} RCC_OscInitTypeDef;
 
 /**
   * @brief  RCC System, AHB and APB busses clock configuration structure definition
@@ -144,7 +142,7 @@ typedef struct
                                        This parameter can be a value of @ref RCC_APB2_Clock_Source                        */
   uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).
                                        This parameter can be a value of @ref RCC_APB4_Clock_Source                        */
-}RCC_ClkInitTypeDef;
+} RCC_ClkInitTypeDef;
 
 /**
   * @}
@@ -1213,7 +1211,7 @@ typedef struct
                                         UNUSED(tmpreg); \
                                        } while(0)
 #endif /* FMAC */
-    
+
 #if defined(CORDIC)
 #define __HAL_RCC_CORDIC_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
@@ -2121,7 +2119,7 @@ typedef struct
 #define __HAL_RCC_TIM23_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_TIM23EN)   != 0U)
 #endif /* TIM23 */
 #if defined(TIM24)
-#define __HAL_RCC_TIM24_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN)   != 0U) 
+#define __HAL_RCC_TIM24_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_TIM24EN)   != 0U)
 #endif /* TIM24 */
 
 #define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)
@@ -7572,7 +7570,7 @@ typedef struct
   *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
   *
   * @param  __PLLP1__: specifies the division factor for system  clock.
-  *          This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed) 
+  *          This parameter must be a number between 2 or 1(**) and 128 (where odd numbers are not allowed)
   *
   * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks
   *          This parameter must be a number between 1 and 128
@@ -7581,7 +7579,7 @@ typedef struct
   *          This parameter must be a number between 1 and 128
   *
   * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)
-  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 
+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible
   *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.
   * @retval None
   *
@@ -7625,7 +7623,7 @@ typedef struct
   *
   * @retval None
   */
- #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
+#define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
 
 
 /** @brief  Macro to select  the PLL1  reference frequency range.
@@ -7960,9 +7958,9 @@ typedef struct
 #include "stm32h7xx_hal_rcc_ex.h"
 
 /* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCC_Exported_Functions
-  * @{
-  */
+/** @addtogroup RCC_Exported_Functions
+ * @{
+ */
 
 /** @addtogroup RCC_Exported_Functions_Group1
   * @{
@@ -7992,7 +7990,7 @@ void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t
 /* CSS NMI IRQ handler */
 void     HAL_RCC_NMI_IRQHandler(void);
 /* User Callbacks in non blocking mode (IT mode) */
-void     HAL_RCC_CCSCallback(void);
+void     HAL_RCC_CSSCallback(void);
 
 /**
   * @}
@@ -8015,6 +8013,7 @@ void     HAL_RCC_CCSCallback(void);
 #define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
 #define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */
 #define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */
+#define PLL_FRAC_TIMEOUT_VALUE     (1U)    /* PLL Fractional part waiting time before new latch enable : 1 ms */
 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */
 #define RCC_DBP_TIMEOUT_VALUE      (100U)
 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
@@ -8265,4 +8264,3 @@ void     HAL_RCC_CCSCallback(void);
 
 #endif /* STM32H7xx_HAL_RCC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c
index afde46b3b8..b771887a86 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c
@@ -10,14 +10,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -113,42 +111,42 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
   /*---------------------------- SPDIFRX configuration -------------------------------*/
 
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
   {
 
-    switch(PeriphClkInit->SpdifrxClockSelection)
+    switch (PeriphClkInit->SpdifrxClockSelection)
     {
-    case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
-      /* Enable PLL1Q Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SPDIFRXCLKSOURCE_PLL:      /* PLL is used as clock source for SPDIFRX*/
+        /* Enable PLL1Q Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SPDIFRX clock source configuration done later after clock selection check */
-      break;
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
+      case RCC_SPDIFRXCLKSOURCE_PLL2: /* PLL2 is used as clock source for SPDIFRX*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 
-      /* SPDIFRX clock source configuration done later after clock selection check */
-      break;
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+      case RCC_SPDIFRXCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPDIFRX*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 
-      /* SPDIFRX clock source configuration done later after clock selection check */
-      break;
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPDIFRXCLKSOURCE_HSI:
-      /* Internal OSC clock is used as source of SPDIFRX clock*/
-      /* SPDIFRX clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPDIFRXCLKSOURCE_HSI:
+        /* Internal OSC clock is used as source of SPDIFRX clock*/
+        /* SPDIFRX clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SPDIFRX clock*/
       __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
@@ -161,46 +159,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- SAI1 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
   {
-    switch(PeriphClkInit->Sai1ClockSelection)
+    switch (PeriphClkInit->Sai1ClockSelection)
     {
-    case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SAI1CLKSOURCE_PLL:      /* PLL is used as clock source for SAI1*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+      case RCC_SAI1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI1*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI1CLKSOURCE_PIN:
-      /* External clock is used as source of SAI1 clock*/
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI1CLKSOURCE_PIN:
+        /* External clock is used as source of SAI1 clock*/
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI1CLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI1CLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SAI1 clock */
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SAI1 clock*/
       __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
@@ -214,46 +212,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(SAI3)
   /*---------------------------- SAI2/3 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI23) == RCC_PERIPHCLK_SAI23)
   {
-    switch(PeriphClkInit->Sai23ClockSelection)
+    switch (PeriphClkInit->Sai23ClockSelection)
     {
-    case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SAI23CLKSOURCE_PLL:      /* PLL is used as clock source for SAI2/3 */
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SAI2/3 clock source configuration done later after clock selection check */
-      break;
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2/3 */
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SAI2/3 clock source configuration done later after clock selection check */
-      break;
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+      case RCC_SAI23CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2/3 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SAI2/3 clock source configuration done later after clock selection check */
-      break;
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI23CLKSOURCE_PIN:
-      /* External clock is used as source of SAI2/3 clock*/
-      /* SAI2/3 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI23CLKSOURCE_PIN:
+        /* External clock is used as source of SAI2/3 clock*/
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI23CLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
-      /* SAI2/3 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI23CLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SAI2/3 clock */
+        /* SAI2/3 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SAI2/3 clock*/
       __HAL_RCC_SAI23_CONFIG(PeriphClkInit->Sai23ClockSelection);
@@ -269,51 +267,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(RCC_CDCCIP1R_SAI2ASEL)
   /*---------------------------- SAI2A configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
   {
-    switch(PeriphClkInit->Sai2AClockSelection)
+    switch (PeriphClkInit->Sai2AClockSelection)
     {
-    case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
-      /* Enable SAI2A Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SAI2ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2A */
+        /* Enable SAI2A Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SAI2A clock source configuration done later after clock selection check */
-      break;
+        /* SAI2A clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
+      case RCC_SAI2ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2A */
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SAI2A clock source configuration done later after clock selection check */
-      break;
+        /* SAI2A clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+      case RCC_SAI2ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2A */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SAI2A clock source configuration done later after clock selection check */
-      break;
+        /* SAI2A clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2ACLKSOURCE_PIN:
-      /* External clock is used as source of SAI2A clock*/
-      /* SAI2A clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI2ACLKSOURCE_PIN:
+        /* External clock is used as source of SAI2A clock*/
+        /* SAI2A clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2ACLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
-      /* SAI2A clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI2ACLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SAI2A clock */
+        /* SAI2A clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2ACLKSOURCE_SPDIF:
-      /* SPDIF clock is used as source of SAI2A clock */
-      /* SAI2A clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI2ACLKSOURCE_SPDIF:
+        /* SPDIF clock is used as source of SAI2A clock */
+        /* SAI2A clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SAI2A clock*/
       __HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
@@ -329,51 +327,51 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #if defined(RCC_CDCCIP1R_SAI2BSEL)
 
   /*---------------------------- SAI2B configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
   {
-    switch(PeriphClkInit->Sai2BClockSelection)
+    switch (PeriphClkInit->Sai2BClockSelection)
     {
-    case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SAI2BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2B */
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SAI2B clock source configuration done later after clock selection check */
-      break;
+        /* SAI2B clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
+      case RCC_SAI2BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2B */
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SAI2B clock source configuration done later after clock selection check */
-      break;
+        /* SAI2B clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+      case RCC_SAI2BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2B */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SAI2B clock source configuration done later after clock selection check */
-      break;
+        /* SAI2B clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2BCLKSOURCE_PIN:
-      /* External clock is used as source of SAI2B clock*/
-      /* SAI2B clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI2BCLKSOURCE_PIN:
+        /* External clock is used as source of SAI2B clock*/
+        /* SAI2B clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2BCLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
-      /* SAI2B clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI2BCLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SAI2B clock */
+        /* SAI2B clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI2BCLKSOURCE_SPDIF:
-      /* SPDIF clock is used as source of SAI2B clock */
-      /* SAI2B clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI2BCLKSOURCE_SPDIF:
+        /* SPDIF clock is used as source of SAI2B clock */
+        /* SAI2B clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SAI2B clock*/
       __HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
@@ -388,53 +386,53 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(SAI4)
   /*---------------------------- SAI4A configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4A) == RCC_PERIPHCLK_SAI4A)
   {
-    switch(PeriphClkInit->Sai4AClockSelection)
+    switch (PeriphClkInit->Sai4AClockSelection)
     {
-    case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SAI4ACLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+      case RCC_SAI4ACLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SAI2 clock source configuration done later after clock selection check */
-      break;
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+      case RCC_SAI4ACLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4ACLKSOURCE_PIN:
-      /* External clock is used as source of SAI2 clock*/
-      /* SAI2 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI4ACLKSOURCE_PIN:
+        /* External clock is used as source of SAI2 clock*/
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
+
+      case RCC_SAI4ACLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4ACLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
- 
 #if defined(RCC_VER_3_0)
-    case RCC_SAI4ACLKSOURCE_SPDIF:
-      /* SPDIF clock is used as source of SAI4A clock */
-      /* SAI4A clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI4ACLKSOURCE_SPDIF:
+        /* SPDIF clock is used as source of SAI4A clock */
+        /* SAI4A clock source configuration done later after clock selection check */
+        break;
 #endif /* RCC_VER_3_0 */
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SAI4A clock*/
       __HAL_RCC_SAI4A_CONFIG(PeriphClkInit->Sai4AClockSelection);
@@ -446,53 +444,53 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     }
   }
   /*---------------------------- SAI4B configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI4B) == RCC_PERIPHCLK_SAI4B)
   {
-    switch(PeriphClkInit->Sai4BClockSelection)
+    switch (PeriphClkInit->Sai4BClockSelection)
     {
-    case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
-      /* Enable SAI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SAI4BCLKSOURCE_PLL:      /* PLL is used as clock source for SAI2*/
+        /* Enable SAI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
+      case RCC_SAI4BCLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SAI2 clock source configuration done later after clock selection check */
-      break;
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+      case RCC_SAI4BCLKSOURCE_PLL3:  /* PLL3 is used as clock source for SAI2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4BCLKSOURCE_PIN:
-      /* External clock is used as source of SAI2 clock*/
-      /* SAI2 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI4BCLKSOURCE_PIN:
+        /* External clock is used as source of SAI2 clock*/
+        /* SAI2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SAI4BCLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
-      /* SAI1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI4BCLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SAI2 clock */
+        /* SAI1 clock source configuration done later after clock selection check */
+        break;
 
 #if defined(RCC_VER_3_0)
-    case RCC_SAI4BCLKSOURCE_SPDIF:
-      /* SPDIF clock is used as source of SAI4B clock */
-      /* SAI4B clock source configuration done later after clock selection check */
-      break;
+      case RCC_SAI4BCLKSOURCE_SPDIF:
+        /* SPDIF clock is used as source of SAI4B clock */
+        /* SAI4B clock source configuration done later after clock selection check */
+        break;
 #endif /* RCC_VER_3_0 */
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SAI4B clock*/
       __HAL_RCC_SAI4B_CONFIG(PeriphClkInit->Sai4BClockSelection);
@@ -507,40 +505,40 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(QUADSPI)
   /*---------------------------- QSPI configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
   {
-    switch(PeriphClkInit->QspiClockSelection)
+    switch (PeriphClkInit->QspiClockSelection)
     {
-    case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
-      /* Enable QSPI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_QSPICLKSOURCE_PLL:      /* PLL is used as clock source for QSPI*/
+        /* Enable QSPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* QSPI clock source configuration done later after clock selection check */
-      break;
+        /* QSPI clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
+      case RCC_QSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for QSPI*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 
-      /* QSPI clock source configuration done later after clock selection check */
-      break;
+        /* QSPI clock source configuration done later after clock selection check */
+        break;
 
 
-    case RCC_QSPICLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
-      /* QSPI clock source configuration done later after clock selection check */
-      break;
+      case RCC_QSPICLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of QSPI clock */
+        /* QSPI clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_QSPICLKSOURCE_D1HCLK:
-      /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
-      break;
+      case RCC_QSPICLKSOURCE_D1HCLK:
+        /* Domain1 HCLK  clock selected as QSPI kernel peripheral clock */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of QSPI clock*/
       __HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
@@ -555,40 +553,40 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(OCTOSPI1) || defined(OCTOSPI2)
   /*---------------------------- OCTOSPI configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
   {
-    switch(PeriphClkInit->OspiClockSelection)
+    switch (PeriphClkInit->OspiClockSelection)
     {
-    case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
-      /* Enable OSPI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_OSPICLKSOURCE_PLL:      /* PLL is used as clock source for OSPI*/
+        /* Enable OSPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* OSPI clock source configuration done later after clock selection check */
-      break;
+        /* OSPI clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
+      case RCC_OSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for OSPI*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 
-      /* OSPI clock source configuration done later after clock selection check */
-      break;
+        /* OSPI clock source configuration done later after clock selection check */
+        break;
 
 
-    case RCC_OSPICLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
-      /* OSPI clock source configuration done later after clock selection check */
-      break;
+      case RCC_OSPICLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of OSPI clock */
+        /* OSPI clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_OSPICLKSOURCE_HCLK:
-      /* HCLK clock selected as OSPI kernel peripheral clock */
-      break;
+      case RCC_OSPICLKSOURCE_HCLK:
+        /* HCLK clock selected as OSPI kernel peripheral clock */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of OSPI clock*/
       __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
@@ -602,45 +600,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #endif  /*OCTOSPI*/
 
   /*---------------------------- SPI1/2/3 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
   {
-    switch(PeriphClkInit->Spi123ClockSelection)
+    switch (PeriphClkInit->Spi123ClockSelection)
     {
-    case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
-      /* Enable SPI Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SPI123CLKSOURCE_PLL:      /* PLL is used as clock source for SPI1/2/3 */
+        /* Enable SPI Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SPI1/2/3 clock source configuration done later after clock selection check */
-      break;
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI1/2/3 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* SPI1/2/3 clock source configuration done later after clock selection check */
-      break;
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_P_UPDATE);
+      case RCC_SPI123CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI1/2/3 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
 
-      /* SPI1/2/3 clock source configuration done later after clock selection check */
-      break;
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI123CLKSOURCE_PIN:
-      /* External clock is used as source of SPI1/2/3 clock*/
-      /* SPI1/2/3 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI123CLKSOURCE_PIN:
+        /* External clock is used as source of SPI1/2/3 clock*/
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI123CLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
-      /* SPI1/2/3 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI123CLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of SPI1/2/3 clock */
+        /* SPI1/2/3 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SPI1/2/3 clock*/
       __HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
@@ -653,46 +651,46 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- SPI4/5 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
   {
-    switch(PeriphClkInit->Spi45ClockSelection)
+    switch (PeriphClkInit->Spi45ClockSelection)
     {
-    case RCC_SPI45CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for SPI4/5 */
-      /* SPI4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI45CLKSOURCE_PCLK2:      /* CD/D2 PCLK2 as clock source for SPI4/5 */
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
+      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI4/5 */
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 
-      /* SPI4/5 clock source configuration done later after clock selection check */
-      break;
-    case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
-      /* SPI4/5 clock source configuration done later after clock selection check */
-      break;
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
+      case RCC_SPI45CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI4/5 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI45CLKSOURCE_HSI:
-      /* HSI oscillator clock is used as source of SPI4/5 clock*/
-      /* SPI4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI45CLKSOURCE_HSI:
+        /* HSI oscillator clock is used as source of SPI4/5 clock*/
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI45CLKSOURCE_CSI:
-      /*  CSI oscillator clock is used as source of SPI4/5 clock */
-      /* SPI4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI45CLKSOURCE_CSI:
+        /*  CSI oscillator clock is used as source of SPI4/5 clock */
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI45CLKSOURCE_HSE:
-      /* HSE,  oscillator is used as source of SPI4/5 clock */
-      /* SPI4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI45CLKSOURCE_HSE:
+        /* HSE,  oscillator is used as source of SPI4/5 clock */
+        /* SPI4/5 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SPI4/5 clock*/
       __HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
@@ -705,52 +703,52 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- SPI6 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
   {
-    switch(PeriphClkInit->Spi6ClockSelection)
+    switch (PeriphClkInit->Spi6ClockSelection)
     {
-    case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI6CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for SPI6*/
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is used as clock source for SPI6*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
-    case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
+      case RCC_SPI6CLKSOURCE_PLL3:  /* PLL3 is used as clock source for SPI6*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI6CLKSOURCE_HSI:
-      /* HSI oscillator clock is used as source of SPI6 clock*/
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI6CLKSOURCE_HSI:
+        /* HSI oscillator clock is used as source of SPI6 clock*/
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI6CLKSOURCE_CSI:
-      /*  CSI oscillator clock is used as source of SPI6 clock */
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI6CLKSOURCE_CSI:
+        /*  CSI oscillator clock is used as source of SPI6 clock */
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SPI6CLKSOURCE_HSE:
-      /* HSE,  oscillator is used as source of SPI6 clock */
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI6CLKSOURCE_HSE:
+        /* HSE,  oscillator is used as source of SPI6 clock */
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
 #if defined(RCC_SPI6CLKSOURCE_PIN)
-    case RCC_SPI6CLKSOURCE_PIN:
-      /* 2S_CKIN is used as source of SPI6 clock */
-      /* SPI6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_SPI6CLKSOURCE_PIN:
+        /* 2S_CKIN is used as source of SPI6 clock */
+        /* SPI6 clock source configuration done later after clock selection check */
+        break;
 #endif
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SPI6 clock*/
       __HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
@@ -764,29 +762,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(DSI)
   /*---------------------------- DSI configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
   {
-    switch(PeriphClkInit->DsiClockSelection)
+    switch (PeriphClkInit->DsiClockSelection)
     {
 
-    case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
+      case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 
-      /* DSI clock source configuration done later after clock selection check */
-      break;
+        /* DSI clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_DSICLKSOURCE_PHY:
-      /* PHY is used as clock source for DSI*/
-      /* DSI clock source configuration done later after clock selection check */
-      break;
+      case RCC_DSICLKSOURCE_PHY:
+        /* PHY is used as clock source for DSI*/
+        /* DSI clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of DSI clock*/
       __HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
@@ -801,35 +799,35 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(FDCAN1) || defined(FDCAN2)
   /*---------------------------- FDCAN configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
   {
-    switch(PeriphClkInit->FdcanClockSelection)
+    switch (PeriphClkInit->FdcanClockSelection)
     {
-    case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
-      /* Enable FDCAN Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_FDCANCLKSOURCE_PLL:      /* PLL is used as clock source for FDCAN*/
+        /* Enable FDCAN Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* FDCAN clock source configuration done later after clock selection check */
-      break;
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
+      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
 
-      /* FDCAN clock source configuration done later after clock selection check */
-      break;
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_FDCANCLKSOURCE_HSE:
-      /* HSE is used as clock source for FDCAN*/
-      /* FDCAN clock source configuration done later after clock selection check */
-      break;
+      case RCC_FDCANCLKSOURCE_HSE:
+        /* HSE is used as clock source for FDCAN*/
+        /* FDCAN clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of FDCAN clock*/
       __HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
@@ -843,40 +841,40 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #endif /*FDCAN1 || FDCAN2*/
 
   /*---------------------------- FMC configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
   {
-    switch(PeriphClkInit->FmcClockSelection)
+    switch (PeriphClkInit->FmcClockSelection)
     {
-    case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
-      /* Enable FMC Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_FMCCLKSOURCE_PLL:      /* PLL is used as clock source for FMC*/
+        /* Enable FMC Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* FMC clock source configuration done later after clock selection check */
-      break;
+        /* FMC clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
+      case RCC_FMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for FMC*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 
-      /* FMC clock source configuration done later after clock selection check */
-      break;
+        /* FMC clock source configuration done later after clock selection check */
+        break;
 
 
-    case RCC_FMCCLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
-      /* FMC clock source configuration done later after clock selection check */
-      break;
+      case RCC_FMCCLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of FMC clock */
+        /* FMC clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_FMCCLKSOURCE_HCLK:
-      /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
-      break;
+      case RCC_FMCCLKSOURCE_HCLK:
+        /* D1/CD HCLK  clock selected as FMC kernel peripheral clock */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of FMC clock*/
       __HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
@@ -889,7 +887,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- RTC configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
   {
     /* check for RTC Parameters used to output RTCCLK */
     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
@@ -900,19 +898,19 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     /* Wait for Backup domain Write protection disable */
     tickstart = HAL_GetTick();
 
-    while((PWR->CR1 & PWR_CR1_DBP) == 0U)
+    while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
     {
-      if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
       {
         ret = HAL_TIMEOUT;
         break;
       }
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Reset the Backup domain only if the RTC Clock source selection is modified */
-      if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
+      if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
       {
         /* Store the content of BDCR register before the reset of Backup Domain */
         tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
@@ -924,15 +922,15 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
       }
 
       /* If LSE is selected as RTC clock source (and enabled prior to Backup Domain reset), wait for LSE reactivation */
-      if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
+      if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
       {
         /* Get Start Tick*/
         tickstart = HAL_GetTick();
 
         /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
+        while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
         {
-          if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
           {
             ret = HAL_TIMEOUT;
             break;
@@ -940,7 +938,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
         }
       }
 
-      if(ret == HAL_OK)
+      if (ret == HAL_OK)
       {
         __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
       }
@@ -959,45 +957,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 
   /*-------------------------- USART1/6 configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
   {
-    switch(PeriphClkInit->Usart16ClockSelection)
+    switch (PeriphClkInit->Usart16ClockSelection)
     {
-    case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
-      /* USART1/6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART16CLKSOURCE_PCLK2: /* CD/D2 PCLK2 as clock source for USART1/6 */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
-      /* USART1/6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART16CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART1/6 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
-      /* USART1/6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART16CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART1/6 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART16CLKSOURCE_HSI:
-      /* HSI oscillator clock is used as source of USART1/6 clock */
-      /* USART1/6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART16CLKSOURCE_HSI:
+        /* HSI oscillator clock is used as source of USART1/6 clock */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART16CLKSOURCE_CSI:
-      /* CSI oscillator clock is used as source of USART1/6 clock */
-      /* USART1/6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART16CLKSOURCE_CSI:
+        /* CSI oscillator clock is used as source of USART1/6 clock */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART16CLKSOURCE_LSE:
-      /* LSE,  oscillator is used as source of USART1/6 clock */
-      /* USART1/6 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART16CLKSOURCE_LSE:
+        /* LSE,  oscillator is used as source of USART1/6 clock */
+        /* USART1/6 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of USART1/6 clock */
       __HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
@@ -1010,45 +1008,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*-------------------------- USART2/3/4/5/7/8 Configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
   {
-    switch(PeriphClkInit->Usart234578ClockSelection)
+    switch (PeriphClkInit->Usart234578ClockSelection)
     {
-    case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
-      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART234578CLKSOURCE_PCLK1: /* CD/D2 PCLK1 as clock source for USART2/3/4/5/7/8 */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
-      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART234578CLKSOURCE_PLL2: /* PLL2 is used as clock source for USART2/3/4/5/7/8 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
-      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART234578CLKSOURCE_PLL3: /* PLL3 is used as clock source for USART2/3/4/5/7/8 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART234578CLKSOURCE_HSI:
-      /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
-      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART234578CLKSOURCE_HSI:
+        /* HSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART234578CLKSOURCE_CSI:
-      /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
-      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART234578CLKSOURCE_CSI:
+        /* CSI oscillator clock is used as source of USART2/3/4/5/7/8 clock */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USART234578CLKSOURCE_LSE:
-      /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
-      /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
-      break;
+      case RCC_USART234578CLKSOURCE_LSE:
+        /* LSE,  oscillator is used as source of USART2/3/4/5/7/8 clock */
+        /* USART2/3/4/5/7/8 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of USART2/3/4/5/7/8 clock */
       __HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
@@ -1061,45 +1059,45 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*-------------------------- LPUART1 Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
   {
-    switch(PeriphClkInit->Lpuart1ClockSelection)
+    switch (PeriphClkInit->Lpuart1ClockSelection)
     {
-    case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
-      /* LPUART1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPUART1CLKSOURCE_PCLK4: /* SRD/D3 PCLK1 (PCLK4) as clock source for LPUART1 */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
-      /* LPUART1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPUART1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPUART1 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
-      /* LPUART1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPUART1CLKSOURCE_PLL3: /* PLL3 is used as clock source for LPUART1 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPUART1CLKSOURCE_HSI:
-      /* HSI oscillator clock is used as source of LPUART1 clock */
-      /* LPUART1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPUART1CLKSOURCE_HSI:
+        /* HSI oscillator clock is used as source of LPUART1 clock */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPUART1CLKSOURCE_CSI:
-      /* CSI oscillator clock is used as source of LPUART1 clock */
-      /* LPUART1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPUART1CLKSOURCE_CSI:
+        /* CSI oscillator clock is used as source of LPUART1 clock */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPUART1CLKSOURCE_LSE:
-      /* LSE,  oscillator is used as source of LPUART1 clock */
-      /* LPUART1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPUART1CLKSOURCE_LSE:
+        /* LSE,  oscillator is used as source of LPUART1 clock */
+        /* LPUART1 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of LPUART1 clock */
       __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
@@ -1112,47 +1110,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- LPTIM1 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
   {
-    switch(PeriphClkInit->Lptim1ClockSelection)
+    switch (PeriphClkInit->Lptim1ClockSelection)
     {
-    case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
-      /* LPTIM1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM1CLKSOURCE_PCLK1:      /* CD/D2 PCLK1 as clock source for LPTIM1*/
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
+      case RCC_LPTIM1CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM1*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* LPTIM1 clock source configuration done later after clock selection check */
-      break;
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+      case RCC_LPTIM1CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM1*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 
-      /* LPTIM1 clock source configuration done later after clock selection check */
-      break;
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM1CLKSOURCE_LSE:
-      /* External low speed OSC clock is used as source of LPTIM1 clock*/
-      /* LPTIM1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM1CLKSOURCE_LSE:
+        /* External low speed OSC clock is used as source of LPTIM1 clock*/
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM1CLKSOURCE_LSI:
-      /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
-      /* LPTIM1 clock source configuration done later after clock selection check */
-      break;
-    case RCC_LPTIM1CLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
-      /* LPTIM1 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM1CLKSOURCE_LSI:
+        /* Internal  low speed OSC clock is used  as source of LPTIM1 clock*/
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
+      case RCC_LPTIM1CLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM1 clock */
+        /* LPTIM1 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of LPTIM1 clock*/
       __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
@@ -1165,47 +1163,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- LPTIM2 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
   {
-    switch(PeriphClkInit->Lptim2ClockSelection)
+    switch (PeriphClkInit->Lptim2ClockSelection)
     {
-    case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
-      /* LPTIM2 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM2CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM2*/
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
+      case RCC_LPTIM2CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM2*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* LPTIM2 clock source configuration done later after clock selection check */
-      break;
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+      case RCC_LPTIM2CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM2*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 
-      /* LPTIM2 clock source configuration done later after clock selection check */
-      break;
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM2CLKSOURCE_LSE:
-      /* External low speed OSC clock is used as source of LPTIM2 clock*/
-      /* LPTIM2 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM2CLKSOURCE_LSE:
+        /* External low speed OSC clock is used as source of LPTIM2 clock*/
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM2CLKSOURCE_LSI:
-      /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
-      /* LPTIM2 clock source configuration done later after clock selection check */
-      break;
-    case RCC_LPTIM2CLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
-      /* LPTIM2 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM2CLKSOURCE_LSI:
+        /* Internal  low speed OSC clock is used  as source of LPTIM2 clock*/
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
+      case RCC_LPTIM2CLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM2 clock */
+        /* LPTIM2 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of LPTIM2 clock*/
       __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
@@ -1218,47 +1216,47 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*---------------------------- LPTIM345 configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
   {
-    switch(PeriphClkInit->Lptim345ClockSelection)
+    switch (PeriphClkInit->Lptim345ClockSelection)
     {
 
-    case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
-      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM345CLKSOURCE_PCLK4:      /* SRD/D3 PCLK1 (PCLK4) as clock source for LPTIM3/4/5 */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+      case RCC_LPTIM345CLKSOURCE_PLL2: /* PLL2 is used as clock source for LPTIM3/4/5 */
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
-      break;
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+      case RCC_LPTIM345CLKSOURCE_PLL3:  /* PLL3 is used as clock source for LPTIM3/4/5 */
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 
-      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
-      break;
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM345CLKSOURCE_LSE:
-      /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
-      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM345CLKSOURCE_LSE:
+        /* External low speed OSC clock is used as source of LPTIM3/4/5 clock */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_LPTIM345CLKSOURCE_LSI:
-      /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
-      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
-      break;
-    case RCC_LPTIM345CLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
-      /* LPTIM3/4/5 clock source configuration done later after clock selection check */
-      break;
+      case RCC_LPTIM345CLKSOURCE_LSI:
+        /* Internal  low speed OSC clock is used  as source of LPTIM3/4/5 clock */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
+      case RCC_LPTIM345CLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of LPTIM3/4/5 clock */
+        /* LPTIM3/4/5 clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of LPTIM3/4/5 clock */
       __HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
@@ -1272,89 +1270,89 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
   /*------------------------------ I2C1/2/3/5* Configuration ------------------------*/
 #if defined(I2C5)
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1235) == RCC_PERIPHCLK_I2C1235)
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C1235CLKSOURCE(PeriphClkInit->I2c1235ClockSelection));
 
-    if ((PeriphClkInit->I2c1235ClockSelection )== RCC_I2C1235CLKSOURCE_PLL3 )
+    if ((PeriphClkInit->I2c1235ClockSelection) == RCC_I2C1235CLKSOURCE_PLL3)
     {
-        if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
-        {
-          status = HAL_ERROR;
-        }
-    }
-
-      __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
-
-  }
-#else
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
-
-    if ((PeriphClkInit->I2c123ClockSelection )== RCC_I2C123CLKSOURCE_PLL3 )
-    {
-        if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
-        {
-          status = HAL_ERROR;
-        }
-    }
-
-      __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
-
-  }
-#endif /* I2C5 */
-
-  /*------------------------------ I2C4 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
-
-    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3 )
-    {
-      if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!= HAL_OK)
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
       {
         status = HAL_ERROR;
       }
     }
 
-      __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
+    __HAL_RCC_I2C1235_CONFIG(PeriphClkInit->I2c1235ClockSelection);
+
+  }
+#else
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C123CLKSOURCE(PeriphClkInit->I2c123ClockSelection));
+
+    if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
+    {
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+    __HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
+
+  }
+#endif /* I2C5 */
+
+  /*------------------------------ I2C4 Configuration ------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
+
+    if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
+    {
+      if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
+      {
+        status = HAL_ERROR;
+      }
+    }
+
+    __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
 
   }
 
   /*---------------------------- ADC configuration -------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
   {
-    switch(PeriphClkInit->AdcClockSelection)
+    switch (PeriphClkInit->AdcClockSelection)
     {
 
-    case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
+      case RCC_ADCCLKSOURCE_PLL2: /* PLL2 is used as clock source for ADC*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_P_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
 
-      /* ADC clock source configuration done later after clock selection check */
-      break;
+        /* ADC clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE);
+      case RCC_ADCCLKSOURCE_PLL3:  /* PLL3 is used as clock source for ADC*/
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
 
-      /* ADC clock source configuration done later after clock selection check */
-      break;
+        /* ADC clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_ADCCLKSOURCE_CLKP:
-      /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
-      /* ADC clock source configuration done later after clock selection check */
-      break;
+      case RCC_ADCCLKSOURCE_CLKP:
+        /* HSI, HSE, or CSI oscillator is used as source of ADC clock */
+        /* ADC clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of ADC clock*/
       __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
@@ -1367,36 +1365,36 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*------------------------------ USB Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
   {
 
-    switch(PeriphClkInit->UsbClockSelection)
+    switch (PeriphClkInit->UsbClockSelection)
     {
-    case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
-      /* Enable USB Clock output generated form System USB . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_USBCLKSOURCE_PLL:      /* PLL is used as clock source for USB*/
+        /* Enable USB Clock output generated form System USB . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* USB clock source configuration done later after clock selection check */
-      break;
+        /* USB clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
+      case RCC_USBCLKSOURCE_PLL3: /* PLL3 is used as clock source for USB*/
 
-      ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_Q_UPDATE);
+        ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
 
-      /* USB clock source configuration done later after clock selection check */
-      break;
+        /* USB clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_USBCLKSOURCE_HSI48:
-      /* HSI48 oscillator is used as source of USB clock */
-      /* USB clock source configuration done later after clock selection check */
-      break;
+      case RCC_USBCLKSOURCE_HSI48:
+        /* HSI48 oscillator is used as source of USB clock */
+        /* USB clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of USB clock*/
       __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
@@ -1410,33 +1408,33 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*------------------------------------- SDMMC Configuration ------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
   {
     /* Check the parameters */
     assert_param(IS_RCC_SDMMC(PeriphClkInit->SdmmcClockSelection));
 
-    switch(PeriphClkInit->SdmmcClockSelection)
+    switch (PeriphClkInit->SdmmcClockSelection)
     {
-    case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
-      /* Enable SDMMC Clock output generated form System PLL . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_SDMMCCLKSOURCE_PLL:      /* PLL is used as clock source for SDMMC*/
+        /* Enable SDMMC Clock output generated form System PLL . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* SDMMC clock source configuration done later after clock selection check */
-      break;
+        /* SDMMC clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is used as clock source for SDMMC*/
 
-      ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_R_UPDATE);
+        ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
 
-      /* SDMMC clock source configuration done later after clock selection check */
-      break;
+        /* SDMMC clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of SDMMC clock*/
       __HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
@@ -1450,48 +1448,48 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(LTDC)
   /*-------------------------------------- LTDC Configuration -----------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
   {
-    if(RCCEx_PLL3_Config(&(PeriphClkInit->PLL3),DIVIDER_R_UPDATE)!=HAL_OK)
+    if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
     {
-      status=HAL_ERROR;
+      status = HAL_ERROR;
     }
   }
 #endif /* LTDC */
 
   /*------------------------------ RNG Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
   {
 
-    switch(PeriphClkInit->RngClockSelection)
+    switch (PeriphClkInit->RngClockSelection)
     {
-    case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
-      /* Enable RNG Clock output generated form System RNG . */
-      __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
+      case RCC_RNGCLKSOURCE_PLL:     /* PLL is used as clock source for RNG*/
+        /* Enable RNG Clock output generated form System RNG . */
+        __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
 
-      /* RNG clock source configuration done later after clock selection check */
-      break;
+        /* RNG clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
+      case RCC_RNGCLKSOURCE_LSE: /* LSE is used as clock source for RNG*/
 
-      /* RNG clock source configuration done later after clock selection check */
-      break;
+        /* RNG clock source configuration done later after clock selection check */
+        break;
 
-    case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
+      case RCC_RNGCLKSOURCE_LSI: /* LSI is used as clock source for RNG*/
 
-      /* RNG clock source configuration done later after clock selection check */
-      break;
-    case RCC_RNGCLKSOURCE_HSI48:
-      /* HSI48 oscillator is used as source of RNG clock */
-      /* RNG clock source configuration done later after clock selection check */
-      break;
+        /* RNG clock source configuration done later after clock selection check */
+        break;
+      case RCC_RNGCLKSOURCE_HSI48:
+        /* HSI48 oscillator is used as source of RNG clock */
+        /* RNG clock source configuration done later after clock selection check */
+        break;
 
-    default:
-      ret = HAL_ERROR;
-      break;
+      default:
+        ret = HAL_ERROR;
+        break;
     }
 
-    if(ret == HAL_OK)
+    if (ret == HAL_OK)
     {
       /* Set the source of RNG clock*/
       __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
@@ -1505,7 +1503,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*------------------------------ SWPMI1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
@@ -1515,7 +1513,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 #if defined(HRTIM1)
   /*------------------------------ HRTIM1 clock Configuration ----------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
@@ -1525,7 +1523,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 #endif  /*HRTIM1*/
   /*------------------------------ DFSDM1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
   {
     /* Check the parameters */
     assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
@@ -1536,7 +1534,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 
 #if defined(DFSDM2_BASE)
   /*------------------------------ DFSDM2 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
   {
     /* Check the parameters */
     assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
@@ -1547,7 +1545,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
 #endif  /* DFSDM2 */
 
   /*------------------------------------ TIM configuration --------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
   {
     /* Check the parameters */
     assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection));
@@ -1557,7 +1555,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*------------------------------------ CKPER configuration --------------------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
   {
     /* Check the parameters */
     assert_param(IS_RCC_CLKPSOURCE(PeriphClkInit->CkperClockSelection));
@@ -1567,7 +1565,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
   }
 
   /*------------------------------ CEC Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
   {
     /* Check the parameters */
     assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
@@ -1576,6 +1574,103 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClk
     __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
   }
 
+  /*---------------------------- PLL2 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
+    
+    if (ret == HAL_OK)
+    {
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    } 
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
+    
+    if (ret == HAL_OK)
+    {
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
+  {
+    ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
+    
+    if (ret == HAL_OK)
+    {
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  
+
+  /*---------------------------- PLL3 configuration -------------------------------*/
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
+  
+    if (ret == HAL_OK)
+    {
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
+    
+    if (ret == HAL_OK)
+    {
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    }
+  }
+  
+  
+  if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
+  {
+    ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
+    
+    if (ret == HAL_OK)
+    {
+      /*Nothing to do*/
+    }
+    else
+    {
+      /* set overall return value */
+      status = ret;
+    } 
+  }
+
   if (status == HAL_OK)
   {
     return HAL_OK;
@@ -1598,26 +1693,26 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
   /* Set all possible values for the extended clock type parameter------------*/
   PeriphClkInit->PeriphClockSelection =
-                 RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
-                 RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
-                 RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
-	         RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
-	         RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
-	         RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
-	         RCC_PERIPHCLK_CKPER;
+    RCC_PERIPHCLK_USART16 | RCC_PERIPHCLK_USART234578 | RCC_PERIPHCLK_LPUART1 |
+    RCC_PERIPHCLK_I2C4    | RCC_PERIPHCLK_LPTIM1      | RCC_PERIPHCLK_LPTIM2  | RCC_PERIPHCLK_LPTIM345 |
+    RCC_PERIPHCLK_SAI1    | RCC_PERIPHCLK_SPI123      | RCC_PERIPHCLK_SPI45   | RCC_PERIPHCLK_SPI6     |
+    RCC_PERIPHCLK_FDCAN   | RCC_PERIPHCLK_SDMMC       | RCC_PERIPHCLK_RNG     | RCC_PERIPHCLK_USB      |
+    RCC_PERIPHCLK_ADC     | RCC_PERIPHCLK_SWPMI1      | RCC_PERIPHCLK_DFSDM1  | RCC_PERIPHCLK_RTC      |
+    RCC_PERIPHCLK_CEC     | RCC_PERIPHCLK_FMC         | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_TIM      |
+    RCC_PERIPHCLK_CKPER;
 
 #if defined(I2C5)
-PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235;
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C1235;
 #else
-PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
+  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
 #endif /*I2C5*/
 #if defined(RCC_CDCCIP1R_SAI2ASEL)
   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2A;
 #endif /* RCC_CDCCIP1R_SAI2ASEL */
-#if defined(RCC_CDCCIP1R_SAI2BSEL)		 
+#if defined(RCC_CDCCIP1R_SAI2BSEL)
   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI2B;
 #endif /* RCC_CDCCIP1R_SAI2BSEL */
-#if defined(SAI3)	 
+#if defined(SAI3)
   PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI23;
 #endif /* SAI3 */
 #if defined(SAI4)
@@ -1644,20 +1739,20 @@ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
 #endif /* DSI */
 
   /* Get the PLL3 Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
-  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos)+ 1U;
-  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos)+ 1U;
-  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos)+ 1U;
-  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos)+ 1U;
+  PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
+  PeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1U;
+  PeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1U;
+  PeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1U;
+  PeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1U;
   PeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3RGE) >> RCC_PLLCFGR_PLL3RGE_Pos);
   PeriphClkInit->PLL3.PLL3VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL3VCOSEL) >> RCC_PLLCFGR_PLL3VCOSEL_Pos);
 
   /* Get the PLL2 Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> RCC_PLLCKSELR_DIVM2_Pos);
-  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos)+ 1U;
-  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos)+ 1U;
-  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos)+ 1U;
-  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos)+ 1U;
+  PeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
+  PeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1U;
+  PeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1U;
+  PeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1U;
+  PeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1U;
   PeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2RGE) >> RCC_PLLCFGR_PLL2RGE_Pos);
   PeriphClkInit->PLL2.PLL2VCOSEL = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLL2VCOSEL) >> RCC_PLLCFGR_PLL2VCOSEL_Pos);
 
@@ -1783,7 +1878,7 @@ PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C123;
   *
   *  (*) : Available on some STM32H7 lines only.
   */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk)
 {
   PLL1_ClocksTypeDef pll1_clocks;
   PLL2_ClocksTypeDef pll2_clocks;
@@ -1797,924 +1892,1004 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
   uint32_t srcclk;
 
   if (PeriphClk == RCC_PERIPHCLK_SAI1)
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
+
+    switch (saiclocksource)
     {
-
-      saiclocksource= __HAL_RCC_GET_SAI1_SOURCE();
-
-      switch (saiclocksource)
-      {
       case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
-           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
-           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
         }
-      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
-          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
-          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-          frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
-        {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-          if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
-        }
-
-      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      default :
+        else
         {
           frequency = 0;
-          break;
         }
+        break;
+      }
+      case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI1CLKSOURCE_CLKP: /* CKPER is the clock source for SAI1*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
+      case (RCC_SAI1CLKSOURCE_PIN): /* External clock is the clock source for SAI1 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+      default :
+      {
+        frequency = 0;
+        break;
       }
     }
+  }
 
 #if defined(SAI3)
   else if (PeriphClk == RCC_PERIPHCLK_SAI23)
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI23_SOURCE();
+
+    switch (saiclocksource)
     {
-
-      saiclocksource= __HAL_RCC_GET_SAI23_SOURCE();
-
-      switch (saiclocksource)
-      {
       case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
-          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
-          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-          frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
-        {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-          if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
-        }
-
-      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      default :
+        else
         {
           frequency = 0;
-          break;
         }
+        break;
+      }
+      case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI23CLKSOURCE_CLKP: /* CKPER is the clock source for SAI2/3 */
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
+      case (RCC_SAI23CLKSOURCE_PIN): /* External clock is the clock source for SAI2/3 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+      default :
+      {
+        frequency = 0;
+        break;
       }
     }
+  }
 #endif /* SAI3 */
 
 #if  defined(RCC_CDCCIP1R_SAI2ASEL)
 
-    else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
-    {
-      saiclocksource= __HAL_RCC_GET_SAI2A_SOURCE();
+  else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
+  {
+    saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE();
 
-      switch (saiclocksource)
-      {
+    switch (saiclocksource)
+    {
       case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
-          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
-          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-          frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
-        {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
-        }
-
-      case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-
-      default :
+        else
         {
           frequency = 0;
-          break;
         }
+        break;
+      }
+      case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
       }
 
+      case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A  */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI2ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI2A  */
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
+      case (RCC_SAI2ACLKSOURCE_PIN): /* External clock is the clock source for SAI2A */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+
+      default :
+      {
+        frequency = 0;
+        break;
+      }
     }
+
+  }
 #endif
 
 #if  defined(RCC_CDCCIP1R_SAI2BSEL_0)
   else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE();
+
+    switch (saiclocksource)
     {
-
-      saiclocksource= __HAL_RCC_GET_SAI2B_SOURCE();
-
-      switch (saiclocksource)
-      {
       case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
-          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
-          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-          frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
-        {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-          break;
-        }
-
-      case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-
-      default :
+        else
         {
           frequency = 0;
-          break;
         }
+        break;
+      }
+      case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_P_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_SAI2BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI2B*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+        break;
+      }
+
+      case (RCC_SAI2BCLKSOURCE_PIN): /* External clock is the clock source for SAI2B */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+
+      default :
+      {
+        frequency = 0;
+        break;
       }
     }
+  }
 #endif
 
 #if defined(SAI4)
   else if (PeriphClk == RCC_PERIPHCLK_SAI4A)
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI4A_SOURCE();
+
+    switch (saiclocksource)
     {
-
-      saiclocksource= __HAL_RCC_GET_SAI4A_SOURCE();
-
-      switch (saiclocksource)
-      {
       case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
           frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
 
       case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
         {
-          if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
           frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
 
       case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
         {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-          if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
         }
 
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
       case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
 
       default :
-        {
-          frequency = 0;
-          break;
-        }
+      {
+        frequency = 0;
+        break;
       }
     }
+  }
 
   else if (PeriphClk == RCC_PERIPHCLK_SAI4B)
+  {
+
+    saiclocksource = __HAL_RCC_GET_SAI4B_SOURCE();
+
+    switch (saiclocksource)
     {
-
-      saiclocksource= __HAL_RCC_GET_SAI4B_SOURCE();
-
-      switch (saiclocksource)
-      {
       case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
           frequency = pll2_clocks.PLL2_P_Frequency;
-          }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
 
       case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
           frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
 
       case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
         {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
         }
 
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
       case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
 
       default :
-        {
-          frequency = 0;
-          break;
-        }
+      {
+        frequency = 0;
+        break;
       }
     }
+  }
 #endif /*SAI4*/
   else if (PeriphClk == RCC_PERIPHCLK_SPI123)
-    {
-      /* Get SPI1/2/3 clock source */
-      srcclk= __HAL_RCC_GET_SPI123_SOURCE();
+  {
+    /* Get SPI1/2/3 clock source */
+    srcclk = __HAL_RCC_GET_SPI123_SOURCE();
 
-      switch (srcclk)
-      {
+    switch (srcclk)
+    {
       case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
           frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
 
       case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
           frequency = pll3_clocks.PLL3_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
 
       case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
         {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
         }
 
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
       case (RCC_SPI123CLKSOURCE_PIN): /* External clock is the clock source for I2S */
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
       default :
-        {
-          frequency = 0;
-          break;
-        }
+      {
+        frequency = 0;
+        break;
       }
     }
-  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI45)
+  {
+    /* Get SPI45 clock source */
+    srcclk = __HAL_RCC_GET_SPI45_SOURCE();
+    switch (srcclk)
     {
-      /* Get ADC clock source */
-      srcclk= __HAL_RCC_GET_ADC_SOURCE();
-
-      switch (srcclk)
+      case RCC_SPI45CLKSOURCE_PCLK2: /* CD/D2 PCLK2 is the clock source for SPI4/5 */
       {
-      case RCC_ADCCLKSOURCE_PLL2:
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
-          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_P_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-      case RCC_ADCCLKSOURCE_PLL3:
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
-          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-          frequency = pll3_clocks.PLL3_R_Frequency;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
-        }
-
-      case RCC_ADCCLKSOURCE_CLKP:
-        {
-
-          ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE();
-
-         if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
-          {
-            /* In Case the CKPER Source is HSI */
-            frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
-          {
-            /* In Case the CKPER Source is CSI */
-            frequency = CSI_VALUE;
-          }
-
-          else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
-          {
-            /* In Case the CKPER Source is HSE */
-            frequency = HSE_VALUE;
-          }
-
-          else
-          {
-            /* In Case the CKPER is disabled*/
-            frequency = 0;
-          }
-
-          break;
-        }
-
-      default :
-        {
-          frequency = 0;
-          break;
-        }
+        frequency = HAL_RCC_GetPCLK1Freq();
+        break;
       }
-    }
-  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
-    {
-      /* Get SDMMC clock source */
-      srcclk= __HAL_RCC_GET_SDMMC_SOURCE();
-
-      switch (srcclk)
+      case RCC_SPI45CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI45 */
       {
-      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
-          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
-          frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
-        }
-      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
-        {
-          if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
-          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_R_Frequency;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
-        }
-
-      default :
-        {
-          frequency = 0;
-          break;
-        }
-      }
-    }
-  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
-    {
-      /* Get SPI6 clock source */
-      srcclk= __HAL_RCC_GET_SPI6_SOURCE();
-
-      switch (srcclk)
-      {
-      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
-        {
-          frequency = HAL_RCCEx_GetD3PCLK1Freq();
-          break;
-        }
-      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
-        {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
           frequency = pll2_clocks.PLL2_Q_Frequency;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
         }
-      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI45CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
-         {
           HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
           frequency = pll3_clocks.PLL3_Q_Frequency;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
         }
-      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+        else
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
-         {
-          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-         }
-         else
-         {
           frequency = 0;
-         }
-          break;
         }
-      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+        break;
+      }
+      case RCC_SPI45CLKSOURCE_HSI: /* HSI is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+        {
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI45CLKSOURCE_CSI: /* CSI is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
-         {
           frequency = CSI_VALUE;
-         }
-         else
-         {
-           frequency = 0;
-         }
-          break;
         }
-      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI45CLKSOURCE_HSE: /* HSE is the clock source for SPI45 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
-         {
           frequency = HSE_VALUE;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
         }
-#if defined(RCC_SPI6CLKSOURCE_PIN)
-      case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
+        else
         {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
+          frequency = 0;
         }
-#endif /* RCC_SPI6CLKSOURCE_PIN */
+        break;
+      }
       default :
-        {
-          frequency = 0;
-          break;
-        }
+      {
+        frequency = 0;
+        break;
       }
     }
-  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
-    {
-      /* Get FDCAN clock source */
-      srcclk= __HAL_RCC_GET_FDCAN_SOURCE();
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_ADC)
+  {
+    /* Get ADC clock source */
+    srcclk = __HAL_RCC_GET_ADC_SOURCE();
 
-      switch (srcclk)
+    switch (srcclk)
+    {
+      case RCC_ADCCLKSOURCE_PLL2:
       {
-      case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
-         {
-          frequency = HSE_VALUE;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_P_Frequency;
         }
-      case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_ADCCLKSOURCE_PLL3:
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_R_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+
+      case RCC_ADCCLKSOURCE_CLKP:
+      {
+
+        ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
+
+        if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
+        {
+          /* In Case the CKPER Source is HSI */
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
+        {
+          /* In Case the CKPER Source is CSI */
+          frequency = CSI_VALUE;
+        }
+
+        else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
+        {
+          /* In Case the CKPER Source is HSE */
+          frequency = HSE_VALUE;
+        }
+
+        else
+        {
+          /* In Case the CKPER is disabled*/
+          frequency = 0;
+        }
+
+        break;
+      }
+
+      default :
+      {
+        frequency = 0;
+        break;
+      }
+    }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
+  {
+    /* Get SDMMC clock source */
+    srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
+
+    switch (srcclk)
+    {
+      case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
-         {
           HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
           frequency = pll1_clocks.PLL1_Q_Frequency;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
         }
-      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
         {
-         if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
-         {
           HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-          frequency = pll2_clocks.PLL2_Q_Frequency;
-         }
-         else
-         {
-          frequency = 0;
-         }
-          break;
+          frequency = pll2_clocks.PLL2_R_Frequency;
         }
-      default :
+        else
         {
           frequency = 0;
-          break;
         }
+        break;
+      }
+
+      default :
+      {
+        frequency = 0;
+        break;
       }
     }
-  else
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_SPI6)
+  {
+    /* Get SPI6 clock source */
+    srcclk = __HAL_RCC_GET_SPI6_SOURCE();
+
+    switch (srcclk)
     {
-      frequency = 0;
+      case RCC_SPI6CLKSOURCE_D3PCLK1: /* D3PCLK1 (PCLK4) is the clock source for SPI6 */
+      {
+        frequency = HAL_RCCEx_GetD3PCLK1Freq();
+        break;
+      }
+      case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
+        {
+          HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
+          frequency = pll3_clocks.PLL3_Q_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
+        {
+          frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
+        {
+          frequency = CSI_VALUE;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+        {
+          frequency = HSE_VALUE;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+#if defined(RCC_SPI6CLKSOURCE_PIN)
+      case RCC_SPI6CLKSOURCE_PIN: /* External clock is the clock source for SPI6 */
+      {
+        frequency = EXTERNAL_CLOCK_VALUE;
+        break;
+      }
+#endif /* RCC_SPI6CLKSOURCE_PIN */
+      default :
+      {
+        frequency = 0;
+        break;
+      }
     }
+  }
+  else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
+  {
+    /* Get FDCAN clock source */
+    srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
+
+    switch (srcclk)
+    {
+      case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
+        {
+          frequency = HSE_VALUE;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
+        {
+          HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
+          frequency = pll1_clocks.PLL1_Q_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */
+      {
+        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
+        {
+          HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
+          frequency = pll2_clocks.PLL2_Q_Frequency;
+        }
+        else
+        {
+          frequency = 0;
+        }
+        break;
+      }
+      default :
+      {
+        frequency = 0;
+        break;
+      }
+    }
+  }
+  else
+  {
+    frequency = 0;
+  }
 
   return frequency;
 }
@@ -2730,10 +2905,10 @@ uint32_t HAL_RCCEx_GetD1PCLK1Freq(void)
 {
 #if defined(RCC_D1CFGR_D1PPRE)
   /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE)>> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos] & 0x1FU));
 #else
-/* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE)>> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
+  /* Get HCLK source and Compute D1PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos] & 0x1FU));
 #endif
 }
 
@@ -2747,10 +2922,10 @@ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
 {
 #if defined(RCC_D3CFGR_D3PPRE)
   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE)>> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->D3CFGR & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos] & 0x1FU));
 #else
   /* Get HCLK source and Compute D3PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE)>> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
+  return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
 #endif
 }
 /**
@@ -2767,7 +2942,7 @@ uint32_t HAL_RCCEx_GetD3PCLK1Freq(void)
   * @param  PLL2_Clocks structure.
   * @retval None
   */
-void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
+void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks)
 {
   uint32_t  pllsource, pll2m,  pll2fracen, hsivalue;
   float_t fracn2, pll2vco;
@@ -2776,43 +2951,43 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
      PLL2xCLK = PLL2_VCO / PLL2x
   */
   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2)>> 12);
+  pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
   pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
-  fracn2 =(float_t)(uint32_t)(pll2fracen* ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2)>> 3));
+  fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
 
   if (pll2m != 0U)
   {
     switch (pllsource)
     {
 
-    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
 
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-      {
-        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-        pll2vco = ( (float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
-      }
-      else
-      {
-        pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
-      }
-      break;
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+          pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        }
+        else
+        {
+          pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
 
-    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
-      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
-      break;
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        break;
 
-    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
-      break;
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        break;
 
-    default:
-      pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2/(float_t)0x2000) +(float_t)1 );
-      break;
+      default:
+        pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
+        break;
     }
-    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >>9)  + (float_t)1 )) ;
-    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >>16) + (float_t)1 )) ;
-    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco/((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >>24) + (float_t)1 )) ;
+    PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9)  + (float_t)1)) ;
+    PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
+    PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
   }
   else
   {
@@ -2836,7 +3011,7 @@ void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks)
   * @param  PLL3_Clocks structure.
   * @retval None
   */
-void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
+void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks)
 {
   uint32_t pllsource, pll3m, pll3fracen, hsivalue;
   float_t fracn3, pll3vco;
@@ -2845,41 +3020,41 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
      PLL3xCLK = PLL3_VCO / PLLxR
   */
   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> 20)  ;
+  pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20)  ;
   pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
-  fracn3 = (float_t)(uint32_t)(pll3fracen* ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3)>> 3));
+  fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
 
   if (pll3m != 0U)
   {
     switch (pllsource)
     {
-    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
 
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-      {
-        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-        pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
-      }
-      else
-      {
-        pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
-      }
-      break;
-    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
-      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
-      break;
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+          pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        }
+        else
+        {
+          pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        break;
 
-    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
-      break;
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        break;
 
-    default:
-      pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3/(float_t)0x2000) +(float_t)1 );
-      break;
+      default:
+        pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
+        break;
     }
-    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >>9)  + (float_t)1 )) ;
-    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >>16) + (float_t)1 )) ;
-    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco/((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >>24) + (float_t)1 )) ;
+    PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9)  + (float_t)1)) ;
+    PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
+    PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
   }
   else
   {
@@ -2904,49 +3079,49 @@ void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks)
   * @param  PLL1_Clocks structure.
   * @retval None
   */
-void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
+void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks)
 {
   uint32_t pllsource, pll1m, pll1fracen, hsivalue;
   float_t fracn1, pll1vco;
 
   pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4);
+  pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
   pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
-  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+  fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
 
   if (pll1m != 0U)
   {
     switch (pllsource)
     {
 
-    case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
+      case RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
 
-      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
-      {
-        hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
-        pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-      }
-      else
-      {
-        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-      }
-      break;
-    case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
-      pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-      break;
+        if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
+        {
+          hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
+          pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        }
+        else
+        {
+          pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        }
+        break;
+      case RCC_PLLSOURCE_CSI:  /* CSI used as PLL clock source */
+        pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        break;
 
-    case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
-      pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-      break;
+      case RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
+        pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        break;
 
-    default:
-      pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-      break;
+      default:
+        pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
+        break;
     }
 
-    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9)  + (float_t)1 )) ;
-    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >>16) + (float_t)1 )) ;
-    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco/((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >>24) + (float_t)1 )) ;
+    PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9)  + (float_t)1)) ;
+    PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
+    PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
   }
   else
   {
@@ -2967,19 +3142,19 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks)
   */
 uint32_t HAL_RCCEx_GetD1SysClockFreq(void)
 {
-uint32_t common_system_clock;
+  uint32_t common_system_clock;
 
 #if defined(RCC_D1CFGR_D1CPRE)
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
 #else
-  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
+  common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
 #endif
 
   /* Update the SystemD2Clock global variable */
 #if defined(RCC_D1CFGR_HPRE)
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 #else
-  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
 #endif
 
 #if defined(DUAL_CORE) && defined(CORE_CM4)
@@ -3308,15 +3483,15 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
   /* Wait for CRS flag or time-out detection */
   do
   {
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
       {
         crsstatus = RCC_CRS_TIMEOUT;
       }
     }
     /* Check CRS SYNCOK flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
+    if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
     {
       /* CRS SYNC event OK */
       crsstatus |= RCC_CRS_SYNCOK;
@@ -3326,7 +3501,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
     }
 
     /* Check CRS SYNCWARN flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
+    if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
     {
       /* CRS SYNC warning */
       crsstatus |= RCC_CRS_SYNCWARN;
@@ -3336,7 +3511,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
     }
 
     /* Check CRS TRIM overflow flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
+    if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
     {
       /* CRS SYNC Error */
       crsstatus |= RCC_CRS_TRIMOVF;
@@ -3346,7 +3521,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
     }
 
     /* Check CRS Error flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
+    if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
     {
       /* CRS SYNC Error */
       crsstatus |= RCC_CRS_SYNCERR;
@@ -3356,7 +3531,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
     }
 
     /* Check CRS SYNC Missed flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
+    if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
     {
       /* CRS SYNC Missed */
       crsstatus |= RCC_CRS_SYNCMISS;
@@ -3366,12 +3541,13 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
     }
 
     /* Check CRS Expected SYNC flag  */
-    if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
+    if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
     {
       /* frequency error counter reached a zero value */
       __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
     }
-  } while(RCC_CRS_NONE == crsstatus);
+  }
+  while (RCC_CRS_NONE == crsstatus);
 
   return crsstatus;
 }
@@ -3388,7 +3564,7 @@ void HAL_RCCEx_CRS_IRQHandler(void)
   uint32_t itsources = READ_REG(CRS->CR);
 
   /* Check CRS SYNCOK flag  */
-  if(((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
+  if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U))
   {
     /* Clear CRS SYNC event OK flag */
     WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
@@ -3397,7 +3573,7 @@ void HAL_RCCEx_CRS_IRQHandler(void)
     HAL_RCCEx_CRS_SyncOkCallback();
   }
   /* Check CRS SYNCWARN flag  */
-  else if(((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
+  else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U))
   {
     /* Clear CRS SYNCWARN flag */
     WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
@@ -3406,7 +3582,7 @@ void HAL_RCCEx_CRS_IRQHandler(void)
     HAL_RCCEx_CRS_SyncWarnCallback();
   }
   /* Check CRS Expected SYNC flag  */
-  else if(((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
+  else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U))
   {
     /* frequency error counter reached a zero value */
     WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
@@ -3417,17 +3593,17 @@ void HAL_RCCEx_CRS_IRQHandler(void)
   /* Check CRS Error flags  */
   else
   {
-    if(((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
+    if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U))
     {
-      if((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
+      if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U)
       {
         crserror |= RCC_CRS_SYNCERR;
       }
-      if((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
+      if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U)
       {
         crserror |= RCC_CRS_SYNCMISS;
       }
-      if((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
+      if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U)
       {
         crserror |= RCC_CRS_TRIMOVF;
       }
@@ -3529,7 +3705,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D
   assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
 
   /* Check that PLL2 OSC clock source is already set */
-  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
   {
     return HAL_ERROR;
   }
@@ -3544,9 +3720,9 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D
     tickstart = HAL_GetTick();
 
     /* Wait till PLL is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
     {
-      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }
@@ -3575,11 +3751,11 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D
     __HAL_RCC_PLL2FRACN_ENABLE();
 
     /* Enable the PLL2 clock output */
-    if(Divider == DIVIDER_P_UPDATE)
+    if (Divider == DIVIDER_P_UPDATE)
     {
       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
     }
-    else if(Divider == DIVIDER_Q_UPDATE)
+    else if (Divider == DIVIDER_Q_UPDATE)
     {
       __HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
     }
@@ -3595,9 +3771,9 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t D
     tickstart = HAL_GetTick();
 
     /* Wait till PLL2 is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
     {
-      if( (HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }
@@ -3633,7 +3809,7 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
   assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
 
   /* Check that PLL3 OSC clock source is already set */
-  if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
+  if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
   {
     return HAL_ERROR;
   }
@@ -3647,9 +3823,9 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
     /* Get Start Tick*/
     tickstart = HAL_GetTick();
     /* Wait till PLL3 is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
     {
-      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }
@@ -3678,11 +3854,11 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
     __HAL_RCC_PLL3FRACN_ENABLE();
 
     /* Enable the PLL3 clock output */
-    if(Divider == DIVIDER_P_UPDATE)
+    if (Divider == DIVIDER_P_UPDATE)
     {
       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
     }
-    else if(Divider == DIVIDER_Q_UPDATE)
+    else if (Divider == DIVIDER_Q_UPDATE)
     {
       __HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
     }
@@ -3698,9 +3874,9 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
     tickstart = HAL_GetTick();
 
     /* Wait till PLL3 is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
+    while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
     {
-      if( (HAL_GetTick() - tickstart ) > PLL3_TIMEOUT_VALUE)
+      if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
       {
         return HAL_TIMEOUT;
       }
@@ -3719,7 +3895,7 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
 void HAL_RCCEx_LSECSS_IRQHandler(void)
 {
   /* Check RCC LSE CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
+  if (__HAL_RCC_GET_IT(RCC_IT_LSECSS))
   {
 
     /* Clear RCC LSE CSS pending bit */
@@ -3757,4 +3933,3 @@ __weak void HAL_RCCEx_LSECSS_Callback(void)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h
index a08e3dba5f..2fb1fd2906 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h
@@ -6,14 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -22,7 +20,7 @@
 #define STM32H7xx_HAL_RCC_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -53,7 +51,7 @@ typedef struct
   uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
                              This parameter must be a number between Min_Data = 4 and Max_Data = 512
                              or between Min_Data = 8 and Max_Data = 420(*)
-                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */   
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */
 
   uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.
                              This parameter must be a number between Min_Data = 2 and Max_Data = 128
@@ -71,7 +69,7 @@ typedef struct
 
   uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
                             PLL2 VCO It should be a value between 0 and 8191                           */
-}RCC_PLL2InitTypeDef;
+} RCC_PLL2InitTypeDef;
 
 /**
   * @brief  PLL3 Clock structure definition
@@ -85,7 +83,7 @@ typedef struct
   uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
                              This parameter must be a number between Min_Data = 4 and Max_Data = 512
                              or between Min_Data = 8 and Max_Data = 420(*)
-                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */  
+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */
 
   uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.
                              This parameter must be a number between Min_Data = 2 and Max_Data = 128
@@ -103,7 +101,7 @@ typedef struct
 
   uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
                             PLL3 VCO It should be a value between 0 and 8191                           */
-}RCC_PLL3InitTypeDef;
+} RCC_PLL3InitTypeDef;
 
 /**
   * @brief  RCC PLL1 Clocks structure definition
@@ -113,7 +111,7 @@ typedef struct
   uint32_t PLL1_P_Frequency;
   uint32_t PLL1_Q_Frequency;
   uint32_t PLL1_R_Frequency;
-}PLL1_ClocksTypeDef;
+} PLL1_ClocksTypeDef;
 
 /**
   * @brief  RCC PLL2 Clocks structure definition
@@ -123,7 +121,7 @@ typedef struct
   uint32_t PLL2_P_Frequency;
   uint32_t PLL2_Q_Frequency;
   uint32_t PLL2_R_Frequency;
-}PLL2_ClocksTypeDef;
+} PLL2_ClocksTypeDef;
 
 /**
   * @brief  RCC PLL3 Clocks structure definition
@@ -133,7 +131,7 @@ typedef struct
   uint32_t PLL3_P_Frequency;
   uint32_t PLL3_Q_Frequency;
   uint32_t PLL3_R_Frequency;
-}PLL3_ClocksTypeDef;
+} PLL3_ClocksTypeDef;
 
 
 /**
@@ -141,7 +139,7 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+  uint64_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
 
   RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.
@@ -224,14 +222,14 @@ typedef struct
   uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source
                                         This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */
 
-   uint32_t RngClockSelection;      /*!< Specifies RNG clock source
+  uint32_t RngClockSelection;      /*!< Specifies RNG clock source
                                         This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */
 
 #if defined(I2C5)
-   uint32_t I2c1235ClockSelection;  /*!< Specifies I2C1/2/3/5 clock source
+  uint32_t I2c1235ClockSelection;  /*!< Specifies I2C1/2/3/5 clock source
                                         This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source    */
-#else 
-   uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
+#else
+  uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source
                                         This parameter can be a value of @ref RCCEx_I2C1235_Clock_Source    */
 #endif /*I2C5*/
 
@@ -279,7 +277,7 @@ typedef struct
 
   uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.
                                        This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
+} RCC_PeriphCLKInitTypeDef;
 
 /*!< Alias for Inter STM32H7 lines compatibility regarding RCC_PeriphCLKInitTypeDef field : I2C5 available on some lines only  */
 #if defined(I2C5)
@@ -313,7 +311,7 @@ typedef struct
   uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
                                      This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
 
-}RCC_CRSInitTypeDef;
+} RCC_CRSInitTypeDef;
 
 /**
   * @brief RCC_CRS Synchronization structure definition
@@ -335,7 +333,7 @@ typedef struct
                                                                     It shows whether the actual frequency is below or above the target.
                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
 
-}RCC_CRSSynchroInfoTypeDef;
+} RCC_CRSSynchroInfoTypeDef;
 
 /**
   * @}
@@ -352,7 +350,7 @@ typedef struct
   */
 
 #if defined(UART9) && defined(USART10)
-#define RCC_PERIPHCLK_USART16910       (0x00000001U)
+#define RCC_PERIPHCLK_USART16910       ((uint64_t)(0x00000001U))
 #define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910
 #define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910
 #define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910
@@ -360,40 +358,40 @@ typedef struct
 /*alias*/
 #define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910
 #else
-#define RCC_PERIPHCLK_USART16          (0x00000001U)
+#define RCC_PERIPHCLK_USART16          ((uint64_t)(0x00000001U))
 #define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16
 #define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16
 /* alias */
 #define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16
 #endif /* UART9 && USART10*/
-#define RCC_PERIPHCLK_USART234578      (0x00000002U)
+#define RCC_PERIPHCLK_USART234578      ((uint64_t)(0x00000002U))
 #define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578
 #define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578
 #define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578
 #define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578
 #define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578
 #define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578
-#define RCC_PERIPHCLK_LPUART1          (0x00000004U)
+#define RCC_PERIPHCLK_LPUART1          ((uint64_t)(0x00000004U))
 #if defined(I2C5)
-#define RCC_PERIPHCLK_I2C1235          (0x00000008U)
+#define RCC_PERIPHCLK_I2C1235          ((uint64_t)(0x00000008U))
 #define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C1235
 #define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C1235
 #define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C1235
 /* alias */
 #define RCC_PERIPHCLK_I2C123           RCC_PERIPHCLK_I2C1235
 #else
-#define RCC_PERIPHCLK_I2C123           (0x00000008U)
+#define RCC_PERIPHCLK_I2C123           ((uint64_t)(0x00000008U))
 #define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123
 #define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123
 #define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123
 #endif /*I2C5*/
-#define RCC_PERIPHCLK_I2C4             (0x00000010U)
+#define RCC_PERIPHCLK_I2C4             ((uint64_t)(0x00000010U))
 #if defined(I2C5)
 #define RCC_PERIPHCLK_I2C5             RCC_PERIPHCLK_I2C1235
 #endif /*I2C5*/
-#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)
-#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)
-#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)
+#define RCC_PERIPHCLK_LPTIM1           ((uint64_t)(0x00000020U))
+#define RCC_PERIPHCLK_LPTIM2           ((uint64_t)(0x00000040U))
+#define RCC_PERIPHCLK_LPTIM345         ((uint64_t)(0x00000080U))
 #define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345
 #if defined(LPTIM4)
 #define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345
@@ -401,59 +399,66 @@ typedef struct
 #if defined(LPTIM5)
 #define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345
 #endif /*LPTIM5*/
-#define RCC_PERIPHCLK_SAI1             (0x00000100U)
+#define RCC_PERIPHCLK_SAI1             ((uint64_t)(0x00000100U))
 #if defined(SAI3)
-#define RCC_PERIPHCLK_SAI23            (0x00000200U)
+#define RCC_PERIPHCLK_SAI23            ((uint64_t)(0x00000200U))
 #define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23
 #define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23
 #endif /* SAI3 */
 #if defined(RCC_CDCCIP1R_SAI2ASEL_0)
-#define RCC_PERIPHCLK_SAI2A            (0x00000200U)
+#define RCC_PERIPHCLK_SAI2A            ((uint64_t)(0x00000200U))
 #endif /* RCC_CDCCIP1R_SAI2ASEL_0 */
 #if defined(RCC_CDCCIP1R_SAI2BSEL_0)
-#define RCC_PERIPHCLK_SAI2B            (0x00000400U)
+#define RCC_PERIPHCLK_SAI2B            ((uint64_t)(0x00000400U))
 #endif /* RCC_CDCCIP1R_SAI2BSEL_0 */
 #if defined(SAI4)
-#define RCC_PERIPHCLK_SAI4A            (0x00000400U)
-#define RCC_PERIPHCLK_SAI4B            (0x00000800U)
+#define RCC_PERIPHCLK_SAI4A            ((uint64_t)(0x00000400U))
+#define RCC_PERIPHCLK_SAI4B            ((uint64_t)(0x00000800U))
 #endif /* SAI4 */
-#define RCC_PERIPHCLK_SPI123           (0x00001000U)
+#define RCC_PERIPHCLK_SPI123           ((uint64_t)(0x00001000U))
 #define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123
 #define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123
 #define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123
-#define RCC_PERIPHCLK_SPI45            (0x00002000U)
+#define RCC_PERIPHCLK_SPI45            ((uint64_t)(0x00002000U))
 #define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45
 #define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45
-#define RCC_PERIPHCLK_SPI6             (0x00004000U)
-#define RCC_PERIPHCLK_FDCAN            (0x00008000U)
-#define RCC_PERIPHCLK_SDMMC            (0x00010000U)
-#define RCC_PERIPHCLK_RNG              (0x00020000U)
-#define RCC_PERIPHCLK_USB              (0x00040000U)
-#define RCC_PERIPHCLK_ADC              (0x00080000U)
-#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)
-#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)
+#define RCC_PERIPHCLK_SPI6             ((uint64_t)(0x00004000U))
+#define RCC_PERIPHCLK_FDCAN            ((uint64_t)(0x00008000U))
+#define RCC_PERIPHCLK_SDMMC            ((uint64_t)(0x00010000U))
+#define RCC_PERIPHCLK_RNG              ((uint64_t)(0x00020000U))
+#define RCC_PERIPHCLK_USB              ((uint64_t)(0x00040000U))
+#define RCC_PERIPHCLK_ADC              ((uint64_t)(0x00080000U))
+#define RCC_PERIPHCLK_SWPMI1           ((uint64_t)(0x00100000U))
+#define RCC_PERIPHCLK_DFSDM1           ((uint64_t)(0x00200000U))
 #if defined(DFSDM2_BASE)
-#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)
+#define RCC_PERIPHCLK_DFSDM2           ((uint64_t)(0x00000800U))
 #endif /* DFSDM2 */
-#define RCC_PERIPHCLK_RTC              (0x00400000U)
-#define RCC_PERIPHCLK_CEC              (0x00800000U)
-#define RCC_PERIPHCLK_FMC              (0x01000000U)
+#define RCC_PERIPHCLK_RTC              ((uint64_t)(0x00400000U))
+#define RCC_PERIPHCLK_CEC              ((uint64_t)(0x00800000U))
+#define RCC_PERIPHCLK_FMC              ((uint64_t)(0x01000000U))
 #if defined(QUADSPI)
-#define RCC_PERIPHCLK_QSPI             (0x02000000U)
+#define RCC_PERIPHCLK_QSPI             ((uint64_t)(0x02000000U))
 #endif /* QUADSPI */
 #if defined(OCTOSPI1) || defined(OCTOSPI2)
-#define RCC_PERIPHCLK_OSPI             (0x02000000U)
+#define RCC_PERIPHCLK_OSPI             ((uint64_t)(0x02000000U))
 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
-#define RCC_PERIPHCLK_DSI              (0x04000000U)
-#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)
+#define RCC_PERIPHCLK_DSI              ((uint64_t)(0x04000000U))
+#define RCC_PERIPHCLK_SPDIFRX          ((uint64_t)(0x08000000U))
 #if defined(HRTIM1)
-#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)
+#define RCC_PERIPHCLK_HRTIM1           ((uint64_t)(0x10000000U))
 #endif /* HRTIM1 */
 #if defined(LTDC)
-#define RCC_PERIPHCLK_LTDC             (0x20000000U)
+#define RCC_PERIPHCLK_LTDC             ((uint64_t)(0x20000000U))
 #endif /* LTDC */
-#define RCC_PERIPHCLK_TIM              (0x40000000U)
-#define RCC_PERIPHCLK_CKPER            (0x80000000U)
+#define RCC_PERIPHCLK_TIM              ((uint64_t)(0x40000000U))
+#define RCC_PERIPHCLK_CKPER            ((uint64_t)(0x80000000U))
+
+#define RCC_PERIPHCLK_PLL2_DIVP        ((uint64_t)(0x0000000100000000U))
+#define RCC_PERIPHCLK_PLL2_DIVQ        ((uint64_t)(0x0000000200000000U))
+#define RCC_PERIPHCLK_PLL2_DIVR        ((uint64_t)(0x0000000400000000U))
+#define RCC_PERIPHCLK_PLL3_DIVP        ((uint64_t)(0x0000000800000000U))
+#define RCC_PERIPHCLK_PLL3_DIVQ        ((uint64_t)(0x0000001000000000U))
+#define RCC_PERIPHCLK_PLL3_DIVR        ((uint64_t)(0x0000002000000000U))
 
 /**
   * @}
@@ -1025,9 +1030,9 @@ typedef struct
 #define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
 #define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2
 #define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
- /**
-  * @}
-  */
+/**
+ * @}
+ */
 #endif /* RCC_CDCCIP1R_SAI2ASEL */
 
 #if defined(RCC_CDCCIP1R_SAI2BSEL)
@@ -1109,18 +1114,18 @@ typedef struct
   * @{
   */
 #if defined(RCC_D2CCIP1R_SPI45SEL)
-#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)
-#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI45CLKSOURCE_D2PCLK2     (0x00000000U)
+#define RCC_SPI45CLKSOURCE_PCLK2        RCC_SPI45CLKSOURCE_D2PCLK2
 #define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0
 #define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1
 #define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
 #define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2
 #define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
 #else
-#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)
+#define RCC_SPI45CLKSOURCE_CDPCLK2     (0x00000000U)
 /* aliases */
-#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
-#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1
+#define RCC_SPI45CLKSOURCE_D2PCLK2      RCC_SPI45CLKSOURCE_CDPCLK2  /* D2PCLK2 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */
+#define RCC_SPI45CLKSOURCE_PCLK2        RCC_SPI45CLKSOURCE_CDPCLK2
 #define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0
 #define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1
 #define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
@@ -1134,7 +1139,7 @@ typedef struct
 /** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
   * @{
   */
-#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI4CLKSOURCE_D2PCLK2     RCC_SPI45CLKSOURCE_D2PCLK2
 #define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
 #define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
 #define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
@@ -1148,7 +1153,7 @@ typedef struct
 /** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
   * @{
   */
-#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1
+#define RCC_SPI5CLKSOURCE_D2PCLK2     RCC_SPI45CLKSOURCE_D2PCLK2
 #define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2
 #define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3
 #define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI
@@ -1974,7 +1979,7 @@ typedef struct
   *
   * @retval None
   */
- #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
+#define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
 
 /** @brief  Macro to select  the PLL3  reference frequency range.
   * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
@@ -3129,12 +3134,12 @@ typedef struct
 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
 #endif /* RCC_D3CCIPR_ADCSEL */
 
- /** @brief  Macro to configure the SWPMI1 clock
-  * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
-  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
-  */
+/** @brief  Macro to configure the SWPMI1 clock
+ * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.
+ *         This parameter can be one of the following values:
+ *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock
+ *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
+ */
 #if defined(RCC_D2CCIP1R_SWPSEL)
 #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
@@ -3154,12 +3159,12 @@ typedef struct
 #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
 #endif /* RCC_D2CCIP1R_SWPSEL */
 
- /** @brief  Macro to configure the DFSDM1 clock
-  * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
-  *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
-  */
+/** @brief  Macro to configure the DFSDM1 clock
+ * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.
+ *         This parameter can be one of the following values:
+ *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock
+ *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock
+ */
 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
                   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
@@ -3180,12 +3185,12 @@ typedef struct
 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
 
 #if defined(DFSDM2_BASE)
- /** @brief  Macro to configure the DFSDM2 clock
-  * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
-  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
-  */
+/** @brief  Macro to configure the DFSDM2 clock
+ * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.
+ *         This parameter can be one of the following values:
+ *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock
+ *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock
+ */
 #define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \
                   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))
 
@@ -3393,7 +3398,7 @@ typedef struct
   * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
   *         from system PCLK, PLL2, PLL3, OSC
   *          This parameter can be one of the following values:
-  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2
   *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
   *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
   *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
@@ -3411,7 +3416,7 @@ typedef struct
 
 /** @brief  Macro to get the SPI4/5 clock source.
   * @retval The clock source can be one of the following values:
-  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2
   *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2
   *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3
   *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI
@@ -3429,7 +3434,7 @@ typedef struct
   * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
   *         from system PCLK, PLL2, PLL3, OSC
   *          This parameter can be one of the following values:
-  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2
   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
@@ -3441,7 +3446,7 @@ typedef struct
 
 /** @brief  Macro to get the SPI4 clock source.
   * @retval The clock source can be one of the following values:
-  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2
   *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2
   *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3
   *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI
@@ -3455,7 +3460,7 @@ typedef struct
   * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
   *         from system PCLK, PLL2, PLL3, OSC
   *          This parameter can be one of the following values:
-  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2
   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
@@ -3467,7 +3472,7 @@ typedef struct
 
 /** @brief  Macro to get the SPI5 clock source.
   * @retval The clock source can be one of the following values:
-  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2
   *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2
   *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3
   *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI
@@ -3728,7 +3733,7 @@ typedef struct
   * @retval None.
   */
 #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
- 
+
 /**
   * @brief  Enable the specified CRS interrupts.
   * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
@@ -3833,9 +3838,9 @@ typedef struct
                                                  } \
                                                } while(0)
 
- /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
-  * @{
-  */
+/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
+ * @{
+ */
 /**
   * @brief  Enable the oscillator clock for frequency error counter.
   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
@@ -3886,22 +3891,22 @@ typedef struct
 
 
 /* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCCEx_Exported_Functions
-  * @{
-  */
+/** @addtogroup RCCEx_Exported_Functions
+ * @{
+ */
 
 /** @addtogroup RCCEx_Exported_Functions_Group1
   * @{
   */
 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk);
 uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
 uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
 uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
-void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
-void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
-void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
+void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks);
+void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks);
+void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks);
 /**
   * @}
   */
@@ -3949,7 +3954,7 @@ void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
   * @}
   */
 
- /* Private macros ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
   * @{
   */
@@ -4114,7 +4119,7 @@ void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
 #define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \
                                         ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \
                                         ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \
-                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_CSI))
 
 #if defined(I2C5)
 #define IS_RCC_I2C5CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C5CLKSOURCE_PLL3)   || \
@@ -4217,7 +4222,7 @@ void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
                 ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
 
 #define IS_RCC_SPI45CLK(__SOURCE__)   \
-               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \
+               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK2)  || \
                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \
                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \
                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \
@@ -4225,7 +4230,7 @@ void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
                 ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
 
 #define IS_RCC_SPI4CLK(__SOURCE__)   \
-               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \
+               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK2)  || \
                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \
                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \
                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \
@@ -4233,7 +4238,7 @@ void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
                 ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
 
 #define IS_RCC_SPI5CLK(__SOURCE__)   \
-               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \
+               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK2)|| \
                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \
                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \
                 ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \
@@ -4475,4 +4480,3 @@ void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
 
 #endif /* STM32H7xx_HAL_RCC_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c
index ff1cf102d9..ef602992f4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c
@@ -9,6 +9,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -31,8 +42,8 @@
     allows the user to configure dynamically the driver callbacks.
 
     [..]
-    Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
-    Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
+    Use Function HAL_RNG_RegisterCallback() to register a user callback.
+    Function HAL_RNG_RegisterCallback() allows to register following callbacks:
     (+) ErrorCallback             : RNG Error Callback.
     (+) MspInitCallback           : RNG MspInit.
     (+) MspDeInitCallback         : RNG MspDeInit.
@@ -40,9 +51,9 @@
     and a pointer to the user callback function.
 
     [..]
-    Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default
+    weak (overridden) function.
+    HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
     (+) ErrorCallback             : RNG Error Callback.
@@ -51,16 +62,16 @@
 
     [..]
     For specific callback ReadyDataCallback, use dedicated register callbacks:
-    respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
+    respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback().
 
     [..]
-    By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    example @ref HAL_RNG_ErrorCallback().
+    By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
+    all callbacks are set to the corresponding weak (overridden) functions:
+    example HAL_RNG_ErrorCallback().
     Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
-    and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
+    reset to the legacy weak (overridden) functions in the HAL_RNG_Init()
+    and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
     [..]
@@ -69,27 +80,16 @@
     in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
     MspInit/DeInit callbacks can be used during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
-    or @ref HAL_RNG_Init() function.
+    using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit()
+    or HAL_RNG_Init() function.
 
     [..]
     When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak (overridden) callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -213,7 +213,6 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
 
   /* Clock Error Detection Configuration when CONDRT bit is set to 1 */
   MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
-
 #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
   /*!< magic number must be written immediately before to RNG_HTCRG */
   WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
@@ -232,9 +231,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
   {
     if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
     {
-      hrng->State = HAL_RNG_STATE_READY;
-      hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
-      return HAL_ERROR;
+      /* New check to avoid false timeout detection in case of preemption */
+      if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+        return HAL_ERROR;
+      }
     }
   }
 #else
@@ -258,9 +261,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
   {
     if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
     {
-      hrng->State = HAL_RNG_STATE_ERROR;
-      hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
-      return HAL_ERROR;
+      /* New check to avoid false timeout detection in case of preemption */
+      if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET)
+      {
+        hrng->State = HAL_RNG_STATE_ERROR;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+        return HAL_ERROR;
+      }
     }
   }
 
@@ -307,11 +314,15 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
   {
     if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
     {
-      hrng->State = HAL_RNG_STATE_READY;
-      hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrng);
-      return HAL_ERROR;
+      /* New check to avoid false timeout detection in case of preemption */
+      if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+      {
+        hrng->State = HAL_RNG_STATE_READY;
+        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+        return HAL_ERROR;
+      }
     }
   }
 
@@ -405,8 +416,6 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
     hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hrng);
 
   if (HAL_RNG_STATE_READY == hrng->State)
   {
@@ -460,14 +469,12 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
   return status;
 }
 
 /**
   * @brief  Unregister an RNG Callback
-  *         RNG callabck is redirected to the weak predefined callback
+  *         RNG callback is redirected to the weak predefined callback
   * @param  hrng RNG handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -480,8 +487,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hrng);
 
   if (HAL_RNG_STATE_READY == hrng->State)
   {
@@ -535,8 +540,6 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hrng);
   return status;
 }
 
@@ -683,11 +686,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
     {
       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
       {
-        hrng->State = HAL_RNG_STATE_READY;
-        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrng);
-        return HAL_ERROR;
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+        {
+          hrng->State = HAL_RNG_STATE_READY;
+          hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+          /* Process Unlocked */
+          __HAL_UNLOCK(hrng);
+          return HAL_ERROR;
+        }
       }
     }
 
@@ -698,10 +705,9 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
        be used as it may not have enough entropy */
     if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
     {
-      /* Update the error code */
+      /* Update the error code and status */
       hrng->ErrorCode = HAL_RNG_ERROR_SEED;
-      /* Clear bit DRDY */
-      CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
+      status = HAL_ERROR;
     }
     else /* No seed error */
     {
@@ -783,18 +789,19 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
 {
   uint32_t rngclockerror = 0U;
+  uint32_t itflag   = hrng->Instance->SR;
 
   /* RNG clock error interrupt occurred */
-  if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
+  if ((itflag & RNG_IT_CEI) == RNG_IT_CEI)
   {
     /* Update the error code */
     hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
     rngclockerror = 1U;
   }
-  else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+  else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI)
   {
     /* Check if Seed Error Current Status (SECS) is set */
-    if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+    if ((itflag & RNG_FLAG_SECS) != RNG_FLAG_SECS)
     {
       /* RNG IP performed the reset automatically (auto-reset) */
       /* Clear bit SEIS */
@@ -834,7 +841,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
   }
 
   /* Check RNG data ready interrupt occurred */
-  if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+  if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY)
   {
     /* Generate random number once, so disable the IT */
     __HAL_RNG_DISABLE_IT(hrng);
@@ -866,7 +873,7 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
   *                the configuration information for RNG.
   * @retval random value
   */
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng)
 {
   return (hrng->RandomNumber);
 }
@@ -933,7 +940,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
   *                the configuration information for RNG.
   * @retval HAL state
   */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng)
 {
   return hrng->State;
 }
@@ -943,7 +950,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
   * @param  hrng: pointer to a RNG_HandleTypeDef structure.
   * @retval RNG Error Code
   */
-uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
+uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng)
 {
   /* Return RNG Error Code */
   return hrng->ErrorCode;
@@ -1004,8 +1011,7 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
         return HAL_ERROR;
       }
-    }
-    while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
+    } while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
 
     if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
     {
@@ -1033,8 +1039,7 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
         return HAL_ERROR;
       }
-    }
-    while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
+    } while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
   }
   /* Update the error code */
   hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED;
@@ -1058,4 +1063,3 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h
index fc4de1ae8c..e7dd55a1e1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -320,7 +319,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
   */
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
 HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng);
 
 void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
 void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
@@ -333,8 +332,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
 /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
   * @{
   */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
+HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng);
+uint32_t             HAL_RNG_GetError(const RNG_HandleTypeDef *hrng);
 /**
   * @}
   */
@@ -392,4 +391,3 @@ HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
 
 #endif /* STM32H7xx_HAL_RNG_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c
index 4377a04088..70c5540524 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c
@@ -11,13 +11,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -31,7 +30,7 @@
 
 #if defined(RNG)
 
-/** @addtogroup RNGEx
+/** @addtogroup RNG_Ex
   * @brief RNG Extended HAL module driver.
   * @{
   */
@@ -40,7 +39,7 @@
 #if defined(RNG_CR_CONDRST)
 /* Private types -------------------------------------------------------------*/
 /* Private defines -----------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Defines RNGEx Private Defines
+/** @defgroup RNG_Ex_Private_Defines RNGEx Private Defines
   * @{
   */
 /*  Health test control register information to use in CCM algorithm */
@@ -55,7 +54,7 @@
   */
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+/** @addtogroup RNG_Ex_Private_Constants
   * @{
   */
 #define RNG_TIMEOUT_VALUE     2U
@@ -67,11 +66,11 @@
 /* Private functions  --------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 
-/** @addtogroup RNGEx_Exported_Functions
+/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
   * @{
   */
 
-/** @addtogroup RNGEx_Exported_Functions_Group1
+/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions
   *  @brief   Configuration functions
   *
 @verbatim
@@ -91,12 +90,12 @@
   *         RNG_ConfigTypeDef.
   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *          the configuration information for RNG.
-  * @param  pConf: pointer to a RNG_ConfigTypeDef structure that contains
+  * @param  pConf pointer to a RNG_ConfigTypeDef structure that contains
   *         the configuration information for RNG module
 
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf)
 {
   uint32_t tickstart;
   uint32_t cr_value;
@@ -156,9 +155,13 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef
     {
       if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
       {
-        hrng->State = HAL_RNG_STATE_READY;
-        hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
-        return HAL_ERROR;
+        /* New check to avoid false timeout detection in case of prememption */
+        if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+        {
+          hrng->State = HAL_RNG_STATE_READY;
+          hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+          return HAL_ERROR;
+        }
       }
     }
 
@@ -186,7 +189,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef
   *         RNG_ConfigTypeDef.
   * @param  hrng pointer to a RNG_HandleTypeDef structure that contains
   *          the configuration information for RNG.
-  * @param  pConf: pointer to a RNG_ConfigTypeDef structure that contains
+  * @param  pConf pointer to a RNG_ConfigTypeDef structure that contains
   *         the configuration information for RNG module
 
   * @retval HAL status
@@ -280,12 +283,12 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
   * @}
   */
 
-/** @addtogroup RNGEx_Exported_Functions_Group2
+/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function
   *  @brief   Recover from seed error function
   *
 @verbatim
  ===============================================================================
-          ##### Configuration and lock functions #####
+          ##### Recover from seed error function #####
  ===============================================================================
     [..]  This section provide function allowing to:
       (+) Recover from a seed error
@@ -348,4 +351,3 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h
index 1f7fc848bd..ee43ec107b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -35,19 +34,19 @@ extern "C" {
 #if defined(RNG)
 #if defined(RNG_CR_CONDRST)
 
-/** @defgroup RNGEx RNGEx
+/** @defgroup RNG_Ex RNG_Ex
   * @brief RNG Extension HAL module driver
   * @{
   */
 
 /* Exported types ------------------------------------------------------------*/
-/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
-  * @brief RNGEx Exported types
+/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
+  * @brief RNG_Ex Exported types
   * @{
   */
 
 /**
-  * @brief RNGEX Configuration Structure definition
+  * @brief RNG_Ex Configuration Structure definition
   */
 
 typedef struct
@@ -56,9 +55,9 @@ typedef struct
   uint32_t        Config2;           /*!< Config2 must be a value between 0 and 0x7 */
   uint32_t        Config3;           /*!< Config3 must be a value between 0 and 0xF */
   uint32_t        ClockDivider;      /*!< Clock Divider factor.This parameter can
-                                          be a value of @ref RNGEX_Clock_Divider_Factor   */
+                                          be a value of @ref RNG_Ex_Clock_Divider_Factor   */
   uint32_t        NistCompliance;    /*!< NIST compliance.This parameter can be a
-                                          value of @ref RNGEX_NIST_Compliance   */
+                                          value of @ref RNG_Ex_NIST_Compliance   */
 } RNG_ConfigTypeDef;
 
 /**
@@ -66,11 +65,11 @@ typedef struct
   */
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants
+/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
   * @{
   */
 
-/** @defgroup RNGEX_Clock_Divider_Factor  Value used to configure an internal
+/** @defgroup RNG_Ex_Clock_Divider_Factor  Value used to configure an internal
   *            programmable divider acting on the incoming RNG clock
   * @{
   */
@@ -109,7 +108,7 @@ typedef struct
   * @}
   */
 
-/** @defgroup RNGEX_NIST_Compliance  NIST Compliance configuration
+/** @defgroup RNG_Ex_NIST_Compliance  NIST Compliance configuration
   * @{
   */
 #define RNG_NIST_COMPLIANT     (0x00000000UL) /*!< NIST compliant configuration*/
@@ -124,7 +123,7 @@ typedef struct
   */
 
 /* Private types -------------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Types RNGEx Private Types
+/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
   * @{
   */
 
@@ -133,7 +132,7 @@ typedef struct
   */
 
 /* Private variables ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
+/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
   * @{
   */
 
@@ -142,7 +141,7 @@ typedef struct
   */
 
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
   * @{
   */
 
@@ -151,7 +150,7 @@ typedef struct
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
+/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
   * @{
   */
 
@@ -188,7 +187,7 @@ typedef struct
   */
 
 /* Private functions ---------------------------------------------------------*/
-/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
+/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
   * @{
   */
 
@@ -197,14 +196,14 @@ typedef struct
   */
 
 /* Exported functions --------------------------------------------------------*/
-/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
+/** @addtogroup RNG_Ex_Exported_Functions
   * @{
   */
 
-/** @addtogroup RNGEx_Exported_Functions_Group1
+/** @addtogroup RNG_Ex_Exported_Functions_Group1
   * @{
   */
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf);
 HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
 HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
 
@@ -212,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
   * @}
   */
 
-/** @addtogroup RNGEx_Exported_Functions_Group2
+/** @addtogroup RNG_Ex_Exported_Functions_Group2
   * @{
   */
 HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
@@ -245,6 +244,5 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
 #endif
 
 
-#endif /* STM32H7xx_HAL_RNGEX_H */
+#endif /* STM32H7xx_HAL_RNG_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.c
index b158d38e3c..140826c0fd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.c
@@ -15,6 +15,17 @@
   *           + RTC Tamper and TimeStamp Pins Selection
   *           + Interrupts and flags management
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                           ##### RTC Operating Condition #####
@@ -93,9 +104,9 @@
 
   The compilation define  USE_RTC_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
-  Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
+  Use Function HAL_RTC_RegisterCallback() to register an interrupt callback.
 
-  Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
+  Function HAL_RTC_RegisterCallback() allows to register following callbacks:
     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
     (+) AlarmBEventCallback          : RTC Alarm B Event callback.
     (+) TimeStampEventCallback       : RTC TimeStamp Event callback.
@@ -108,9 +119,9 @@
   This function takes as parameters the HAL peripheral handle, the Callback ID
   and a pointer to the user callback function.
 
-  Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
+  Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default
   weak function.
-  @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+  HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
   and the Callback ID.
   This function allows to reset following callbacks:
     (+) AlarmAEventCallback          : RTC Alarm A Event callback.
@@ -123,13 +134,13 @@
     (+) MspInitCallback              : RTC MspInit callback.
     (+) MspDeInitCallback            : RTC MspDeInit callback.
 
-  By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
+  By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
   all callbacks are set to the corresponding weak functions :
-  examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
+  examples AlarmAEventCallback(), WakeUpTimerEventCallback().
   Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function
-  in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null
+  in the HAL_RTC_Init()/HAL_RTC_DeInit() only when these callbacks are null
   (not registered beforehand).
-  If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
+  If not, MspInit or MspDeInit are not null, HAL_RTC_Init()/HAL_RTC_DeInit()
   keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
   Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
@@ -137,26 +148,14 @@
   in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
   thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-  using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
-  or @ref HAL_RTC_Init() function.
+  using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit()
+  or HAL_RTC_Init() function.
 
   When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
   not defined, the callback registration feature is not available and all callbacks
   are set to the corresponding weak functions.
    @endverbatim
 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -240,9 +239,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
     assert_param(IS_RTC_OUTPUT_REMAP(hrtc->Init.OutPutRemap));
     assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
     assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-#if defined(RTC_CR_TAMPALRM_PU)
+#if defined(TAMP)
     assert_param(IS_RTC_OUTPUT_PULLUP(hrtc->Init.OutPutPullUp));
-#endif /* RTC_CR_TAMPALRM_PU */
+#endif /* TAMP */
 
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
     if(hrtc->State == HAL_RTC_STATE_RESET)
@@ -258,27 +257,15 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
       hrtc->Tamper2EventCallback         =  HAL_RTCEx_Tamper2EventCallback;          /* Legacy weak Tamper2EventCallback     */
       hrtc->Tamper3EventCallback         =  HAL_RTCEx_Tamper3EventCallback;          /* Legacy weak Tamper3EventCallback     */
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
       hrtc->InternalTamper1EventCallback =  HAL_RTCEx_InternalTamper1EventCallback;
-#endif /* TAMP_CR1_ITAMP1E */
-#if defined(TAMP_CR1_ITAMP2E)
       hrtc->InternalTamper2EventCallback =  HAL_RTCEx_InternalTamper2EventCallback;
-#endif /* TAMP_CR1_ITAMP2E */
-#if defined(TAMP_CR1_ITAMP3E)
       hrtc->InternalTamper3EventCallback =  HAL_RTCEx_InternalTamper3EventCallback;
-#endif /* TAMP_CR1_ITAMP3E */
-#if defined(TAMP_CR1_ITAMP4E)
       hrtc->InternalTamper4EventCallback =  HAL_RTCEx_InternalTamper4EventCallback;
-#endif /* TAMP_CR1_ITAMP4E */
-#if defined(TAMP_CR1_ITAMP5E)
       hrtc->InternalTamper5EventCallback =  HAL_RTCEx_InternalTamper5EventCallback;
-#endif /* TAMP_CR1_ITAMP5E */
-#if defined(TAMP_CR1_ITAMP6E)
       hrtc->InternalTamper6EventCallback =  HAL_RTCEx_InternalTamper6EventCallback;
-#endif /* TAMP_CR1_ITAMP6E */
-#if defined(TAMP_CR1_ITAMP8E)
       hrtc->InternalTamper8EventCallback =  HAL_RTCEx_InternalTamper8EventCallback;
-#endif /* TAMP_CR1_ITAMP8E */
+#endif /* TAMP */
 
 
       if(hrtc->MspInitCallback == NULL)
@@ -307,45 +294,53 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
     /* Set RTC state */
     hrtc->State = HAL_RTC_STATE_BUSY;
 
-    /* Disable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-   /* Enter Initialization mode */
-    status = RTC_EnterInitMode(hrtc);
-    if (status == HAL_OK)
+    /* Check whether the calendar needs to be initialized */
+    if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
     {
-#if defined(RTC_CR_TAMPOE)
-      /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
-      hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
-#else  /* RTC_CR_TAMPOE */
-      /* Clear RTC_CR FMT, OSEL and POL Bits */
-      hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL);
-#endif /* RTC_CR_TAMPOE */
+      /* Disable the write protection for RTC registers */
+      __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
-      /* Set RTC_CR register */
-      hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+     /* Enter Initialization mode */
+      status = RTC_EnterInitMode(hrtc);
+      if (status == HAL_OK)
+      {
+#if defined(TAMP)
+        /* Clear RTC_CR FMT, OSEL, POL and TAMPOE Bits */
+        hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE);
+#else
+        /* Clear RTC_CR FMT, OSEL and POL Bits */
+        hrtc->Instance->CR &= ~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL);
+#endif /* TAMP */
 
-      /* Configure the RTC PRER */
-      hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos);
+        /* Set RTC_CR register */
+        hrtc->Instance->CR |= (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
 
-      /* Exit Initialization mode */
-      status = RTC_ExitInitMode(hrtc);
+        /* Configure the RTC PRER */
+        hrtc->Instance->PRER = (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos) | (hrtc->Init.SynchPrediv << RTC_PRER_PREDIV_S_Pos);
 
+        /* Exit Initialization mode */
+        status = RTC_ExitInitMode(hrtc);
+      }
       if(status == HAL_OK)
       {
-#if defined(RTC_CR_TAMPALRM_PU) && defined(RTC_CR_TAMPALRM_TYPE) && defined(RTC_CR_OUT2EN)
+#if defined(TAMP)
         hrtc->Instance->CR &= ~(RTC_CR_TAMPALRM_PU | RTC_CR_TAMPALRM_TYPE | RTC_CR_OUT2EN);
         hrtc->Instance->CR |= (hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-#endif /* RTC_CR_TAMPALRM_TYPE && RTC_CR_OUT2EN && RTC_CR_TAMPALRM_PU */
-
-#if defined(RTC_OR_ALARMOUTTYPE) && defined(RTC_OR_OUT_RMP)
+#else
         hrtc->Instance->OR &= ~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
         hrtc->Instance->OR |= (hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-#endif /* ALARMOUTTYPE && RTC_OR_OUT_RMP */
+#endif /* TAMP */
       }
-    }
+
     /* Enable the write protection for RTC registers */
     __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+    }
+    else
+    {
+      /* The calendar is already initialized */
+      status = HAL_OK;
+    }
+
     if (status == HAL_OK)
     {
       /* Set RTC state */
@@ -379,71 +374,75 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
 
     /* Disable the write protection for RTC registers */
     __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
+
     /* Enter Initialization mode */
     status = RTC_EnterInitMode(hrtc);
+
     if (status == HAL_OK)
     {
       /* Reset TR, DR and CR registers */
       hrtc->Instance->TR = 0x00000000U;
       hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
-      /* Reset All CR bits except CR[2:0] */
-      hrtc->Instance->CR &= RTC_CR_WUCKSEL;
 
+      /* Reset All CR bits except CR[2:0] (which cannot be written before bit
+           WUTE of CR is cleared) */
+      hrtc->Instance->CR = 0x00000000U;
+
+      /* Wait till WUTWF is set (to be able to reset CR[2:0] and WUTR) and if
+         timeout is reached exit */
       tickstart = HAL_GetTick();
 
-      /* Wait till WUTWF flag is set and if Time out is reached exit */
-#if defined(RTC_ICSR_WUTWF)
-      while (((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U)
-#endif /* RTC_ICSR_WUTWF */
-#if defined(RTC_ISR_WUTWF)
-        while (((hrtc->Instance->ISR)  & RTC_ISR_WUTWF)  == 0U)
-#endif /* RTC_ISR_WUTWF */
+#if defined(TAMP)
+      while ((((hrtc->Instance->ICSR) & RTC_ICSR_WUTWF) == 0U) && (status != HAL_TIMEOUT))
+#else
+      while ((((hrtc->Instance->ISR)  & RTC_ISR_WUTWF)  == 0U) && (status != HAL_TIMEOUT))
+#endif /* TAMP */
+      {
+        if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
         {
-          if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-          {
-            /* Enable the write protection for RTC registers */
-            __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+          /* Enable the write protection for RTC registers */
+          __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-            /* Set RTC state */
-            hrtc->State = HAL_RTC_STATE_TIMEOUT;
+          /* Set RTC state */
+          hrtc->State = HAL_RTC_STATE_TIMEOUT;
+          status = HAL_TIMEOUT;
 
-          }
         }
+      }
+    }
+
+    if (status == HAL_OK)
+    {
+      /* Reset RTC CR register bits [2:0] */
+      hrtc->Instance->CR = 0x00000000U;
+
+      /* Reset other RTC registers */
+      hrtc->Instance->WUTR     = RTC_WUTR_WUT;
+      hrtc->Instance->PRER     = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
+      hrtc->Instance->ALRMAR   = 0x00000000U;
+      hrtc->Instance->ALRMBR   = 0x00000000U;
+      hrtc->Instance->SHIFTR   = 0x00000000U;
+      hrtc->Instance->CALR     = 0x00000000U;
+      hrtc->Instance->ALRMASSR = 0x00000000U;
+      hrtc->Instance->ALRMBSSR = 0x00000000U;
 
       /* Exit initialization mode */
       status = RTC_ExitInitMode(hrtc);
-      if (status == HAL_OK)
-      {
-        /* Reset all RTC CR register bits */
-        hrtc->Instance->CR &= 0x00000000U;
-
-        /* Reset other RTC registers */
-        hrtc->Instance->WUTR = RTC_WUTR_WUT;
-        hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU));
-        hrtc->Instance->ALRMAR = 0x00000000U;
-        hrtc->Instance->ALRMBR = 0x00000000U;
-        hrtc->Instance->SHIFTR = 0x00000000U;
-        hrtc->Instance->CALR = 0x00000000U;
-        hrtc->Instance->ALRMASSR = 0x00000000U;
-        hrtc->Instance->ALRMBSSR = 0x00000000U;
-
-#if defined(RTC_ISR_INIT)
-        /* Reset Tamper configuration register */
-        hrtc->Instance->TAMPCR = 0x00000000U;
-
-        /* Reset Option register */
-        hrtc->Instance->OR = 0x00000000U;
-#endif /* RTC_ISR_INIT */
-      }
     }
 
     if(status == HAL_OK)
     {
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
       /* Reset TAMP registers */
       ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->CR1 = 0xFFFF0000U;
       ((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->CR2 = 0x00000000U;
-#endif /* TAMP_CR1_TAMP1E */
+#else
+      /* Reset Tamper configuration register */
+      hrtc->Instance->TAMPCR = 0x00000000U;
+
+      /* Reset Option register */
+      hrtc->Instance->OR = 0x00000000U;
+#endif /* TAMP */
 
       /* Enable the write protection for RTC registers */
       __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
@@ -542,47 +541,35 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
         hrtc->Tamper3EventCallback = pCallback;
         break;
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
       case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
         hrtc->InternalTamper1EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP1E */
 
-#if defined(TAMP_CR1_ITAMP2E)
       case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
         hrtc->InternalTamper2EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP2E */
 
-#if defined(TAMP_CR1_ITAMP3E)
       case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
         hrtc->InternalTamper3EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP3E */
 
-#if defined(TAMP_CR1_ITAMP4E)
       case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
         hrtc->InternalTamper4EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP4E */
 
-#if defined(TAMP_CR1_ITAMP5E)
       case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
         hrtc->InternalTamper5EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP5E */
 
-#if defined(TAMP_CR1_ITAMP6E)
       case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
         hrtc->InternalTamper6EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP6E */
 
-#if defined(TAMP_CR1_ITAMP8E)
       case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
         hrtc->InternalTamper8EventCallback =  pCallback;
         break;
-#endif /* TAMP_CR1_ITAMP8E */
+#endif /* TAMP */
 
       case HAL_RTC_MSPINIT_CB_ID :
         hrtc->MspInitCallback = pCallback;
@@ -630,7 +617,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
 
 /**
   * @brief  Unregister an RTC Callback
-  *         RTC callabck is redirected to the weak predefined callback
+  *         RTC callback is redirected to the weak predefined callback
   * @param  hrtc RTC handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -691,47 +678,35 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca
         hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback;         /* Legacy weak Tamper3EventCallback         */
         break;
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
       case HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID :
         hrtc->InternalTamper1EventCallback =  HAL_RTCEx_InternalTamper1EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP1E */
 
-#if defined(TAMP_CR1_ITAMP2E)
       case HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID :
         hrtc->InternalTamper2EventCallback =  HAL_RTCEx_InternalTamper2EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP2E */
 
-#if defined(TAMP_CR1_ITAMP3E)
       case HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID :
         hrtc->InternalTamper3EventCallback =  HAL_RTCEx_InternalTamper3EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP3E */
 
-#if defined(TAMP_CR1_ITAMP4E)
       case HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID :
         hrtc->InternalTamper4EventCallback =  HAL_RTCEx_InternalTamper4EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP4E */
 
-#if defined(TAMP_CR1_ITAMP5E)
       case HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID :
         hrtc->InternalTamper5EventCallback =  HAL_RTCEx_InternalTamper5EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP5E */
 
-#if defined(TAMP_CR1_ITAMP6E)
       case HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID :
         hrtc->InternalTamper6EventCallback =  HAL_RTCEx_InternalTamper6EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP6E */
 
-#if defined(TAMP_CR1_ITAMP8E)
       case HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID :
         hrtc->InternalTamper8EventCallback =  HAL_RTCEx_InternalTamper8EventCallback;
         break;
-#endif /* TAMP_CR1_ITAMP8E */
+#endif /* TAMP */
 
       case HAL_RTC_MSPINIT_CB_ID :
         hrtc->MspInitCallback = HAL_RTC_MspInit;
@@ -1233,13 +1208,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
 
     tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-  #if defined(RTC_ICSR_ALRAWF)
+    /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
-  #endif /* RTC_ICSR_ALRAWF */
-  #if defined(RTC_ISR_ALRAWF)
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-  #endif /* RTC_ISR_ALRAWF */
+#else
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+#endif /* TAMP */
     {
       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1271,13 +1245,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA
     __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
 
     tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-  #if defined(RTC_ICSR_ALRBWF)
+    /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U)
-  #endif /* RTC_ICSR_ALRBWF */
-  #if defined(RTC_ISR_ALRBWF)
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-  #endif /* RTC_ISR_ALRBWF */
+#else
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
+#endif /* TAMP */
     {
       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1425,13 +1398,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
 
     tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-  #if defined(RTC_ICSR_ALRAWF)
+    /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
-  #endif /* RTC_ICSR_ALRAWF */
-  #if defined(RTC_ISR_ALRAWF)
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-  #endif /* RTC_ISR_ALRAWF */
+#else
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+#endif /* TAMP */
     {
       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1464,13 +1436,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
 
     tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-#if defined(RTC_ICSR_ALRBWF)
+    /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U)
-#endif /* RTC_ICSR_ALRBWF */
-#if defined(RTC_ISR_ALRBWF)
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-#endif /* RTC_ISR_ALRBWF */
+#else
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
+#endif /* TAMP */
     {
       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1495,8 +1466,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
     __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
   }
 
-#if !defined(DUAL_CORE)
   /* RTC Alarm Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    __HAL_RTC_ALARM_EXTI_ENABLE_IT();
+  }
+  else
+  {
+    __HAL_RTC_ALARM_EXTID2_ENABLE_IT();
+  }
+#else  /* SINGLE_CORE */
   __HAL_RTC_ALARM_EXTI_ENABLE_IT();
 #endif
 
@@ -1547,13 +1527,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
 
     tickstart = HAL_GetTick();
 
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-#if defined(RTC_ICSR_ALRAWF)
+    /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRAWF) == 0U)
-#endif /* RTC_ICSR_ALRAWF */
-#if defined(RTC_ISR_ALRAWF)
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
-#endif /* RTC_ISR_ALRAWF */
+#else
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U)
+#endif /* TAMP */
     {
       if((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1579,13 +1558,12 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar
 
     tickstart = HAL_GetTick();
 
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-#if defined(RTC_ICSR_ALRBWF)
+    /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
     while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_ALRBWF) == 0U)
-#endif /* RTC_ICSR_ALRBWF */
-#if defined(RTC_ISR_ALRBWF)
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
-#endif /* RTC_ISR_ALRBWF */
+#else
+    while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U)
+#endif /* TAMP */
     {
       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1703,40 +1681,36 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
   __HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
 #endif /* DUAL_CORE */
 
-#if defined(RTC_MISR_ALRAMF)
+#if defined(TAMP)
   /* Get interrupt status */
   uint32_t tmp = hrtc->Instance->MISR;
 
-  if((tmp & RTC_MISR_ALRAMF) != 0u)
+  if((tmp & RTC_FLAG_ALRAF) != 0u)
   {
     /* Clear the AlarmA interrupt pending bit */
-    hrtc->Instance->SCR = RTC_SCR_CALRAF;
+    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
 
+    /* Call Alarm A Callback */
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Compare Match registered Callback */
     hrtc->AlarmAEventCallback(hrtc);
 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     HAL_RTC_AlarmAEventCallback(hrtc);
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
   }
-#endif /* RTC_MISR_ALRAMF */
 
-#if defined(RTC_MISR_ALRBMF)
   if((tmp & RTC_MISR_ALRBMF) != 0u)
   {
     /* Clear the AlarmB interrupt pending bit */
     hrtc->Instance->SCR = RTC_SCR_CALRBF;
 
+    /* Call Alarm B Callback */
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Compare Match registered Callback */
     hrtc->AlarmBEventCallback(hrtc);
 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     HAL_RTCEx_AlarmBEventCallback(hrtc);
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
   }
-#endif /* RTC_MISR_ALRBMF */
-
-#if defined(RTC_ISR_ALRAF)
+#else
   /* Get the AlarmA interrupt source enable status */
   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U)
   {
@@ -1753,9 +1727,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     }
   }
-#endif /* RTC_ISR_ALRAF */
 
-#if defined(RTC_ISR_ALRBF)
   /* Get the AlarmB interrupt source enable status */
   if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U)
   {
@@ -1773,7 +1745,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc)
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     }
   }
-#endif /* RTC_ISR_ALRBF */
+#endif /* TAMP */
 
   /* Change RTC state */
   hrtc->State = HAL_RTC_STATE_READY;
@@ -1863,23 +1835,21 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
 {
   uint32_t tickstart;
 
-  /* Clear RSF flag */
-#if defined(RTC_ICSR_RSF)
-  hrtc->Instance->ICSR &= (uint32_t)RTC_RSF_MASK;
-#endif /* RTC_ICSR_RSF */
-#if defined(RTC_ISR_RSF)
-  hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-#endif /* RTC_ISR_RSF */
+  /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */
+#if defined(TAMP)
+  hrtc->Instance->ICSR = ((uint32_t)(RTC_RSF_MASK & RTC_ICSR_RESERVED_MASK));
+#else
+  hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK));
+#endif /* TAMP */
 
   tickstart = HAL_GetTick();
 
   /* Wait the registers to be synchronised */
-#if defined(RTC_ICSR_RSF)
+#if defined(TAMP)
   while ((hrtc->Instance->ICSR & RTC_ICSR_RSF) == 0U)
-#endif /* RTC_ICSR_RSF */
-#if defined(RTC_ISR_RSF)
+#else
     while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
-#endif /* RTC_ISR_RSF */
+#endif /* TAMP */
     {
       if((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1942,33 +1912,27 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
   uint32_t tickstart;
   HAL_StatusTypeDef status = HAL_OK;
   /* Check if the Initialization mode is set */
-#if defined(RTC_ICSR_INITF)
-  if((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
+#if defined(TAMP)
+  if ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
   {
     /* Set the Initialization mode */
     SET_BIT(hrtc->Instance->ICSR, RTC_ICSR_INIT);
 
     tickstart = HAL_GetTick();
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while ((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U)
-    {
-      if((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
-      {
-        status = HAL_TIMEOUT;
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-      }
-    }
-  }
-#endif /* RTC_ICSR_INITF */
-#if defined(RTC_ISR_INITF)
-  if((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
+
+    /* Wait till RTC is in INIT state and if timeout is reached exit */
+    while (((hrtc->Instance->ICSR & RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT))
+#else
+  if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
   {
     /* Set the Initialization mode */
     hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
 
     tickstart = HAL_GetTick();
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
+
+    /* Wait till RTC is in INIT state and if timeout is reached exit */
+    while (((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) && (status != HAL_TIMEOUT))
+#endif /* TAMP */
     {
       if((HAL_GetTick()  - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -1977,7 +1941,6 @@ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
       }
     }
   }
-#endif /* RTC_ISR_INITF */
 
   return status;
 }
@@ -1992,17 +1955,14 @@ HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc)
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Check if the Initialization mode is set */
-#if defined(RTC_ICSR_INITF)
 
   /* Exit Initialization mode */
+#if defined(TAMP)
   CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT);
+#else
+  CLEAR_BIT(RTC->ISR, RTC_ISR_INIT);
+#endif /* TAMP */
 
-#elif defined(RTC_ISR_INITF)
-
-  /* Exit Initialization mode */
-  CLEAR_BIT(RTC->ISR, RTC_ISR_INITF);
-
-#endif /* RTC_ISR_INITF */
   /* If CR_BYPSHAD bit = 0, wait for synchro */
   if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U)
   {
@@ -2072,4 +2032,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.h
index 99c0dd1e9c..ad0fa135f4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -79,10 +78,10 @@ typedef struct
 
   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-#if defined(RTC_CR_TAMPALRM_PU)
+#if defined(TAMP)
   uint32_t OutPutPullUp;    /*!< Specifies the RTC Output Pull-Up mode.
                                  This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
-#endif /* RTC_CR_TAMPALRM_PU */
+#endif /* TAMP */
 } RTC_InitTypeDef;
 
 /**
@@ -196,33 +195,21 @@ typedef struct
 
   void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 3 Event callback        */
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
   void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 1 Event callback  */
-#endif /* TAMP_CR1_ITAMP1E */
 
-#if defined(TAMP_CR1_ITAMP2E)
   void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 2 Event callback  */
-#endif /* TAMP_CR1_ITAMP2E */
 
-#if defined(TAMP_CR1_ITAMP3E)
   void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 3 Event callback  */
-#endif /* TAMP_CR1_ITAMP3E */
 
-#if defined(TAMP_CR1_ITAMP4E)
   void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 4 Event callback  */
-#endif /* TAMP_CR1_ITAMP4E */
 
-#if defined(TAMP_CR1_ITAMP5E)
   void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 5 Event callback  */
-#endif /* TAMP_CR1_ITAMP5E */
 
-#if defined(TAMP_CR1_ITAMP6E)
   void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 6 Event callback  */
-#endif /* TAMP_CR1_ITAMP6E */
 
-#if defined(TAMP_CR1_ITAMP8E)
   void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 8 Event callback  */
-#endif /* TAMP_CR1_ITAMP8E */
+#endif /* TAMP */
 
   void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                /*!< RTC Msp Init callback              */
 
@@ -245,28 +232,15 @@ typedef enum
   HAL_RTC_TAMPER1_EVENT_CB_ID           = 4u,    /*!< RTC Tamper 1 Callback ID           */
   HAL_RTC_TAMPER2_EVENT_CB_ID           = 5u,    /*!< RTC Tamper 2 Callback ID           */
   HAL_RTC_TAMPER3_EVENT_CB_ID           = 6u,    /*!< RTC Tamper 3 Callback ID           */
-
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
   HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID  = 12u,   /*!< RTC Internal Tamper 1 Callback ID  */
-#endif /* TAMP_CR1_ITAMP1E */
-#if defined(TAMP_CR1_ITAMP2E)
   HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID  = 13u,   /*!< RTC Internal Tamper 2 Callback ID  */
-#endif /* TAMP_CR1_ITAMP2E */
-#if defined(TAMP_CR1_ITAMP3E)
   HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 14u,   /*!< RTC Internal Tamper 3 Callback ID  */
-#endif /* TAMP_CR1_ITAMP3E */
-#if defined(TAMP_CR1_ITAMP4E)
   HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 15u,   /*!< RTC Internal Tamper 4 Callback ID  */
-#endif /* TAMP_CR1_ITAMP4E */
-#if defined(TAMP_CR1_ITAMP5E)
   HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 16u,   /*!< RTC Internal Tamper 5 Callback ID  */
-#endif /* TAMP_CR1_ITAMP5E */
-#if defined(TAMP_CR1_ITAMP6E)
   HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 17u,   /*!< RTC Internal Tamper 6 Callback ID  */
-#endif /* TAMP_CR1_ITAMP6E */
-#if defined(TAMP_CR1_ITAMP8E)
   HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID  = 19u,   /*!< RTC Internal Tamper 8 Callback ID  */
-#endif /* TAMP_CR1_ITAMP8E */
+#endif /* TAMP */
   HAL_RTC_MSPINIT_CB_ID                 = 20u,   /*!< RTC Msp Init callback ID           */
   HAL_RTC_MSPDEINIT_CB_ID               = 21u    /*!< RTC Msp DeInit callback ID         */
 } HAL_RTC_CallbackIDTypeDef;
@@ -302,9 +276,9 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 #define RTC_OUTPUT_ALARMA              RTC_CR_OSEL_0
 #define RTC_OUTPUT_ALARMB              RTC_CR_OSEL_1
 #define RTC_OUTPUT_WAKEUP              RTC_CR_OSEL
-#if defined(RTC_CR_TAMPOE)
+#if defined(TAMP)
 #define RTC_OUTPUT_TAMPER              RTC_CR_TAMPOE
-#endif /* RTC_CR_TAMPOE */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -321,17 +295,15 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
   * @{
   */
-#if defined(RTC_CR_TAMPALRM_TYPE)
+#if defined(TAMP)
 #define RTC_OUTPUT_TYPE_PUSHPULL       0x00000000u
 #define RTC_OUTPUT_TYPE_OPENDRAIN      RTC_CR_TAMPALRM_TYPE
 #define RTC_ALARM_OUTPUT_TYPE          RTC_CR_TAMPALRM_TYPE
-#endif /* RTC_CR_TAMPALRM_TYPE */
-
-#if defined(RTC_OR_ALARMOUTTYPE)
+#else
 #define RTC_OUTPUT_TYPE_PUSHPULL       RTC_OR_ALARMOUTTYPE
 #define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000u
 #define RTC_ALARM_OUTPUT_TYPE          RTC_OR_ALARMOUTTYPE
-#endif /* RTC_OR_ALARMOUTTYPE */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -339,10 +311,10 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 /** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
   * @{
   */
-#if defined(RTC_CR_TAMPALRM_PU)
+#if defined(TAMP)
 #define RTC_OUTPUT_PULLUP_NONE         0x00000000u
 #define RTC_OUTPUT_PULLUP_ON           RTC_CR_TAMPALRM_PU
-#endif /* RTC_CR_TAMPALRM_PU */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -350,15 +322,13 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
   * @{
   */
-#if defined(RTC_CR_OUT2EN)
+#if defined(TAMP)
 #define RTC_OUTPUT_REMAP_NONE          0x00000000u
 #define RTC_OUTPUT_REMAP_POS1          RTC_CR_OUT2EN
-#endif /* RTC_CR_OUT2EN */
-
-#if defined(RTC_OR_OUT_RMP)
+#else
 #define RTC_OUTPUT_REMAP_NONE          0x00000000u
 #define RTC_OUTPUT_REMAP_POS1          RTC_OR_OUT_RMP
-#endif /* RTC_OR_OUT_RMP */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -524,48 +494,37 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
   * @{
   */
-#if defined(RTC_ICSR_RECALPF)
+#if defined(TAMP)
 #define RTC_FLAG_RECALPF                  RTC_ICSR_RECALPF  /*!< Recalibration pending Flag */
-#endif /* RTC_ICSR_RECALPF */
-#if defined(RTC_ICSR_INITF)
 #define RTC_FLAG_INITF                    RTC_ICSR_INITF    /*!< Initialization pending flag */
-#endif /* RTC_ICSR_INITF */
-#if defined(RTC_ICSR_RSF)
 #define RTC_FLAG_RSF                      RTC_ICSR_RSF      /*!< Registers synchronization flag */
-#endif /* RTC_ICSR_RSF */
-#if defined(RTC_ICSR_INITS)
 #define RTC_FLAG_INITS                    RTC_ICSR_INITS    /*!< Initialization status flag */
-#endif /* RTC_ICSR_INITS */
-#if defined(RTC_ICSR_SHPF)
 #define RTC_FLAG_SHPF                     RTC_ICSR_SHPF     /*!< Shift operation pending flag */
-#endif /* RTC_ICSR_SHPF */
-#if defined(RTC_ICSR_WUTWF)
 #define RTC_FLAG_WUTWF                    RTC_ICSR_WUTWF    /*!< Wakeup timer write operation pending flag */
-#endif /* RTC_ICSR_WUTWF */
-#if defined(RTC_ICSR_ALRBWF)
 #define RTC_FLAG_ALRBWF                   RTC_ICSR_ALRBWF   /*!< Alarm B write operation pending flag */
-#endif /* RTC_ICSR_ALRBWF */
-#if defined(RTC_ICSR_ALRAWF)
 #define RTC_FLAG_ALRAWF                   RTC_ICSR_ALRAWF   /*!< Alarm A write operation pending flag */
-#endif /* RTC_ICSR_ALRAWF */
-#if defined(RTC_SR_ITSF)
 #define RTC_FLAG_ITSF                     RTC_SR_ITSF       /*!< Internal Time-stamp flag */
-#endif /* RTC_SR_ITSF */
-#if defined(RTC_SR_TSOVF)
 #define RTC_FLAG_TSOVF                    RTC_SR_TSOVF      /*!< Time-stamp overflow flag */
-#endif /* RTC_SR_TSOVF */
-#if defined(RTC_SR_TSF)
 #define RTC_FLAG_TSF                      RTC_SR_TSF        /*!< Time-stamp flag */
-#endif /* RTC_SR_TSF */
-#if defined(RTC_SR_WUTF)
 #define RTC_FLAG_WUTF                     RTC_SR_WUTF       /*!< Wakeup timer flag */
-#endif /* RTC_SR_WUTF */
-#if defined(RTC_SR_ALRBF)
 #define RTC_FLAG_ALRBF                    RTC_SR_ALRBF      /*!< Alarm B flag */
-#endif /* RTC_SR_ALRBF */
-#if defined(RTC_SR_ALRAF)
 #define RTC_FLAG_ALRAF                    RTC_SR_ALRAF      /*!< Alarm A flag */
-#endif /* RTC_SR_ALRAF */
+#else
+#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
+#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
+#define RTC_FLAG_TSF                      RTC_ISR_TSF
+#define RTC_FLAG_ITSF                     RTC_ISR_ITSF
+#define RTC_FLAG_WUTF                     RTC_ISR_WUTF
+#define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF
+#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
+#define RTC_FLAG_INITF                    RTC_ISR_INITF
+#define RTC_FLAG_RSF                      RTC_ISR_RSF
+#define RTC_FLAG_INITS                    RTC_ISR_INITS
+#define RTC_FLAG_SHPF                     RTC_ISR_SHPF
+#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
+#define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF
+#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
+#endif /* TAMP */
 /**
   * @}
   */
@@ -573,73 +532,15 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 /** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
   * @{
   */
-#if defined(RTC_SCR_CITSF)
+#if defined(TAMP)
 #define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
-#endif /* RTC_SCR_CITSF */
-#if defined(RTC_SCR_CTSOVF)
 #define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
-#endif /* RTC_SCR_CTSOVF */
-#if defined(RTC_SCR_CTSF)
 #define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */
-#endif /* RTC_SCR_CTSF */
-#if defined(RTC_SCR_CWUTF)
 #define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */
-#endif /* RTC_SCR_CWUTF */
-#if defined(RTC_SCR_CALRBF)
 #define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */
-#endif /* RTC_SCR_CALRBF */
-#if defined(RTC_SCR_CALRAF)
 #define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */
-#endif /* RTC_SCR_CALRAF */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
-  * @{
-  */
-#if defined(RTC_ISR_RECALPF)
-#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
-#endif /* RTC_ISR_RECALPF */
-#if defined(RTC_ISR_TSOVF)
-#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
-#endif /* RTC_ISR_TSOVF */
-#if defined(RTC_ISR_TSF)
-#define RTC_FLAG_TSF                      RTC_ISR_TSF
-#endif /* RTC_ISR_TSF */
-#if defined(RTC_ISR_ITSF)
-#define RTC_FLAG_ITSF                     RTC_ISR_ITSF
-#endif /* RTC_ISR_ITSF */
-#if defined(RTC_ISR_WUTF)
-#define RTC_FLAG_WUTF                     RTC_ISR_WUTF
-#endif /* RTC_ISR_WUTF */
-#if defined(RTC_ISR_ALRBF)
-#define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF
-#endif /* RTC_ISR_ALRBF */
-#if defined(RTC_ISR_ALRAF)
-#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
-#endif /* RTC_ISR_ALRAF */
-#if defined(RTC_ISR_INITF)
-#define RTC_FLAG_INITF                    RTC_ISR_INITF
-#endif /* RTC_ISR_INITF */
-#if defined(RTC_ISR_RSF)
-#define RTC_FLAG_RSF                      RTC_ISR_RSF
-#endif /* RTC_ISR_RSF */
-#if defined(RTC_ISR_INITS)
-#define RTC_FLAG_INITS                    RTC_ISR_INITS
-#endif /* RTC_ISR_INITS */
-#if defined(RTC_ISR_SHPF)
-#define RTC_FLAG_SHPF                     RTC_ISR_SHPF
-#endif /* RTC_ISR_SHPF */
-#if defined(RTC_ISR_WUTWF)
-#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
-#endif /* RTC_ISR_WUTWF */
-#if defined(RTC_ISR_ALRBWF)
-#define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF
-#endif /* RTC_ISR_ALRBWF */
-#if defined(RTC_ISR_ALRAWF)
-#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
-#endif /* RTC_ISR_ALRAWF */
+#endif /* TAMP
+ */
 /**
   * @}
   */
@@ -688,6 +589,17 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
                             (__HANDLE__)->Instance->WPR = 0xFFU;   \
                           } while(0u)
 
+/**
+  * @brief  Check whether the RTC Calendar is initialized.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @retval None
+  */
+#if defined(TAMP)
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__)  (((((__HANDLE__)->Instance->ICSR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
+#else
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__)  (((((__HANDLE__)->Instance->ISR)  & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U)
+#endif /* TAMP */
+
 /**
   * @brief  Add 1 hour (summer time change).
   * @param  __HANDLE__ specifies the RTC handle.
@@ -781,12 +693,11 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   *            @arg @ref RTC_IT_ALRB Alarm B interrupt
   * @retval None
   */
-#if defined(RTC_MISR_ALRAMF)
+#if defined(TAMP)
 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)
-#endif /* RTC_MISR_ALRAMF */
-#if defined(RTC_ISR_ALRAF)
+#else
 #define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U)
-#endif /* RTC_ISR_ALRAF */
+#endif /* TAMP */
 
 /**
   * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
@@ -799,7 +710,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   */
 #define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
 
-#if defined(RTC_SR_ALRAF)
+#if defined(TAMP)
 /**
   * @brief  Get the selected RTC Alarm's flag status.
   * @param  __HANDLE__ specifies the RTC handle.
@@ -810,8 +721,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   * @retval None
   */
 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_SR_ALRAF */
-#if defined(RTC_ISR_ALRAF)
+#else
 /**
   * @brief  Get the selected RTC Alarm's flag status.
   * @param  __HANDLE__ specifies the RTC handle.
@@ -824,7 +734,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   * @retval None
   */
 #define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_ALRAF */
+#endif /* TAMP */
 
 /**
   * @brief  Clear the RTC Alarm's pending flags.
@@ -835,12 +745,11 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   *             @arg @ref RTC_FLAG_ALRBF
   * @retval None
   */
-#if defined(RTC_SCR_CALRAF)
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->SCR |= __FLAG__)
-#endif /* RTC_SCR_CALRAF */
-#if defined(RTC_ISR_ALRAF)
+#if defined(TAMP)
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->SCR = __FLAG__)
+#else
 #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
-#endif /* RTC_ISR_ALRAF */
+#endif /* TAMP */
 
 
 /**
@@ -908,7 +817,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   */
 #define __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT()       (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
-#endif
+#endif /* DUAL_CORE */
 /**
   * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None
@@ -983,7 +892,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   * @retval None
   */
 #define __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG()          (EXTI_D2->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
-#endif
+#endif /* DUAL_CORE */
 /**
   * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
   * @retval None
@@ -1087,13 +996,13 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 
 #define RTC_INIT_MASK           0xFFFFFFFFu
 
-#if defined(RTC_ICSR_INIT) && defined(RTC_ICSR_RSF)
+#if defined(TAMP)
+#define RTC_ICSR_RESERVED_MASK              0x000100FFu
 #define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
-#endif /* RTC_ICSR_INIT && RTC_ICSR_RSF */
-
-#if defined(RTC_ISR_INIT) && defined(RTC_ISR_RSF)
+#else
+#define RTC_ISR_RESERVED_MASK               0x0003FFFFu
 #define RTC_RSF_MASK                        (~(RTC_ISR_INIT | RTC_ISR_RSF))
-#endif /* RTC_ISR_INIT && RTC_ISR_RSF */
+#endif /* TAMP */
 
 #define RTC_TIMEOUT_VALUE  1000u
 
@@ -1112,18 +1021,18 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   * @{
   */
 
-#if defined(RTC_CR_TAMPOE)
+#if defined(TAMP)
 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
                                ((OUTPUT) == RTC_OUTPUT_WAKEUP)      || \
                                ((OUTPUT) == RTC_OUTPUT_TAMPER))
-#else  /* RTC_CR_TAMPOE not defined */
+#else
 #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
                                ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
                                ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-#endif /* RTC_CR_TAMPOE */
+#endif /* TAMP */
 
 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
                                         ((FORMAT) == RTC_HOURFORMAT_24))
@@ -1134,10 +1043,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
 
-#if defined(RTC_CR_TAMPALRM_PU)
+#if defined(TAMP)
 #define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
                                     ((TYPE) == RTC_OUTPUT_PULLUP_ON))
-#endif /* RTC_CR_TAMPALRM_PU */
+#endif /* TAMP */
 
 #define IS_RTC_OUTPUT_REMAP(REMAP)     (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                         ((REMAP) == RTC_OUTPUT_REMAP_POS1))
@@ -1239,4 +1148,3 @@ uint8_t            RTC_Bcd2ToByte(uint8_t Value);
 
 #endif /* STM32H7xx_HAL_RTC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.c
index e1a0d3aba7..252dce91b8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.c
@@ -11,6 +11,17 @@
   *           + Extended Control functions
   *           + Extended RTC features functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                   ##### How to use this driver #####
@@ -86,18 +97,6 @@
         function.
 
    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -251,10 +250,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
   /* Enable IT timestamp */
   __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS);
 
-#if !defined(DUAL_CORE)
   /* RTC timestamp Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+  }
+  else
+  {
+    __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT();
+  }
+#else /* SINGLE_CORE */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-#endif
+#endif /* DUAL_CORE */
 
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
 
@@ -454,7 +462,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe
 * @{
 */
 
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Set Tamper
   * @param  hrtc RTC handle
@@ -521,8 +529,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe
 
   return HAL_OK;
 }
-#endif /* TAMP_CR1_TAMP1E */
-#if defined (RTC_TAMPCR_TAMP1E)
+#else
 /**
   * @brief  Set Tamper.
   * @note   By calling this API we disable the tamper interrupt for all tampers.
@@ -572,89 +579,65 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe
   /* Configure the tamper backup registers erasure bit */
   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
   else
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
 
   /* Configure the tamper flags masking bit */
   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
   else
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
 
   /* Clearing remaining fields before setting them */
@@ -679,9 +662,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef * hrtc, RTC_TamperTypeDe
 
   return HAL_OK;
 }
-#endif /* RTC_TAMPCR_TAMP1E */
+#endif /* TAMP */
 
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Set Tamper with interrupt.
   * @param  hrtc RTC handle
@@ -757,8 +740,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp
 
   return HAL_OK;
 }
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP1E)
+#else
 /**
   * @brief  Set Tamper with interrupt.
   * @note   By calling this API we force the tamper interrupt for all tampers.
@@ -809,89 +791,65 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp
   /* Configure the tamper backup registers erasure bit */
   if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
   else
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
 
   /* Configure the tamper flags masking bit */
   if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
   else
   {
-#if defined(RTC_TAMPCR_TAMP1E)
     if ((sTamper->Tamper & RTC_TAMPER_1) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF);
     }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
     if ((sTamper->Tamper & RTC_TAMPER_2) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF);
     }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
     if ((sTamper->Tamper & RTC_TAMPER_3) != 0U)
     {
       tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF);
     }
-#endif /* RTC_TAMPCR_TAMP3E */
   }
 
   /* Clearing remaining fields before setting them */
@@ -912,10 +870,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp
   /* Copy desired configuration into configuration register */
   hrtc->Instance->TAMPCR = tmpreg;
 
-#if !defined(DUAL_CORE)
   /* RTC Tamper Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
+  }
+  else
+  {
+    __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT();
+  }
+#else /* SINGLE_CORE */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
-#endif
+#endif /* DUAL_CORE */
 
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
 
@@ -926,9 +893,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef * hrtc, RTC_TamperTyp
 
   return HAL_OK;
 }
-#endif /* RTC_TAMPCR_TAMP1E */
+#endif /* TAMP */
 
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Deactivate Tamper.
   * @param  hrtc RTC handle
@@ -959,8 +926,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t
 
   return HAL_OK;
 }
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP1E)
+#else
 /**
   * @brief  Deactivate Tamper.
   * @param  hrtc RTC handle
@@ -984,24 +950,20 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t
   hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper);
 
   /* Disable the selected Tamper interrupt */
-#if defined(RTC_TAMPCR_TAMP1E)
   if ((Tamper & RTC_TAMPER_1) != 0U)
   {
     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1));
   }
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
+
   if ((Tamper & RTC_TAMPER_2) != 0U)
   {
     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2));
   }
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
+
   if ((Tamper & RTC_TAMPER_3) != 0U)
   {
     hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3));
   }
-#endif /* RTC_TAMPCR_TAMP3E */
 
   hrtc->State = HAL_RTC_STATE_READY;
 
@@ -1010,9 +972,9 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef * hrtc, uint32_t
 
   return HAL_OK;
 }
-#endif /* RTC_TAMPCR_TAMP1E */
+#endif /* TAMP */
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Set Internal Tamper
   * @param  hrtc RTC handle
@@ -1094,9 +1056,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui
 
   return HAL_OK;
 }
-#endif /* TAMP_CR1_ITAMP1E */
 
-#if defined(TAMP_ATCR1_TAMP1AM)
 /**
   * @brief  Set all active Tampers at the same time.
   * @param  hrtc RTC handle
@@ -1112,11 +1072,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active
   {
     assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase));
     assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag));
-    /* Mask flag only supported by TAMPER 1, 2 and 3 */
+    /* Mask flag only supported by TAMPER 1, 2, and 3 */
     assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3)));
   }
+
   assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection));
-#endif /* #ifdef  USE_FULL_ASSERT */
+#endif /* USE_FULL_ASSERT */
 
   /* Active Tampers must not be already enabled */
   if (READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) != 0U)
@@ -1196,7 +1157,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active
     WRITE_REG(TAMP->ATSEEDR, sAllTamper->Seed[i]);
   }
 
-  /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
+  /* Wait till RTC SEEDF flag is set and if timeout is reached exit */
   tickstart = HAL_GetTick();
   while (READ_BIT(TAMP->ATOR,  TAMP_ATOR_SEEDF) != 0u)
   {
@@ -1209,9 +1170,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active
 
   return HAL_OK;
 }
-#endif /* TAMP_ATCR1_TAMP1AM */
 
-#if defined(TAMP_ATSEEDR_SEED)
 /**
   * @brief  Write a new seed. Active tamper must be enabled.
   * @param  hrtc RTC handle
@@ -1233,7 +1192,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe
     WRITE_REG(TAMP->ATSEEDR, pSeed[i]);
   }
 
-  /* Wait till RTC SEEDF flag is set and if Time out is reached exit */
+  /* Wait till RTC SEEDF flag is set and if timeout is reached exit */
   tickstart = HAL_GetTick();
   while (READ_BIT(TAMP->ATOR,  TAMP_ATOR_SEEDF) != 0U)
   {
@@ -1246,9 +1205,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe
 
   return HAL_OK;
 }
-#endif /* TAMP_ATSEEDR_SEED */
 
-#if defined(TAMP_ATCR1_TAMP1AM)
 /**
   * @brief  Deactivate all Active Tampers at the same time.
   * @param  hrtc RTC handle
@@ -1281,7 +1238,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc)
 
   return HAL_OK;
 }
-#endif /* TAMP_ATCR1_TAMP1AM */
+#endif /* TAMP */
 
 /**
   * @}
@@ -1294,11 +1251,11 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc)
 */
 
 /**
-  * @brief  Handle TimeStamp interrupt request.
+  * @brief  Handle Tamper and TimeStamp interrupt request.
   * @param  hrtc RTC handle
   * @retval None
   */
-#if defined(RTC_MISR_TSMF)
+#if defined(TAMP)
 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
 {
 
@@ -1315,7 +1272,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
     hrtc->TimeStampEventCallback(hrtc);
 #else
     HAL_RTCEx_TimeStampEventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
     /* Not immediately clear flags because the content of RTC_TSTR and RTC_TSDR are cleared when TSF bit is reset.*/
     hrtc->Instance->SCR = RTC_SCR_CTSF;
   }
@@ -1326,151 +1283,130 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
   /* Immediately clear flags */
   tamp->SCR = tmp;
 
-#if defined(TAMP_CR1_TAMP1E)
-  /* Check Tamper1 status */
+  /* Check Tamper 1 status */
   if ((tmp & RTC_TAMPER_1) == RTC_TAMPER_1)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
     /* Call Tamper 1 Event registered Callback */
     hrtc->Tamper1EventCallback(hrtc);
 #else
-    /* Tamper1 callback */
+    /* Tamper 1 callback */
     HAL_RTCEx_Tamper1EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR1_TAMP2E)
-  /* Check Tamper2 status */
+  /* Check Tamper 2 status */
   if ((tmp & RTC_TAMPER_2) == RTC_TAMPER_2)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
     /* Call Tamper 2 Event registered Callback */
     hrtc->Tamper2EventCallback(hrtc);
 #else
-    /* Tamper2 callback */
+    /* Tamper 2 callback */
     HAL_RTCEx_Tamper2EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_TAMP2E */
 
-#if defined(TAMP_CR1_TAMP3E)
-  /* Check Tamper3 status */
+  /* Check Tamper 3 status */
   if ((tmp & RTC_TAMPER_3) == RTC_TAMPER_3)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
     /* Call Tamper 3 Event registered Callback */
     hrtc->Tamper3EventCallback(hrtc);
 #else
-    /* Tamper3 callback */
+    /* Tamper 3 callback */
     HAL_RTCEx_Tamper3EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_TAMP3E */
 
-#if defined(TAMP_CR1_ITAMP1E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 1 status */
   if ((tmp & RTC_INT_TAMPER_1) == RTC_INT_TAMPER_1)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 1 Event registered callback */
     hrtc->InternalTamper1EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 1 Event by-default callback */
     HAL_RTCEx_InternalTamper1EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP1E */
 
-#if defined(TAMP_CR1_ITAMP2E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 2 status */
   if ((tmp & RTC_INT_TAMPER_2) == RTC_INT_TAMPER_2)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 2 Event registered callback */
     hrtc->InternalTamper2EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 2 Event by-default callback */
     HAL_RTCEx_InternalTamper2EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP2E */
 
-#if defined(TAMP_CR1_ITAMP3E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 3 status */
   if ((tmp & RTC_INT_TAMPER_3) == RTC_INT_TAMPER_3)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 3 Event registered callback */
     hrtc->InternalTamper3EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 3 Event by-default callback */
     HAL_RTCEx_InternalTamper3EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP3E */
 
-#if defined(TAMP_CR1_ITAMP4E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 4 status */
   if ((tmp & RTC_INT_TAMPER_4) == RTC_INT_TAMPER_4)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 4 Event registered callback */
     hrtc->InternalTamper4EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 4 Event by-default callback */
     HAL_RTCEx_InternalTamper4EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP4E */
 
-#if defined(TAMP_CR1_ITAMP5E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 5 status */
   if ((tmp & RTC_INT_TAMPER_5) == RTC_INT_TAMPER_5)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 5 Event registered callback */
     hrtc->InternalTamper5EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 5 Event by-default callback */
     HAL_RTCEx_InternalTamper5EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP5E */
 
-#if defined(TAMP_CR1_ITAMP6E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 6 status */
   if ((tmp & RTC_INT_TAMPER_6) == RTC_INT_TAMPER_6)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 6 Event registered callback */
     hrtc->InternalTamper6EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 6 Event by-default callback */
     HAL_RTCEx_InternalTamper6EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP6E */
 
-#if defined(TAMP_CR1_ITAMP8E)
-  /* Check Internal Tamper status */
+  /* Check Internal Tamper 8 status */
   if ((tmp & RTC_INT_TAMPER_8) == RTC_INT_TAMPER_8)
   {
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-    /* Call Internal Tamper Event registered callback */
+    /* Call Internal Tamper 8 Event registered callback */
     hrtc->InternalTamper8EventCallback(hrtc);
 #else
-    /* Call Internal Tamper Event by-default callback */
+    /* Call Internal Tamper 8 Event by-default callback */
     HAL_RTCEx_InternalTamper8EventCallback(hrtc);
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* TAMP_CR1_ITAMP8E */
 
   /* Change RTC state */
   hrtc->State = HAL_RTC_STATE_READY;
 }
-#endif /* RTC_MISR_TSMF */
-#if defined(RTC_ISR_TSF)
+#else
 void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
 {
   /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
@@ -1483,7 +1419,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
   {
     __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG();
   }
-#else  /* SINGLE_CORE */
+#else /* SINGLE_CORE */
   __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
 #endif /* DUAL_CORE */
 
@@ -1505,17 +1441,16 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
     }
   }
 
-#if defined(RTC_TAMPCR_TAMP1E)
-  /* Get the Tamper1 interrupt source enable status */
+  /* Get the Tamper 1 interrupt source enable status */
   if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U)
   {
-    /* Get the pending status of the Tamper1 Interrupt */
+    /* Get the pending status of the Tamper 1 Interrupt */
     if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U)
     {
-      /* Clear the Tamper1 interrupt pending bit */
+      /* Clear the Tamper 1 interrupt pending bit */
       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F);
 
-      /* Tamper1 callback */
+      /* Tamper 1 callback */
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
       hrtc->Tamper1EventCallback(hrtc);
 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
@@ -1523,19 +1458,17 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     }
   }
-#endif /* RTC_TAMPCR_TAMP1E */
 
-#if defined(RTC_TAMPCR_TAMP2E)
-  /* Get the Tamper2 interrupt source enable status */
+  /* Get the Tamper 2 interrupt source enable status */
   if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U)
   {
-    /* Get the pending status of the Tamper2 Interrupt */
+    /* Get the pending status of the Tamper 2 Interrupt */
     if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U)
     {
-      /* Clear the Tamper2 interrupt pending bit */
+      /* Clear the Tamper 2 interrupt pending bit */
       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
 
-      /* Tamper2 callback */
+      /* Tamper 2 callback */
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
       hrtc->Tamper2EventCallback(hrtc);
 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
@@ -1543,19 +1476,17 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     }
   }
-#endif /* RTC_TAMPCR_TAMP2E */
 
-#if defined(RTC_TAMPCR_TAMP3E)
-  /* Get the Tamper3 interrupts source enable status */
+  /* Get the Tamper 3 interrupts source enable status */
   if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U)
   {
-    /* Get the pending status of the Tamper3 Interrupt */
+    /* Get the pending status of the Tamper 3 Interrupt */
     if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U)
     {
-      /* Clear the Tamper3 interrupt pending bit */
+      /* Clear the Tamper 3 interrupt pending bit */
       __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
 
-      /* Tamper3 callback */
+      /* Tamper 3 callback */
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
       hrtc->Tamper3EventCallback(hrtc);
 #else  /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
@@ -1563,12 +1494,11 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
 #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
     }
   }
-#endif /* RTC_TAMPCR_TAMP3E */
 
   /* Change RTC state */
   hrtc->State = HAL_RTC_STATE_READY;
 }
-#endif /* RTC_ISR_TSF */
+#endif /* TAMP */
 
 /**
   * @brief  TimeStamp callback.
@@ -1595,7 +1525,6 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
 * @{
 */
 
-#if defined(RTC_TAMPER_1)
 /**
   * @brief  Tamper 1 callback.
   * @param  hrtc RTC handle
@@ -1610,9 +1539,7 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef * hrtc)
             the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
    */
 }
-#endif /* RTC_TAMPER_1 */
 
-#if defined(RTC_TAMPER_2)
 /**
   * @brief  Tamper 2 callback.
   * @param  hrtc RTC handle
@@ -1627,9 +1554,7 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef * hrtc)
             the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
    */
 }
-#endif /* RTC_TAMPER_2 */
 
-#if defined(RTC_TAMPER_3)
 /**
   * @brief  Tamper 3 callback.
   * @param  hrtc RTC handle
@@ -1644,8 +1569,8 @@ __weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef * hrtc)
             the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
    */
 }
-#endif /* RTC_TAMPER_3 */
 
+#if defined(TAMP)
 /**
   * @brief  Internal Tamper 1 callback.
   * @param  hrtc RTC handle
@@ -1750,6 +1675,8 @@ __weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc)
             the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file
    */
 }
+#endif /* TAMP */
+
 /**
   * @}
   */
@@ -1809,7 +1736,6 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
 * @{
 */
 
-#if defined(RTC_TAMPER_1)
 /**
   * @brief  Handle Tamper1 Polling.
   * @param  hrtc RTC handle
@@ -1841,9 +1767,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef * hrtc, uint32
 
   return HAL_OK;
 }
-#endif /* RTC_TAMPER_1 */
 
-#if defined(RTC_TAMPER_2)
 /**
   * @brief  Handle Tamper2 Polling.
   * @param  hrtc RTC handle
@@ -1875,9 +1799,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef * hrtc, uint32
 
   return HAL_OK;
 }
-#endif /* RTC_TAMPER_2 */
 
-#if defined(RTC_TAMPER_3)
 /**
   * @brief  Handle Tamper3 Polling.
   * @param  hrtc RTC handle
@@ -1909,9 +1831,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef * hrtc, uint32
 
   return HAL_OK;
 }
-#endif /* RTC_TAMPER_3 */
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Internal Tamper event polling.
   * @param  hrtc RTC handle
@@ -1944,7 +1865,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc,
 
   return HAL_OK;
 }
-#endif /* TAMP_CR1_ITAMP1E */
+#endif /* TAMP */
 
 /**
   * @}
@@ -1993,36 +1914,34 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak
   /* Poll WUTWF until it is set in RTC_ICSR / RTC_ISR to make sure the access to wakeup autoreload
   counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
   calendar initialization mode. */
-#if defined(RTC_ISR_INITF)
+#if defined(TAMP)
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+  {
+    tickstart = HAL_GetTick();
+
+    while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
+#else
   if (READ_BIT(RTC->ISR, RTC_ISR_INITF) == 0U)
-#endif /* RTC_ISR_INITF */
-#if defined(RTC_ICSR_INITF)
-    if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
-#endif /* RTC_ICSR_INITF */
+  {
+    tickstart = HAL_GetTick();
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
+#endif /* TAMP */
     {
-      tickstart = HAL_GetTick();
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-#if defined(RTC_ICSR_WUTWF)
-      while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
-#endif /* RTC_ICSR_WUTWF */
-#if defined(RTC_ISR_WUTWF)
-        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-#endif /* RTC_ISR_WUTWF */
-        {
-          if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-          {
-            /* Enable the write protection for RTC registers */
-            __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-            hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
 
-            /* Process Unlocked */
-            __HAL_UNLOCK(hrtc);
-
-            return HAL_TIMEOUT;
-          }
-        }
+        return HAL_TIMEOUT;
+      }
     }
+  }
 
   /* Clear the Wakeup Timer clock source bits and configure the clock source in CR register */
   uint32_t CR_tmp = hrtc->Instance->CR;
@@ -2076,36 +1995,34 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
   /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload
   counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in
   calendar initialization mode. */
-#if defined(RTC_ISR_INITF)
+#if defined(TAMP)
+  if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
+  {
+    tickstart = HAL_GetTick();
+
+    while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
+#else
   if (READ_BIT(RTC->ISR, RTC_ISR_INITF) == 0U)
-#endif /* RTC_ISR_INITF */
-#if defined(RTC_ICSR_INITF)
-    if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U)
-#endif /* RTC_ICSR_INITF */
+  {
+    tickstart = HAL_GetTick();
+
+    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
+#endif /* TAMP */
     {
-      tickstart = HAL_GetTick();
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-#if defined(RTC_ICSR_WUTWF)
-      while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
-#endif /* RTC_ICSR_WUTWF */
-#if defined(RTC_ISR_WUTWF)
-        while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-#endif /* RTC_ISR_WUTWF */
-        {
-          if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-          {
-            /* Enable the write protection for RTC registers */
-            __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-            hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
 
-            /* Process Unlocked */
-            __HAL_UNLOCK(hrtc);
-
-            return HAL_TIMEOUT;
-          }
-        }
+        return HAL_TIMEOUT;
+      }
     }
+  }
 
   /* Configure the Wakeup Timer counter */
   hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
@@ -2118,10 +2035,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
     hrtc->Instance->CR = CR_tmp;
   }
 
-#if !defined(DUAL_CORE)
   /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
+#if defined(DUAL_CORE)
+  if (HAL_GetCurrentCPUID() == CM7_CPUID)
+  {
+    __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
+  }
+  else
+  {
+    __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT();
+  }
+#else /* SINGLE_CORE */
   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
-#endif
+#endif /* DUAL_CORE */
 
   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
 
@@ -2166,13 +2092,12 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
   __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT);
 
   tickstart = HAL_GetTick();
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  #if defined(RTC_ICSR_WUTWF)
-    while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
-  #endif /* RTC_ICSR_WUTWF */
-  #if defined(RTC_ISR_WUTWF)
-    while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
-  #endif /* RTC_ISR_WUTWF */
+  /* Wait till RTC WUTWF flag is set and if timeout is reached exit */
+#if defined(TAMP)
+  while (READ_BIT(hrtc->Instance->ICSR, RTC_FLAG_WUTWF) == 0U)
+#else
+  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U)
+#endif /* TAMP */
   {
     if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
     {
@@ -2227,11 +2152,11 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
   {
     __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG();
   }
-#else  /* SINGLE_CORE */
+#else /* SINGLE_CORE */
   __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
 #endif /* DUAL_CORE */
 
-#if defined(RTC_MISR_WUTMF)
+#if defined(TAMP)
   /* Get the pending status of the WAKEUPTIMER Interrupt */
   if ((hrtc->Instance->MISR & RTC_MISR_WUTMF) != 0u)
   {
@@ -2246,8 +2171,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
   #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* RTC_MISR_WUTMF */
-#if defined(RTC_ISR_WUTF)
+#else
   /* Get the pending status of the WAKEUPTIMER Interrupt */
   if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U)
   {
@@ -2262,7 +2186,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
     HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
   #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
   }
-#endif /* RTC_ISR_WUTF */
+#endif /* TAMP */
 
   /* Change RTC state */
   hrtc->State = HAL_RTC_STATE_READY;
@@ -2357,12 +2281,11 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister, uint
   assert_param(IS_RTC_BKP(BackupRegister));
 
   /* Point on address of first backup register */
-#if defined(TAMP_BKP0R)
+#if defined(TAMP)
   tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R);
-#endif /* TAMP_BKP0R */
-#if defined(RTC_BKP0R)
+#else
   tmp = (uint32_t) & (hrtc->Instance->BKP0R);
-#endif /* RTC_BKP0R */
+#endif /* TAMP */
 
   tmp += (BackupRegister * 4U);
 
@@ -2387,12 +2310,11 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef * hrtc, uint32_t BackupRegister)
   assert_param(IS_RTC_BKP(BackupRegister));
 
   /* Point on address of first backup register */
-#if defined(TAMP_BKP0R)
+#if defined(TAMP)
   tmp = (uint32_t) & (((TAMP_TypeDef *)((uint32_t)hrtc->Instance + TAMP_OFFSET))->BKP0R);
-#endif /* TAMP_BKP0R */
-#if defined(RTC_BKP0R)
+#else
   tmp = (uint32_t) & (hrtc->Instance->BKP0R);
-#endif /* RTC_BKP0R */
+#endif /* TAMP */
 
   tmp += (BackupRegister * 4U);
 
@@ -2468,39 +2390,39 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef * hrtc, uint32_t Sm
   /* Disable the write protection for RTC registers */
   __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 
+#if defined(TAMP)
   /* check if a calibration operation is pending */
-#if defined(RTC_ICSR_RECALPF)
   if ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
-#endif /* RTC_ICSR_RECALPF */
-#if defined(RTC_ISR_RECALPF)
-    if ((hrtc->Instance->ISR  & RTC_ISR_RECALPF)  != 0U)
-#endif /* RTC_ISR_RECALPF */
+  {
+    tickstart = HAL_GetTick();
+
+    /* Wait for pending calibration operation to finish */
+    while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
+#else
+  /* check if a calibration operation is pending */
+  if ((hrtc->Instance->ISR  & RTC_ISR_RECALPF)  != 0U)
+  {
+    tickstart = HAL_GetTick();
+
+    /* Wait for pending calibration operation to finish */
+    while ((hrtc->Instance->ISR  & RTC_ISR_RECALPF)  != 0U)
+#endif /* TAMP */
     {
-      tickstart = HAL_GetTick();
+      if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
+      {
+        /* Enable the write protection for RTC registers */
+        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 
-      /* Wait for pending calibration operation to finish */
-#if defined(RTC_ICSR_RECALPF)
-      while ((hrtc->Instance->ICSR & RTC_ICSR_RECALPF) != 0U)
-#endif /* RTC_ICSR_RECALPF */
-#if defined(RTC_ISR_RECALPF)
-        while ((hrtc->Instance->ISR  & RTC_ISR_RECALPF)  != 0U)
-#endif /* RTC_ISR_RECALPF */
-        {
-          if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
-          {
-            /* Enable the write protection for RTC registers */
-            __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+        /* Change RTC state */
+        hrtc->State = HAL_RTC_STATE_TIMEOUT;
 
-            /* Change RTC state */
-            hrtc->State = HAL_RTC_STATE_TIMEOUT;
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrtc);
 
-            /* Process Unlocked */
-            __HAL_UNLOCK(hrtc);
-
-            return HAL_TIMEOUT;
-          }
-        }
+        return HAL_TIMEOUT;
+      }
     }
+  }
 
   /* Configure the Smooth calibration settings */
   MODIFY_REG(hrtc->Instance->CALR, (RTC_CALR_CALP | RTC_CALR_CALW8 | RTC_CALR_CALW16 | RTC_CALR_CALM), (uint32_t)(SmoothCalibPeriod | SmoothCalibPlusPulses | SmoothCalibMinusPulsesValue));
@@ -2548,12 +2470,11 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef * hrtc, uint32_t S
   tickstart = HAL_GetTick();
 
   /* Wait until the shift is completed */
-#if defined(RTC_ICSR_SHPF)
+#if defined(TAMP)
   while ((hrtc->Instance->ICSR & RTC_ICSR_SHPF) != 0U)
-#endif /* RTC_ICSR_SHPF */
-#if defined(RTC_ISR_SHPF)
+#else
     while ((hrtc->Instance->ISR  & RTC_ISR_SHPF)  != 0U)
-#endif /* RTC_ISR_SHPF */
+#endif /* TAMP */
     {
       if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE)
       {
@@ -2834,7 +2755,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef * hrtc)
   return HAL_OK;
 }
 
-#if defined(TAMP_COUNTR)
+#if defined(TAMP)
 /**
   * @brief  Increment Monotonic counter.
   * @param  hrtc RTC handle
@@ -2873,7 +2794,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_
 
   return HAL_OK;
 }
-#endif /* TAMP_COUNTR */
+#endif /* TAMP */
 
 /**
   * @}
@@ -2959,4 +2880,3 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef * hrtc, uint32_
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h
index 833ae6f9c7..bb29abe868 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -81,24 +80,22 @@ typedef struct
   * @}
   */
 
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
 /** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
   * @{
   */
 typedef struct
 {
   uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.
-                                             This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
+                                             This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins_Definitions */
 
   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
 } RTC_InternalTamperTypeDef;
 /**
   * @}
   */
-#endif /* TAMP_CR1_ITAMP1E */
 
-#if defined(TAMP_ATCR1_TAMP1AM)
 /** @defgroup RTCEx_Active_Seed_Size Seed size Definitions
   * @{
   */
@@ -131,10 +128,10 @@ typedef struct
                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */
 
   uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
-                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
+                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */
 
   uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
-                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
+                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */
 
 } RTC_ATampInputTypeDef;
 
@@ -148,7 +145,7 @@ typedef struct
                                              This parameter can be a value of @ref RTCEx_ActiveTamper_Async_prescaler */
 
   uint32_t TimeStampOnTamperDetection;  /*!< Specifies the timeStamp on tamper detection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */
 
   uint32_t ActiveOutputChangePeriod;    /*!< Specifies the Active Tamper output change period .
                                              This parameter can be a value from 0 to 7. */
@@ -165,7 +162,7 @@ typedef struct
 /**
   * @}
   */
-#endif /* TAMP_ATCR1_TAMP1AM */
+#endif /* TAMP */
 
 /**
   * @}
@@ -184,12 +181,11 @@ typedef struct
 /** @defgroup RTCEx_Backup_Registers_Number_Definitions RTC Backup Registers Number Definitions
   * @{
   */
-#if defined(RTC_BKP_NUMBER)
-#define BKP_REG_NUMBER                       RTC_BKP_NUMBER
-#endif /* RTC_BKP_NUMBER */
-#if defined(TAMP_BKP_NUMBER)
+#if defined(TAMP)
 #define BKP_REG_NUMBER                       TAMP_BKP_NUMBER
-#endif /* TAMP_BKP_NUMBER */
+#else
+#define BKP_REG_NUMBER                       RTC_BKP_NUMBER
+#endif /* TAMP */
 /**
   * @}
   */
@@ -263,25 +259,15 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions
   * @{
   */
-#if defined(TAMP_CR1_TAMP1E)
-#define RTC_TAMPER_1                        TAMP_CR1_TAMP1E
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(TAMP_CR1_TAMP2E)
-#define RTC_TAMPER_2                        TAMP_CR1_TAMP2E
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(TAMP_CR1_TAMP3E)
-#define RTC_TAMPER_3                        TAMP_CR1_TAMP3E
-#endif /* TAMP_CR1_TAMP3E */
-
-#if defined(RTC_TAMPCR_TAMP1E)
+#if defined(TAMP)
+#define RTC_TAMPER_1                       TAMP_CR1_TAMP1E
+#define RTC_TAMPER_2                       TAMP_CR1_TAMP2E
+#define RTC_TAMPER_3                       TAMP_CR1_TAMP3E
+#else
 #define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP2E)
 #define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP3E)
 #define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E
-#endif /* RTC_TAMPCR_TAMP3E */
+#endif /* TAMP */
 
 #define RTC_TAMPER_ALL                     (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)
 /**
@@ -291,33 +277,23 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions
   * @{
   */
-#if defined(TAMP_IER_TAMP1IE)
+#if defined(TAMP)
 #define RTC_IT_TAMP1                      TAMP_IER_TAMP1IE    /*!< Enable Tamper 1 Interrupt                */
-#endif /* TAMP_IER_TAMP1IE */
-#if defined(TAMP_IER_TAMP2IE)
 #define RTC_IT_TAMP2                      TAMP_IER_TAMP2IE    /*!< Enable Tamper 2 Interrupt                */
-#endif /* TAMP_IER_TAMP2IE */
-#if defined(TAMP_IER_TAMP3IE)
 #define RTC_IT_TAMP3                      TAMP_IER_TAMP3IE    /*!< Enable Tamper 3 Interrupt                */
-#endif /* TAMP_IER_TAMP3IE */
-
-#if defined(RTC_TAMPCR_TAMP1IE)
+#else
 #define RTC_IT_TAMP1                      RTC_TAMPCR_TAMP1IE  /*!< Enable Tamper 1 Interrupt                */
-#endif /* RTC_TAMPCR_TAMP1IE */
-#if defined(RTC_TAMPCR_TAMP2IE)
 #define RTC_IT_TAMP2                      RTC_TAMPCR_TAMP2IE  /*!< Enable Tamper 2 Interrupt                */
-#endif /* RTC_TAMPCR_TAMP2IE */
-#if defined(RTC_TAMPCR_TAMP3IE)
 #define RTC_IT_TAMP3                      RTC_TAMPCR_TAMP3IE  /*!< Enable Tamper 3 Interrupt                */
-#endif /* RTC_TAMPCR_TAMP3IE */
+#endif /* TAMP */
 
-#if defined(RTC_TAMPCR_TAMPIE)
-#define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE   /*!< Enable all Tamper Interrupts              */
-#define RTC_IT_TAMPALL                    RTC_IT_TAMP
-#else /* RTC_TAMPCR_TAMPIE not defined */
+#if defined(TAMP)
 #define RTC_IT_TAMP                       0x00000000u         /*!< No such feature in RTC3                   */
 #define RTC_IT_TAMPALL                    (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)
-#endif /* RTC_TAMPCR_TAMPIE */
+#else
+#define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE   /*!< Enable all Tamper Interrupts              */
+#define RTC_IT_TAMPALL                    RTC_IT_TAMP
+#endif /* TAMP */
 /**
   * @}
   */
@@ -325,31 +301,20 @@ typedef struct
 /** @defgroup RTCEx_Internal_Tamper_Pins_Definitions  RTCEx Internal Tamper Pins Definition
   * @{
   */
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
 #define RTC_INT_TAMPER_1                    TAMP_CR1_ITAMP1E
-#endif /* TAMP_CR1_ITAMP1E */
-#if defined(TAMP_CR1_ITAMP2E)
 #define RTC_INT_TAMPER_2                    TAMP_CR1_ITAMP2E
-#endif /* TAMP_CR1_ITAMP2E */
-#if defined(TAMP_CR1_ITAMP3E)
 #define RTC_INT_TAMPER_3                    TAMP_CR1_ITAMP3E
-#endif /* TAMP_CR1_ITAMP3E */
-#if defined(TAMP_CR1_ITAMP4E)
 #define RTC_INT_TAMPER_4                    TAMP_CR1_ITAMP4E
-#endif /* TAMP_CR1_ITAMP4E */
-#if defined(TAMP_CR1_ITAMP5E)
 #define RTC_INT_TAMPER_5                    TAMP_CR1_ITAMP5E
-#endif /* TAMP_CR1_ITAMP5E */
-#if defined(TAMP_CR1_ITAMP6E)
 #define RTC_INT_TAMPER_6                    TAMP_CR1_ITAMP6E
-#endif /* TAMP_CR1_ITAMP6E */
-#if defined(TAMP_CR1_ITAMP8E)
 #define RTC_INT_TAMPER_8                    TAMP_CR1_ITAMP8E
+
 #define RTC_INT_TAMPER_ALL                  (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
                                              RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
                                              RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
                                              RTC_INT_TAMPER_8)
-#endif /* TAMP_CR1_ITAMP8E */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -357,27 +322,15 @@ typedef struct
 /** @defgroup RTCEx_Internal_Tamper_Interrupt_Definitions  RTC Internal Tamper Interrupt
   * @{
   */
-#if defined(TAMP_IER_ITAMP1IE)
+#if defined(TAMP)
 #define RTC_INTERNAL_TAMPER1_INTERRUPT     TAMP_IER_ITAMP1IE  /*!< Enable Internal Tamper 1 Interrupt   */
-#endif /* TAMP_IER_ITAMP1IE */
-#if defined(TAMP_IER_ITAMP2IE)
 #define RTC_INTERNAL_TAMPER2_INTERRUPT     TAMP_IER_ITAMP2IE  /*!< Enable Internal Tamper 2 Interrupt   */
-#endif /* TAMP_IER_ITAMP2IE */
-#if defined(TAMP_IER_ITAMP3IE)
 #define RTC_INTERNAL_TAMPER3_INTERRUPT     TAMP_IER_ITAMP3IE  /*!< Enable Internal Tamper 3 Interrupt   */
-#endif /* TAMP_IER_ITAMP3IE */
-#if defined(TAMP_IER_ITAMP4IE)
 #define RTC_INTERNAL_TAMPER4_INTERRUPT     TAMP_IER_ITAMP4IE  /*!< Enable Internal Tamper 4 Interrupt   */
-#endif /* TAMP_IER_ITAMP4IE */
-#if defined(TAMP_IER_ITAMP5IE)
 #define RTC_INTERNAL_TAMPER5_INTERRUPT     TAMP_IER_ITAMP5IE  /*!< Enable Internal Tamper 5 Interrupt   */
-#endif /* TAMP_IER_ITAMP5IE */
-#if defined(TAMP_IER_ITAMP6IE)
 #define RTC_INTERNAL_TAMPER6_INTERRUPT     TAMP_IER_ITAMP6IE  /*!< Enable Internal Tamper 6 Interrupt   */
-#endif /* TAMP_IER_ITAMP6IE */
-#if defined(TAMP_IER_ITAMP8IE)
 #define RTC_INTERNAL_TAMPER8_INTERRUPT     TAMP_IER_ITAMP8IE  /*!< Enable Internal Tamper 8 Interrupt   */
-#endif /* TAMP_IER_ITAMP8IE */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -385,30 +338,20 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions
   * @{
   */
-#define RTC_TAMPERTRIGGER_RISINGEDGE        0x01u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_FALLINGEDGE       0x02u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
+#define RTC_TAMPERTRIGGER_RISINGEDGE        0x01u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE     */
+#define RTC_TAMPERTRIGGER_FALLINGEDGE       0x02u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE     */
 #define RTC_TAMPERTRIGGER_LOWLEVEL          0x04u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
 #define RTC_TAMPERTRIGGER_HIGHLEVEL         0x08u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
 
-#if defined(TAMP_CR2_TAMP1TRG)
+#if defined(TAMP)
 #define RTC_TAMPER_1_TRIGGER                TAMP_CR2_TAMP1TRG
-#endif /* TAMP_CR2_TAMP1TRG */
-#if defined(TAMP_CR2_TAMP2TRG)
 #define RTC_TAMPER_2_TRIGGER                TAMP_CR2_TAMP2TRG
-#endif /* TAMP_CR2_TAMP2TRG */
-#if defined(TAMP_CR2_TAMP3TRG)
 #define RTC_TAMPER_3_TRIGGER                TAMP_CR2_TAMP3TRG
-#endif /* TAMP_CR2_TAMP3TRG */
-
-#if defined(RTC_TAMPCR_TAMP1TRG)
+#else
 #define RTC_TAMPER_1_TRIGGER                RTC_TAMPCR_TAMP1TRG
-#endif /* RTC_TAMPCR_TAMP1TRG */
-#if defined(RTC_TAMPCR_TAMP2TRG)
 #define RTC_TAMPER_2_TRIGGER                RTC_TAMPCR_TAMP2TRG
-#endif /* RTC_TAMPCR_TAMP2TRG */
-#if defined(RTC_TAMPCR_TAMP3TRG)
 #define RTC_TAMPER_3_TRIGGER                RTC_TAMPCR_TAMP3TRG
-#endif /* RTC_TAMPCR_TAMP3TRG */
+#endif /* TAMP */
 
 #define RTC_TAMPER_X_TRIGGER                (RTC_TAMPER_1_TRIGGER |\
                                              RTC_TAMPER_2_TRIGGER |\
@@ -420,34 +363,23 @@ typedef struct
 /** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions
 * @{
 */
-#if defined(TAMP_CR2_TAMP1NOERASE)
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE      0x00u
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE     0x01u
-#endif /* TAMP_CR2_TAMP1NOERASE */
-#if defined(RTC_TAMPCR_TAMP1NOERASE)
+#if defined(TAMP)
+#define RTC_TAMPER_ERASE_BACKUP_ENABLE     0x00u
+#define RTC_TAMPER_ERASE_BACKUP_DISABLE    0x01u
+#else
 #define RTC_TAMPER_ERASE_BACKUP_ENABLE     0x00000000u
 #define RTC_TAMPER_ERASE_BACKUP_DISABLE    RTC_TAMPCR_TAMP1NOERASE
-#endif /* RTC_TAMPCR_TAMP1NOERASE */
+#endif /* TAMP */
 
-#if defined(TAMP_CR2_TAMP1NOERASE)
+#if defined(TAMP)
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1  TAMP_CR2_TAMP1NOERASE
-#endif /* TAMP_CR2_TAMP1NOERASE */
-#if defined(TAMP_CR2_TAMP2NOERASE)
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2  TAMP_CR2_TAMP2NOERASE
-#endif /* TAMP_CR2_TAMP2NOERASE */
-#if defined(TAMP_CR2_TAMP3NOERASE)
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3  TAMP_CR2_TAMP3NOERASE
-#endif /* TAMP_CR2_TAMP3NOERASE */
-
-#if defined(RTC_TAMPCR_TAMP1NOERASE)
+#else
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1  RTC_TAMPCR_TAMP1NOERASE
-#endif /* RTC_TAMPCR_TAMP1NOERASE */
-#if defined(RTC_TAMPCR_TAMP2NOERASE)
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2  RTC_TAMPCR_TAMP2NOERASE
-#endif /* RTC_TAMPCR_TAMP2NOERASE */
-#if defined(RTC_TAMPCR_TAMP3NOERASE)
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3  RTC_TAMPCR_TAMP3NOERASE
-#endif /* RTC_TAMPCR_TAMP3NOERASE */
+#endif /* TAMP */
 
 #define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK (RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\
                                               RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\
@@ -459,34 +391,23 @@ typedef struct
 /** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions
 * @{
 */
-#if defined(TAMP_CR2_TAMP1MSK)
-#define RTC_TAMPERMASK_FLAG_DISABLE         0x00u
-#define RTC_TAMPERMASK_FLAG_ENABLE          0x01u
-#endif /* TAMP_CR2_TAMP1MSK */
-#if defined(RTC_TAMPCR_TAMP1MF)
+#if defined(TAMP)
+#define RTC_TAMPERMASK_FLAG_DISABLE        0x00u
+#define RTC_TAMPERMASK_FLAG_ENABLE         0x01u
+#else
 #define RTC_TAMPERMASK_FLAG_DISABLE        0x00000000u
 #define RTC_TAMPERMASK_FLAG_ENABLE         RTC_TAMPCR_TAMP1MF
-#endif /* RTC_TAMPCR_TAMP1MF */
+#endif /* TAMP */
 
-#if defined(TAMP_CR2_TAMP1MSK)
+#if defined(TAMP)
 #define RTC_TAMPER_1_MASK_FLAG             TAMP_CR2_TAMP1MSK
-#endif /* TAMP_CR2_TAMP1MSK */
-#if defined(TAMP_CR2_TAMP2MSK)
 #define RTC_TAMPER_2_MASK_FLAG             TAMP_CR2_TAMP2MSK
-#endif /* TAMP_CR2_TAMP2MSK */
-#if defined(TAMP_CR2_TAMP3MSK)
 #define RTC_TAMPER_3_MASK_FLAG             TAMP_CR2_TAMP3MSK
-#endif /* TAMP_CR2_TAMP3MSK */
-
-#if defined(RTC_TAMPCR_TAMP1MF)
+#else
 #define RTC_TAMPER_1_MASK_FLAG             RTC_TAMPCR_TAMP1MF
-#endif /* RTC_TAMPCR_TAMP1MF */
-#if defined(RTC_TAMPCR_TAMP2MF)
 #define RTC_TAMPER_2_MASK_FLAG             RTC_TAMPCR_TAMP2MF
-#endif /* RTC_TAMPCR_TAMP2MF */
-#if defined(RTC_TAMPCR_TAMP3MF)
 #define RTC_TAMPER_3_MASK_FLAG             RTC_TAMPCR_TAMP3MF
-#endif /* RTC_TAMPCR_TAMP3MF */
+#endif /* TAMP */
 
 #define RTC_TAMPER_X_MASK_FLAG             (RTC_TAMPER_1_MASK_FLAG |\
                                             RTC_TAMPER_2_MASK_FLAG |\
@@ -498,7 +419,7 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions
   * @{
   */
-#if defined(TAMP_FLTCR_TAMPFLT)
+#if defined(TAMP)
 #define RTC_TAMPERFILTER_DISABLE   0x00000000U             /*!< Tamper filter is disabled */
 
 #define RTC_TAMPERFILTER_2SAMPLE   TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2
@@ -509,8 +430,7 @@ typedef struct
                                                                  consecutive samples at the active level */
 #define RTC_TAMPERFILTER_MASK      TAMP_FLTCR_TAMPFLT      /*!< Masking all bits except those of
                                                                  field TAMPFLT[1:0]. */
-#endif /* TAMP_FLTCR_TAMPFLT */
-#if defined(RTC_TAMPCR_TAMPFLT)
+#else
 #define RTC_TAMPERFILTER_DISABLE   0x00000000u             /*!< Tamper filter is disabled */
 
 #define RTC_TAMPERFILTER_2SAMPLE   RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2
@@ -521,7 +441,7 @@ typedef struct
                                                                  consecutive samples at the active level. */
 #define RTC_TAMPERFILTER_MASK      RTC_TAMPCR_TAMPFLT      /*!< Masking all bits except those of
                                                                  field TAMPFLT[1:0]. */
-#endif /* RTC_TAMPCR_TAMPFLT */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -529,7 +449,7 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions
   * @{
   */
-#if defined(TAMP_FLTCR_TAMPFREQ)
+#if defined(TAMP)
 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U                                     /*!< Each of the tamper inputs are sampled
                                                                                                       with a frequency =  RTCCLK / 32768 */
 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
@@ -548,8 +468,7 @@ typedef struct
                                                                                                       with a frequency =  RTCCLK / 256   */
 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK      TAMP_FLTCR_TAMPFREQ                             /*!< Masking all bits except those of
                                                                                                       field TAMPFREQ[2:0]*/
-#endif /* TAMP_FLTCR_TAMPFREQ */
-#if defined(RTC_TAMPCR_TAMPFREQ)
+#else
 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000u                                     /*!< Each of the tamper inputs are sampled
                                                                                                       with a frequency =  RTCCLK / 32768 */
 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
@@ -568,7 +487,7 @@ typedef struct
                                                                                                       with a frequency =  RTCCLK / 256   */
 #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK      RTC_TAMPCR_TAMPFREQ                             /*!< Masking all bits except those of
                                                                                                       field TAMPFREQ[2:0]*/
-#endif /* RTC_TAMPCR_TAMPFREQ */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -576,7 +495,7 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions
   * @{
   */
-#if defined(TAMP_FLTCR_TAMPPRCH)
+#if defined(TAMP)
 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000U             /*!< Tamper pins are pre-charged before
                                                                               sampling during 1 RTCCLK cycle  */
 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0   /*!< Tamper pins are pre-charged before
@@ -587,8 +506,7 @@ typedef struct
                                                                               sampling during 8 RTCCLK cycles */
 #define RTC_TAMPERPRECHARGEDURATION_MASK        TAMP_FLTCR_TAMPPRCH     /*!< Masking all bits except those of
                                                                               field TAMPPRCH[1:0] */
-#endif /* TAMP_FLTCR_TAMPPRCH */
-#if defined(RTC_TAMPCR_TAMPPRCH)
+#else
 #define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000u             /*!< Tamper pins are pre-charged before
                                                                               sampling during 1 RTCCLK cycle  */
 #define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0   /*!< Tamper pins are pre-charged before
@@ -599,7 +517,7 @@ typedef struct
                                                                               sampling during 8 RTCCLK cycles */
 #define RTC_TAMPERPRECHARGEDURATION_MASK        RTC_TAMPCR_TAMPPRCH     /*!< Masking all bits except those of
                                                                               field TAMPPRCH[1:0] */
-#endif /* RTC_TAMPCR_TAMPPRCH */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -607,16 +525,15 @@ typedef struct
 /** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions
   * @{
   */
-#if defined(RTC_CR_TAMPTS)
+#if defined(TAMP)
 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u                   /*!< TimeStamp on Tamper Detection event is not saved */
 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS                 /*!< TimeStamp on Tamper Detection event saved        */
 #define RTC_TIMESTAMPONTAMPERDETECTION_MASK     RTC_CR_TAMPTS                 /*!< Masking all bits except bit TAMPTS               */
-#endif  /* RTC_CR_TAMPTS */
-#if defined(RTC_TAMPCR_TAMPTS)
+#else
 #define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u                   /*!< TimeStamp on Tamper Detection event is not saved */
 #define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_TAMPCR_TAMPTS             /*!< TimeStamp on Tamper Detection event saved        */
 #define RTC_TIMESTAMPONTAMPERDETECTION_MASK     RTC_TAMPCR_TAMPTS             /*!< Masking all bits except bit TAMPTS               */
-#endif /* RTC_TAMPCR_TAMPTS */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -624,16 +541,15 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions
   * @{
   */
-#if defined(TAMP_FLTCR_TAMPPUDIS)
+#if defined(TAMP)
 #define RTC_TAMPER_PULLUP_ENABLE           0x00000000u              /*!< Tamper pins are pre-charged before sampling */
 #define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS     /*!< Tamper pins pre-charge is disabled          */
 #define RTC_TAMPER_PULLUP_MASK             TAMP_FLTCR_TAMPPUDIS     /*!< Maskin all bits except bit TAMPPUDIS        */
-#endif /* TAMP_FLTCR_TAMPPUDIS */
-#if defined(RTC_TAMPCR_TAMPPUDIS)
+#else
 #define RTC_TAMPER_PULLUP_ENABLE           0x00000000u              /*!< TimeStamp on Tamper Detection event saved        */
 #define RTC_TAMPER_PULLUP_DISABLE          RTC_TAMPCR_TAMPPUDIS     /*!< TimeStamp on Tamper Detection event is not saved */
 #define RTC_TAMPER_PULLUP_MASK             RTC_TAMPCR_TAMPPUDIS     /*!< Maskin all bits except bit TAMPPUDIS        */
-#endif /* RTC_TAMPCR_TAMPPUDIS */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -641,11 +557,11 @@ typedef struct
 /** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Output Definitions
   * @{
   */
-#if defined(RTC_CR_TAMPOE)
+#if defined(TAMP)
 #define RTC_TAMPERDETECTIONOUTPUT_DISABLE  0x00000000u                   /*!< The tamper flag is not routed on TAMPALRM */
 #define RTC_TAMPERDETECTIONOUTPUT_ENABLE   RTC_CR_TAMPOE                 /*!< The tamper flag is routed on TAMPALRM combined with the signal
                                                                                provided by OSEL and with the polarity provided by POL */
-#endif  /* RTC_CR_TAMPOE */
+#endif  /* TAMP */
 /**
   * @}
   */
@@ -653,25 +569,15 @@ typedef struct
 /** @defgroup RTC_Tamper_Flags_Definitions RTC Tamper Flags Definitions
   * @{
   */
-#if defined(TAMP_SR_TAMP1F)
+#if defined(TAMP)
 #define RTC_FLAG_TAMP1F                   TAMP_SR_TAMP1F
-#endif /* TAMP_SR_TAMP1F */
-#if defined(TAMP_SR_TAMP2F)
 #define RTC_FLAG_TAMP2F                   TAMP_SR_TAMP2F
-#endif /* TAMP_SR_TAMP2F */
-#if defined(TAMP_SR_TAMP3F)
 #define RTC_FLAG_TAMP3F                   TAMP_SR_TAMP3F
-#endif /* TAMP_SR_TAMP3F */
-
-#if defined(RTC_ISR_TAMP1F)
+#else
 #define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
-#endif /* RTC_ISR_TAMP1F */
-#if defined(RTC_ISR_TAMP2F)
 #define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
-#endif /* RTC_ISR_TAMP2F */
-#if defined(RTC_ISR_TAMP3F)
 #define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F
-#endif /* RTC_ISR_TAMP3F */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -744,10 +650,10 @@ typedef struct
 /** @defgroup RTCEx_Tamper_Registers_Offset  RTC Tamper Registers Offset
   * @{
   */
-#if defined (TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 /* Add this offset to RTC registers base address to reach TAMP registers base address. */
 #define TAMP_OFFSET (TAMP_BASE - RTC_BASE)
-#endif /* TAMP_CR1_TAMP1E */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -872,12 +778,11 @@ typedef struct
   *            @arg RTC_FLAG_WUTF WakeUpTimer interrupt flag
   * @retval None
   */
-#if defined(RTC_SR_WUTF)
+#if defined(TAMP)
 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->SR)  & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* RTC_SR_WUTF */
-#if defined(RTC_ISR_WUTF)
+#else
 #define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_WUTF */
+#endif /* TAMP */
 
 /**
   * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
@@ -889,7 +794,7 @@ typedef struct
   */
 #define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
 
-#if defined(RTC_SR_WUTF)
+#if defined(TAMP)
 /**
   * @brief  Get the selected RTC WakeUpTimer's flag status.
   * @param  __HANDLE__ specifies the RTC handle.
@@ -899,8 +804,7 @@ typedef struct
   * @retval Flag status
   */
 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_SR_WUTF */
-#if defined(RTC_ISR_WUTF)
+#else
 /**
   * @brief  Get the selected RTC WakeUpTimer's flag status.
   * @param  __HANDLE__ specifies the RTC handle.
@@ -911,7 +815,7 @@ typedef struct
   * @retval Flag status
   */
 #define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_WUTF */
+#endif /* TAMP */
 
 /**
   * @brief  Clear the RTC Wake Up timer's pending flags.
@@ -921,12 +825,11 @@ typedef struct
   *            @arg @ref RTC_FLAG_WUTF
   * @retval None
   */
-#if defined(RTC_SCR_CWUTF)
+#if defined(TAMP)
 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)
-#endif /* RTC_SCR_CWUTF */
-#if defined(RTC_ISR_WUTF)
+#else
 #define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#endif /* RTC_ISR_WUTF */
+#endif /* TAMP */
 
 /* ========================================================================== */
 /*                     ##### RTC Tamper exported macros #####                 */
@@ -937,72 +840,66 @@ typedef struct
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E))
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP1E)
+#else
 #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)           ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))
-#endif /* RTC_TAMPCR_TAMP1E */
+#endif /* TAMP */
 
 /**
   * @brief  Disable the RTC Tamper1 input detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E))
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(RTC_TAMPCR_TAMP1E)
+#else
 #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))
-#endif /* RTC_TAMPCR_TAMP1E */
+#endif /* TAMP */
 
 /**
   * @brief  Enable the RTC Tamper2 input detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(TAMP_CR1_TAMP2E)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E))
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP2E)
+#else
 #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)           ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))
-#endif /* RTC_TAMPCR_TAMP2E */
+#endif /* TAMP */
 
 /**
   * @brief  Disable the RTC Tamper2 input detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(TAMP_CR1_TAMP2E)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E))
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP2E)
+#else
 #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))
-#endif /* RTC_TAMPCR_TAMP2E */
+#endif /* TAMP */
 
 /**
   * @brief  Enable the RTC Tamper3 input detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(TAMP_CR1_TAMP3E)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E))
-#endif /* TAMP_CR1_TAMP3E */
-#if defined(RTC_TAMPCR_TAMP3E)
+#else
 #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))
-#endif /* RTC_TAMPCR_TAMP3E */
+#endif /* TAMP */
 
 /**
   * @brief  Disable the RTC Tamper3 input detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(TAMP_CR1_TAMP3E)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E))
-#endif /* TAMP_CR1_TAMP3E */
-#if defined(RTC_TAMPCR_TAMP3E)
+#else
 #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))
-#endif /* RTC_TAMPCR_TAMP3E */
+#endif /* TAMP */
 
 /**
   * @brief  Enable the RTC Tamper interrupt.
@@ -1015,12 +912,11 @@ typedef struct
   *             @arg  RTC_IT_TAMP3: Tamper3 interrupt
   * @retval None
   */
-#if defined(TAMP_IER_TAMP1IE)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__))
-#endif /* TAMP_IER_TAMP1IE */
-#if defined(RTC_TAMPCR_TAMP1IE)
+#else
 #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
-#endif /* RTC_TAMPCR_TAMP1IE */
+#endif /* TAMP */
 
 /**
   * @brief  Disable the RTC Tamper interrupt.
@@ -1033,29 +929,11 @@ typedef struct
   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
   * @retval None
   */
-#if defined(TAMP_IER_TAMP1IE)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__))
-#endif /* TAMP_IER_TAMP1IE */
-#if defined(RTC_TAMPCR_TAMP1IE)
+#else
 #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
-#endif /* RTC_TAMPCR_TAMP1IE */
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_FLAG_TAMP1F: Tamper1 interrupt flag
-  *            @arg  RTC_FLAG_TAMP2F: Tamper2 interrupt flag
-  *            @arg  RTC_FLAG_TAMP3F: Tamper3 interrupt flag
-  * @retval Flag status
-  */
-#if defined(TAMP_SR_TAMP1F)
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* TAMP_SR_TAMP1F */
-#if defined(RTC_ISR_TAMP1F)
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_TAMP1F */
+#endif /* TAMP */
 
 /**
   * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
@@ -1068,12 +946,11 @@ typedef struct
   *            @arg  RTC_IT_TAMP3: Tamper3 interrupt
   * @retval Flag status
   */
-#if defined(TAMP_IER_TAMP1IE)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* TAMP_IER_TAMP1IE */
-#if defined(RTC_TAMPCR_TAMP1IE)
+#else
 #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* RTC_TAMPCR_TAMP1IE */
+#endif /* TAMP */
 
 /**
   * @brief  Get the selected RTC Tamper's flag status.
@@ -1085,12 +962,11 @@ typedef struct
   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
   * @retval Flag status
   */
-#if defined(TAMP_SR_TAMP1F)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)   ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* TAMP_SR_TAMP1F */
-#if defined(RTC_ISR_TAMP1F)
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)                               (((((__HANDLE__)->Instance->ISR)                  & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_TAMP1F */
+#else
+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)                                (((((__HANDLE__)->Instance->ISR)                 & (__FLAG__)) != 0U) ? 1U : 0U)
+#endif /* TAMP */
 
 /**
   * @brief  Clear the RTC Tamper's pending flags.
@@ -1102,12 +978,11 @@ typedef struct
   *             @arg RTC_FLAG_TAMP3F: Tamper3 flag
   * @retval None
   */
-#if defined(TAMP_SCR_CTAMP1F)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__))
-#endif /* TAMP_SCR_CTAMP1F */
-#if defined(RTC_ISR_TAMP1F)
+#else
 #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#endif /* RTC_ISR_TAMP1F */
+#endif /* TAMP */
 
 /**
   * @brief  Get the frequency at which each of the Tamper inputs are sampled.
@@ -1122,12 +997,11 @@ typedef struct
   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512
   *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256
   */
-#if defined(TAMP_FLTCR_TAMPFREQ)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))
-#endif /* TAMP_FLTCR_TAMPFREQ */
-#if defined(RTC_TAMPCR_TAMPFREQ)
+#else
 #define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))
-#endif /* RTC_TAMPCR_TAMPFREQ */
+#endif /* TAMP */
 
 /**
   * @brief  Get the number of consecutive samples at the specified level needed
@@ -1140,12 +1014,11 @@ typedef struct
   *            @arg RTC_TAMPERFILTER_4SAMPLE
   *            @arg RTC_TAMPERFILTER_8SAMPLE
   */
-#if defined(TAMP_FLTCR_TAMPFLT)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK)))
-#endif /* TAMP_FLTCR_TAMPFLT */
-#if defined(RTC_TAMPCR_TAMPFLT)
+#else
 #define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERFILTER_MASK)))
-#endif /* RTC_TAMPCR_TAMPFLT */
+#endif /* TAMP */
 
 /**
   * @brief  Get the pull-up resistors precharge duration.
@@ -1157,12 +1030,11 @@ typedef struct
   *            @arg RTC_TAMPERPRECHARGEDURATION_4RTCCLK
   *            @arg RTC_TAMPERPRECHARGEDURATION_8RTCCLK
   */
-#if defined(TAMP_FLTCR_TAMPPRCH)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))
-#endif /* TAMP_FLTCR_TAMPPRCH */
-#if defined(RTC_TAMPCR_TAMPPRCH)
+#else
 #define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))
-#endif /* RTC_TAMPCR_TAMPPRCH */
+#endif /* TAMP */
 
 /**
   * @brief  Get the pull-up resistors status.
@@ -1172,12 +1044,11 @@ typedef struct
   *            @arg RTC_TAMPER_PULLUP_ENABLE
   *            @arg RTC_TAMPER_PULLUP_DISABLE
   */
-#if defined(TAMP_FLTCR_TAMPPUDIS)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK)))
-#endif /* TAMP_FLTCR_TAMPPUDIS */
-#if defined(RTC_TAMPCR_TAMPPUDIS)
+#else
 #define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPER_PULLUP_MASK)))
-#endif /* RTC_TAMPCR_TAMPPUDIS */
+#endif /* TAMP */
 
 /* ========================================================================== */
 /*                  ##### RTC TimeStamp exported macros #####                 */
@@ -1225,12 +1096,11 @@ typedef struct
   *            @arg @ref RTC_IT_TS TimeStamp interrupt
   * @retval None
   */
-#if defined(RTC_SR_TSF)
+#if defined(TAMP)
 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U)
-#endif /* RTC_SR_TSF */
-#if defined(RTC_ISR_TSF)
+#else
 #define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_TSF */
+#endif /* TAMP */
 /**
   * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
   * @param  __HANDLE__ specifies the RTC handle.
@@ -1250,12 +1120,11 @@ typedef struct
   *            @arg RTC_FLAG_TSOVF
   * @retval Flag status
   */
-#if defined(RTC_SR_TSF)
+#if defined(TAMP)
 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_SR_TSF */
-#if defined(RTC_ISR_TSF)
+#else
 #define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_TSF */
+#endif /* TAMP */
 
 /**
   * @brief  Clear the RTC Time Stamp's pending flags.
@@ -1266,12 +1135,11 @@ typedef struct
   *             @arg RTC_FLAG_TSOVF
   * @retval None
   */
-#if defined(RTC_SCR_CTSF)
+#if defined(TAMP)
 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->SCR |= __FLAG__)
-#endif /* RTC_SCR_CTSF */
-#if defined(RTC_ISR_TSF)
+#else
 #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
-#endif /* RTC_ISR_TSF */
+#endif /* TAMP */
 
 /**
   * @brief  Enable the RTC internal TimeStamp peripheral.
@@ -1295,12 +1163,11 @@ typedef struct
   *            @arg RTC_FLAG_ITSF
   * @retval Flag status
   */
-#if defined(RTC_SR_ITSF)
+#if defined(TAMP)
 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_SR_ITSF */
-#if defined(RTC_ISR_ITSF)
+#else
 #define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_ITSF */
+#endif /* TAMP */
 
 /**
   * @brief  Clear the RTC Internal Time Stamp's pending flags.
@@ -1311,36 +1178,33 @@ typedef struct
   * @note   This flag must be cleared together with TSF flag.
   * @retval None
   */
-#if defined(RTC_SCR_CITSF)
+#if defined(TAMP)
 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->SCR |= __FLAG__)
-#endif /* RTC_SCR_CITSF */
-#if defined(RTC_ISR_ITSF)
+#else
 #define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
-#endif /* RTC_ISR_ITSF */
+#endif /* TAMP */
 
 /**
   * @brief  Enable the RTC TimeStamp on Tamper detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(RTC_CR_TAMPTS)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))
-#endif /* RTC_CR_TAMPTS */
-#if defined(RTC_TAMPCR_TAMPTS)
+#else
 #define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->TAMPCR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))
-#endif /* RTC_TAMPCR_TAMPTS */
+#endif /* TAMP */
 
 /**
   * @brief  Disable the RTC TimeStamp on Tamper detection.
   * @param  __HANDLE__ specifies the RTC handle.
   * @retval None
   */
-#if defined(RTC_CR_TAMPTS)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))
-#endif /* RTC_CR_TAMPTS */
-#if defined(RTC_TAMPCR_TAMPTS)
+#else
 #define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))
-#endif /* RTC_TAMPCR_TAMPTS */
+#endif /* TAMP */
 
 /**
   * @brief  Get activation status of the RTC TimeStamp on Tamper detection.
@@ -1350,14 +1214,13 @@ typedef struct
   *            @arg RTC_TIMESTAMPONTAMPERDETECTION_ENABLE
   *            @arg RTC_TIMESTAMPONTAMPERDETECTION_DISABLE
   */
-#if defined(RTC_CR_TAMPTS)
+#if defined(TAMP)
 #define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__)                   ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)
-#endif /* RTC_CR_TAMPTS */
-#if defined(RTC_TAMPCR_TAMPTS)
+#else
 #define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__)                   ((__HANDLE__)->Instance->TAMPCR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)
-#endif /* RTC_TAMPCR_TAMPTS */
+#endif /* TAMP */
 
-#if defined(RTC_CR_TAMPOE)
+#if defined(TAMP)
 /**
   * @brief  Enable the RTC Tamper detection output.
   * @param  __HANDLE__ specifies the RTC handle.
@@ -1371,7 +1234,7 @@ typedef struct
   * @retval None
   */
 #define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
-#endif /* RTC_CR_TAMPOE */
+#endif /* TAMP */
 
 /* ========================================================================== */
 /*         ##### Extended RTC Peripheral Control exported macros #####        */
@@ -1413,12 +1276,11 @@ typedef struct
   *             @arg RTC_FLAG_SHPF
   * @retval Flag status
   */
-#if defined(RTC_ICSR_SHPF)
+#if defined(TAMP)
 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ICSR_SHPF */
-#if defined(RTC_ISR_SHPF)
+#else
 #define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR)  & (__FLAG__)) != 0U) ? 1U : 0U)
-#endif /* RTC_ISR_SHPF */
+#endif /* TAMP */
 
 /* ========================================================================== */
 /*               ##### RTC Wake-up Interrupt exported macros #####            */
@@ -1799,30 +1661,17 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3
 HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
 HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-#if defined(RTC_TAMPER_1)
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER_1 */
-#if defined(RTC_TAMPER_2)
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER_2 */
-#if defined(RTC_TAMPER_3)
 HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* RTC_TAMPER_3 */
-#if defined(RTC_TAMPER_1)
 void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER_1 */
-#if defined(RTC_TAMPER_2)
 void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER_2 */
-#if defined(RTC_TAMPER_3)
 void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* RTC_TAMPER_3 */
-#if defined(TAMP_CR1_ITAMP1E)
+#if defined(TAMP)
 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
 HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
 HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
-#endif /* TAMP_CR1_ITAMP1E */
 void              HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
 void              HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
 void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
@@ -1830,15 +1679,10 @@ void              HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc
 void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
 void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
 void              HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(TAMP_ATCR1_TAMP1AM)
 HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper);
-#endif /* TAMP_ATCR1_TAMP1AM */
-#if defined(TAMP_ATSEEDR_SEED)
 HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed);
-#endif /* TAMP_ATSEEDR_SEED */
-#if defined(TAMP_ATCR1_TAMP1AM)
 HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc);
-#endif /* TAMP_ATCR1_TAMP1AM */
+#endif /* TAMP */
 
 /**
   * @}
@@ -1896,10 +1740,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-#if defined(TAMP_COUNTR)
+#if defined(TAMP)
 HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc,  uint32_t Instance);
 HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter,  uint32_t Instance);
-#endif /* TAMP_COUNTR */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -2006,15 +1850,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 #define IS_RTC_TAMPER(__TAMPER__)  ((((__TAMPER__) &  RTC_TAMPER_X) != 0x00U) &&  \
                                     (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U))
 
-#if defined(RTC_ALL_TAMPER_INTERRUPT)
 #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)                                                           \
-              ((((__INTERRUPT__) & (  RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT )) != 0x00U) &&  \
-               (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))) == 0x00U))
-#else  /* RTC_ALL_TAMPER_INTERRUPT not defined */
-#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)                              \
-              ((((__INTERRUPT__) &   RTC_TAMPER_X_INTERRUPT ) != 0x00U) &&  \
-               (((__INTERRUPT__) & (~RTC_TAMPER_X_INTERRUPT)) == 0x00U))
-#endif /* RTC_ALL_TAMPER_INTERRUPT */
+              ((((__INTERRUPT__) & (  RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL )) != 0x00U) &&  \
+               (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_IT_TAMPALL))) == 0x00U))
 
 #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)    || \
                                             ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE)   || \
@@ -2052,10 +1890,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 #define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
                                                                   ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
 
-#if defined(RTC_CR_TAMPOE)
+#if defined(TAMP)
 #define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(__MODE__) (((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
                                                        ((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
-#endif /* RTC_CR_TAMPOE */
+#endif /* TAMP */
 
 #define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER)            \
                   (  (  ((FILTER) != RTC_TAMPERFILTER_DISABLE)          \
@@ -2090,4 +1928,3 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
 
 #endif /* STM32H7xx_HAL_RTC_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c
index fefb0116e0..6a1143316c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                   ##### How to use this driver #####
@@ -161,7 +172,7 @@
 
     [..]
     Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
+    weak function.
     HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the callback ID.
     [..]
@@ -176,10 +187,10 @@
 
     [..]
     By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
-    all callbacks are reset to the corresponding legacy weak (surcharged) functions:
+    all callbacks are reset to the corresponding legacy weak functions:
     examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
     Exception done for MspInit and MspDeInit callbacks that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
+    reset to the legacy weak functions in the HAL_SAI_Init
     and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
     If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -196,21 +207,9 @@
     [..]
     When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registering feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak callbacks are used.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -246,6 +245,8 @@ typedef enum
   */
 #define SAI_DEFAULT_TIMEOUT      4U
 #define SAI_LONG_TIMEOUT         1000U
+#define SAI_SPDIF_FRAME_LENGTH   64U
+#define SAI_AC97_FRAME_LENGTH    256U
 /**
   * @}
   */
@@ -391,7 +392,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
   assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
   assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
   assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
-#if defined(SAI_VER_V2_X) 
+#if defined(SAI_VER_V2_X)
   /* SAI Peripheral version depends on STM32H7 device revision ID */
   if (HAL_GetREVID() >= REV_ID_B) /* STM32H7xx Rev.B and above */
   {
@@ -621,12 +622,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
       if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
       {
         /* For SPDIF protocol, frame length is set by hardware to 64 */
-        tmpframelength = 64U;
+        tmpframelength = SAI_SPDIF_FRAME_LENGTH;
       }
       else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
       {
         /* For AC97 protocol, frame length is set by hardware to 256 */
-        tmpframelength = 256U;
+        tmpframelength = SAI_AC97_FRAME_LENGTH;
       }
       else
       {
@@ -1515,6 +1516,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
   /* Process Locked */
   __HAL_LOCK(hsai);
 
+  /* Disable SAI peripheral */
+  if (SAI_Disable(hsai) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+
   /* Disable the SAI DMA request */
   hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
 
@@ -1546,12 +1553,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
     }
   }
 
-  /* Disable SAI peripheral */
-  if (SAI_Disable(hsai) != HAL_OK)
-  {
-    status = HAL_ERROR;
-  }
-
   /* Flush the fifo */
   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
 
@@ -1577,6 +1578,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
   /* Process Locked */
   __HAL_LOCK(hsai);
 
+  /* Disable SAI peripheral */
+  if (SAI_Disable(hsai) != HAL_OK)
+  {
+    status = HAL_ERROR;
+  }
+
   /* Check SAI DMA is enabled or not */
   if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
   {
@@ -1616,12 +1623,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
   hsai->Instance->IMR = 0;
   hsai->Instance->CLRFR = 0xFFFFFFFFU;
 
-  /* Disable SAI peripheral */
-  if (SAI_Disable(hsai) != HAL_OK)
-  {
-    status = HAL_ERROR;
-  }
-
   /* Flush the fifo */
   SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
 
@@ -2249,7 +2250,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai)
   *              the configuration information for SAI module.
   * @retval HAL state
   */
-HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
+HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai)
 {
   return hsai->State;
 }
@@ -2260,7 +2261,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai)
   *              the configuration information for the specified SAI Block.
   * @retval SAI Error Code
   */
-uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai)
+uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai)
 {
   return hsai->ErrorCode;
 }
@@ -2943,4 +2944,3 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.h
index 7db7eb8a80..f9ca3649bb 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -817,8 +816,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
   * @{
   */
 /* Peripheral State functions  ************************************************/
-HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
-uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
+HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai);
+uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai);
 /**
   * @}
   */
@@ -984,4 +983,3 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 
 #endif /* STM32H7xx_HAL_SAI_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.c
index 2af598fc8b..702e1309de 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.c
@@ -10,13 +10,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -68,7 +67,8 @@
   * @param  pdmMicDelay Microphone delays configuration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
+                                              const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
 {
   HAL_StatusTypeDef status = HAL_OK;
   uint32_t offset;
@@ -132,4 +132,3 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.h
index d323c59c9a..edc87c2861 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -70,7 +69,8 @@ typedef struct
 /** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
   * @{
   */
-HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(const SAI_HandleTypeDef *hsai,
+                                              const SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
 /**
   * @}
   */
@@ -102,4 +102,3 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
 
 #endif /* STM32H7xx_HAL_SAI_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c
index 6bf4dcc5d2..704d1bafc7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -182,7 +193,7 @@
     The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
 
-    Use Functions @ref HAL_SD_RegisterCallback() to register a user callback,
+    Use Functions HAL_SD_RegisterCallback() to register a user callback,
     it allows to register following callbacks:
       (+) TxCpltCallback : callback when a transmission transfer is completed.
       (+) RxCpltCallback : callback when a reception transfer is completed.
@@ -197,9 +208,9 @@
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
     For specific callbacks TransceiverCallback use dedicated register callbacks:
-    respectively @ref HAL_SD_RegisterTransceiverCallback().
+    respectively HAL_SD_RegisterTransceiverCallback().
 
-    Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default
+    Use function HAL_SD_UnRegisterCallback() to reset a callback to the default
     weak (surcharged) function. It allows to reset following callbacks:
       (+) TxCpltCallback : callback when a transmission transfer is completed.
       (+) RxCpltCallback : callback when a reception transfer is completed.
@@ -213,14 +224,14 @@
       (+) MspDeInitCallback  : SD MspDeInit.
     This function) takes as parameters the HAL peripheral handle and the Callback ID.
     For specific callbacks TransceiverCallback use dedicated unregister callbacks:
-    respectively @ref HAL_SD_UnRegisterTransceiverCallback().
+    respectively HAL_SD_UnRegisterTransceiverCallback().
 
-    By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET
+    By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET
     all callbacks are reset to the corresponding legacy weak (surcharged) functions.
     Exception done for MspInit and MspDeInit callbacks that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init
-    and @ref  HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit
+    reset to the legacy weak (surcharged) functions in the HAL_SD_Init
+    and HAL_SD_DeInit only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
     Callbacks can be registered/unregistered in READY state only.
@@ -228,8 +239,8 @@
     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
     during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit
-    or @ref HAL_SD_Init function.
+    using HAL_SD_RegisterCallback before calling HAL_SD_DeInit
+    or HAL_SD_Init function.
 
     When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registering feature is not available
@@ -237,17 +248,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -269,7 +269,7 @@
   * @{
   */
 /* Frequencies used in the driver for clock divider calculation */
-#define SD_INIT_FREQ                   400000U   /* Initalization phase : 400 kHz max */
+#define SD_INIT_FREQ                   400000U   /* Initialization phase : 400 kHz max */
 #define SD_NORMAL_SPEED_FREQ           25000000U /* Normal speed phase : 25 MHz max */
 #define SD_HIGH_SPEED_FREQ             50000000U /* High speed phase : 50 MHz max */
 /* Private macro -------------------------------------------------------------*/
@@ -300,9 +300,9 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);
 static void     SD_PowerOFF(SD_HandleTypeDef *hsd);
 static void     SD_Write_IT(SD_HandleTypeDef *hsd);
 static void     SD_Read_IT(SD_HandleTypeDef *hsd);
-static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode);
 #if (USE_SD_TRANSCEIVER != 0U)
-static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode);
 static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
 #endif /* USE_SD_TRANSCEIVER */
 /**
@@ -398,7 +398,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
 #endif /* USE_HAL_SD_REGISTER_CALLBACKS */
   }
 
-  hsd->State = HAL_SD_STATE_BUSY;
+  hsd->State = HAL_SD_STATE_PROGRAMMING;
 
   /* Initialize the Card parameters */
   if (HAL_SD_InitCard(hsd) != HAL_OK)
@@ -509,8 +509,15 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
 
   /* wait 74 Cycles: required power up waiting time before starting
      the SD initialization sequence */
-  sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
-  HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  if (Init.ClockDiv != 0U)
+  {
+    sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv);
+  }
+
+  if (sdmmc_clk != 0U)
+  {
+    HAL_Delay(1U + (74U * 1000U / (sdmmc_clk)));
+  }
 
   /* Identify card operating voltage */
   errorstate = SD_PowerON(hsd);
@@ -847,8 +854,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3
   * @param  Timeout: Specify timeout value
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
-                                     uint32_t Timeout)
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks, uint32_t Timeout)
 {
   SDMMC_DataInitTypeDef config;
   uint32_t errorstate;
@@ -857,7 +864,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint
   uint32_t data;
   uint32_t dataremaining;
   uint32_t add = BlockAdd;
-  uint8_t *tempbuff = pData;
+  const uint8_t *tempbuff = pData;
 
   if (NULL == pData)
   {
@@ -1129,7 +1136,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui
   * @param  NumberOfBlocks: Number of blocks to write
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
                                         uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -1325,7 +1332,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
   * @param  NumberOfBlocks: Number of blocks to write
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
                                          uint32_t NumberOfBlocks)
 {
   SDMMC_DataInitTypeDef config;
@@ -1854,6 +1861,9 @@ __weak  void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status)
 /**
   * @brief  Register a User SD Callback
   *         To be used instead of the weak (surcharged) predefined callback
+  * @note   The HAL_SD_RegisterCallback() may be called before HAL_SD_Init() in 
+  *         HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID 
+  *         and HAL_SD_MSP_DEINIT_CB_ID.
   * @param hsd : SD handle
   * @param CallbackID : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -1882,9 +1892,6 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hsd);
-
   if (hsd->State == HAL_SD_STATE_READY)
   {
     switch (CallbackID)
@@ -1953,14 +1960,15 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsd);
   return status;
 }
 
 /**
   * @brief  Unregister a User SD Callback
   *         SD Callback is redirected to the weak (surcharged) predefined callback
+  * @note   The HAL_SD_UnRegisterCallback() may be called before HAL_SD_Init() in 
+  *         HAL_SD_STATE_RESET to register callbacks for HAL_SD_MSP_INIT_CB_ID 
+  *         and HAL_SD_MSP_DEINIT_CB_ID.
   * @param hsd : SD handle
   * @param CallbackID : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -1980,9 +1988,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hsd);
-
   if (hsd->State == HAL_SD_STATE_READY)
   {
     switch (CallbackID)
@@ -2051,8 +2056,6 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsd);
   return status;
 }
 
@@ -2295,7 +2298,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef
 }
 
 /**
-  * @brief  Gets the SD status info.
+  * @brief  Gets the SD status info.( shall be called if there is no SD transaction ongoing )
   * @param  hsd: Pointer to SD handle
   * @param  pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
   *         will contain the SD card status information
@@ -2307,6 +2310,11 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
   uint32_t errorstate;
   HAL_StatusTypeDef status = HAL_OK;
 
+  if (hsd->State == HAL_SD_STATE_BUSY)
+  {
+    return HAL_ERROR;
+  }
+
   errorstate = SD_SendSDStatus(hsd, sd_status);
   if (errorstate != HAL_SD_ERROR_NONE)
   {
@@ -2355,6 +2363,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT
     status = HAL_ERROR;
   }
 
+
   return status;
 }
 
@@ -2429,7 +2438,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
   }
   else
   {
-    /* MMC Card does not support this feature */
+    /* SD Card does not support this feature */
     hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
   }
 
@@ -2476,7 +2485,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
         }
         else
         {
-          if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ)
           {
             Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ);
           }
@@ -2502,7 +2511,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t
         }
         else
         {
-          if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
+          if ((sdmmc_clk / (2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ)
           {
             Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ);
           }
@@ -2577,9 +2586,9 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
         {
           hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
           /* Enable Ultra High Speed */
-          if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
           {
-            if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+            if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
             {
               hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
               status = HAL_ERROR;
@@ -2589,7 +2598,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
         else if (hsd->SdCard.CardSpeed  == CARD_HIGH_SPEED)
         {
           /* Enable High Speed */
-          if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
           {
             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
             status = HAL_ERROR;
@@ -2601,13 +2610,33 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
         }
         break;
       }
-      case SDMMC_SPEED_MODE_ULTRA:
+      case SDMMC_SPEED_MODE_ULTRA_SDR104:
       {
         if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
         {
           /* Enable UltraHigh Speed */
-          if (SD_UltraHighSpeed(hsd) != HAL_SD_ERROR_NONE)
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR104_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+          {
+            hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+            status = HAL_ERROR;
+          }
+          hsd->Instance->CLKCR |= SDMMC_CLKCR_BUSSPEED;
+        }
+        else
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+        break;
+      }
+      case SDMMC_SPEED_MODE_ULTRA_SDR50:
+      {
+        if ((hsd->SdCard.CardSpeed  == CARD_ULTRA_HIGH_SPEED) ||
+            (hsd->SdCard.CardType == CARD_SDHC_SDXC))
+        {
+          /* Enable UltraHigh Speed */
+          if (SD_UltraHighSpeed(hsd, SDMMC_SDR50_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
           {
             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
             status = HAL_ERROR;
@@ -2648,7 +2677,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
         {
           /* Enable High Speed */
-          if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
           {
             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
             status = HAL_ERROR;
@@ -2662,7 +2691,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
         break;
       }
       case SDMMC_SPEED_MODE_DEFAULT:
+      {
+        /* Switch to default Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+
         break;
+      }
       default:
         hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
         status = HAL_ERROR;
@@ -2680,7 +2718,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
         {
           /* Enable High Speed */
-          if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
           {
             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
             status = HAL_ERROR;
@@ -2699,7 +2737,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
             (hsd->SdCard.CardType == CARD_SDHC_SDXC))
         {
           /* Enable High Speed */
-          if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+          if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
           {
             hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
             status = HAL_ERROR;
@@ -2713,7 +2751,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
         break;
       }
       case SDMMC_SPEED_MODE_DEFAULT:
+      {
+        /* Switch to default Speed */
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+        {
+          hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+          status = HAL_ERROR;
+        }
+
         break;
+      }
       case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
       default:
         hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -2731,7 +2778,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
           (hsd->SdCard.CardType == CARD_SDHC_SDXC))
       {
         /* Enable High Speed */
-        if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
         {
           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
           status = HAL_ERROR;
@@ -2750,7 +2797,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
           (hsd->SdCard.CardType == CARD_SDHC_SDXC))
       {
         /* Enable High Speed */
-        if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE)
+        if (SD_SwitchSpeed(hsd, SDMMC_SDR25_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
         {
           hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
           status = HAL_ERROR;
@@ -2764,7 +2811,16 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
       break;
     }
     case SDMMC_SPEED_MODE_DEFAULT:
+    {
+      /* Switch to default Speed */
+      if (SD_SwitchSpeed(hsd, SDMMC_SDR12_SWITCH_PATTERN) != HAL_SD_ERROR_NONE)
+      {
+        hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
+        status = HAL_ERROR;
+      }
+
       break;
+    }
     case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/
     default:
       hsd->ErrorCode |= HAL_SD_ERROR_PARAM;
@@ -2830,35 +2886,94 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
   */
 HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd)
 {
-  HAL_SD_CardStateTypeDef CardState;
+  uint32_t error_code;
+  uint32_t tickstart;
 
-  /* DIsable All interrupts */
-  __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
-                      SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
-
-  /* Clear All flags */
-  __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
-
-  /* If IDMA Context, disable Internal DMA */
-  hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
-
-  hsd->State = HAL_SD_STATE_READY;
-
-  /* Initialize the SD operation */
-  hsd->Context = SD_CONTEXT_NONE;
-
-  CardState = HAL_SD_GetCardState(hsd);
-  if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING))
+  if (hsd->State == HAL_SD_STATE_BUSY)
   {
+    /* DIsable All interrupts */
+    __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \
+                         SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR);
+    __SDMMC_CMDTRANS_DISABLE(hsd->Instance);
+
+    /*we will send the CMD12 in all cases in order to stop the data transfers*/
+    /*In case the data transfer just finished , the external memory will not respond and will return HAL_SD_ERROR_CMD_RSP_TIMEOUT*/
+    /*In case the data transfer aborted , the external memory will respond and will return HAL_SD_ERROR_NONE*/
+    /*Other scenario will return HAL_ERROR*/
+
     hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance);
-  }
-  if (hsd->ErrorCode != HAL_SD_ERROR_NONE)
-  {
-    return HAL_ERROR;
+    error_code = hsd->ErrorCode;
+    if ((error_code != HAL_SD_ERROR_NONE) && (error_code != HAL_SD_ERROR_CMD_RSP_TIMEOUT))
+    {
+      return HAL_ERROR;
+    }
+
+    tickstart = HAL_GetTick();
+    if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_CARD)
+    {
+      if (hsd->ErrorCode == HAL_SD_ERROR_NONE)
+      {
+         while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_BUSYD0END))
+        {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+              hsd->State = HAL_SD_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+        }
+      }
+
+      if (hsd->ErrorCode == HAL_SD_ERROR_CMD_RSP_TIMEOUT)
+      {
+        while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND))
+        {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+              hsd->State = HAL_SD_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+        }
+      }
+    }
+    else if ((hsd->Instance->DCTRL & SDMMC_DCTRL_DTDIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)
+    {
+      while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DABORT | SDMMC_FLAG_DATAEND))
+      {
+           if ((HAL_GetTick() - tickstart) >=  SDMMC_DATATIMEOUT)
+           {
+              hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
+              hsd->State = HAL_SD_STATE_READY;
+              return HAL_TIMEOUT;
+           }
+      }
+    }
+    else
+    {
+      /* Nothing to do*/
+    }
+
+    /*The reason of all these while conditions previously is that we need to wait the SDMMC and clear
+      the appropriate flags that will be set depending of the abort/non abort of the memory */
+    /*Not waiting the SDMMC flags will cause the next SDMMC_DISABLE_IDMA to not get cleared
+      and will result in next SDMMC read/write operation to fail */
+
+    /*SDMMC ready for clear data flags*/
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_BUSYD0END);
+    __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
+      /* If IDMA Context, disable Internal DMA */
+    hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
+
+    hsd->State = HAL_SD_STATE_READY;
+
+    /* Initialize the SD operation */
+    hsd->Context = SD_CONTEXT_NONE;
   }
   return HAL_OK;
 }
 
+
 /**
   * @brief  Abort the current transfer and disable the SD (IT mode).
   * @param  hsd: pointer to a SD_HandleTypeDef structure that contains
@@ -2926,7 +3041,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
 {
   HAL_SD_CardCSDTypeDef CSD;
   uint32_t errorstate;
-  uint16_t sd_rca = 1U;
+  uint16_t sd_rca = 0U;
+  uint32_t tickstart = HAL_GetTick();
 
   /* Check the power State */
   if (SDMMC_GetPowerState(hsd->Instance) == 0U)
@@ -2957,10 +3073,17 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
   {
     /* Send CMD3 SET_REL_ADDR with argument 0 */
     /* SD Card publishes its RCA. */
-    errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
-    if (errorstate != HAL_SD_ERROR_NONE)
+    while (sd_rca == 0U)
     {
-      return errorstate;
+      errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca);
+      if (errorstate != HAL_SD_ERROR_NONE)
+      {
+        return errorstate;
+      }
+      if ((HAL_GetTick() - tickstart) >=  SDMMC_CMDTIMEOUT)
+      {
+        return HAL_SD_ERROR_TIMEOUT;
+      }
     }
   }
   if (hsd->SdCard.CardType != CARD_SECURED)
@@ -3030,7 +3153,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
 
   /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
   errorstate = SDMMC_CmdOperCond(hsd->Instance);
-  if (errorstate != HAL_SD_ERROR_NONE)
+  if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */
   {
     hsd->SdCard.CardVersion = CARD_V1_X;
     /* CMD0: GO_IDLE_STATE */
@@ -3088,7 +3211,10 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
     return HAL_SD_ERROR_INVALID_VOLTRANGE;
   }
 
-  if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
+  /* Set default card type */
+  hsd->SdCard.CardType = CARD_SDSC;
+
+  if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY)
   {
     hsd->SdCard.CardType = CARD_SDHC_SDXC;
 #if (USE_SD_TRANSCEIVER != 0U)
@@ -3554,7 +3680,7 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
 {
   uint32_t count;
   uint32_t data;
-  uint8_t *tmp;
+  const uint8_t *tmp;
 
   tmp = hsd->pTxBuffPtr;
 
@@ -3583,11 +3709,12 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd)
   * @brief  Switches the SD card to High Speed mode.
   *         This API must be used after "Transfer State"
   * @note   This operation should be followed by the configuration
-  *         of PLL to have SDMMCCK clock between 50 and 120 MHz
+  *         of PLL to have SDMMCCK clock between 25 and 50 MHz
   * @param  hsd: SD handle
+  * @param  SwitchSpeedMode: SD speed mode( SDMMC_SDR12_SWITCH_PATTERN, SDMMC_SDR25_SWITCH_PATTERN)
   * @retval SD Card error state
   */
-uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
+uint32_t SD_SwitchSpeed(SD_HandleTypeDef *hsd, uint32_t SwitchSpeedMode)
 {
   uint32_t errorstate = HAL_SD_ERROR_NONE;
   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -3602,7 +3729,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
     return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
   }
 
-  if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED)
+  if (hsd->SdCard.CardSpeed >= CARD_HIGH_SPEED)
   {
     /* Initialize the Data control register */
     hsd->Instance->DCTRL = 0;
@@ -3624,7 +3751,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
     (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure);
 
 
-    errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN);
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, SwitchSpeedMode);
     if (errorstate != HAL_SD_ERROR_NONE)
     {
       return errorstate;
@@ -3698,9 +3825,10 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
   * @note   This operation should be followed by the configuration
   *         of PLL to have SDMMCCK clock between 50 and 120 MHz
   * @param  hsd: SD handle
+  * @param  UltraHighSpeedMode: SD speed mode( SDMMC_SDR50_SWITCH_PATTERN, SDMMC_SDR104_SWITCH_PATTERN)
   * @retval SD Card error state
   */
-static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
+static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd, uint32_t UltraHighSpeedMode)
 {
   uint32_t errorstate = HAL_SD_ERROR_NONE;
   SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@@ -3739,7 +3867,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
       return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
     }
 
-    errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN);
+    errorstate = SDMMC_CmdSwitch(hsd->Instance, UltraHighSpeedMode);
     if (errorstate != HAL_SD_ERROR_NONE)
     {
       return errorstate;
@@ -4028,5 +4156,3 @@ __weak void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h
index 83c97aba1a..83fa74fded 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -127,7 +126,7 @@ typedef struct
 
   HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
 
-  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
+  const uint8_t                *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
 
   uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
 
@@ -298,7 +297,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
   */
 
 /* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants Exported Constants
+/** @defgroup SD_Exported_Constants SD Exported Constants
   * @{
   */
 
@@ -635,18 +634,18 @@ void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
 /* Blocking mode: Polling */
 HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
                                     uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks,
-                                     uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
+                                     uint32_t NumberOfBlocks, uint32_t Timeout);
 HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
 /* Non-Blocking mode: IT */
 HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
                                        uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
                                         uint32_t NumberOfBlocks);
 /* Non-Blocking mode: DMA */
 HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
                                         uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd,
+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, const uint8_t *pData, uint32_t BlockAdd,
                                          uint32_t NumberOfBlocks);
 
 void              HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
@@ -799,5 +798,3 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
 
 
 #endif /* STM32H7xx_HAL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c
index 67124cb771..1cc19e3135 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c
@@ -7,6 +7,17 @@
   *          functionalities of the Secure Digital (SD) peripheral:
   *           + Extended features functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -19,17 +30,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -311,9 +311,3 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu
 /**
   * @}
   */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h
index 9c71954d93..450e7dfad1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -109,5 +108,3 @@ void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
 
 
 #endif /* stm32h7xx_HAL_SD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c
index 47c34a5d8d..8859a08cdd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c
@@ -6,6 +6,17 @@
   *          This file provides a generic firmware to drive SDRAM memories mounted
   *          as external device.
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                        ##### How to use this driver #####
@@ -63,25 +74,25 @@
       The compilation define  USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
       allows the user to configure dynamically the driver callbacks.
 
-      Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback,
+      Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
         (+) MspInitCallback    : SDRAM MspInit.
         (+) MspDeInitCallback  : SDRAM MspDeInit.
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
-      Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
+      Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
         (+) MspInitCallback    : SDRAM MspInit.
         (+) MspDeInitCallback  : SDRAM MspDeInit.
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-      By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init
-      and @ref  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit
+      reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
+      and  HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
       Callbacks can be registered/unregistered in READY state only.
@@ -89,26 +100,15 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit
-      or @ref HAL_SDRAM_Init function.
+      using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
+      or HAL_SDRAM_Init function.
 
       When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak (overridden) callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -131,9 +131,15 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
+  * @{
+  */
 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma);
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
@@ -787,7 +793,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User SDRAM Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hsdram : SDRAM handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -808,9 +814,6 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hsdram);
-
   state = hsdram->State;
   if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
   {
@@ -853,14 +856,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsdram);
   return status;
 }
 
 /**
   * @brief  Unregister a User SDRAM Callback
-  *         SDRAM Callback is redirected to the weak (surcharged) predefined callback
+  *         SDRAM Callback is redirected to the weak predefined callback
   * @param hsdram : SDRAM handle
   * @param CallbackId : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -876,9 +877,6 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_
   HAL_StatusTypeDef status = HAL_OK;
   HAL_SDRAM_StateTypeDef state;
 
-  /* Process locked */
-  __HAL_LOCK(hsdram);
-
   state = hsdram->State;
   if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
   {
@@ -927,14 +925,12 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsdram);
   return status;
 }
 
 /**
   * @brief  Register a User SDRAM Callback for DMA transfers
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hsdram : SDRAM handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -1231,6 +1227,9 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
   * @}
   */
 
+/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
+  * @{
+  */
 /**
   * @brief  MDMA SDRAM process complete callback.
   * @param  hmdma : MDMA handle
@@ -1297,6 +1296,9 @@ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
 }
 
+/**
+  * @}
+  */
 /**
   * @}
   */
@@ -1307,5 +1309,3 @@ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
   * @}
   */
 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h
index ba189d4398..cee1ffdd39 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -235,5 +234,3 @@ HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
 #endif
 
 #endif /* STM32H7xx_HAL_SDRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c
index 900480304c..4641fc2c9e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State and Error functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -125,7 +136,7 @@
 
     [..]
     Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
+    weak function.
     HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
@@ -142,10 +153,10 @@
 
     [..]
     By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
+    all callbacks are set to the corresponding weak functions:
     examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
     Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+    reset to the legacy weak functions in the HAL_SMARTCARD_Init()
     and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
     If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
@@ -162,22 +173,11 @@
     [..]
     When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak callbacks are used.
 
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -467,7 +467,10 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User SMARTCARD Callback
-  *         To be used instead of the weak predefined callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
+  *         in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+  *         and HAL_SMARTCARD_MSPDEINIT_CB_ID
   * @param  hsmartcard smartcard handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -497,8 +500,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hsmartcard);
 
   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
   {
@@ -584,15 +585,15 @@ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmart
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsmartcard);
-
   return status;
 }
 
 /**
   * @brief  Unregister an SMARTCARD callback
   *         SMARTCARD callback is redirected to the weak predefined callback
+  * @note   The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
+  *         in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+  *         and HAL_SMARTCARD_MSPDEINIT_CB_ID
   * @param  hsmartcard smartcard handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -613,9 +614,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hsmartcard);
-
   if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
   {
     switch (CallbackID)
@@ -701,9 +699,6 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsmartcard);
-
   return status;
 }
 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -809,11 +804,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
   * @param  Timeout  Timeout duration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
                                          uint32_t Timeout)
 {
   uint32_t tickstart;
-  uint8_t  *ptmpdata = pData;
+  const uint8_t  *ptmpdata = pData;
 
   /* Check that a Tx process is not already ongoing */
   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -983,7 +978,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
   * @param  Size amount of data to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
 {
   /* Check that a Tx process is not already ongoing */
   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -1141,7 +1136,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard,
   * @param  Size amount of data to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size)
 {
   /* Check that a Tx process is not already ongoing */
   if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
@@ -2276,7 +2271,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsma
   *                    the configuration information for the specified SMARTCARD module.
   * @retval SMARTCARD handle state
   */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard)
 {
   /* Return SMARTCARD handle state */
   uint32_t temp1;
@@ -2293,7 +2288,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmar
   *                    the configuration information for the specified SMARTCARD module.
   * @retval SMARTCARD handle Error Code
   */
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard)
 {
   return hsmartcard->ErrorCode;
 }
@@ -2422,43 +2417,43 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
   {
     case SMARTCARD_CLOCKSOURCE_D2PCLK1:
       pclk = HAL_RCC_GetPCLK1Freq();
-      tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+      tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       break;
     case SMARTCARD_CLOCKSOURCE_D2PCLK2:
       pclk = HAL_RCC_GetPCLK2Freq();
-      tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+      tmpreg = (uint32_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       break;
     case SMARTCARD_CLOCKSOURCE_PLL2Q:
       HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
-      tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+      tmpreg = (uint32_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       break;
     case SMARTCARD_CLOCKSOURCE_PLL3Q:
       HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
-      tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+      tmpreg = (uint32_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       break;
     case SMARTCARD_CLOCKSOURCE_HSI:
       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
       {
-        tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) /
+        tmpreg = (uint32_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) /
                               SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                              (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       }
       else
       {
-        tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+        tmpreg = (uint32_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                              (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       }
       break;
     case SMARTCARD_CLOCKSOURCE_CSI:
-      tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+      tmpreg = (uint32_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       break;
     case SMARTCARD_CLOCKSOURCE_LSE:
-      tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+      tmpreg = (uint32_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
                            (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
       break;
     default:
@@ -2469,7 +2464,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
   /* USARTDIV must be greater than or equal to 0d16 */
   if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX))
   {
-    hsmartcard->Instance->BRR = tmpreg;
+    hsmartcard->Instance->BRR = (uint16_t)tmpreg;
   }
   else
   {
@@ -2600,11 +2595,12 @@ static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmar
 }
 
 /**
-  * @brief  Handle SMARTCARD Communication Timeout.
+  * @brief  Handle SMARTCARD Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
   * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
   *                   the configuration information for the specified SMARTCARD module.
   * @param  Flag Specifies the SMARTCARD flag to check.
-  * @param  Status The new Flag status (SET or RESET).
+  * @param  Status The actual Flag status (SET or RESET).
   * @param  Tickstart Tick start value
   * @param  Timeout Timeout duration.
   * @retval HAL status
@@ -3204,4 +3200,3 @@ static void SMARTCARD_RxISR_FIFOEN(SMARTCARD_HandleTypeDef *hsmartcard)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h
index 1c7aee87ea..823ab354d9 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -202,7 +201,7 @@ typedef struct __SMARTCARD_HandleTypeDef
 
   SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
 
-  uint8_t                           *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
+  const uint8_t                     *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
 
   uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
 
@@ -1345,13 +1344,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
   * @{
   */
 
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
                                          uint32_t Timeout);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
                                         uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
 /* Transfer Abort functions */
 HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
@@ -1378,8 +1377,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
   * @{
   */
 
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t                   HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard);
 
 /**
   * @}
@@ -1403,4 +1402,3 @@ uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmar
 
 #endif /* STM32H7xx_HAL_SMARTCARD_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c
index 35505d8b1a..5c76a67d6b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c
@@ -8,6 +8,17 @@
   *           + Initialization and de-initialization functions
   *           + Peripheral Control functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   =============================================================================
                ##### SMARTCARD peripheral extended features  #####
@@ -27,17 +38,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -493,4 +493,3 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.h
index d6650a1569..3910005572 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -335,4 +334,3 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hs
 
 #endif /* STM32H7xx_HAL_SMARTCARD_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c
index 3d0c843705..f821427c9f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c
@@ -10,6 +10,17 @@
   *           + IO operation functions
   *           + Peripheral State and Errors functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -20,7 +31,7 @@
     (#) Declare a SMBUS_HandleTypeDef handle structure, for example:
         SMBUS_HandleTypeDef  hsmbus;
 
-    (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API:
+    (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API:
         (##) Enable the SMBUSx interface clock
         (##) SMBUS pins configuration
             (+++) Enable the clock for the SMBUS GPIOs
@@ -33,69 +44,75 @@
         Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode,
         Peripheral mode and Packet Error Check mode in the hsmbus Init structure.
 
-    (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init() API:
+    (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API:
         (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API.
+             by calling the customized HAL_SMBUS_MspInit(&hsmbus) API.
 
-    (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady()
+    (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady()
 
     (#) For SMBUS IO operations, only one mode of operations is available within this driver
 
     *** Interrupt mode IO operation ***
     ===================================
     [..]
-      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Transmit_IT()
-      (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback()
-      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Master_Receive_IT()
-      (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback()
-      (+) Abort a master/host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT()
+      (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Master_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback()
+      (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Master_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback()
+      (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT()
       (++) The associated previous transfer callback is called at the end of abort process
-      (++) mean @ref HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
-      (++) mean @ref HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
+      (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit
+      (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive
       (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode
-           using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT()
-      (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can
-           add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read).
-      (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback()
-      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT()
-      (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback()
-      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode using @ref HAL_SMBUS_Slave_Receive_IT()
-      (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback()
-      (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() @ref HAL_SMBUS_DisableAlert_IT()
-      (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
-           to check the Alert Error Code using function @ref HAL_SMBUS_GetError()
-      (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or @ref HAL_SMBUS_GetError()
-      (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback()
-           to check the Error Code using function @ref HAL_SMBUS_GetError()
+           using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT()
+      (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can
+           add their own code to check the Address Match Code and the transmission direction
+           request by master/host (Write/Read).
+      (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback()
+      (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Slave_Transmit_IT()
+      (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback()
+      (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode
+          using HAL_SMBUS_Slave_Receive_IT()
+      (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback()
+      (+) Enable/Disable the SMBUS alert mode using
+          HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT()
+      (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Alert Error Code using function HAL_SMBUS_GetError()
+      (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError()
+      (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can
+           add their own code by customization of function pointer HAL_SMBUS_ErrorCallback()
+           to check the Error Code using function HAL_SMBUS_GetError()
 
      *** SMBUS HAL driver macros list ***
      ==================================
      [..]
        Below the list of most used macros in SMBUS HAL driver.
 
-      (+) @ref __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
-      (+) @ref __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
-      (+) @ref __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
-      (+) @ref __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
-      (+) @ref __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
-      (+) @ref __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
+      (+) __HAL_SMBUS_ENABLE:      Enable the SMBUS peripheral
+      (+) __HAL_SMBUS_DISABLE:     Disable the SMBUS peripheral
+      (+) __HAL_SMBUS_GET_FLAG:    Check whether the specified SMBUS flag is set or not
+      (+) __HAL_SMBUS_CLEAR_FLAG:  Clear the specified SMBUS pending flag
+      (+) __HAL_SMBUS_ENABLE_IT:   Enable the specified SMBUS interrupt
+      (+) __HAL_SMBUS_DISABLE_IT:  Disable the specified SMBUS interrupt
 
      *** Callback registration ***
      =============================================
     [..]
      The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
      allows the user to configure dynamically the driver callbacks.
-     Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
+     Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback()
      to register an interrupt callback.
     [..]
-     Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
+     Function HAL_SMBUS_RegisterCallback() allows to register following callbacks:
        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
        (+) MasterRxCpltCallback : callback for Master reception end of transfer.
        (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.
@@ -107,11 +124,11 @@
      This function takes as parameters the HAL peripheral handle, the Callback ID
      and a pointer to the user callback function.
     [..]
-     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
+     For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback.
     [..]
-     Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
+     Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default
      weak function.
-     @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
      and the Callback ID.
      This function allows to reset following callbacks:
        (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
@@ -123,24 +140,24 @@
        (+) MspInitCallback      : callback for Msp Init.
        (+) MspDeInitCallback    : callback for Msp DeInit.
     [..]
-     For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
+     For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback.
     [..]
-     By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
+     By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET
      all callbacks are set to the corresponding weak functions:
-     examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
+     examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback().
      Exception done for MspInit and MspDeInit functions that are
-     reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when
+     reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when
      these callbacks are null (not registered beforehand).
-     If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
+     If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit()
      keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
     [..]
-     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
+     Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only.
      Exception done MspInit/MspDeInit functions that can be registered/unregistered
-     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
+     in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state,
      thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
      Then, the user first registers the MspInit/MspDeInit user callbacks
-     using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
-     or @ref HAL_SMBUS_Init() function.
+     using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit()
+     or HAL_SMBUS_Init() function.
     [..]
      When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registration feature is not available and all callbacks
@@ -150,18 +167,6 @@
        (@) You can refer to the SMBUS HAL driver header file for more useful macros
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -203,20 +208,28 @@
 /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
   * @{
   */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
-                                                      uint32_t Timeout);
+/* Private functions to handle flags during polling transfer */
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+                                                      FlagStatus Status, uint32_t Timeout);
 
-static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
-static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+/* Private functions for SMBUS transfer IRQ handler */
 static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
 static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags);
-
-static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
-
 static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
 
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode,
-                                 uint32_t Request);
+/* Private functions to centralize the enable/disable of Interrupts */
+static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
+
+/* Private function to flush TXDR register */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus);
+
+/* Private function to handle start, restart or stop a transfer */
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
+                                 uint32_t Mode, uint32_t Request);
+
+/* Private function to Convert Specific options */
+static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
 /**
   * @}
   */
@@ -364,15 +377,20 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
 
   /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/
   /* Configure SMBUSx: Dual mode and Own Address2 */
-  hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | (hsmbus->Init.OwnAddress2Masks << 8U));
+  hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \
+                            (hsmbus->Init.OwnAddress2Masks << 8U));
 
   /*---------------------------- SMBUSx CR1 Configuration ------------------------*/
   /* Configure SMBUSx: Generalcall and NoStretch mode */
-  hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
+  hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \
+                           hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \
+                           hsmbus->Init.AnalogFilter);
 
-  /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
-  if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
-      && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
+  /* Enable Slave Byte Control only in case of Packet Error Check is enabled
+     and SMBUS Peripheral is set in Slave mode */
+  if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \
+      ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+       (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
   {
     hsmbus->Instance->CR1 |= I2C_CR1_SBC;
   }
@@ -566,6 +584,9 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
 /**
   * @brief  Register a User SMBUS Callback
   *         To be used instead of the weak predefined callback
+  * @note   The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in
+  *         HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+  *         HAL_SMBUS_MSPDEINIT_CB_ID.
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
   * @param  CallbackID ID of the callback to be registered
@@ -581,7 +602,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
                                              pSMBUS_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
@@ -594,9 +616,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
   if (HAL_SMBUS_STATE_READY == hsmbus->State)
   {
     switch (CallbackID)
@@ -672,14 +691,15 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
   return status;
 }
 
 /**
   * @brief  Unregister an SMBUS Callback
   *         SMBUS callback is redirected to the weak predefined callback
+  * @note   The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in
+  *         HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and
+  *         HAL_SMBUS_MSPDEINIT_CB_ID
   * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
   *                the configuration information for the specified SMBUS.
   * @param  CallbackID ID of the callback to be unregistered
@@ -695,13 +715,11 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SM
   *          @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                               HAL_SMBUS_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
   if (HAL_SMBUS_STATE_READY == hsmbus->State)
   {
     switch (CallbackID)
@@ -777,8 +795,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
   return status;
 }
 
@@ -790,7 +806,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_
   * @param  pCallback pointer to the Address Match Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+                                                 pSMBUS_AddrCallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -801,8 +818,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pS
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
 
   if (HAL_SMBUS_STATE_READY == hsmbus->State)
   {
@@ -817,8 +832,6 @@ HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pS
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
   return status;
 }
 
@@ -833,9 +846,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hsmbus);
-
   if (HAL_SMBUS_STATE_READY == hsmbus->State)
   {
     hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback  */
@@ -849,8 +859,6 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsmbus);
   return status;
 }
 
@@ -914,10 +922,11 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus)
   * @param  XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
-                                               uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions)
 {
   uint32_t tmp;
+  uint32_t sizetoxfer;
 
   /* Check the parameters */
   assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -950,12 +959,37 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
       hsmbus->XferSize = Size;
     }
 
+    sizetoxfer = hsmbus->XferSize;
+    if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) ||
+                              (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) ||
+                              (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) ||
+                              (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)))
+    {
+      if (hsmbus->pBuffPtr != NULL)
+      {
+        /* Preload TX register */
+        /* Write data to TXDR */
+        hsmbus->Instance->TXDR = *hsmbus->pBuffPtr;
+
+        /* Increment Buffer pointer */
+        hsmbus->pBuffPtr++;
+
+        hsmbus->XferCount--;
+        hsmbus->XferSize--;
+      }
+      else
+      {
+        return HAL_ERROR;
+      }
+    }
+
     /* Send Slave Address */
     /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
-    if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
+    if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE))
     {
-      SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
-                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+      SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
+                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                           SMBUS_GENERATE_START_WRITE);
     }
     else
     {
@@ -965,9 +999,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
       /* Store current volatile XferOptions, misra rule */
       tmp = hsmbus->XferOptions;
 
-      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \
+          (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
       {
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions,
+                             SMBUS_NO_STARTSTOP);
       }
       /* Else transfer direction change, so generate Restart with new transfer direction */
       else
@@ -976,15 +1012,24 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint
         SMBUS_ConvertOtherXferOptions(hsmbus);
 
         /* Handle Transfer */
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer,
+                             hsmbus->XferOptions,
+                             SMBUS_GENERATE_START_WRITE);
       }
 
       /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
       if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
       {
-        hsmbus->XferSize--;
-        hsmbus->XferCount--;
+        if (hsmbus->XferSize > 0U)
+        {
+          hsmbus->XferSize--;
+          hsmbus->XferCount--;
+        }
+        else
+        {
+          return HAL_ERROR;
+        }
       }
     }
 
@@ -1057,7 +1102,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
     {
       SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
-                           SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+                           SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                           SMBUS_GENERATE_START_READ);
     }
     else
     {
@@ -1067,9 +1113,11 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
       /* Store current volatile XferOptions, Misra rule */
       tmp = hsmbus->XferOptions;
 
-      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
+      if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \
+          (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0))
       {
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                             SMBUS_NO_STARTSTOP);
       }
       /* Else transfer direction change, so generate Restart with new transfer direction */
       else
@@ -1078,7 +1126,9 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1
         SMBUS_ConvertOtherXferOptions(hsmbus);
 
         /* Handle Transfer */
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+                             hsmbus->XferOptions,
+                             SMBUS_GENERATE_START_READ);
       }
     }
 
@@ -1222,12 +1272,14 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8
     if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
     {
       SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
-                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+                           SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                           SMBUS_NO_STARTSTOP);
     }
     else
     {
       /* Set NBYTE to transmit */
-      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                           SMBUS_NO_STARTSTOP);
 
       /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
       /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
@@ -1313,7 +1365,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_
     /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
     if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U))
     {
-      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+      SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                           SMBUS_NO_STARTSTOP);
     }
     else
     {
@@ -1576,7 +1629,8 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
   uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
 
   /* SMBUS in mode Transmitter ---------------------------------------------------*/
-  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+                                           SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
@@ -1600,7 +1654,8 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
   }
 
   /* SMBUS in mode Receiver ----------------------------------------------------*/
-  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+  if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI |
+                                           SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
       ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
        (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
@@ -1720,7 +1775,8 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus)
   * @param  AddrMatchCode Address Match Code
   * @retval None
   */
-__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
+__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+                                   uint16_t AddrMatchCode)
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hsmbus);
@@ -1789,7 +1845,7 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus)
   *                the configuration information for the specified SMBUS.
   * @retval HAL state
   */
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus)
 {
   /* Return SMBUS handle state */
   return hsmbus->State;
@@ -1801,7 +1857,7 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus)
   *              the configuration information for the specified SMBUS.
   * @retval SMBUS Error Code
   */
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus)
 {
   return hsmbus->ErrorCode;
 }
@@ -1842,6 +1898,9 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t
     /* No need to generate STOP, it is automatically done */
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
 
+    /* Flush TX register */
+    SMBUS_Flush_TXDR(hsmbus);
+
     /* Process Unlocked */
     __HAL_UNLOCK(hsmbus);
 
@@ -1967,13 +2026,15 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t
       if (hsmbus->XferCount > MAX_NBYTE_SIZE)
       {
         SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
-                             (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+                             (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+                             SMBUS_NO_STARTSTOP);
         hsmbus->XferSize = MAX_NBYTE_SIZE;
       }
       else
       {
         hsmbus->XferSize = hsmbus->XferCount;
-        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                             SMBUS_NO_STARTSTOP);
         /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
         /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
         if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
@@ -2130,6 +2191,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
       /* Clear NACK Flag */
       __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
 
+      /* Flush TX register */
+      SMBUS_Flush_TXDR(hsmbus);
+
       /* Process Unlocked */
       __HAL_UNLOCK(hsmbus);
     }
@@ -2151,6 +2215,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
       /* Set ErrorCode corresponding to a Non-Acknowledge */
       hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF;
 
+      /* Flush TX register */
+      SMBUS_Flush_TXDR(hsmbus);
+
       /* Process Unlocked */
       __HAL_UNLOCK(hsmbus);
 
@@ -2225,7 +2292,9 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
       else
       {
         /* Set Reload for next Bytes */
-        SMBUS_TransferConfig(hsmbus, 0, 1, SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+        SMBUS_TransferConfig(hsmbus, 0, 1,
+                             SMBUS_RELOAD_MODE  | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE),
+                             SMBUS_NO_STARTSTOP);
 
         /* Ack last Byte Read */
         hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
@@ -2237,14 +2306,16 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S
       {
         if (hsmbus->XferCount > MAX_NBYTE_SIZE)
         {
-          SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+          SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE,
+                               (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
                                SMBUS_NO_STARTSTOP);
           hsmbus->XferSize = MAX_NBYTE_SIZE;
         }
         else
         {
           hsmbus->XferSize = hsmbus->XferCount;
-          SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+          SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions,
+                               SMBUS_NO_STARTSTOP);
           /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
           /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
           if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL)
@@ -2489,7 +2560,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   uint32_t tmperror;
 
   /* SMBUS Bus error interrupt occurred ------------------------------------*/
-  if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
   {
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
 
@@ -2498,7 +2570,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   }
 
   /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
-  if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
   {
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
 
@@ -2507,7 +2580,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   }
 
   /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
-  if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
   {
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
 
@@ -2516,7 +2590,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   }
 
   /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
-  if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
   {
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
 
@@ -2525,7 +2600,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   }
 
   /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
-  if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
   {
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
 
@@ -2534,7 +2610,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   }
 
   /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
-  if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
+  if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \
+      ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI))
   {
     hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
 
@@ -2542,7 +2619,13 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
     __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
   }
 
-  /* Store current volatile hsmbus->State, misra rule */
+  if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+  {
+    /* Flush TX register */
+    SMBUS_Flush_TXDR(hsmbus);
+  }
+
+  /* Store current volatile hsmbus->ErrorCode, misra rule */
   tmperror = hsmbus->ErrorCode;
 
   /* Call the Error Callback in case of Error detected */
@@ -2582,8 +2665,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
-                                                      uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag,
+                                                      FlagStatus Status, uint32_t Timeout)
 {
   uint32_t tickstart = HAL_GetTick();
 
@@ -2612,6 +2695,27 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
   return HAL_OK;
 }
 
+/**
+  * @brief  SMBUS Tx data register flush process.
+  * @param  hsmbus SMBUS handle.
+  * @retval None
+  */
+static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* If a pending TXIS flag is set */
+  /* Write a dummy data in TXDR to clear it */
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+  {
+    hsmbus->Instance->TXDR = 0x00U;
+  }
+
+  /* Flush TX register if not empty */
+  if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET)
+  {
+    __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE);
+  }
+}
+
 /**
   * @brief  Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set).
   * @param  hsmbus SMBUS handle.
@@ -2632,8 +2736,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu
   *     @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
   * @retval None
   */
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size, uint32_t Mode,
-                                 uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddress, uint8_t Size,
+                                 uint32_t Mode, uint32_t Request)
 {
   /* Check the parameters */
   assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2644,9 +2748,10 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus,  uint16_t DevAddre
   MODIFY_REG(hsmbus->Instance->CR2,
              ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
                (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
-               I2C_CR2_START | I2C_CR2_STOP  | I2C_CR2_PECBYTE)), \
+               I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
              (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
-                        (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+                        (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                        (uint32_t)Mode | (uint32_t)Request));
 }
 
 /**
@@ -2703,5 +2808,3 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h
index 426760dc69..a36f58c5c8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -48,42 +47,43 @@ extern "C" {
 typedef struct
 {
   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
-                                     This parameter calculated by referring to SMBUS initialization
-                                            section in Reference manual */
+                                        This parameter calculated by referring to SMBUS initialization section
+                                        in Reference manual */
   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
-                                     This parameter can be a value of @ref SMBUS_Analog_Filter */
+                                        This parameter can be a value of @ref SMBUS_Analog_Filter */
 
   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
-                                     This parameter can be a 7-bit or 10-bit address. */
+                                        This parameter can be a 7-bit or 10-bit address. */
 
   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
-                                     This parameter can be a value of @ref SMBUS_addressing_mode */
+                                        This parameter can be a value of @ref SMBUS_addressing_mode */
 
   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
-                                     This parameter can be a value of @ref SMBUS_dual_addressing_mode */
+                                        This parameter can be a value of @ref SMBUS_dual_addressing_mode */
 
   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
-                                     This parameter can be a 7-bit address. */
+                                        This parameter can be a 7-bit address. */
 
-  uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
-                                     This parameter can be a value of @ref SMBUS_own_address2_masks. */
+  uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
+                                        if dual addressing mode is selected
+                                        This parameter can be a value of @ref SMBUS_own_address2_masks. */
 
   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
-                                     This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
+                                        This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
 
   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
-                                     This parameter can be a value of @ref SMBUS_nostretch_mode */
+                                        This parameter can be a value of @ref SMBUS_nostretch_mode */
 
   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
-                                     This parameter can be a value of @ref SMBUS_packet_error_check_mode */
+                                        This parameter can be a value of @ref SMBUS_packet_error_check_mode */
 
   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
-                                     This parameter can be a value of @ref SMBUS_peripheral_mode */
+                                        This parameter can be a value of @ref SMBUS_peripheral_mode */
 
   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
-                                      (Enable bits and different timeout values)
-                                     This parameter calculated by referring to SMBUS initialization
-                                         section in Reference manual */
+                                        (Enable bits and different timeout values)
+                                        This parameter calculated by referring to SMBUS initialization section
+                                        in Reference manual */
 } SMBUS_InitTypeDef;
 /**
   * @}
@@ -100,9 +100,7 @@ typedef struct
 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
-#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
-#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
-#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
+#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
 /**
   * @}
   */
@@ -121,7 +119,7 @@ typedef struct
 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
+#define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
 #define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
 /**
@@ -159,17 +157,26 @@ typedef struct
   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
 
 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);             /*!< SMBUS Listen Complete callback              */
-  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                  /*!< SMBUS Error callback                        */
+  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Master Tx Transfer completed callback */
+  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Master Rx Transfer completed callback */
+  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Slave Tx Transfer completed callback  */
+  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Slave Rx Transfer completed callback  */
+  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Listen Complete callback              */
+  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Error callback                        */
 
-  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< SMBUS Slave Address Match callback */
+  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
+  /*!< SMBUS Slave Address Match callback */
 
-  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                /*!< SMBUS Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);              /*!< SMBUS Msp DeInit callback                   */
+  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Msp Init callback                     */
+  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
+  /*!< SMBUS Msp DeInit callback                   */
 
 #endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
 } SMBUS_HandleTypeDef;
@@ -195,8 +202,11 @@ typedef enum
 /**
   * @brief  HAL SMBUS Callback pointer definition
   */
-typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */
-typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */
+typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
+/*!< pointer to an SMBUS callback function */
+typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
+                                            uint16_t AddrMatchCode);
+/*!< pointer to an SMBUS Address Match callback function */
 
 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
 /**
@@ -358,9 +368,10 @@ typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
-#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \
-                                                 SMBUS_IT_TXI)
-#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
+#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
+                                                 SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
+                                                 SMBUS_IT_RXI)
 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
 /**
@@ -408,14 +419,14 @@ typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
   * @retval None
   */
 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                                   \
-                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;       \
+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
+                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
                                                                  (__HANDLE__)->MspInitCallback = NULL;            \
                                                                  (__HANDLE__)->MspDeInitCallback = NULL;          \
                                                                } while(0)
 #else
 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-#endif
+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
 
 /** @brief  Enable the specified SMBUS interrupts.
   * @param  __HANDLE__ specifies the SMBUS Handle.
@@ -491,12 +502,14 @@ typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
   */
 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
-  (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+  (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+    ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
 
 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
   * @param  __HANDLE__ specifies the SMBUS Handle.
   * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
@@ -509,7 +522,9 @@ typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
   *
   * @retval None
   */
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__)  (((__FLAG__) == SMBUS_FLAG_TXE) ? \
+                                                       ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
+                                                       ((__HANDLE__)->Instance->ICR = (__FLAG__)))
 
 /** @brief  Enable the specified SMBUS peripheral.
   * @param  __HANDLE__ specifies the SMBUS Handle.
@@ -574,43 +589,52 @@ typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
 
-#define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                          || \
-                                                         ((MODE) == SMBUS_AUTOEND_MODE)                         || \
-                                                         ((MODE) == SMBUS_SOFTEND_MODE)                         || \
-                                                         ((MODE) == SMBUS_SENDPEC_MODE)                         || \
-                                                         ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
-                                                         ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
-                                                         ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
-                                                         ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+#define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
+                                                      ((MODE) == SMBUS_AUTOEND_MODE)                         || \
+                                                      ((MODE) == SMBUS_SOFTEND_MODE)                         || \
+                                                      ((MODE) == SMBUS_SENDPEC_MODE)                         || \
+                                                      ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
+                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
+                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
+                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
+                                                                  SMBUS_RELOAD_MODE )))
 
 
 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
-                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
-                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
+                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
+                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))
 
 
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
-                                                         ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
-                                                         ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
-                                                         ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
-                                                         ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
-                                                         ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
-                                                         ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
-                                                         ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
+                                                      ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
+                                                      ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
+                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
+                                                      ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
+                                                      ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
+                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
+                                                      ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
 
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
-                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
-                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
 
-#define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= \
-                                                           (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= \
-                                                           (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
+                                                        (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
+                                                                               I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
+                                                        (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
+                                                                               I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
+                                                                               I2C_CR2_RD_WRN)))
 
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
-                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
+                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
+                                                                       (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
+                                                                      (~I2C_CR2_RD_WRN)) : \
+                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & \
+                                                                        (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
+                                                                       (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
 
 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
@@ -629,6 +653,9 @@ typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t
   * @}
   */
 
+/* Include SMBUS HAL Extended module */
+#include "stm32h7xx_hal_smbus_ex.h"
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
   * @{
@@ -648,11 +675,14 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
                                              pSMBUS_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
+                                               HAL_SMBUS_CallbackIDTypeDef CallbackID);
 
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
+                                                 pSMBUS_AddrCallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
 /**
@@ -678,10 +708,10 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t
   * @{
   */
 /******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
-                                               uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
-                                              uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
+                                              uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
                                               uint32_t XferOptions);
@@ -719,8 +749,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
   */
 
 /* Peripheral State and Errors functions  **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
+uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
 
 /**
   * @}
@@ -757,5 +787,3 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
 
 
 #endif /* STM32H7xx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.c
new file mode 100644
index 0000000000..354966a13e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.c
@@ -0,0 +1,258 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_smbus_ex.c
+  * @author  MCD Application Team
+  * @brief   SMBUS Extended HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of SMBUS Extended peripheral:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### SMBUS peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the SMBUS interface for STM32H7xx
+       devices contains the following additional features
+
+       (+) Disable or enable wakeup from Stop mode(s)
+       (+) Disable or enable Fast Mode Plus
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    (#) Configure the enable or disable of SMBUS Wake Up Mode using the functions :
+          (++) HAL_SMBUSEx_EnableWakeUp()
+          (++) HAL_SMBUSEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_SMBUSEx_EnableFastModePlus()
+          (++) HAL_SMBUSEx_DisableFastModePlus()
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMBUSEx SMBUSEx
+  * @brief SMBUS Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @brief    WakeUp Mode Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### WakeUp Mode Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Wake Up Feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable SMBUS wakeup from Stop mode(s).
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Enable wakeup from stop mode */
+    hsmbus->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Disable SMBUS wakeup from Stop mode(s).
+  * @param  hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMBUSx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hsmbus->Instance));
+
+  if (hsmbus->State == HAL_SMBUS_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+    /* Disable the selected SMBUS peripheral */
+    __HAL_SMBUS_DISABLE(hsmbus);
+
+    /* Disable wakeup from stop mode */
+    hsmbus->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_SMBUS_ENABLE(hsmbus);
+
+    hsmbus->State = HAL_SMBUS_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmbus);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @brief    Fast Mode Plus Functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Fast Mode Plus Functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Fast Mode Plus
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enable the SMBUS fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be enabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
+  * @note  For all I2C5 pins fast mode plus driving capability can be enabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C5 parameter.
+  * @retval None
+  */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the SMBUS fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref SMBUSEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using SMBUS_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using SMBUS_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C3 parameter.
+  * @note  For all I2C4 pins fast mode plus driving capability can be disabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C4 parameter.
+  * @note  For all I2C5 pins fast mode plus driving capability can be disabled
+  *        only by using SMBUS_FASTMODEPLUS_I2C5 parameter.
+  * @retval None
+  */
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->PMCR, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.h
new file mode 100644
index 0000000000..0fde990957
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus_ex.h
@@ -0,0 +1,152 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_smbus_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of SMBUS HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_SMBUS_EX_H
+#define STM32H7xx_HAL_SMBUS_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMBUSEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
+  * @{
+  */
+#define SMBUS_FMP_NOT_SUPPORTED           0xAAAA0000U                                     /*!< Fast Mode Plus not supported       */
+#define SMBUS_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
+#define SMBUS_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
+#define SMBUS_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
+#define SMBUS_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
+#define SMBUS_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
+#define SMBUS_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
+#define SMBUS_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
+#define SMBUS_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */
+#if defined(SYSCFG_PMCR_I2C5_FMP)
+#define SMBUS_FASTMODEPLUS_I2C5           SYSCFG_PMCR_I2C5_FMP                           /*!< Enable Fast Mode Plus on I2C5 pins */
+#else
+#define SMBUS_FASTMODEPLUS_I2C5           (uint32_t)(0x00001000U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C5 not supported  */
+#endif /* SYSCFG_PMCR_I2C5_FMP */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
+/**
+  * @}
+  */
+
+/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
+  * @{
+  */
+void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
+  * @{
+  */
+#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FASTMODEPLUS_PB6)  == SMBUS_FASTMODEPLUS_PB6)    || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB7)  == SMBUS_FASTMODEPLUS_PB7)    || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB8)  == SMBUS_FASTMODEPLUS_PB8)    || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_PB9)  == SMBUS_FASTMODEPLUS_PB9)    || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C1) == SMBUS_FASTMODEPLUS_I2C1)   || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C2) == SMBUS_FASTMODEPLUS_I2C2)   || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C3) == SMBUS_FASTMODEPLUS_I2C3)   || \
+                                           (((__CONFIG__) & SMBUS_FASTMODEPLUS_I2C4) == SMBUS_FASTMODEPLUS_I2C4))
+/**
+  * @}
+  */
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32h7xx_hal_smbus_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_SMBUS_EX_H */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c
index e0536b6459..bf61ef937a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c
@@ -8,6 +8,18 @@
   *           + Data transfers functions
   *           + DMA transfers management
   *           + Interrupts and flags management
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                   ##### How to use this driver #####
@@ -21,10 +33,12 @@
         (##) SPDIFRX pins configuration:
             (+++) Enable the clock for the SPDIFRX GPIOs.
             (+++) Configure these SPDIFRX pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
+        (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveCtrlFlow_IT() and
+             HAL_SPDIFRX_ReceiveDataFlow_IT() API's).
             (+++) Configure the SPDIFRX interrupt priority.
             (+++) Enable the NVIC SPDIFRX IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
+        (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and
+             HAL_SPDIFRX_ReceiveCtrlFlow_DMA() API's).
             (+++) Declare a DMA handle structure for the reception of the Data Flow channel.
             (+++) Declare a DMA handle structure for the reception of the Control Flow channel.
             (+++) Enable the DMAx interface clock.
@@ -34,8 +48,8 @@
             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
                 DMA CtrlRx/DataRx channel.
 
-   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, stereo mode and masking of user bits
-       using HAL_SPDIFRX_Init() function.
+   (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format,
+       stereo mode and masking of user bits using HAL_SPDIFRX_Init() function.
 
    -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros
        __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process.
@@ -78,7 +92,7 @@
    =============================================
    [..]
      Below the list of most used macros in SPDIFRX HAL driver.
-      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDEL State)
+      (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State)
       (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State)
       (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State)
       (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts
@@ -142,18 +156,6 @@
   are set to the corresponding weak functions.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -173,8 +175,13 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define SPDIFRX_TIMEOUT_VALUE  0xFFFFU
-
+/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines
+  * @{
+  */
+#define SPDIFRX_TIMEOUT_VALUE  10U
+/**
+  * @}
+  */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -188,7 +195,8 @@ static void  SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma);
 static void  SPDIFRX_DMAError(DMA_HandleTypeDef *hdma);
 static void  SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
 static void  SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif);
-static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
+static HAL_StatusTypeDef  SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag,
+                                                         FlagStatus Status, uint32_t Timeout, uint32_t tickstart);
 /**
   * @}
   */
@@ -238,7 +246,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
   uint32_t tmpreg;
 
   /* Check the SPDIFRX handle allocation */
-  if(hspdif == NULL)
+  if (hspdif == NULL)
   {
     return HAL_ERROR;
   }
@@ -258,7 +266,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
   assert_param(IS_SYMBOL_CLOCK_GEN(hspdif->Init.BackupSymbolClockGen));
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-  if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+  if (hspdif->State == HAL_SPDIFRX_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hspdif->Lock = HAL_UNLOCKED;
@@ -269,7 +277,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
     hspdif->CxCpltCallback      = HAL_SPDIFRX_CxCpltCallback;     /* Legacy weak CxCpltCallback     */
     hspdif->ErrorCallback       = HAL_SPDIFRX_ErrorCallback;      /* Legacy weak ErrorCallback      */
 
-    if(hspdif->MspInitCallback == NULL)
+    if (hspdif->MspInitCallback == NULL)
     {
       hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit  */
     }
@@ -278,7 +286,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
     hspdif->MspInitCallback(hspdif);
   }
 #else
-  if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
+  if (hspdif->State == HAL_SPDIFRX_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hspdif->Lock = HAL_UNLOCKED;
@@ -313,14 +321,14 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
              hspdif->Init.ChannelStatusMask |
              hspdif->Init.ValidityBitMask |
              hspdif->Init.ParityErrorMask
-             );
+            );
 
-  if(hspdif->Init.SymbolClockGen == ENABLE)
+  if (hspdif->Init.SymbolClockGen == ENABLE)
   {
     tmpreg |= SPDIFRX_CR_CKSEN;
   }
 
-  if(hspdif->Init.BackupSymbolClockGen == ENABLE)
+  if (hspdif->Init.BackupSymbolClockGen == ENABLE)
   {
     tmpreg |= SPDIFRX_CR_CKSBKPEN;
   }
@@ -343,7 +351,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
 HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
 {
   /* Check the SPDIFRX handle allocation */
-  if(hspdif == NULL)
+  if (hspdif == NULL)
   {
     return HAL_ERROR;
   }
@@ -357,7 +365,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif)
   __HAL_SPDIFRX_IDLE(hspdif);
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-  if(hspdif->MspDeInitCallback == NULL)
+  if (hspdif->MspDeInitCallback == NULL)
   {
     hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit  */
   }
@@ -427,11 +435,12 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif)
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
+                                               pSPDIFRX_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(pCallback == NULL)
+  if (pCallback == NULL)
   {
     /* Update the error code */
     hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
@@ -440,7 +449,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
   /* Process locked */
   __HAL_LOCK(hspdif);
 
-  if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+  if (HAL_SPDIFRX_STATE_READY == hspdif->State)
   {
     switch (CallbackID)
     {
@@ -480,7 +489,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
         break;
     }
   }
-  else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+  else if (HAL_SPDIFRX_STATE_RESET == hspdif->State)
   {
     switch (CallbackID)
     {
@@ -495,7 +504,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
       default :
         /* Update the error code */
         hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
-       /* Return error status */
+        /* Return error status */
         status =  HAL_ERROR;
         break;
     }
@@ -515,7 +524,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
 
 /**
   * @brief  Unregister a SPDIFRX Callback
-  *         SPDIFRX callabck is redirected to the weak predefined callback
+  *         SPDIFRX callback is redirected to the weak predefined callback
   * @param  hspdif SPDIFRX handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -528,14 +537,15 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA
   *          @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID  MspDeInit callback ID
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
+                                                 HAL_SPDIFRX_CallbackIDTypeDef CallbackID)
 {
-HAL_StatusTypeDef status = HAL_OK;
+  HAL_StatusTypeDef status = HAL_OK;
 
   /* Process locked */
   __HAL_LOCK(hspdif);
 
-  if(HAL_SPDIFRX_STATE_READY == hspdif->State)
+  if (HAL_SPDIFRX_STATE_READY == hspdif->State)
   {
     switch (CallbackID)
     {
@@ -562,12 +572,12 @@ HAL_StatusTypeDef status = HAL_OK;
       default :
         /* Update the error code */
         hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK;
-       /* Return error status */
+        /* Return error status */
         status =  HAL_ERROR;
         break;
     }
   }
-  else if(HAL_SPDIFRX_STATE_RESET == hspdif->State)
+  else if (HAL_SPDIFRX_STATE_RESET == hspdif->State)
   {
     switch (CallbackID)
     {
@@ -613,7 +623,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   uint32_t tmpreg;
 
   /* Check the SPDIFRX handle allocation */
-  if(hspdif == NULL)
+  if (hspdif == NULL)
   {
     return HAL_ERROR;
   }
@@ -629,9 +639,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   /* Reset the old SPDIFRX CR configuration */
   tmpreg = hspdif->Instance->CR;
 
-  if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
-     (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
-      ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
+  if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
+      (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
+       ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
   {
     return HAL_ERROR;
   }
@@ -695,8 +705,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
         (++) HAL_SPDIFRX_CxCpltCallback()
 
 @endverbatim
-* @{
-*/
+  * @{
+  */
 
 /**
   * @brief  Receives an amount of data (Data Flow) in blocking mode.
@@ -707,18 +717,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout)
 {
   uint32_t tickstart;
   uint16_t sizeCounter = Size;
   uint32_t *pTmpBuf = pData;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
-  if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+  if (hspdif->State == HAL_SPDIFRX_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hspdif);
@@ -732,7 +743,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
     tickstart = HAL_GetTick();
 
     /* Wait until SYNCD flag is set */
-    if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
+    if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -741,13 +752,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
     __HAL_SPDIFRX_RCV(hspdif);
 
     /* Receive data flow */
-    while(sizeCounter > 0U)
+    while (sizeCounter > 0U)
     {
       /* Get tick */
       tickstart = HAL_GetTick();
 
       /* Wait until RXNE flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+      if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
@@ -780,18 +791,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout)
 {
   uint32_t tickstart;
   uint16_t sizeCounter = Size;
   uint32_t *pTmpBuf = pData;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
-  if(hspdif->State == HAL_SPDIFRX_STATE_READY)
+  if (hspdif->State == HAL_SPDIFRX_STATE_READY)
   {
     /* Process Locked */
     __HAL_LOCK(hspdif);
@@ -805,7 +817,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin
     tickstart = HAL_GetTick();
 
     /* Wait until SYNCD flag is set */
-    if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
+    if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK)
     {
       return HAL_TIMEOUT;
     }
@@ -814,13 +826,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uin
     __HAL_SPDIFRX_RCV(hspdif);
 
     /* Receive control flow */
-    while(sizeCounter > 0U)
+    while (sizeCounter > 0U)
     {
       /* Get tick */
       tickstart = HAL_GetTick();
 
       /* Wait until CSRNE flag is set */
-      if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
+      if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK)
       {
         return HAL_TIMEOUT;
       }
@@ -857,9 +869,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
 
   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
 
-  if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
   {
-    if((pData == NULL) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -885,7 +897,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
     /* Enable the SPDIFRX RXNE interrupt */
     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE);
 
-    if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
     {
       /* Start synchronization */
       __HAL_SPDIFRX_SYNC(hspdif);
@@ -895,7 +907,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
       {
         if (count == 0U)
         {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -904,7 +917,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
 
-          hspdif->State= HAL_SPDIFRX_STATE_READY;
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
 
           /* Process Unlocked */
           __HAL_UNLOCK(hspdif);
@@ -942,9 +955,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
 
   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
 
-  if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
   {
-    if((pData == NULL ) || (Size == 0U))
+    if ((pData == NULL) || (Size == 0U))
     {
       return HAL_ERROR;
     }
@@ -970,7 +983,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
     /* Enable the SPDIFRX CSRNE interrupt */
     __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
 
-    if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
     {
       /* Start synchronization */
       __HAL_SPDIFRX_SYNC(hspdif);
@@ -980,7 +993,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
       {
         if (count == 0U)
         {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -989,7 +1003,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif,
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
 
-          hspdif->State= HAL_SPDIFRX_STATE_READY;
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
 
           /* Process Unlocked */
           __HAL_UNLOCK(hspdif);
@@ -1027,12 +1041,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
 
   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
 
-  if((pData == NULL) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
-  if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX))
   {
     /* Process Locked */
     __HAL_LOCK(hspdif);
@@ -1054,7 +1068,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
     hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError;
 
     /* Enable the DMA request */
-    if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK)
+    if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) !=
+        HAL_OK)
     {
       /* Set SPDIFRX error */
       hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
@@ -1071,7 +1086,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
     /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/
     hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN;
 
-    if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
     {
       /* Start synchronization */
       __HAL_SPDIFRX_SYNC(hspdif);
@@ -1081,7 +1096,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
       {
         if (count == 0U)
         {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1090,7 +1106,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
 
-          hspdif->State= HAL_SPDIFRX_STATE_READY;
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
 
           /* Process Unlocked */
           __HAL_UNLOCK(hspdif);
@@ -1128,12 +1144,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
 
   const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State;
 
-  if((pData == NULL) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     return  HAL_ERROR;
   }
 
-  if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
+  if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX))
   {
     hspdif->pCsBuffPtr = pData;
     hspdif->CsXferSize = Size;
@@ -1155,7 +1171,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
     hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError;
 
     /* Enable the DMA request */
-    if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK)
+    if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) !=
+        HAL_OK)
     {
       /* Set SPDIFRX error */
       hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA;
@@ -1172,7 +1189,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
     /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/
     hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN;
 
-    if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
+    if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV)
     {
       /* Start synchronization */
       __HAL_SPDIFRX_SYNC(hspdif);
@@ -1182,7 +1199,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
       {
         if (count == 0U)
         {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+             process */
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1191,7 +1209,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif,
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
           __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
 
-          hspdif->State= HAL_SPDIFRX_STATE_READY;
+          hspdif->State = HAL_SPDIFRX_STATE_READY;
 
           /* Process Unlocked */
           __HAL_UNLOCK(hspdif);
@@ -1231,8 +1249,14 @@ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif)
   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
 
   /* Disable the SPDIFRX DMA channel */
-  __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
-  __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+  if (hspdif->hdmaDrRx != NULL)
+  {
+    __HAL_DMA_DISABLE(hspdif->hdmaDrRx);
+  }
+  if (hspdif->hdmaCsRx != NULL)
+  {
+    __HAL_DMA_DISABLE(hspdif->hdmaCsRx);
+  }
 
   /* Disable SPDIFRX peripheral */
   __HAL_SPDIFRX_IDLE(hspdif);
@@ -1256,21 +1280,21 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
   uint32_t itSource = hspdif->Instance->IMR;
 
   /* SPDIFRX in mode Data Flow Reception */
-  if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource &  SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
+  if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource &  SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE))
   {
     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE);
     SPDIFRX_ReceiveDataFlow_IT(hspdif);
   }
 
   /* SPDIFRX in mode Control Flow Reception */
-  if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource &  SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
+  if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource &  SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE))
   {
     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE);
     SPDIFRX_ReceiveControlFlow_IT(hspdif);
   }
 
   /* SPDIFRX Overrun error interrupt occurred */
-  if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource &  SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
+  if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource &  SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE))
   {
     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE);
 
@@ -1282,7 +1306,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif)
   }
 
   /* SPDIFRX Parity error interrupt occurred */
-  if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource &  SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
+  if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource &  SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE))
   {
     __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE);
 
@@ -1393,7 +1417,7 @@ and the data flow.
   * @param  hspdif SPDIFRX handle
   * @retval HAL state
   */
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif)
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif)
 {
   return hspdif->State;
 }
@@ -1403,7 +1427,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * cons
   * @param  hspdif SPDIFRX handle
   * @retval SPDIFRX Error Code
   */
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif)
 {
   return hspdif->ErrorCode;
 }
@@ -1419,10 +1443,10 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif)
   */
 static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
 {
-  SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable Rx DMA Request */
-  if(hdma->Init.Mode != DMA_CIRCULAR)
+  if (hdma->Init.Mode != DMA_CIRCULAR)
   {
     hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN);
     hspdif->RxXferCount = 0;
@@ -1442,7 +1466,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma)
   */
 static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
   hspdif->RxHalfCpltCallback(hspdif);
@@ -1459,7 +1483,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
 {
-  SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable Cb DMA Request */
   hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN);
@@ -1480,7 +1504,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma)
   */
 static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
   hspdif->CxHalfCpltCallback(hspdif);
@@ -1496,13 +1520,13 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma)
 {
-  SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Disable Rx and Cb DMA Request */
   hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN));
   hspdif->RxXferCount = 0;
 
-  hspdif->State= HAL_SPDIFRX_STATE_READY;
+  hspdif->State = HAL_SPDIFRX_STATE_READY;
 
   /* Set the error code and execute error callback*/
   hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA;
@@ -1528,7 +1552,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
   hspdif->pRxBuffPtr++;
   hspdif->RxXferCount--;
 
-  if(hspdif->RxXferCount == 0U)
+  if (hspdif->RxXferCount == 0U)
   {
     /* Disable RXNE/PE and OVR interrupts */
     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE);
@@ -1539,9 +1563,9 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
     __HAL_UNLOCK(hspdif);
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-  hspdif->RxCpltCallback(hspdif);
+    hspdif->RxCpltCallback(hspdif);
 #else
-  HAL_SPDIFRX_RxCpltCallback(hspdif);
+    HAL_SPDIFRX_RxCpltCallback(hspdif);
 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
   }
 }
@@ -1558,7 +1582,7 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
   hspdif->pCsBuffPtr++;
   hspdif->CsXferCount--;
 
-  if(hspdif->CsXferCount == 0U)
+  if (hspdif->CsXferCount == 0U)
   {
     /* Disable CSRNE interrupt */
     __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
@@ -1569,9 +1593,9 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
     __HAL_UNLOCK(hspdif);
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-  hspdif->CxCpltCallback(hspdif);
+    hspdif->CxCpltCallback(hspdif);
 #else
-  HAL_SPDIFRX_CxCpltCallback(hspdif);
+    HAL_SPDIFRX_CxCpltCallback(hspdif);
 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
   }
 }
@@ -1585,17 +1609,19 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif)
   * @param tickstart Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
+static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag,
+                                                        FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
 {
   /* Wait until flag is set */
-  while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
+  while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status)
   {
     /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    if (Timeout != HAL_MAX_DELAY)
     {
-      if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U))
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
       {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt
+           process */
         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE);
         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE);
         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE);
@@ -1604,7 +1630,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE);
         __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE);
 
-        hspdif->State= HAL_SPDIFRX_STATE_READY;
+        hspdif->State = HAL_SPDIFRX_STATE_READY;
 
         /* Process Unlocked */
         __HAL_UNLOCK(hspdif);
@@ -1631,5 +1657,3 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.h
index 66176ec243..7c58960964 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,7 +21,7 @@
 #define STM32H7xx_HAL_SPDIFRX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -57,7 +56,8 @@ typedef struct
   uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.
                                           This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
 
-  uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.
+  uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status
+                                          from channel A or B.
                                           This parameter can be a value of @ref SPDIFRX_Channel_Selection */
 
   uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).
@@ -66,22 +66,25 @@ typedef struct
   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
 
-  uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
-                                           This parameter can be a value of @ref SPDIFRX_PT_Mask */
+  uint32_t PreambleTypeMask;         /*!< Specifies whether The preamble type bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PT_Mask */
 
-  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
+  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not
+                                          into the received frame.
                                           This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
 
   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
                                           This parameter can be a value of @ref SPDIFRX_V_Mask */
 
-  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
+  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not
+                                          into the received frame.
                                           This parameter can be a value of @ref SPDIFRX_PE_Mask */
   FunctionalState SymbolClockGen;     /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
-                                          This parameter can be set to Enable or Disable */
+                                           This parameter can be set to Enable or Disable */
 
   FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
-                                          This parameter can be set to Enable or Disable */
+                                             This parameter can be set to Enable or Disable */
 } SPDIFRX_InitTypeDef;
 
 /**
@@ -95,17 +98,20 @@ typedef struct
   uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.
                                           This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
 
-  uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.
-                                                                                   This parameter can be a value of @ref SPDIFRX_PT_Mask */
+  uint32_t PreambleTypeMask;         /*!< Specifies whether The preamble type bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PT_Mask */
 
-  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
-                                                                                  This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
+  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
 
   uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.
-                                                                                  This parameter can be a value of @ref SPDIFRX_V_Mask */
+                                          This parameter can be a value of @ref SPDIFRX_V_Mask */
 
-  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.
-                                                                                  This parameter can be a value of @ref SPDIFRX_PE_Mask */
+  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not
+                                          into the received frame.
+                                          This parameter can be a value of @ref SPDIFRX_PE_Mask */
 
 } SPDIFRX_SetDataFormatTypeDef;
 
@@ -129,7 +135,7 @@ typedef enum
 typedef struct __SPDIFRX_HandleTypeDef
 #else
 typedef struct
-#endif
+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
 {
   SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */
 
@@ -157,7 +163,8 @@ typedef struct
                                                decremented when a sample is received.
                                                NbSamplesReceived = RxBufferSize-RxBufferCount) */
 
-  DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
+  DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information
+                                              DMA handle parameters */
 
   DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */
 
@@ -168,19 +175,18 @@ typedef struct
   __IO uint32_t  ErrorCode;                /* SPDIFRX Error code */
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-  void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Data flow half completed callback */
+  void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Data flow half completed
+                                                                             callback */
   void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Data flow completed callback */
-  void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Control flow half completed callback */
+  void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Control flow half completed
+                                                                             callback */
   void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Control flow completed callback */
   void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);        /*!< SPDIFRX error callback */
-  void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif);   /*!< SPDIFRX Msp Init callback  */
-  void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback  */
+  void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);     /*!< SPDIFRX Msp Init callback  */
+  void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Msp DeInit callback  */
 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
 
 } SPDIFRX_HandleTypeDef;
-/**
-  * @}
-  */
 
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
 /**
@@ -195,14 +201,17 @@ typedef enum
   HAL_SPDIFRX_ERROR_CB_ID     = 0x04U,    /*!< SPDIFRX error callback */
   HAL_SPDIFRX_MSPINIT_CB_ID   = 0x05U,    /*!< SPDIFRX Msp Init callback ID     */
   HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U     /*!< SPDIFRX Msp DeInit callback ID   */
-}HAL_SPDIFRX_CallbackIDTypeDef;
+} HAL_SPDIFRX_CallbackIDTypeDef;
 
 /**
   * @brief  HAL SPDIFRX Callback pointer definition
   */
-typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */
+typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif);  /*!< pointer to an SPDIFRX callback
+                                                                                function */
 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
-
+/**
+  * @}
+  */
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
   * @{
@@ -266,15 +275,17 @@ typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
 /** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask
   * @{
   */
-#define SPDIFRX_CHANNELSTATUS_OFF   ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */
-#define SPDIFRX_CHANNELSTATUS_ON    ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
+#define SPDIFRX_CHANNELSTATUS_OFF   ((uint32_t)0x00000000U)       /* The channel status and user bits are copied
+                                                                     into the SPDIF_DR */
+#define SPDIFRX_CHANNELSTATUS_ON    ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied
+                                                                     into the SPDIF_DR, zeros are written instead*/
 /**
   * @}
   */
 
 /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
-* @{
-*/
+  * @{
+  */
 #define SPDIFRX_VALIDITYMASK_OFF    ((uint32_t)0x00000000U)
 #define SPDIFRX_VALIDITYMASK_ON     ((uint32_t)SPDIFRX_CR_VMSK)
 /**
@@ -374,10 +385,10 @@ typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
   */
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0)
+                                                         (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\
+                                                         (__HANDLE__)->MspInitCallback = NULL;\
+                                                         (__HANDLE__)->MspDeInitCallback = NULL;\
+                                                       }while(0)
 #else
 #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)
 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
@@ -416,7 +427,8 @@ typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
   * @retval None
   */
 #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
-#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\
+                                                             &= (uint16_t)(~(__INTERRUPT__)))
 
 /** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.
   * @param  __HANDLE__    specifies the SPDIFRX Handle.
@@ -431,7 +443,8 @@ typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
   *            @arg SPDIFRX_IT_IFEIE
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
+                                                                  & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified SPDIFRX flag is set or not.
   * @param  __HANDLE__  specifies the SPDIFRX Handle.
@@ -448,7 +461,8 @@ typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
   *            @arg SPDIFRX_FLAG_TERR
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\
+                                                        & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
 
 /** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
   * @param  __HANDLE__    specifies the USART Handle.
@@ -477,15 +491,17 @@ typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!<
   */
 /* Initialization/de-initialization functions  **********************************/
 HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
-HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
+HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif);
 void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
 void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
 HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID,
+                                               pSPDIFRX_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
+                                                 HAL_SPDIFRX_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */
 /**
   * @}
@@ -495,9 +511,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif,
   * @{
   */
 /* I/O operation functions  ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size,
+                                              uint32_t Timeout);
 
 /* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
@@ -523,8 +541,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
   * @{
   */
 /* Peripheral Control and State functions  ************************************/
-HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif);
-uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif);
+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif);
 /**
   * @}
   */
@@ -540,39 +558,39 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
   * @{
   */
 #define IS_SPDIFRX_INPUT_SELECT(INPUT)      (((INPUT) == SPDIFRX_INPUT_IN1) || \
-                                            ((INPUT) == SPDIFRX_INPUT_IN2)  || \
-                                            ((INPUT) == SPDIFRX_INPUT_IN3)  || \
-                                            ((INPUT) == SPDIFRX_INPUT_IN0))
+                                             ((INPUT) == SPDIFRX_INPUT_IN2)  || \
+                                             ((INPUT) == SPDIFRX_INPUT_IN3)  || \
+                                             ((INPUT) == SPDIFRX_INPUT_IN0))
 
 #define IS_SPDIFRX_MAX_RETRIES(RET)         (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
-                                            ((RET) == SPDIFRX_MAXRETRIES_3)     || \
-                                            ((RET) == SPDIFRX_MAXRETRIES_15)    || \
-                                            ((RET) == SPDIFRX_MAXRETRIES_63))
+                                             ((RET) == SPDIFRX_MAXRETRIES_3)     || \
+                                             ((RET) == SPDIFRX_MAXRETRIES_15)    || \
+                                             ((RET) == SPDIFRX_MAXRETRIES_63))
 
 #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)   (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
-                                            ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
+                                             ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
 
 #define IS_PREAMBLE_TYPE_MASK(VAL)          (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
-                                            ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
+                                             ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
 
 #define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
-                                            ((VAL) == SPDIFRX_VALIDITYMASK_ON))
+                                             ((VAL) == SPDIFRX_VALIDITYMASK_ON))
 
 #define IS_PARITY_ERROR_MASK(VAL)           (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
-                                            ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
+                                             ((VAL) == SPDIFRX_PARITYERRORMASK_ON))
 
 #define IS_SPDIFRX_CHANNEL(CHANNEL)         (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
-                                            ((CHANNEL) == SPDIFRX_CHANNEL_B))
+                                             ((CHANNEL) == SPDIFRX_CHANNEL_B))
 
 #define IS_SPDIFRX_DATA_FORMAT(FORMAT)      (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
-                                            ((FORMAT) == SPDIFRX_DATAFORMAT_MSB)  || \
-                                            ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
+                                             ((FORMAT) == SPDIFRX_DATAFORMAT_MSB)  || \
+                                             ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
 
 #define IS_STEREO_MODE(MODE)                (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
-                                            ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
+                                             ((MODE) == SPDIFRX_STEREOMODE_ENABLE))
 
 #define IS_CHANNEL_STATUS_MASK(VAL)         (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
-                                            ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
+                                             ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
 
 #define IS_SYMBOL_CLOCK_GEN(VAL)            (((VAL) == ENABLE) || ((VAL) == DISABLE))
 /**
@@ -601,6 +619,4 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);
 #endif
 
 
-#endif /* __STM32H7xx_HAL_SPDIFRX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+#endif /* STM32H7xx_HAL_SPDIFRX_H */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c
index 95f6c25022..932eb3fb3d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### How to use this driver #####
@@ -34,7 +45,8 @@
               (+++) Configure the DMA handle parameters
               (+++) Configure the DMA Tx or Rx Stream/Channel
               (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
+              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx
+                    or Rx Stream/Channel
 
       (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
           management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
@@ -58,6 +70,7 @@
             (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
             (+) ErrorCallback         : SPI Error callback
             (+) AbortCpltCallback     : SPI Abort callback
+            (+) SuspendCallback       : SPI Suspend callback
             (+) MspInitCallback       : SPI Msp Init callback
             (+) MspDeInitCallback     : SPI Msp DeInit callback
           This function takes as parameters the HAL peripheral handle, the Callback ID
@@ -77,6 +90,7 @@
             (+) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
             (+) ErrorCallback         : SPI Error callback
             (+) AbortCpltCallback     : SPI Abort callback
+            (+) SuspendCallback       : SPI Suspend callback
             (+) MspInitCallback       : SPI Msp Init callback
             (+) MspDeInitCallback     : SPI Msp DeInit callback
 
@@ -97,10 +111,13 @@
        using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
        or HAL_SPI_Init() function.
 
-       When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
-       not defined, the callback registering feature is not available
-       and weak (surcharged) callbacks are used.
+       When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined,
+       the callback registering feature is not available and weak callbacks are used.
 
+       SuspendCallback restriction:
+           SuspendCallback is called only when MasterReceiverAutoSusp is enabled and
+       EOT interrupt is activated. SuspendCallback is used in relation with functions
+       HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT.
 
     [..]
       Circular mode restriction:
@@ -113,18 +130,6 @@
           Those functions are maintained for backward compatibility reasons.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -146,7 +151,6 @@
   * @{
   */
 #define SPI_DEFAULT_TIMEOUT 100UL
-#define MAX_FIFO_LENGTH     16UL
 /**
   * @}
   */
@@ -167,8 +171,8 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma);
 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus FlagStatus,
-                                                    uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag,
+                                                    FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart);
 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi);
 static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi);
 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi);
@@ -177,7 +181,7 @@ static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi);
 static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi);
 static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi);
 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi);
-static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
+static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi);
 
 
 /**
@@ -190,8 +194,8 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
   */
 
 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
+  *  @brief    Initialization and Configuration functions
+  *
 @verbatim
  ===============================================================================
               ##### Initialization and de-initialization functions #####
@@ -234,12 +238,11 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi);
   */
 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
 {
-#if (USE_SPI_CRC != 0UL)
   uint32_t crc_length;
-#else
-  uint32_t crc_length = 0UL;
-#endif
   uint32_t packet_length;
+#if (USE_SPI_CRC != 0UL)
+  uint32_t crc_poly_msb_mask;
+#endif /* USE_SPI_CRC */
 
   /* Check the SPI handle allocation */
   if (hspi == NULL)
@@ -267,8 +270,8 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
-    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
     assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
+    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
     assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern));
     assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern));
   }
@@ -309,6 +312,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
       crc_length = hspi->Init.CRCLength;
     }
 
+    /* Verify the correctness of polynom size */
+    assert_param(IS_SPI_CRC_POLYNOMIAL_SIZE(hspi->Init.CRCPolynomial, crc_length));
+
     /* Verify that the CRC Length is higher than DataSize */
     if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos))
     {
@@ -336,6 +342,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
     hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
     hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
     hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
+    hspi->SuspendCallback      = HAL_SPI_SuspendCallback;      /* Legacy weak SuspendCallback      */
 
     if (hspi->MspInitCallback == NULL)
     {
@@ -355,26 +362,45 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
   /* Disable the selected SPI peripheral */
   __HAL_SPI_DISABLE(hspi);
 
+#if (USE_SPI_CRC == 0)
+  /* Keep the default value of CRCSIZE in case of CRC is not used */
+  crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE;
+#endif /* USE_SPI_CRC */
+
   /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
   /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
   Communication speed, First bit, CRC calculation state, CRC Length */
 
   /* SPIx NSS Software Management Configuration */
-  if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
-     ((hspi->Init.Mode == SPI_MODE_SLAVE) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
+  if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) &&  \
+                                            (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
+                                           ((hspi->Init.Mode == SPI_MODE_SLAVE) && \
+                                            (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
   {
     SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
   }
 
+  /* SPIx Master Rx Auto Suspend Configuration */
+  if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT))
+  {
+    MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp);
+  }
+  else
+  {
+    CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX);
+  }
+
   /* SPIx CFG1 Configuration */
   WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
                                    hspi->Init.FifoThreshold     | hspi->Init.DataSize));
 
   /* SPIx CFG2 Configuration */
-  WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode     | hspi->Init.TIMode           | hspi->Init.NSSPolarity             |
-                                   hspi->Init.NSS          | hspi->Init.CLKPolarity      | hspi->Init.CLKPhase                |
-                                   hspi->Init.FirstBit     | hspi->Init.Mode             | hspi->Init.MasterInterDataIdleness |
-                                   hspi->Init.Direction    | hspi->Init.MasterSSIdleness | hspi->Init.IOSwap));
+  WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode                | hspi->Init.TIMode    |
+                                   hspi->Init.NSSPolarity             | hspi->Init.NSS       |
+                                   hspi->Init.CLKPolarity             | hspi->Init.CLKPhase  |
+                                   hspi->Init.FirstBit                | hspi->Init.Mode      |
+                                   hspi->Init.MasterInterDataIdleness | hspi->Init.Direction |
+                                   hspi->Init.MasterSSIdleness        | hspi->Init.IOSwap));
 
 #if (USE_SPI_CRC != 0UL)
   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
@@ -405,15 +431,21 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
     if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) ||
         ((IS_SPI_HIGHEND_INSTANCE(hspi->Instance))  && (crc_length == SPI_CRC_LENGTH_32BIT)))
     {
+      /* Set SPI_CR1_CRC33_17 bit */
       SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
+      /* Write CRC polynomial in SPI Register */
+      WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
     }
     else
     {
+      /* Clear SPI_CR1_CRC33_17 bit */
       CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17);
-    }
 
-    /* Write CRC polynomial in SPI Register */
-    WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial);
+      /* Write CRC polynomial and set MSB bit at 1 in SPI Register */
+      /* Set MSB is mandatory for a correct CRC computation        */
+      crc_poly_msb_mask = (0x1UL << ((crc_length >> SPI_CFG1_CRCSIZE_Pos) + 0x1U));
+      WRITE_REG(hspi->Instance->CRCPOLY, (hspi->Init.CRCPolynomial) | crc_poly_msb_mask);
+    }
   }
 #endif /* USE_SPI_CRC */
 
@@ -423,7 +455,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
     /* Set Default Underrun configuration */
 #if (USE_SPI_CRC != 0UL)
     if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_DISABLE)
-#endif
+#endif /* USE_SPI_CRC */
     {
       MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
     }
@@ -532,9 +564,12 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
   *                the configuration information for the specified SPI.
   * @param  CallbackID ID of the callback to be registered
   * @param  pCallback pointer to the Callback function
+  * @note   The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
+  *         to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+                                           pSPI_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -545,8 +580,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(hspi);
 
   if (HAL_SPI_STATE_READY == hspi->State)
   {
@@ -584,6 +617,10 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call
         hspi->AbortCpltCallback = pCallback;
         break;
 
+      case HAL_SPI_SUSPEND_CB_ID :
+        hspi->SuspendCallback = pCallback;
+        break;
+
       case HAL_SPI_MSPINIT_CB_ID :
         hspi->MspInitCallback = pCallback;
         break;
@@ -631,8 +668,6 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
   return status;
 }
 
@@ -642,15 +677,14 @@ HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Call
   * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
   *                the configuration information for the specified SPI.
   * @param  CallbackID ID of the callback to be unregistered
+  * @note   The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET
+  *         to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
   if (HAL_SPI_STATE_READY == hspi->State)
   {
     switch (CallbackID)
@@ -687,6 +721,10 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
         hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
         break;
 
+      case HAL_SPI_SUSPEND_CB_ID :
+        hspi->SuspendCallback = HAL_SPI_SuspendCallback;           /* Legacy weak SuspendCallback      */
+        break;
+
       case HAL_SPI_MSPINIT_CB_ID :
         hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
         break;
@@ -734,8 +772,6 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
   return status;
 }
 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@@ -744,8 +780,8 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
   */
 
 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
+  *  @brief   Data transfers functions
+  *
 @verbatim
   ==============================================================================
                       ##### IO operation functions #####
@@ -785,42 +821,37 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
 #if defined (__GNUC__)
   __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
 #endif /* __GNUC__ */
 
   uint32_t tickstart;
-  HAL_StatusTypeDef errorcode = HAL_OK;
 
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
 
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
   /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
   if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_TX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->pTxBuffPtr  = (const uint8_t *)pData;
   hspi->TxXferSize  = Size;
   hspi->TxXferCount = Size;
 
@@ -836,6 +867,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   {
     SPI_1LINE_TX(hspi);
   }
+  else
+  {
+    SPI_2LINES_TX(hspi);
+  }
 
   /* Set the number of data at current transfer */
   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
@@ -858,7 +893,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
       /* Wait until TXP flag is set to send data */
       if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP))
       {
-        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
         hspi->pTxBuffPtr += sizeof(uint32_t);
         hspi->TxXferCount--;
       }
@@ -870,12 +905,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
           /* Call standard close procedure with error check */
           SPI_CloseTransfer(hspi);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
           hspi->State = HAL_SPI_STATE_READY;
-          return HAL_ERROR;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
         }
       }
     }
@@ -891,16 +927,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
       {
         if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
         {
-          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
           hspi->pTxBuffPtr += sizeof(uint32_t);
           hspi->TxXferCount -= (uint16_t)2UL;
         }
         else
         {
 #if defined (__GNUC__)
-          *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+          *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
 #else
-          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
 #endif /* __GNUC__ */
           hspi->pTxBuffPtr += sizeof(uint16_t);
           hspi->TxXferCount--;
@@ -914,12 +950,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
           /* Call standard close procedure with error check */
           SPI_CloseTransfer(hspi);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
           hspi->State = HAL_SPI_STATE_READY;
-          return HAL_ERROR;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
         }
       }
     }
@@ -934,23 +971,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
       {
         if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
         {
-          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
           hspi->pTxBuffPtr += sizeof(uint32_t);
           hspi->TxXferCount -= (uint16_t)4UL;
         }
         else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
         {
 #if defined (__GNUC__)
-          *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+          *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
 #else
-          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
 #endif /* __GNUC__ */
           hspi->pTxBuffPtr += sizeof(uint16_t);
           hspi->TxXferCount -= (uint16_t)2UL;
         }
         else
         {
-          *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
+          *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
           hspi->pTxBuffPtr += sizeof(uint8_t);
           hspi->TxXferCount--;
         }
@@ -963,19 +1000,20 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
           /* Call standard close procedure with error check */
           SPI_CloseTransfer(hspi);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
           hspi->State = HAL_SPI_STATE_READY;
-          return HAL_ERROR;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
         }
       }
     }
   }
 
   /* Wait for Tx (and CRC) data to be sent */
-  if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+  if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
   {
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
   }
@@ -983,16 +1021,19 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
   /* Call standard close procedure with error check */
   SPI_CloseTransfer(hspi);
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
   hspi->State = HAL_SPI_STATE_READY;
 
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
     return HAL_ERROR;
   }
-  return errorcode;
+  else
+  {
+    return HAL_OK;
+  }
 }
 
 /**
@@ -1007,7 +1048,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint32_t tickstart;
-  HAL_StatusTypeDef errorcode = HAL_OK;
+  uint32_t temp_sr_reg;
+  uint16_t init_max_data_in_fifo;
+  init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
 #if defined (__GNUC__)
   __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
 #endif /* __GNUC__ */
@@ -1015,33 +1058,22 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
 
-  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
   /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
   if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
@@ -1061,6 +1093,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   {
     SPI_1LINE_RX(hspi);
   }
+  else
+  {
+    SPI_2LINES_RX(hspi);
+  }
 
   /* Set the number of data at current transfer */
   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
@@ -1080,8 +1116,18 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
     /* Transfer loop */
     while (hspi->RxXferCount > 0UL)
     {
-      /* Check the RXWNE/EOT flag */
-      if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL)
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      /* Check the RXP flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+      {
+        *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint32_t);
+        hspi->RxXferCount--;
+      }
+      /* Check RXWNE flag if RXP cannot be reached */
+      else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
       {
         *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
         hspi->pRxBuffPtr += sizeof(uint32_t);
@@ -1095,12 +1141,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
           /* Call standard close procedure with error check */
           SPI_CloseTransfer(hspi);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
           hspi->State = HAL_SPI_STATE_READY;
-          return HAL_ERROR;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
         }
       }
     }
@@ -1111,25 +1158,47 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
     /* Transfer loop */
     while (hspi->RxXferCount > 0UL)
     {
-      /* Check the RXWNE/FRLVL flag */
-      if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      /* Check the RXP flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
       {
-        if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
-        {
-          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
-          hspi->pRxBuffPtr += sizeof(uint32_t);
-          hspi->RxXferCount -= (uint16_t)2UL;
-        }
-        else
-        {
 #if defined (__GNUC__)
-          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
 #else
-          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
 #endif /* __GNUC__ */
-          hspi->pRxBuffPtr += sizeof(uint16_t);
-          hspi->RxXferCount--;
-        }
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount--;
+      }
+      /* Check RXWNE flag if RXP cannot be reached */
+      else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+      {
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount -= (uint16_t)2UL;
+      }
+      /* Check RXPLVL flags when RXWNE cannot be reached */
+      else if ((hspi->RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
+      {
+#if defined (__GNUC__)
+        *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+        *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+        hspi->pRxBuffPtr += sizeof(uint16_t);
+        hspi->RxXferCount--;
       }
       else
       {
@@ -1139,12 +1208,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
           /* Call standard close procedure with error check */
           SPI_CloseTransfer(hspi);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
           hspi->State = HAL_SPI_STATE_READY;
-          return HAL_ERROR;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
         }
       }
     }
@@ -1155,31 +1225,35 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
     /* Transfer loop */
     while (hspi->RxXferCount > 0UL)
     {
-      /* Check the RXWNE/FRLVL flag */
-      if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL)
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      /* Check the RXP flag */
+      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
       {
-        if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
-        {
-          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
-          hspi->pRxBuffPtr += sizeof(uint32_t);
-          hspi->RxXferCount -= (uint16_t)4UL;
-        }
-        else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
-        {
-#if defined (__GNUC__)
-          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
-#else
-          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
-#endif /* __GNUC__ */
-          hspi->pRxBuffPtr += sizeof(uint16_t);
-          hspi->RxXferCount -= (uint16_t)2UL;
-        }
-        else
-        {
-          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
-          hspi->pRxBuffPtr += sizeof(uint8_t);
-          hspi->RxXferCount--;
-        }
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        hspi->RxXferCount--;
+      }
+      /* Check RXWNE flag if RXP cannot be reached */
+      else if ((hspi->RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+      {
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        hspi->RxXferCount -= (uint16_t)4UL;
+      }
+      /* Check RXPLVL flags when RXWNE cannot be reached */
+      else if ((hspi->RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
+      {
+        *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+        hspi->pRxBuffPtr += sizeof(uint8_t);
+        hspi->RxXferCount--;
       }
       else
       {
@@ -1189,12 +1263,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
           /* Call standard close procedure with error check */
           SPI_CloseTransfer(hspi);
 
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
           SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
           hspi->State = HAL_SPI_STATE_READY;
-          return HAL_ERROR;
+
+          /* Unlock the process */
+          __HAL_UNLOCK(hspi);
+
+          return HAL_TIMEOUT;
         }
       }
     }
@@ -1204,7 +1279,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
   {
     /* Wait for crc data to be received */
-    if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+    if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
     {
       SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
     }
@@ -1214,16 +1289,20 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   /* Call standard close procedure with error check */
   SPI_CloseTransfer(hspi);
 
-  /* Process Unlocked */
+  hspi->State = HAL_SPI_STATE_READY;
+
+  /* Unlock the process */
   __HAL_UNLOCK(hspi);
 
-  hspi->State = HAL_SPI_STATE_READY;
 
   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
     return HAL_ERROR;
   }
-  return errorcode;
+  else
+  {
+    return HAL_OK;
+  }
 }
 
 /**
@@ -1236,62 +1315,51 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1
   * @param  Timeout: Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                          uint16_t Size, uint32_t Timeout)
 {
-  HAL_SPI_StateTypeDef tmp_state;
-  HAL_StatusTypeDef errorcode = HAL_OK;
 #if defined (__GNUC__)
   __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
   __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
 #endif /* __GNUC__ */
 
   uint32_t   tickstart;
-  uint32_t   tmp_mode;
+  uint32_t   fifo_length;
+  uint32_t   temp_sr_reg;
   uint16_t   initial_TxXferCount;
   uint16_t   initial_RxXferCount;
+  uint16_t   init_max_data_in_fifo;
+  init_max_data_in_fifo = (((uint16_t)(hspi->Init.FifoThreshold >> 5U) + 1U));
 
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
   /* Init tickstart for timeout management*/
   tickstart = HAL_GetTick();
 
   initial_TxXferCount = Size;
   initial_RxXferCount = Size;
-  tmp_state           = hspi->State;
-  tmp_mode            = hspi->Init.Mode;
 
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+  if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
+  /* Lock the process */
+  __HAL_LOCK(hspi);
 
   /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
   hspi->RxXferCount = Size;
   hspi->RxXferSize  = Size;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->pTxBuffPtr  = (const uint8_t *)pTxData;
   hspi->TxXferCount = Size;
   hspi->TxXferSize  = Size;
 
@@ -1299,6 +1367,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   hspi->RxISR       = NULL;
   hspi->TxISR       = NULL;
 
+  /* Set Full-Duplex mode */
+  SPI_2LINES(hspi);
+
+  /* Initialize FIFO length */
+  if (IS_SPI_HIGHEND_INSTANCE(hspi->Instance))
+  {
+    fifo_length = SPI_HIGHEND_FIFO_SIZE;
+  }
+  else
+  {
+    fifo_length = SPI_LOWEND_FIFO_SIZE;
+  }
+
   /* Set the number of data at current transfer */
   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
 
@@ -1313,80 +1394,91 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   /* Transmit and Receive data in 32 Bit mode */
   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
   {
+    /* Adapt fifo length to 32bits data width */
+    fifo_length = (fifo_length / 4UL);
+
     while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
     {
       /* Check TXP flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+          (initial_RxXferCount  < (initial_TxXferCount + fifo_length)))
       {
-        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
         hspi->pTxBuffPtr += sizeof(uint32_t);
         hspi->TxXferCount --;
         initial_TxXferCount = hspi->TxXferCount;
       }
 
-      /* Check RXWNE/EOT flag */
-      if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL))
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      if (initial_RxXferCount > 0UL)
       {
-        *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
-        hspi->pRxBuffPtr += sizeof(uint32_t);
-        hspi->RxXferCount --;
-        initial_RxXferCount = hspi->RxXferCount;
-      }
+        /* Check the RXP flag */
+        if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
+        {
+          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint32_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXWNE flag if RXP cannot be reached */
+        else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+        {
+          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint32_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        else
+        {
+          /* Timeout management */
+          if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+          {
+            /* Call standard close procedure with error check */
+            SPI_CloseTransfer(hspi);
 
-      /* Timeout management */
-      if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-      {
-        /* Call standard close procedure with error check */
-        SPI_CloseTransfer(hspi);
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+            hspi->State = HAL_SPI_STATE_READY;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
+            /* Unlock the process */
+            __HAL_UNLOCK(hspi);
 
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
-        hspi->State = HAL_SPI_STATE_READY;
-        return HAL_ERROR;
+            return HAL_TIMEOUT;
+          }
+        }
       }
     }
   }
   /* Transmit and Receive data in 16 Bit mode */
   else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
   {
+    /* Adapt fifo length to 16bits data width */
+    fifo_length = (fifo_length / 2UL);
+
     while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
     {
-      /* Check TXP flag */
-      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP) && (initial_TxXferCount > 0UL))
+      /* Check the TXP flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+          (initial_RxXferCount  < (initial_TxXferCount + fifo_length)))
       {
-        if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
-        {
-          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint32_t);
-          hspi->TxXferCount -= (uint16_t)2UL;
-          initial_TxXferCount = hspi->TxXferCount;
-        }
-        else
-        {
 #if defined (__GNUC__)
-          *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+        *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
 #else
-          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+        *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
 #endif /* __GNUC__ */
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount--;
-          initial_TxXferCount = hspi->TxXferCount;
-        }
+        hspi->pTxBuffPtr += sizeof(uint16_t);
+        hspi->TxXferCount--;
+        initial_TxXferCount = hspi->TxXferCount;
       }
 
-      /* Check RXWNE/FRLVL flag */
-      if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      if (initial_RxXferCount > 0UL)
       {
-        if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
-        {
-          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
-          hspi->pRxBuffPtr += sizeof(uint32_t);
-          hspi->RxXferCount -= (uint16_t)2UL;
-          initial_RxXferCount = hspi->RxXferCount;
-        }
-        else
+        /* Check the RXP flag */
+        if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
         {
 #if defined (__GNUC__)
           *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
@@ -1397,20 +1489,53 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
           hspi->RxXferCount--;
           initial_RxXferCount = hspi->RxXferCount;
         }
-      }
+        /* Check RXWNE flag if RXP cannot be reached */
+        else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+          hspi->RxXferCount -= (uint16_t)2UL;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXPLVL flags when RXWNE cannot be reached */
+        else if ((initial_RxXferCount == 1UL) && ((temp_sr_reg & SPI_SR_RXPLVL_0) != 0UL))
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
+#else
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        else
+        {
+          /* Timeout management */
+          if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+          {
+            /* Call standard close procedure with error check */
+            SPI_CloseTransfer(hspi);
 
-      /* Timeout management */
-      if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-      {
-        /* Call standard close procedure with error check */
-        SPI_CloseTransfer(hspi);
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+            hspi->State = HAL_SPI_STATE_READY;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
+            /* Unlock the process */
+            __HAL_UNLOCK(hspi);
 
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
-        hspi->State = HAL_SPI_STATE_READY;
-        return HAL_ERROR;
+            return HAL_TIMEOUT;
+          }
+        }
       }
     }
   }
@@ -1419,84 +1544,74 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   {
     while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL))
     {
-      /* check TXP flag */
-      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL))
+      /* Check the TXP flag */
+      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) &&
+          (initial_RxXferCount  < (initial_TxXferCount + fifo_length)))
       {
-        if ((initial_TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
-        {
-          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint32_t);
-          hspi->TxXferCount -= (uint16_t)4UL;
-          initial_TxXferCount = hspi->TxXferCount;
-        }
-        else if ((initial_TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
-        {
-#if defined (__GNUC__)
-          *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
-#else
-          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
-#endif /* __GNUC__ */
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount -= (uint16_t)2UL;
-          initial_TxXferCount = hspi->TxXferCount;
-        }
-        else
-        {
-          *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint8_t);
-          hspi->TxXferCount--;
-          initial_TxXferCount = hspi->TxXferCount;
-        }
+        *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
+        hspi->pTxBuffPtr += sizeof(uint8_t);
+        hspi->TxXferCount--;
+        initial_TxXferCount = hspi->TxXferCount;
       }
 
-      /* Wait until RXWNE/FRLVL flag is reset */
-      if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_FRLVL)) != 0UL) && (initial_RxXferCount > 0UL))
+      /* Evaluate state of SR register */
+      temp_sr_reg = hspi->Instance->SR;
+
+      if (initial_RxXferCount > 0UL)
       {
-        if ((hspi->Instance->SR & SPI_FLAG_RXWNE) != 0UL)
-        {
-          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
-          hspi->pRxBuffPtr += sizeof(uint32_t);
-          hspi->RxXferCount -= (uint16_t)4UL;
-          initial_RxXferCount = hspi->RxXferCount;
-        }
-        else if ((hspi->Instance->SR & SPI_FLAG_FRLVL) > SPI_RX_FIFO_1PACKET)
-        {
-#if defined (__GNUC__)
-          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
-#else
-          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
-#endif /* __GNUC__ */
-          hspi->pRxBuffPtr += sizeof(uint16_t);
-          hspi->RxXferCount -= (uint16_t)2UL;
-          initial_RxXferCount = hspi->RxXferCount;
-        }
-        else
+        /* Check the RXP flag */
+        if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP))
         {
           *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
           hspi->pRxBuffPtr += sizeof(uint8_t);
           hspi->RxXferCount--;
           initial_RxXferCount = hspi->RxXferCount;
         }
-      }
+        /* Check RXWNE flag if RXP cannot be reached */
+        else if ((initial_RxXferCount < init_max_data_in_fifo) && ((temp_sr_reg & SPI_SR_RXWNE_Msk) != 0UL))
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          hspi->RxXferCount -= (uint16_t)4UL;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        /* Check RXPLVL flags when RXWNE cannot be reached */
+        else if ((initial_RxXferCount < 4UL) && ((temp_sr_reg & SPI_SR_RXPLVL_Msk) != 0UL))
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+          hspi->RxXferCount--;
+          initial_RxXferCount = hspi->RxXferCount;
+        }
+        else
+        {
+          /* Timeout management */
+          if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
+          {
+            /* Call standard close procedure with error check */
+            SPI_CloseTransfer(hspi);
 
-      /* Timeout management */
-      if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
-      {
-        /* Call standard close procedure with error check */
-        SPI_CloseTransfer(hspi);
+            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
+            hspi->State = HAL_SPI_STATE_READY;
 
-        /* Process Unlocked */
-        __HAL_UNLOCK(hspi);
+            /* Unlock the process */
+            __HAL_UNLOCK(hspi);
 
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT);
-        hspi->State = HAL_SPI_STATE_READY;
-        return HAL_ERROR;
+            return HAL_TIMEOUT;
+          }
+        }
       }
     }
   }
 
   /* Wait for Tx/Rx (and CRC) data to be sent/received */
-  if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, tickstart, Timeout) != HAL_OK)
+  if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK)
   {
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
   }
@@ -1504,16 +1619,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   /* Call standard close procedure with error check */
   SPI_CloseTransfer(hspi);
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
   hspi->State = HAL_SPI_STATE_READY;
 
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
   if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
   {
     return HAL_ERROR;
   }
-  return errorcode;
+  else
+  {
+    return HAL_OK;
+  }
 }
 
 /**
@@ -1524,34 +1642,28 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD
   * @param  Size : amount of data to be sent
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
 
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
   if ((pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_TX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->pTxBuffPtr  = (const uint8_t *)pData;
   hspi->TxXferSize  = Size;
   hspi->TxXferCount = Size;
 
@@ -1561,6 +1673,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   hspi->RxXferCount = (uint16_t) 0UL;
   hspi->RxISR       = NULL;
 
+#if defined(USE_SPI_RELOAD_TRANSFER)
+  hspi->Reload.Requested   = 0UL;
+  hspi->Reload.pTxBuffPtr  = NULL;
+  hspi->Reload.TxXferSize  = NULL;
+#endif /* USE_SPI_RELOAD_TRANSFER */
+
   /* Set the function for IT treatment */
   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
   {
@@ -1580,6 +1698,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   {
     SPI_1LINE_TX(hspi);
   }
+  else
+  {
+    SPI_2LINES_TX(hspi);
+  }
 
   /* Set the number of data at current transfer */
   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
@@ -1587,6 +1709,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   /* Enable SPI peripheral */
   __HAL_SPI_ENABLE(hspi);
 
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
   /* Enable EOT, TXP, FRE, MODF, UDR and TSERF interrupts */
   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
 
@@ -1596,8 +1721,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
   }
 
-  __HAL_UNLOCK(hspi);
-  return errorcode;
+  return HAL_OK;
 }
 
 /**
@@ -1610,35 +1734,22 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   */
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
 
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
   if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
@@ -1652,6 +1763,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
   hspi->TxXferCount = (uint16_t) 0UL;
   hspi->TxISR       = NULL;
 
+#if defined(USE_SPI_RELOAD_TRANSFER)
+  hspi->Reload.Requested   = 0UL;
+  hspi->Reload.pRxBuffPtr  = NULL;
+  hspi->Reload.RxXferSize  = NULL;
+#endif /* USE_SPI_RELOAD_TRANSFER */
+
   /* Set the function for IT treatment */
   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
   {
@@ -1671,6 +1788,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
   {
     SPI_1LINE_RX(hspi);
   }
+  else
+  {
+    SPI_2LINES_RX(hspi);
+  }
 
   /* Note : The SPI must be enabled after unlocking current process
             to avoid the risk of SPI interrupt handle execution before current
@@ -1682,6 +1803,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
   /* Enable SPI peripheral */
   __HAL_SPI_ENABLE(hspi);
 
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
   /* Enable EOT, RXP, OVR, FRE, MODF and TSERF interrupts */
   __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
 
@@ -1691,9 +1815,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
   }
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
+  return HAL_OK;
 }
 
 /**
@@ -1705,57 +1827,48 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
   * @param  Size   : amount of data to be sent and received
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size)
 {
-  HAL_SPI_StateTypeDef  tmp_state;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  uint32_t max_fifo_length = 0UL;
   uint32_t tmp_TxXferCount;
-  #if defined (__GNUC__)
+#if defined (__GNUC__)
   __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
-  #endif /* __GNUC__ */
-  uint32_t  tmp_mode;
+#endif /* __GNUC__ */
 
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  /* Init temporary variables */
-  tmp_state  = hspi->State;
-  tmp_mode   = hspi->Init.Mode;
-
-  if (!((tmp_state == HAL_SPI_STATE_READY) || \
-        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
+  if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
+  /* Lock the process */
+  __HAL_LOCK(hspi);
 
   /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->pTxBuffPtr  = (const uint8_t *)pTxData;
   hspi->TxXferSize  = Size;
   hspi->TxXferCount = Size;
   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
   hspi->RxXferSize  = Size;
   hspi->RxXferCount = Size;
-  tmp_TxXferCount = hspi->TxXferCount;
+  tmp_TxXferCount   = hspi->TxXferCount;
+
+#if defined(USE_SPI_RELOAD_TRANSFER)
+  hspi->Reload.Requested   = 0UL;
+  hspi->Reload.pRxBuffPtr  = NULL;
+  hspi->Reload.RxXferSize  = NULL;
+  hspi->Reload.pTxBuffPtr  = NULL;
+  hspi->Reload.TxXferSize  = NULL;
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
   /* Set the function for IT treatment */
   if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
@@ -1774,6 +1887,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
     hspi->TxISR     = SPI_TxISR_8BIT;
   }
 
+  /* Set Full-Duplex mode */
+  SPI_2LINES(hspi);
+
   /* Set the number of data at current transfer */
   MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size);
 
@@ -1783,90 +1899,50 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
   /* Fill in the TxFIFO */
   while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL))
   {
-    if (max_fifo_length < MAX_FIFO_LENGTH)
+    /* Transmit data in 32 Bit mode */
+    if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
     {
-      /* Transmit data in 32 Bit mode */
-      if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
-      {
-        *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr += sizeof(uint32_t);
-        hspi->TxXferCount--;
-        tmp_TxXferCount = hspi->TxXferCount;
-      }
-      /* Transmit data in 16 Bit mode */
-      else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-      {
-        if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
-        {
-          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint32_t);
-          hspi->TxXferCount -= (uint16_t)2UL;
-          tmp_TxXferCount = hspi->TxXferCount;
-        }
-        else
-        {
-#if defined (__GNUC__)
-          *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
-#else
-          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
-#endif /* __GNUC__ */
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount--;
-          tmp_TxXferCount = hspi->TxXferCount;
-        }
-      }
-      /* Transmit data in 8 Bit mode */
-      else
-      {
-        if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA))
-        {
-          *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint32_t);
-          hspi->TxXferCount -= (uint16_t)4UL;
-          tmp_TxXferCount = hspi->TxXferCount;
-        }
-        else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA))
-        {
-#if defined (__GNUC__)
-          *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
-#else
-          *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
-#endif /* __GNUC__ */
-          hspi->pTxBuffPtr += sizeof(uint16_t);
-          hspi->TxXferCount -= (uint16_t)2UL;
-          tmp_TxXferCount = hspi->TxXferCount;
-        }
-        else
-        {
-          *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr += sizeof(uint8_t);
-          hspi->TxXferCount--;
-          tmp_TxXferCount = hspi->TxXferCount;
-        }
-      }
-
-      max_fifo_length++;
+      *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint32_t);
+      hspi->TxXferCount--;
+      tmp_TxXferCount = hspi->TxXferCount;
     }
+    /* Transmit data in 16 Bit mode */
+    else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+    {
+#if defined (__GNUC__)
+      *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
+#else
+      *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
+#endif /* __GNUC__ */
+      hspi->pTxBuffPtr += sizeof(uint16_t);
+      hspi->TxXferCount--;
+      tmp_TxXferCount = hspi->TxXferCount;
+    }
+    /* Transmit data in 8 Bit mode */
     else
     {
-      errorcode = HAL_BUSY;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
+      *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr);
+      hspi->pTxBuffPtr += sizeof(uint8_t);
+      hspi->TxXferCount--;
+      tmp_TxXferCount = hspi->TxXferCount;
     }
   }
 
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
   /* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */
-  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
+  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR |
+                             SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF));
 
   if (hspi->Init.Mode == SPI_MODE_MASTER)
   {
-    /* Master transfer start */
+    /* Start Master transfer */
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
   }
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  return errorcode;
+  return HAL_OK;
 }
 
 #if defined(USE_SPI_RELOAD_TRANSFER)
@@ -1878,62 +1954,38 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
   * @param  Size : amount of data to be sent
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  HAL_SPI_StateTypeDef  tmp_state;
-
-  /* Lock the process */
-  __HAL_LOCK(hspi);
-
-  if ((pData == NULL) || (Size == 0UL))
+  /* check if there is already a request to reload */
+  if ((hspi->Reload.Requested == 1UL) || (pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   if (hspi->State == HAL_SPI_STATE_BUSY_TX)
   {
-    /* check if there is already a request to reload */
-    if (hspi->Reload.Requested == 1UL)
-    {
-      errorcode = HAL_ERROR;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
-    }
+    /* Lock the process */
+    __HAL_LOCK(hspi);
 
     /* Insert the new number of data to be sent just after the current one */
     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
 
     /* Set the transaction information */
     hspi->Reload.Requested   = 1UL;
-    hspi->Reload.pTxBuffPtr  = (uint8_t *)pData;
+    hspi->Reload.pTxBuffPtr  = (const uint8_t *)pData;
     hspi->Reload.TxXferSize  = Size;
 
-    tmp_state = hspi->State;
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
 
-    /* Check if the current transmit is already completed */
-    if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
-    {
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
-      MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
-      hspi->Reload.Requested = 0UL;
-      errorcode = HAL_ERROR;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
-    }
+    return HAL_OK;
   }
   else
   {
-    errorcode = HAL_ERROR;
-    return errorcode;
+    return HAL_ERROR;
   }
-
-  __HAL_UNLOCK(hspi);
-  return errorcode;
 }
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
 #if defined(USE_SPI_RELOAD_TRANSFER)
 /**
@@ -1946,28 +1998,16 @@ HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *p
   */
 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  HAL_SPI_StateTypeDef  tmp_state;
-
-  /* Lock the process */
-  __HAL_LOCK(hspi);
-
-  if ((pData == NULL) || (Size == 0UL))
+  /* check if there is already a request to reload */
+  if ((hspi->Reload.Requested == 1UL) || (pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   if (hspi->State == HAL_SPI_STATE_BUSY_RX)
   {
-    /* check if there is already a request to reload */
-    if (hspi->Reload.Requested == 1UL)
-    {
-      errorcode = HAL_ERROR;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
-    }
+    /* Lock the process */
+    __HAL_LOCK(hspi);
 
     /* Insert the new number of data that will be received just after the current one */
     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
@@ -1977,29 +2017,17 @@ HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pD
     hspi->Reload.pRxBuffPtr  = (uint8_t *)pData;
     hspi->Reload.RxXferSize  = Size;
 
-    tmp_state = hspi->State;
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
 
-    /* Check if the current reception is already completed */
-    if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
-    {
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
-      MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
-      hspi->Reload.Requested = 0UL;
-      errorcode = HAL_ERROR;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
-    }
+    return HAL_OK;
   }
   else
   {
-    errorcode = HAL_ERROR;
-    return errorcode;
+    return HAL_ERROR;
   }
-
-  __HAL_UNLOCK(hspi);
-  return errorcode;
 }
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
 #if defined(USE_SPI_RELOAD_TRANSFER)
 /**
@@ -2011,64 +2039,41 @@ HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pD
   * @param  Size   : amount of data to be sent and received
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData,
+                                                    uint8_t *pRxData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
-  HAL_SPI_StateTypeDef  tmp_state;
-
-  /* Lock the process */
-  __HAL_LOCK(hspi);
-
-  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
+  /* check if there is already a request to reload */
+  if ((hspi->Reload.Requested == 1UL) || (pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   if (hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
   {
-    /* check if there is already a request to reload */
-    if (hspi->Reload.Requested == 1UL)
-    {
-      errorcode = HAL_ERROR;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
-    }
+    /* Lock the process */
+    __HAL_LOCK(hspi);
 
     /* Insert the new number of data that will be sent and received just after the current one */
     MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, (Size & 0xFFFFFFFFUL) << 16UL);
 
     /* Set the transaction information */
     hspi->Reload.Requested   = 1UL;
-    hspi->Reload.pTxBuffPtr  = (uint8_t *)pTxData;
+    hspi->Reload.pTxBuffPtr  = (const uint8_t *)pTxData;
     hspi->Reload.TxXferSize  = Size;
     hspi->Reload.pRxBuffPtr  = (uint8_t *)pRxData;
     hspi->Reload.RxXferSize  = Size;
 
-    tmp_state = hspi->State;
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
 
-    /* Check if the current transmit is already completed */
-    if (((hspi->Instance->CR2 & SPI_CR2_TSER) != 0UL) && (tmp_state == HAL_SPI_STATE_READY))
-    {
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TSERF);
-      MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSER, 0UL);
-      hspi->Reload.Requested = 0UL;
-      errorcode = HAL_ERROR;
-      __HAL_UNLOCK(hspi);
-      return errorcode;
-    }
+    return HAL_OK;
   }
   else
   {
-    errorcode = HAL_ERROR;
-    return errorcode;
+    return HAL_ERROR;
   }
-
-  __HAL_UNLOCK(hspi);
-  return errorcode;
 }
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
 /**
   * @brief  Transmit an amount of data in non-blocking mode with DMA.
@@ -2078,34 +2083,29 @@ HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uin
   * @param  Size : amount of data to be sent
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
 
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction));
 
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-
   if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_TX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pData;
+  hspi->pTxBuffPtr  = (const uint8_t *)pData;
   hspi->TxXferSize  = Size;
   hspi->TxXferCount = Size;
 
@@ -2121,6 +2121,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
   {
     SPI_1LINE_TX(hspi);
   }
+  else
+  {
+    SPI_2LINES_TX(hspi);
+  }
 
   /* Packing mode management is enabled by the DMA settings */
   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
@@ -2128,9 +2132,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
                                                      (hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
   {
     /* Restriction the DMA data received is not allowed in this mode */
-    errorcode = HAL_ERROR;
     __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   /* Adjust XferCount according to DMA alignment / Data size */
@@ -2173,13 +2176,17 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN);
 
   /* Enable the Tx DMA Stream/Channel */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+                                 hspi->TxXferCount))
   {
     /* Update SPI error code */
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
     hspi->State = HAL_SPI_STATE_READY;
-    return errorcode;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
   }
 
   /* Set the number of data at current transfer */
@@ -2207,9 +2214,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
   }
 
-  /* Process Unlocked */
+  /* Unlock the process */
   __HAL_UNLOCK(hspi);
-  return errorcode;
+
+  return HAL_OK;
 }
 
 /**
@@ -2223,35 +2231,26 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
   */
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef errorcode = HAL_OK;
 
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
 
-  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_RX;
-    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hspi);
 
   if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
     __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
     __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
+  /* Lock the process */
+  __HAL_LOCK(hspi);
+
   /* Set the transaction information */
   hspi->State       = HAL_SPI_STATE_BUSY_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
@@ -2270,6 +2269,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   {
     SPI_1LINE_RX(hspi);
   }
+  else
+  {
+    SPI_2LINES_RX(hspi);
+  }
 
   /* Packing mode management is enabled by the DMA settings */
   if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))    || \
@@ -2277,9 +2280,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
                                                      (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
   {
     /* Restriction the DMA data received is not allowed in this mode */
-    errorcode = HAL_ERROR;
     __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   /* Clear RXDMAEN bit */
@@ -2322,13 +2324,17 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   hspi->hdmarx->XferAbortCallback = NULL;
 
   /* Enable the Rx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+                                 hspi->RxXferCount))
   {
     /* Update SPI error code */
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
     hspi->State = HAL_SPI_STATE_READY;
-    return errorcode;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
   }
 
   /* Set the number of data at current transfer */
@@ -2356,9 +2362,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
   }
 
-  /* Process Unlocked */
+  /* Unlock the process */
   __HAL_UNLOCK(hspi);
-  return errorcode;
+
+  return HAL_OK;
 }
 
 /**
@@ -2371,47 +2378,29 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
   * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
                                               uint16_t Size)
 {
-  HAL_SPI_StateTypeDef tmp_state;
-  HAL_StatusTypeDef errorcode = HAL_OK;
-
-  uint32_t             tmp_mode;
-
   /* Check Direction parameter */
   assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 
-  /* Process locked */
-  __HAL_LOCK(hspi);
-
-  /* Init temporary variables */
-  tmp_state   = hspi->State;
-  tmp_mode    = hspi->Init.Mode;
-
-  if (!(((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)) || (tmp_state == HAL_SPI_STATE_READY)))
+  if (hspi->State != HAL_SPI_STATE_READY)
   {
-    errorcode = HAL_BUSY;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_BUSY;
   }
 
   if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL))
   {
-    errorcode = HAL_ERROR;
-    __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
-  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
-  {
-    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-  }
+  /* Lock the process */
+  __HAL_LOCK(hspi);
 
   /* Set the transaction information */
+  hspi->State       = HAL_SPI_STATE_BUSY_TX_RX;
   hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
+  hspi->pTxBuffPtr  = (const uint8_t *)pTxData;
   hspi->TxXferSize  = Size;
   hspi->TxXferCount = Size;
   hspi->pRxBuffPtr  = (uint8_t *)pRxData;
@@ -2422,6 +2411,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   hspi->RxISR       = NULL;
   hspi->TxISR       = NULL;
 
+  /* Set Full-Duplex mode */
+  SPI_2LINES(hspi);
+
   /* Reset the Tx/Rx DMA bits */
   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
 
@@ -2431,10 +2423,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
                                                      (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
   {
     /* Restriction the DMA data received is not allowed in this mode */
-    errorcode = HAL_ERROR;
-    /* Process Unlocked */
+    /* Unlock the process */
     __HAL_UNLOCK(hspi);
-    return errorcode;
+    return HAL_ERROR;
   }
 
   /* Adjust XferCount according to DMA alignment / Data size */
@@ -2473,19 +2464,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
     /* Adjustment done */
   }
 
-  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
-  {
-    /* Set the SPI Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
-  }
-  else
-  {
-    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
-  }
+  /* Set the SPI Tx/Rx DMA Half transfer complete callback */
+  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
+  hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
 
   /* Set the DMA error callback */
   hspi->hdmarx->XferErrorCallback = SPI_DMAError;
@@ -2494,13 +2475,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   hspi->hdmarx->XferAbortCallback = NULL;
 
   /* Enable the Rx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount))
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr,
+                                 hspi->RxXferCount))
   {
     /* Update SPI error code */
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
     hspi->State = HAL_SPI_STATE_READY;
-    return errorcode;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
   }
 
   /* Enable Rx DMA Request */
@@ -2510,17 +2495,26 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   is performed in DMA reception complete callback  */
   hspi->hdmatx->XferHalfCpltCallback = NULL;
   hspi->hdmatx->XferCpltCallback     = NULL;
-  hspi->hdmatx->XferErrorCallback    = NULL;
   hspi->hdmatx->XferAbortCallback    = NULL;
 
+  /* Set the DMA error callback */
+  hspi->hdmatx->XferErrorCallback    = SPI_DMAError;
+
   /* Enable the Tx DMA Stream/Channel  */
-  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, hspi->TxXferCount))
+  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR,
+                                 hspi->TxXferCount))
   {
+    /* Abort Rx DMA Channel already started */
+    (void)HAL_DMA_Abort(hspi->hdmarx);
+
     /* Update SPI error code */
     SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-    errorcode = HAL_ERROR;
     hspi->State = HAL_SPI_STATE_READY;
-    return errorcode;
+
+    /* Unlock the process */
+    __HAL_UNLOCK(hspi);
+
+    return HAL_ERROR;
   }
 
   if (hspi->hdmatx->Init.Mode == DMA_CIRCULAR)
@@ -2547,9 +2541,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART);
   }
 
-  /* Process Unlocked */
+  /* Unlock the process */
   __HAL_UNLOCK(hspi);
-  return errorcode;
+
+  return HAL_OK;
 }
 
 /**
@@ -2564,14 +2559,14 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
   *          + Set handle State to READY.
   * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
   * @retval HAL status
-*/
+  */
 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
 {
   HAL_StatusTypeDef errorcode;
 
   __IO uint32_t count;
 
-  /* Process locked */
+  /* Lock the process */
   __HAL_LOCK(hspi);
 
   /* Set hspi->state to aborting to avoid any interaction */
@@ -2584,6 +2579,19 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
   /* If master communication on going, make sure current frame is done before closing the connection */
   if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
   {
+    /* Disable EOT interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
+
+    /* Request a Suspend transfer */
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
     do
     {
@@ -2593,8 +2601,19 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
         break;
       }
-    }
-    while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+    } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+
+    /* Clear SUSP flag */
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
   }
 
   /* Disable the SPI DMA Tx request if enabled */
@@ -2639,7 +2658,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
   SPI_AbortTransfer(hspi);
 
   /* Check error during Abort procedure */
-  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+  if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT))
   {
     /* return HAL_Error in case of error during Abort procedure */
     errorcode = HAL_ERROR;
@@ -2650,12 +2669,12 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
     hspi->ErrorCode = HAL_SPI_ERROR_NONE;
   }
 
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-
   /* Restore hspi->state to ready */
   hspi->State = HAL_SPI_STATE_READY;
 
+  /* Unlock the process */
+  __HAL_UNLOCK(hspi);
+
   return errorcode;
 }
 
@@ -2673,12 +2692,13 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
   * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
   *         considered as completed only when user abort complete callback is executed (not when exiting function).
   * @retval HAL status
-*/
+  */
 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
 {
   HAL_StatusTypeDef errorcode;
   __IO uint32_t count;
-  uint32_t dma_tx_abort_done = 1UL, dma_rx_abort_done = 1UL;
+  uint32_t dma_tx_abort_done = 1UL;
+  uint32_t dma_rx_abort_done = 1UL;
 
   /* Set hspi->state to aborting to avoid any interaction */
   hspi->State = HAL_SPI_STATE_ABORT;
@@ -2690,6 +2710,19 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
   /* If master communication on going, make sure current frame is done before closing the connection */
   if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART))
   {
+    /* Disable EOT interrupt */
+    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT));
+
+    /* Request a Suspend transfer */
     SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP);
     do
     {
@@ -2699,14 +2732,25 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
         SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
         break;
       }
-    }
-    while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+    } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
+
+    /* Clear SUSP flag */
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+    do
+    {
+      count--;
+      if (count == 0UL)
+      {
+        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
+        break;
+      }
+    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP));
   }
 
   /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
      before any call to DMA Abort functions */
 
-  if(hspi->hdmatx != NULL)
+  if (hspi->hdmatx != NULL)
   {
     if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
     {
@@ -2731,7 +2775,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
     }
   }
 
-  if(hspi->hdmarx != NULL)
+  if (hspi->hdmarx != NULL)
   {
     if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
     {
@@ -2763,7 +2807,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
     SPI_AbortTransfer(hspi);
 
     /* Check error during Abort procedure */
-    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
+    if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT))
     {
       /* return HAL_Error in case of error during Abort procedure */
       errorcode = HAL_ERROR;
@@ -2852,9 +2896,24 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
   __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR));
 #endif /* __GNUC__ */
 
+  /* SPI in SUSPEND mode  ----------------------------------------------------*/
+  if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
+  {
+    /* Clear the Suspend flag */
+    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
+
+    /* Suspend on going, Call the Suspend callback */
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+    hspi->SuspendCallback(hspi);
+#else
+    HAL_SPI_SuspendCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+    return;
+  }
 
   /* SPI in mode Transmitter and Receiver ------------------------------------*/
-  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
+  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \
+      HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP))
   {
     hspi->TxISR(hspi);
     hspi->RxISR(hspi);
@@ -2862,14 +2921,16 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
   }
 
   /* SPI in mode Receiver ----------------------------------------------------*/
-  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \
+      HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
   {
     hspi->RxISR(hspi);
     handled = 1UL;
   }
 
   /* SPI in mode Transmitter -------------------------------------------------*/
-  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
+  if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \
+      HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP))
   {
     hspi->TxISR(hspi);
     handled = 1UL;
@@ -2879,10 +2940,9 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
   /* SPI Reload  -------------------------------------------------*/
   if (HAL_IS_BIT_SET(trigger, SPI_FLAG_TSERF))
   {
-    hspi->Reload.Requested = 0UL;
     __HAL_SPI_CLEAR_TSERFFLAG(hspi);
   }
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
   if (handled != 0UL)
   {
@@ -2900,59 +2960,53 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
     /* Disable EOT interrupt */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT);
 
-    /* DMA Normal Mode */
-    if (HAL_IS_BIT_CLR(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN) ||                    // IT based transfer is done
-      ((State != HAL_SPI_STATE_BUSY_RX) && (hspi->hdmatx->Init.Mode == DMA_NORMAL)) ||  // DMA is used in normal mode
-      ((State != HAL_SPI_STATE_BUSY_TX) && (hspi->hdmarx->Init.Mode == DMA_NORMAL)))    // DMA is used in normal mode
+    /* For the IT based receive extra polling maybe required for last packet */
+    if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
     {
-      /* For the IT based receive extra polling maybe required for last packet */
-      if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
+      /* Pooling remaining data */
+      while (hspi->RxXferCount != 0UL)
       {
-        /* Pooling remaining data */
-        while (hspi->RxXferCount != 0UL)
+        /* Receive data in 32 Bit mode */
+        if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
         {
-          /* Receive data in 32 Bit mode */
-          if (hspi->Init.DataSize > SPI_DATASIZE_16BIT)
-          {
-            *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
-            hspi->pRxBuffPtr += sizeof(uint32_t);
-          }
-          /* Receive data in 16 Bit mode */
-          else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
-          {
-#if defined (__GNUC__)
-            *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
-#else
-            *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
-#endif /* __GNUC__ */
-            hspi->pRxBuffPtr += sizeof(uint16_t);
-          }
-          /* Receive data in 8 Bit mode */
-          else
-          {
-            *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
-            hspi->pRxBuffPtr += sizeof(uint8_t);
-          }
-
-          hspi->RxXferCount--;
+          *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint32_t);
         }
-      }
-
-      /* Call SPI Standard close procedure */
-      SPI_CloseTransfer(hspi);
-
-      hspi->State = HAL_SPI_STATE_READY;
-      if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-      {
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
-        hspi->ErrorCallback(hspi);
+        /* Receive data in 16 Bit mode */
+        else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+        {
+#if defined (__GNUC__)
+          *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits;
 #else
-        HAL_SPI_ErrorCallback(hspi);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-        return;
+          *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR);
+#endif /* __GNUC__ */
+          hspi->pRxBuffPtr += sizeof(uint16_t);
+        }
+        /* Receive data in 8 Bit mode */
+        else
+        {
+          *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR);
+          hspi->pRxBuffPtr += sizeof(uint8_t);
+        }
+
+        hspi->RxXferCount--;
       }
     }
 
+    /* Call SPI Standard close procedure */
+    SPI_CloseTransfer(hspi);
+
+    hspi->State = HAL_SPI_STATE_READY;
+    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
+    {
+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
+      hspi->ErrorCallback(hspi);
+#else
+      HAL_SPI_ErrorCallback(hspi);
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
+      return;
+    }
+
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
     /* Call appropriate user callback */
     if (State == HAL_SPI_STATE_BUSY_TX_RX)
@@ -2982,7 +3036,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
       HAL_SPI_TxCpltCallback(hspi);
     }
 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-	else
+    else
     {
       /* End of the appropriate call */
     }
@@ -2990,14 +3044,6 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
     return;
   }
 
-  if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT))
-  {
-    /* Abort on going, clear SUSP flag to avoid infinite looping */
-    __HAL_SPI_CLEAR_SUSPFLAG(hspi);
-
-    return;
-  }
-
   /* SPI in Error Treatment --------------------------------------------------*/
   if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL)
   {
@@ -3035,7 +3081,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
       __HAL_SPI_DISABLE(hspi);
 
       /* Disable all interrupts */
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR);
+      __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF |
+                                  SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR));
 
       /* Disable the SPI DMA requests if enabled */
       if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN))
@@ -3089,7 +3136,7 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3105,7 +3152,7 @@ __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3121,7 +3168,7 @@ __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3137,7 +3184,7 @@ __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3153,7 +3200,7 @@ __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3169,7 +3216,7 @@ __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3185,7 +3232,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval None
   */
-__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3203,7 +3250,7 @@ __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
   * @param  hspi SPI handle.
   * @retval None
   */
-__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
+__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
 {
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hspi);
@@ -3213,6 +3260,21 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
    */
 }
 
+/**
+  * @brief  SPI Suspend callback.
+  * @param  hspi SPI handle.
+  * @retval None
+  */
+__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hspi);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SPI_SuspendCallback can be implemented in the user file.
+   */
+}
+
 /**
   * @}
   */
@@ -3238,7 +3300,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval SPI state
   */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
 {
   /* Return SPI handle state */
   return hspi->State;
@@ -3250,7 +3312,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
   *               the configuration information for SPI module.
   * @retval SPI error code in bitmap format
   */
-uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
+uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
 {
   /* Return SPI ErrorCode */
   return hspi->ErrorCode;
@@ -3359,9 +3421,10 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
   *               the configuration information for the specified DMA module.
   * @retval None
   */
-static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
 {
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+                            ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
 
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
   hspi->TxHalfCpltCallback(hspi);
@@ -3376,9 +3439,10 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
   *               the configuration information for the specified DMA module.
   * @retval None
   */
-static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
 {
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+                            ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
 
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
   hspi->RxHalfCpltCallback(hspi);
@@ -3393,9 +3457,10 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
   *               the configuration information for the specified DMA module.
   * @retval None
   */
-static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
+static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */
 {
-  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)
+                            ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */
 
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
   hspi->TxRxHalfCpltCallback(hspi);
@@ -3549,6 +3614,7 @@ static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
       hspi->RxXferSize  = hspi->Reload.RxXferSize;
       hspi->RxXferCount = hspi->Reload.RxXferSize;
       hspi->pRxBuffPtr  = hspi->Reload.pRxBuffPtr;
+      hspi->Reload.Requested = 0UL;
     }
     else
     {
@@ -3558,7 +3624,7 @@ static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi)
 #else
     /* Disable RXP interrupts */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
   }
 }
 
@@ -3592,6 +3658,7 @@ static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
       hspi->RxXferSize  = hspi->Reload.RxXferSize;
       hspi->RxXferCount = hspi->Reload.RxXferSize;
       hspi->pRxBuffPtr  = hspi->Reload.pRxBuffPtr;
+      hspi->Reload.Requested = 0UL;
     }
     else
     {
@@ -3601,7 +3668,7 @@ static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi)
 #else
     /* Disable RXP interrupts */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
   }
 }
 
@@ -3629,6 +3696,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
       hspi->RxXferSize  = hspi->Reload.RxXferSize;
       hspi->RxXferCount = hspi->Reload.RxXferSize;
       hspi->pRxBuffPtr  = hspi->Reload.pRxBuffPtr;
+      hspi->Reload.Requested = 0UL;
     }
     else
     {
@@ -3638,7 +3706,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
 #else
     /* Disable RXP interrupts */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
   }
 }
 
@@ -3652,7 +3720,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi)
 static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
 {
   /* Transmit data in 8 Bit mode */
-  *(__IO uint8_t *)&hspi->Instance->TXDR = *((uint8_t *)hspi->pTxBuffPtr);
+  *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr);
   hspi->pTxBuffPtr += sizeof(uint8_t);
   hspi->TxXferCount--;
 
@@ -3666,6 +3734,12 @@ static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
       hspi->TxXferSize  = hspi->Reload.TxXferSize;
       hspi->TxXferCount = hspi->Reload.TxXferSize;
       hspi->pTxBuffPtr  = hspi->Reload.pTxBuffPtr;
+
+      /* In full duplex mode the reload request is reset in RX side */
+      if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+      {
+        hspi->Reload.Requested = 0UL;
+      }
     }
     else
     {
@@ -3675,7 +3749,7 @@ static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi)
 #else
     /* Disable TXP interrupts */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
   }
 }
 
@@ -3691,9 +3765,9 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
 #if defined (__GNUC__)
   __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR));
 
-  *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr);
+  *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr);
 #else
-  *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr);
+  *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr);
 #endif /* __GNUC__ */
   hspi->pTxBuffPtr += sizeof(uint16_t);
   hspi->TxXferCount--;
@@ -3708,6 +3782,12 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
       hspi->TxXferSize  = hspi->Reload.TxXferSize;
       hspi->TxXferCount = hspi->Reload.TxXferSize;
       hspi->pTxBuffPtr  = hspi->Reload.pTxBuffPtr;
+
+      /* In full duplex mode the reload request is reset in RX side */
+      if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+      {
+        hspi->Reload.Requested = 0UL;
+      }
     }
     else
     {
@@ -3717,7 +3797,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
 #else
     /* Disable TXP interrupts */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
   }
 }
 
@@ -3730,7 +3810,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi)
 static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
 {
   /* Transmit data in 32 Bit mode */
-  *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr);
+  *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr);
   hspi->pTxBuffPtr += sizeof(uint32_t);
   hspi->TxXferCount--;
 
@@ -3744,6 +3824,12 @@ static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
       hspi->TxXferSize  = hspi->Reload.TxXferSize;
       hspi->TxXferCount = hspi->Reload.TxXferSize;
       hspi->pTxBuffPtr  = hspi->Reload.pTxBuffPtr;
+
+      /* In full duplex mode the reload request is reset in RX side */
+      if (hspi->State == HAL_SPI_STATE_BUSY_TX)
+      {
+        hspi->Reload.Requested = 0UL;
+      }
     }
     else
     {
@@ -3753,7 +3839,7 @@ static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi)
 #else
     /* Disable TXP interrupts */
     __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
   }
 }
 
@@ -3769,7 +3855,8 @@ static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
   __HAL_SPI_DISABLE(hspi);
 
   /* Disable ITs */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+                              SPI_IT_FRE | SPI_IT_MODF));
 
   /* Clear the Status flags in the SR register */
   __HAL_SPI_CLEAR_EOTFLAG(hspi);
@@ -3799,7 +3886,7 @@ static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi)
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
   *               the configuration information for SPI module.
   * @retval HAL_ERROR: if any error detected
-*         HAL_OK: if nothing detected
+  *         HAL_OK: if nothing detected
   */
 static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
 {
@@ -3812,7 +3899,8 @@ static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
   __HAL_SPI_DISABLE(hspi);
 
   /* Disable ITs */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF));
+  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \
+                              SPI_IT_FRE | SPI_IT_MODF));
 
   /* Disable Tx DMA Request */
   CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
@@ -3877,8 +3965,8 @@ static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi)
   * @param Tickstart: Tick start value
   * @retval HAL status
   */
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
-                                                    uint32_t Tickstart, uint32_t Timeout)
+static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status,
+                                                    uint32_t Timeout, uint32_t Tickstart)
 {
   /* Wait until flag is set */
   while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status)
@@ -3898,7 +3986,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
   *               the configuration information for SPI module.
   * @retval Packet size occupied in the fifo
   */
-static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
+static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi)
 {
   uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
   uint32_t data_size       = (hspi->Init.DataSize      >> SPI_CFG1_DSIZE_Pos) + 1UL;
@@ -3909,7 +3997,6 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
   return data_size * fifo_threashold;
 }
 
-
 /**
   * @}
   */
@@ -3923,5 +4010,3 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h
index fb4e2c5e55..71a7b1da69 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -63,7 +62,8 @@ typedef struct
 
   uint32_t NSS;                               /*!< Specifies whether the NSS signal is managed by
                                                      hardware (NSS pin) or by software using the SSI bit.
-                                                     This parameter can be a value of @ref SPI_Slave_Select_Management */
+                                                     This parameter can be a value of
+                                                     @ref SPI_Slave_Select_Management */
 
   uint32_t BaudRatePrescaler;                 /*!< Specifies the Baud Rate prescaler value which will be
                                                      used to configure the transmit and receive SCK clock.
@@ -81,40 +81,45 @@ typedef struct
                                                      This parameter can be a value of @ref SPI_CRC_Calculation */
 
   uint32_t CRCPolynomial;                     /*!< Specifies the polynomial used for the CRC calculation.
-                                                     This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
+                                                     This parameter must be an odd number between
+                                                     Min_Data = 0 and Max_Data = 65535 */
 
   uint32_t CRCLength;                         /*!< Specifies the CRC Length used for the CRC calculation.
                                                      This parameter can be a value of @ref SPI_CRC_length */
 
   uint32_t NSSPMode;                          /*!< Specifies whether the NSSP signal is enabled or not .
                                                      This parameter can be a value of @ref SPI_NSSP_Mode
-                                                     This mode is activated by the SSOM bit in the SPIx_CR2 register and
-                                                     it takes effect only if the SPI interface is configured as Motorola SPI
-                                                     master (FRF=0). */
+                                                     This mode is activated by the SSOM bit in the SPIx_CR2 register
+                                                     and it takes effect only if the SPI interface is configured
+                                                     as Motorola SPI master (FRF=0). */
 
-  uint32_t NSSPolarity;                       /*!< Specifies which level of SS input/output external signal (present on SS pin) is
-                                                     considered as active one.
+  uint32_t NSSPolarity;                       /*!< Specifies which level of SS input/output external signal
+                                                     (present on SS pin) is considered as active one.
                                                      This parameter can be a value of @ref SPI_NSS_Polarity */
 
   uint32_t FifoThreshold;                     /*!< Specifies the FIFO threshold level.
                                                      This parameter can be a value of @ref SPI_Fifo_Threshold */
 
-  uint32_t TxCRCInitializationPattern;        /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
-                                                     This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
+  uint32_t TxCRCInitializationPattern;        /*!< Specifies the transmitter CRC initialization Pattern used for
+                                                     the CRC calculation. This parameter can be a value of
+                                                     @ref SPI_CRC_Calculation_Initialization_Pattern */
 
-  uint32_t RxCRCInitializationPattern;        /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
-                                                     This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
+  uint32_t RxCRCInitializationPattern;        /*!< Specifies the receiver CRC initialization Pattern used for
+                                                     the CRC calculation. This parameter can be a value of
+                                                     @ref SPI_CRC_Calculation_Initialization_Pattern */
 
-  uint32_t MasterSSIdleness;                  /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
-                                                     additionally between active edge of SS and first data transaction start in master mode.
+  uint32_t MasterSSIdleness;                  /*!< Specifies an extra delay, expressed in number of SPI clock cycle
+                                                     periods, inserted additionally between active edge of SS
+                                                     and first data transaction start in master mode.
                                                      This parameter can be a value of @ref SPI_Master_SS_Idleness */
 
-  uint32_t MasterInterDataIdleness;           /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
-                                                     two consecutive data frames in master mode
-                                                     This parameter can be a value of @ref SPI_Master_InterData_Idleness */
+  uint32_t MasterInterDataIdleness;           /*!< Specifies minimum time delay (expressed in SPI clock cycles periods)
+                                                     inserted between two consecutive data frames in master mode.
+                                                     This parameter can be a value of
+                                                     @ref SPI_Master_InterData_Idleness */
 
-  uint32_t MasterReceiverAutoSusp;            /*!< Control continuous SPI transfer in master receiver mode and automatic management
-                                                     in order to avoid overrun condition.
+  uint32_t MasterReceiverAutoSusp;            /*!< Control continuous SPI transfer in master receiver mode
+                                                     and automatic management in order to avoid overrun condition.
                                                      This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
 
   uint32_t MasterKeepIOState;                 /*!< Control of Alternate function GPIOs state
@@ -122,7 +127,6 @@ typedef struct
 
   uint32_t IOSwap;                            /*!< Invert MISO/MOSI alternate functions
                                                      This parameter can be a value of @ref SPI_IO_Swap */
-
 } SPI_InitTypeDef;
 
 /**
@@ -146,7 +150,7 @@ typedef enum
   */
 typedef struct
 {
-  uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
+  const uint8_t              *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
 
   uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size to reload           */
 
@@ -157,7 +161,7 @@ typedef struct
   uint32_t                   Requested;                    /*!< SPI reload request                       */
 
 } SPI_ReloadTypeDef;
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
 /**
   * @brief  SPI handle Structure definition
@@ -168,7 +172,7 @@ typedef struct __SPI_HandleTypeDef
 
   SPI_InitTypeDef            Init;                         /*!< SPI communication parameters             */
 
-  uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
+  const uint8_t              *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */
 
   uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size                     */
 
@@ -195,12 +199,12 @@ typedef struct __SPI_HandleTypeDef
   __IO HAL_SPI_StateTypeDef  State;                        /*!< SPI communication state                  */
 
   __IO uint32_t              ErrorCode;                    /*!< SPI Error code                           */
-  
+
 #if defined(USE_SPI_RELOAD_TRANSFER)
 
   SPI_ReloadTypeDef          Reload;                       /*!< SPI reload parameters                    */
-  
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
   void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Tx Completed callback          */
@@ -211,6 +215,7 @@ typedef struct __SPI_HandleTypeDef
   void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback   */
   void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);        /*!< SPI Error callback                 */
   void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Abort callback                 */
+  void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi);      /*!< SPI Suspend callback               */
   void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);      /*!< SPI Msp Init callback              */
   void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Msp DeInit callback            */
 
@@ -231,8 +236,9 @@ typedef enum
   HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05UL,    /*!< SPI TxRx Half Completed callback ID  */
   HAL_SPI_ERROR_CB_ID                   = 0x06UL,    /*!< SPI Error callback ID                */
   HAL_SPI_ABORT_CB_ID                   = 0x07UL,    /*!< SPI Abort callback ID                */
-  HAL_SPI_MSPINIT_CB_ID                 = 0x08UL,    /*!< SPI Msp Init callback ID             */
-  HAL_SPI_MSPDEINIT_CB_ID               = 0x09UL     /*!< SPI Msp DeInit callback ID           */
+  HAL_SPI_SUSPEND_CB_ID                 = 0x08UL,    /*!< SPI Suspend callback ID              */
+  HAL_SPI_MSPINIT_CB_ID                 = 0x09UL,    /*!< SPI Msp Init callback ID             */
+  HAL_SPI_MSPDEINIT_CB_ID               = 0x0AUL     /*!< SPI Msp DeInit callback ID           */
 
 } HAL_SPI_CallbackIDTypeDef;
 
@@ -270,14 +276,15 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
 #define HAL_SPI_ERROR_OVR                             (0x00000004UL)   /*!< OVR error                              */
 #define HAL_SPI_ERROR_FRE                             (0x00000008UL)   /*!< FRE error                              */
 #define HAL_SPI_ERROR_DMA                             (0x00000010UL)   /*!< DMA transfer error                     */
-#define HAL_SPI_ERROR_FLAG                            (0x00000020UL)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_FLAG                            (0x00000020UL)   /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag  */
 #define HAL_SPI_ERROR_ABORT                           (0x00000040UL)   /*!< Error during SPI Abort procedure       */
 #define HAL_SPI_ERROR_UDR                             (0x00000080UL)   /*!< Underrun error                         */
 #define HAL_SPI_ERROR_TIMEOUT                         (0x00000100UL)   /*!< Timeout error                          */
-#define HAL_SPI_ERROR_UNKNOW                          (0x00000200UL)   /*!< Unknown error                           */
+#define HAL_SPI_ERROR_UNKNOW                          (0x00000200UL)   /*!< Unknown error                          */
 #define HAL_SPI_ERROR_NOT_SUPPORTED                   (0x00000400UL)   /*!< Requested operation not supported      */
+#define HAL_SPI_ERROR_RELOAD                          (0x00000800UL)   /*!< Reload error                           */
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
-#define HAL_SPI_ERROR_INVALID_CALLBACK                (0x00000800UL)   /*!< Invalid Callback error                 */
+#define HAL_SPI_ERROR_INVALID_CALLBACK                (0x00001000UL)   /*!< Invalid Callback error                 */
 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
   * @}
@@ -569,16 +576,6 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   * @}
   */
 
-/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
-  * @{
-  */
-#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME          (0x00000000UL)
-#define SPI_UNDERRUN_DETECT_END_DATA_FRAME            SPI_CFG1_UDRDET_0
-#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS          SPI_CFG1_UDRDET_1
-/**
-  * @}
-  */
-
 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
   * @{
   */
@@ -589,6 +586,16 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   * @}
   */
 
+/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
+  * @{
+  */
+#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME          (0x00000000UL)
+#define SPI_UNDERRUN_DETECT_END_DATA_FRAME            SPI_CFG1_UDRDET_0
+#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS          SPI_CFG1_UDRDET_1
+/**
+  * @}
+  */
+
 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
   * @{
   */
@@ -633,10 +640,10 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
   * @{
   */
-#define SPI_RX_FIFO_0PACKET                           (0x00000000UL)                      /* 0 or multiple of 4 packets available in the RxFIFO */
-#define SPI_RX_FIFO_1PACKET                           (SPI_SR_RXPLVL_0)
-#define SPI_RX_FIFO_2PACKET                           (SPI_SR_RXPLVL_1)
-#define SPI_RX_FIFO_3PACKET                           (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_0PACKET             (0x00000000UL)         /* 0 or multiple of 4 packets available in the RxFIFO */
+#define SPI_RX_FIFO_1PACKET             (SPI_SR_RXPLVL_0)
+#define SPI_RX_FIFO_2PACKET             (SPI_SR_RXPLVL_1)
+#define SPI_RX_FIFO_3PACKET             (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
 /**
   * @}
   */
@@ -663,7 +670,7 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
                                                      } while(0)
 #else
 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif
+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 
 /** @brief  Enable the specified SPI interrupts.
   * @param  __HANDLE__: specifies the SPI Handle.
@@ -726,7 +733,8 @@ typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
   *            @arg SPI_IT_ERR    : Error interrupt
   * @retval The new state of __IT__ (TRUE or FALSE).
   */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
+                                                              (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Check whether the specified SPI flag is set or not.
   * @param  __HANDLE__: specifies the SPI Handle.
@@ -842,7 +850,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
+                                           pSPI_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 /**
@@ -853,23 +862,26 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
   * @{
   */
 /* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                          uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                             uint16_t Size);
 
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
+                                              uint16_t Size);
 
 #if defined(USE_SPI_RELOAD_TRANSFER)
-HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-#endif /* USE_HSPI_RELOAD_TRANSFER */
+HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData,
+                                                    uint8_t *pRxData, uint16_t Size);
+#endif /* USE_SPI_RELOAD_TRANSFER */
 
 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@@ -888,6 +900,7 @@ void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
@@ -897,8 +910,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
   */
 
 /* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
+uint32_t             HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
@@ -912,19 +925,40 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
   * @{
   */
 
-/** @brief  Set the SPI transmit-only mode.
+/** @brief  Set the SPI transmit-only mode in 1Line configuration.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
 
-/** @brief  Set the SPI receive-only mode.
+/** @brief  Set the SPI receive-only mode in 1Line configuration.
   * @param  __HANDLE__: specifies the SPI Handle.
   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
   * @retval None
   */
-#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR)
+
+/** @brief  Set the SPI transmit-only mode in 2Lines configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0)
+
+/** @brief  Set the SPI receive-only mode in 2Lines configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1)
+
+/** @brief  Set the SPI Transmit-Receive mode in 2Lines configuration.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL)
 
 #define IS_SPI_MODE(MODE)                          (((MODE) == SPI_MODE_SLAVE) || \
                                                     ((MODE) == SPI_MODE_MASTER))
@@ -936,15 +970,13 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 
 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
 
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (                         \
-                                                    ((MODE) == SPI_DIRECTION_2LINES)|| \
-                                                    ((MODE) == SPI_DIRECTION_1LINE) || \
-                                                    ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+                                                              ((MODE) == SPI_DIRECTION_1LINE) || \
+                                                              ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
 
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (                         \
-                                                    ((MODE) == SPI_DIRECTION_2LINES)|| \
-                                                    ((MODE) == SPI_DIRECTION_1LINE) || \
-                                                    ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+                                                              ((MODE) == SPI_DIRECTION_1LINE) || \
+                                                              ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
 
 #define IS_SPI_DATASIZE(DATASIZE)                  (((DATASIZE) == SPI_DATASIZE_32BIT) || \
                                                     ((DATASIZE) == SPI_DATASIZE_31BIT) || \
@@ -1007,13 +1039,13 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 #define IS_SPI_NSSP(NSSP)                          (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
                                                     ((NSSP) == SPI_NSS_PULSE_DISABLE))
 
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)       (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
-                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
-                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
-                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
-                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
-                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
-                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)       (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)      || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)      || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)      || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)     || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)     || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)     || \
+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128)    || \
                                                     ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
 
 #define IS_SPI_FIRST_BIT(BIT)                      (((BIT) == SPI_FIRSTBIT_MSB) || \
@@ -1059,7 +1091,11 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
                                                     ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \
                                                     ((LENGTH) == SPI_CRC_LENGTH_4BIT))
 
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)           ((POLYNOMIAL) >= 0x1UL)
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)          ((POLYNOMIAL) > 0x0UL)
+
+#define IS_SPI_CRC_POLYNOMIAL_SIZE(POLYNOM, LENGTH) (((POLYNOM) >> (((LENGTH) >> SPI_CFG1_CRCSIZE_Pos) + 1UL)) == 0UL)
+
 
 #define IS_SPI_UNDERRUN_DETECTION(MODE)            (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
                                                     ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \
@@ -1068,6 +1104,9 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE)            (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
                                                     ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)    || \
                                                     ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
+
+#define IS_SPI_MASTER_RX_AUTOSUSP(MODE)            (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \
+                                                    ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE))
 /**
   * @}
   */
@@ -1089,4 +1128,3 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.c
index ade9c64733..7cf5fb343f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.c
@@ -11,13 +11,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -73,7 +72,7 @@
   *               the configuration information for the specified SPI module.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
 {
   uint8_t  count  = 0;
   uint32_t itflag = hspi->Instance->SR;
@@ -160,7 +159,8 @@ HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi)
   *                             This parameter can be a value of @ref SPI_Underrun_Behaviour.
   * @retval None
   */
-HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour)
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+                                              uint32_t UnderrunBehaviour)
 {
   HAL_StatusTypeDef errorcode = HAL_OK;
 
@@ -225,5 +225,3 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.h
index c9c579e609..3e32a0e633 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -37,8 +36,32 @@ extern "C" {
   */
 
 /* Exported types ------------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Types SPIEx Exported Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
 /* Exported constants --------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
 /* Exported macros -----------------------------------------------------------*/
+/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup SPIEx_Exported_Functions
   * @{
@@ -49,9 +72,13 @@ extern "C" {
 /** @addtogroup SPIEx_Exported_Functions_Group1
   * @{
   */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
 HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection,
+                                              uint32_t UnderrunBehaviour);
+/**
+  * @}
+  */
 /**
   * @}
   */
@@ -64,14 +91,9 @@ HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t
   * @}
   */
 
-/**
-  * @}
-  */
 
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* STM32H7xx_HAL_SPI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c
index daf8e3f969..94d93ca06d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c
@@ -6,6 +6,17 @@
   *          This file provides a generic firmware to drive SRAM memories
   *          mounted as external device.
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                           ##### How to use this driver #####
@@ -64,25 +75,25 @@
       The compilation define  USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1
       allows the user to configure dynamically the driver callbacks.
 
-      Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback,
+      Use Functions HAL_SRAM_RegisterCallback() to register a user callback,
       it allows to register following callbacks:
         (+) MspInitCallback    : SRAM MspInit.
         (+) MspDeInitCallback  : SRAM MspDeInit.
       This function takes as parameters the HAL peripheral handle, the Callback ID
       and a pointer to the user callback function.
 
-      Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default
-      weak (surcharged) function. It allows to reset following callbacks:
+      Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
         (+) MspInitCallback    : SRAM MspInit.
         (+) MspDeInitCallback  : SRAM MspDeInit.
       This function) takes as parameters the HAL peripheral handle and the Callback ID.
 
-      By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
-      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
       Exception done for MspInit and MspDeInit callbacks that are respectively
-      reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init
-      and @ref  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
-      If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit
+      reset to the legacy weak (overridden) functions in the HAL_SRAM_Init
+      and  HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
 
       Callbacks can be registered/unregistered in READY state only.
@@ -90,26 +101,15 @@
       in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
       during the Init/DeInit.
       In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit
-      or @ref HAL_SRAM_Init function.
+      using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit
+      or HAL_SRAM_Init function.
 
       When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or
       not defined, the callback registering feature is not available
-      and weak (surcharged) callbacks are used.
+      and weak (overridden) callbacks are used.
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -132,9 +132,15 @@
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SRAM_Private_Functions SRAM Private Functions
+  * @{
+  */
 static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
 static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
 static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma);
+/**
+  * @}
+  */
 
 /* Exported functions --------------------------------------------------------*/
 
@@ -733,7 +739,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre
 #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User SRAM Callback
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hsram : SRAM handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -753,9 +759,6 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(hsram);
-
   state = hsram->State;
   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
   {
@@ -779,14 +782,12 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
   return status;
 }
 
 /**
   * @brief  Unregister a User SRAM Callback
-  *         SRAM Callback is redirected to the weak (surcharged) predefined callback
+  *         SRAM Callback is redirected to the weak predefined callback
   * @param hsram : SRAM handle
   * @param CallbackId : ID of the callback to be unregistered
   *        This parameter can be one of the following values:
@@ -801,9 +802,6 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA
   HAL_StatusTypeDef status = HAL_OK;
   HAL_SRAM_StateTypeDef state;
 
-  /* Process locked */
-  __HAL_LOCK(hsram);
-
   state = hsram->State;
   if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
   {
@@ -849,14 +847,12 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRA
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
   return status;
 }
 
 /**
   * @brief  Register a User SRAM Callback for DMA transfers
-  *         To be used instead of the weak (surcharged) predefined callback
+  *         To be used to override the weak predefined callback
   * @param hsram : SRAM handle
   * @param CallbackId : ID of the callback to be registered
   *        This parameter can be one of the following values:
@@ -1020,7 +1016,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
   *                the configuration information for SRAM module.
   * @retval HAL state
   */
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram)
 {
   return hsram->State;
 }
@@ -1033,6 +1029,10 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
   * @}
   */
 
+/** @addtogroup SRAM_Private_Functions SRAM Private Functions
+  * @{
+  */
+
 /**
   * @brief  MDMA SRAM process complete callback.
   * @param  hmdma : MDMA handle
@@ -1099,6 +1099,10 @@ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
 #endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
 }
 
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -1109,5 +1113,3 @@ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma)
   * @}
   */
 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h
index 6384026daf..b50dc29a3e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -205,7 +204,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
   */
 
 /* SRAM  State functions ******************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
 
 /**
   * @}
@@ -229,5 +228,3 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
 #endif
 
 #endif /* STM32H7xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c
index 839af3ba12..0cf0c1c42f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c
@@ -9,6 +9,17 @@
   *           + Data transfers functions
   *           + DMA transfers management
   *           + Interrupts and flags management
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -146,7 +157,7 @@
     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
     during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_SWPMI_RegisterCallback before calling @ref HAL_SWPMI_DeInit
+    using HAL_SWPMI_RegisterCallback before calling HAL_SWPMI_DeInit
     or HAL_SWPMI_Init function.
     [..]
     When the compilation define USE_HAL_SWPMI_REGISTER_CALLBACKS is set to 0 or
@@ -154,18 +165,6 @@
     and weak (surcharged) callbacks are used.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -243,7 +242,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
   uint32_t tickstart = HAL_GetTick();
 
   /* Check the SWPMI handle allocation */
-  if(hswpmi == NULL)
+  if (hswpmi == NULL)
   {
     status = HAL_ERROR;
   }
@@ -255,7 +254,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
     assert_param(IS_SWPMI_TX_BUFFERING_MODE(hswpmi->Init.TxBufferingMode));
     assert_param(IS_SWPMI_RX_BUFFERING_MODE(hswpmi->Init.RxBufferingMode));
 
-    if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+    if (hswpmi->State == HAL_SWPMI_STATE_RESET)
     {
       /* Allocate lock resource and initialize it */
       hswpmi->Lock = HAL_UNLOCKED;
@@ -269,7 +268,7 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
       hswpmi->ErrorCallback      = HAL_SWPMI_ErrorCallback;
 
       /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-      if(hswpmi->MspInitCallback == NULL)
+      if (hswpmi->MspInitCallback == NULL)
       {
         hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
       }
@@ -303,12 +302,12 @@ HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi)
     /* Enable the SWPMI transceiver */
     SET_BIT(hswpmi->Instance->CR, SWPMI_CR_SWPEN);
     /* Wait on RDYF flag to activate SWPMI */
-    if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK)
+    if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_RDYF, tickstart, SWPMI_TRANSCEIVER_RDY_TIMEOUT_VALUE) != HAL_OK)
     {
       status = HAL_TIMEOUT;
     }
 
-    if(status == HAL_OK)
+    if (status == HAL_OK)
     {
       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
       hswpmi->State = HAL_SWPMI_STATE_READY;
@@ -336,7 +335,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Check the SWPMI handle allocation */
-  if(hswpmi == NULL)
+  if (hswpmi == NULL)
   {
     status = HAL_ERROR;
   }
@@ -359,7 +358,7 @@ HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi)
 
     /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
-    if(hswpmi->MspDeInitCallback == NULL)
+    if (hswpmi->MspDeInitCallback == NULL)
     {
       hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
     }
@@ -426,12 +425,12 @@ __weak void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi)
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
-                                           HAL_SWPMI_CallbackIDTypeDef CallbackID,
-                                           pSWPMI_CallbackTypeDef      pCallback)
+                                             HAL_SWPMI_CallbackIDTypeDef CallbackID,
+                                             pSWPMI_CallbackTypeDef      pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(pCallback == NULL)
+  if (pCallback == NULL)
   {
     /* update the error code */
     hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
@@ -440,55 +439,55 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
   }
   else
   {
-    if(hswpmi->State == HAL_SWPMI_STATE_READY)
+    if (hswpmi->State == HAL_SWPMI_STATE_READY)
     {
       switch (CallbackID)
       {
-      case HAL_SWPMI_RX_COMPLETE_CB_ID :
-        hswpmi->RxCpltCallback = pCallback;
-        break;
-      case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
-        hswpmi->RxHalfCpltCallback = pCallback;
-        break;
-      case HAL_SWPMI_TX_COMPLETE_CB_ID :
-        hswpmi->TxCpltCallback = pCallback;
-        break;
-      case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
-        hswpmi->TxHalfCpltCallback = pCallback;
-        break;
-      case HAL_SWPMI_ERROR_CB_ID :
-        hswpmi->ErrorCallback = pCallback;
-        break;
-      case HAL_SWPMI_MSPINIT_CB_ID :
-        hswpmi->MspInitCallback = pCallback;
-        break;
-      case HAL_SWPMI_MSPDEINIT_CB_ID :
-        hswpmi->MspDeInitCallback = pCallback;
-        break;
-      default :
-        /* update the error code */
-        hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
-        /* update return status */
-        status = HAL_ERROR;
-        break;
+        case HAL_SWPMI_RX_COMPLETE_CB_ID :
+          hswpmi->RxCpltCallback = pCallback;
+          break;
+        case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
+          hswpmi->RxHalfCpltCallback = pCallback;
+          break;
+        case HAL_SWPMI_TX_COMPLETE_CB_ID :
+          hswpmi->TxCpltCallback = pCallback;
+          break;
+        case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
+          hswpmi->TxHalfCpltCallback = pCallback;
+          break;
+        case HAL_SWPMI_ERROR_CB_ID :
+          hswpmi->ErrorCallback = pCallback;
+          break;
+        case HAL_SWPMI_MSPINIT_CB_ID :
+          hswpmi->MspInitCallback = pCallback;
+          break;
+        case HAL_SWPMI_MSPDEINIT_CB_ID :
+          hswpmi->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
       }
     }
-    else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+    else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
     {
       switch (CallbackID)
       {
-      case HAL_SWPMI_MSPINIT_CB_ID :
-        hswpmi->MspInitCallback = pCallback;
-        break;
-      case HAL_SWPMI_MSPDEINIT_CB_ID :
-        hswpmi->MspDeInitCallback = pCallback;
-        break;
-      default :
-        /* update the error code */
-        hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
-        /* update return status */
-        status = HAL_ERROR;
-        break;
+        case HAL_SWPMI_MSPINIT_CB_ID :
+          hswpmi->MspInitCallback = pCallback;
+          break;
+        case HAL_SWPMI_MSPDEINIT_CB_ID :
+          hswpmi->MspDeInitCallback = pCallback;
+          break;
+        default :
+          /* update the error code */
+          hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+          /* update return status */
+          status = HAL_ERROR;
+          break;
       }
     }
     else
@@ -518,59 +517,59 @@ HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef        *hswpmi,
-                                             HAL_SWPMI_CallbackIDTypeDef CallbackID)
+                                               HAL_SWPMI_CallbackIDTypeDef CallbackID)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  if(hswpmi->State == HAL_SWPMI_STATE_READY)
+  if (hswpmi->State == HAL_SWPMI_STATE_READY)
   {
     switch (CallbackID)
     {
-    case HAL_SWPMI_RX_COMPLETE_CB_ID :
-      hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
-      break;
-    case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
-      hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
-      break;
-    case HAL_SWPMI_TX_COMPLETE_CB_ID :
-      hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
-      break;
-    case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
-      hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
-      break;
-    case HAL_SWPMI_ERROR_CB_ID :
-      hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
-      break;
-    case HAL_SWPMI_MSPINIT_CB_ID :
-      hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
-      break;
-    case HAL_SWPMI_MSPDEINIT_CB_ID :
-      hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
-      break;
-    default :
-      /* update the error code */
-      hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status = HAL_ERROR;
-      break;
+      case HAL_SWPMI_RX_COMPLETE_CB_ID :
+        hswpmi->RxCpltCallback = HAL_SWPMI_RxCpltCallback;
+        break;
+      case HAL_SWPMI_RX_HALFCOMPLETE_CB_ID :
+        hswpmi->RxHalfCpltCallback = HAL_SWPMI_RxHalfCpltCallback;
+        break;
+      case HAL_SWPMI_TX_COMPLETE_CB_ID :
+        hswpmi->TxCpltCallback = HAL_SWPMI_TxCpltCallback;
+        break;
+      case HAL_SWPMI_TX_HALFCOMPLETE_CB_ID :
+        hswpmi->TxHalfCpltCallback = HAL_SWPMI_TxHalfCpltCallback;
+        break;
+      case HAL_SWPMI_ERROR_CB_ID :
+        hswpmi->ErrorCallback = HAL_SWPMI_ErrorCallback;
+        break;
+      case HAL_SWPMI_MSPINIT_CB_ID :
+        hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
+        break;
+      case HAL_SWPMI_MSPDEINIT_CB_ID :
+        hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
     }
   }
-  else if(hswpmi->State == HAL_SWPMI_STATE_RESET)
+  else if (hswpmi->State == HAL_SWPMI_STATE_RESET)
   {
     switch (CallbackID)
     {
-    case HAL_SWPMI_MSPINIT_CB_ID :
-      hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
-      break;
-    case HAL_SWPMI_MSPDEINIT_CB_ID :
-      hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
-      break;
-    default :
-      /* update the error code */
-      hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
-      /* update return status */
-      status = HAL_ERROR;
-      break;
+      case HAL_SWPMI_MSPINIT_CB_ID :
+        hswpmi->MspInitCallback = HAL_SWPMI_MspInit;
+        break;
+      case HAL_SWPMI_MSPDEINIT_CB_ID :
+        hswpmi->MspDeInitCallback = HAL_SWPMI_MspDeInit;
+        break;
+      default :
+        /* update the error code */
+        hswpmi->ErrorCode |= HAL_SWPMI_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status = HAL_ERROR;
+        break;
     }
   }
   else
@@ -652,7 +651,7 @@ HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef        *hswpm
   * @param  Timeout Timeout duration
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout)
 {
   uint32_t tickstart = HAL_GetTick();
   HAL_StatusTypeDef status = HAL_OK;
@@ -660,7 +659,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat
   uint32_t *ptmp_data;
   uint32_t tmp_size;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     status = HAL_ERROR;
   }
@@ -670,10 +669,10 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat
     __HAL_LOCK(hswpmi);
 
     tmp_state = hswpmi->State;
-    if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+    if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
     {
       /* Check if a non-blocking receive process is ongoing or not */
-      if(tmp_state == HAL_SWPMI_STATE_READY)
+      if (tmp_state == HAL_SWPMI_STATE_READY)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
 
@@ -696,7 +695,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat
       do
       {
         /* Wait the TXE to write data */
-        if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
+        if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_TXE))
         {
           hswpmi->Instance->TDR = *ptmp_data;
           ptmp_data++;
@@ -705,19 +704,20 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat
         else
         {
           /* Check for the Timeout */
-          if(Timeout != HAL_MAX_DELAY)
+          if (Timeout != HAL_MAX_DELAY)
           {
-            if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+            if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
             {
               status = HAL_TIMEOUT;
               break;
             }
           }
         }
-      } while(tmp_size != 0U);
+      }
+      while (tmp_size != 0U);
 
       /* Wait on TXBEF flag to be able to start a second transfer */
-      if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
+      if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, Timeout) != HAL_OK)
       {
         /* Timeout occurred */
         hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
@@ -725,10 +725,10 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat
         status = HAL_TIMEOUT;
       }
 
-      if(status == HAL_OK)
+      if (status == HAL_OK)
       {
         /* Check if a non-blocking receive Process is ongoing or not */
-        if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+        if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
         {
           hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
         }
@@ -744,7 +744,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t* pDat
     }
   }
 
-  if((status != HAL_OK) && (status != HAL_BUSY))
+  if ((status != HAL_OK) && (status != HAL_BUSY))
   {
     hswpmi->State = HAL_SWPMI_STATE_READY;
   }
@@ -771,7 +771,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData
   uint32_t *ptmp_data;
   uint32_t tmp_size;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     status = HAL_ERROR;
   }
@@ -781,10 +781,10 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData
     __HAL_LOCK(hswpmi);
 
     tmp_state = hswpmi->State;
-    if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+    if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
     {
       /* Check if a non-blocking transmit process is ongoing or not */
-      if(tmp_state == HAL_SWPMI_STATE_READY)
+      if (tmp_state == HAL_SWPMI_STATE_READY)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
 
@@ -804,7 +804,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData
       do
       {
         /* Wait the RXNE to read data */
-        if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
+        if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXNE))
         {
           *ptmp_data = hswpmi->Instance->RDR;
           ptmp_data++;
@@ -813,27 +813,28 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData
         else
         {
           /* Check for the Timeout */
-          if(Timeout != HAL_MAX_DELAY)
+          if (Timeout != HAL_MAX_DELAY)
           {
-            if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+            if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
             {
               status = HAL_TIMEOUT;
               break;
             }
           }
         }
-      } while(tmp_size != 0U);
+      }
+      while (tmp_size != 0U);
 
-      if(status == HAL_OK)
+      if (status == HAL_OK)
       {
-        if(HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
+        if (HAL_IS_BIT_SET(hswpmi->Instance->ISR, SWPMI_FLAG_RXBFF))
         {
           /* Clear RXBFF at end of reception */
           WRITE_REG(hswpmi->Instance->ICR, SWPMI_FLAG_RXBFF);
         }
 
         /* Check if a non-blocking transmit Process is ongoing or not */
-        if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+        if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
         {
           hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
         }
@@ -849,7 +850,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData
     }
   }
 
-  if((status != HAL_OK) && (status != HAL_BUSY))
+  if ((status != HAL_OK) && (status != HAL_BUSY))
   {
     hswpmi->State = HAL_SWPMI_STATE_READY;
   }
@@ -872,7 +873,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
   HAL_StatusTypeDef status = HAL_OK;
   HAL_SWPMI_StateTypeDef tmp_state;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     status =  HAL_ERROR;
   }
@@ -882,7 +883,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
     __HAL_LOCK(hswpmi);
 
     tmp_state = hswpmi->State;
-    if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+    if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
     {
       /* Update handle */
       hswpmi->pTxBuffPtr = pData;
@@ -891,7 +892,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
 
       /* Check if a receive process is ongoing or not */
-      if(tmp_state == HAL_SWPMI_STATE_READY)
+      if (tmp_state == HAL_SWPMI_STATE_READY)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
 
@@ -939,7 +940,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD
   HAL_StatusTypeDef status = HAL_OK;
   HAL_SWPMI_StateTypeDef tmp_state;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     status =  HAL_ERROR;
   }
@@ -949,7 +950,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD
     __HAL_LOCK(hswpmi);
 
     tmp_state = hswpmi->State;
-    if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+    if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
     {
       /* Update handle */
       hswpmi->pRxBuffPtr = pData;
@@ -958,7 +959,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pD
       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
 
       /* Check if a transmit process is ongoing or not */
-      if(tmp_state == HAL_SWPMI_STATE_READY)
+      if (tmp_state == HAL_SWPMI_STATE_READY)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
 
@@ -1002,7 +1003,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *
   HAL_StatusTypeDef status = HAL_OK;
   HAL_SWPMI_StateTypeDef tmp_state;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     status =  HAL_ERROR;
   }
@@ -1012,7 +1013,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *
     __HAL_LOCK(hswpmi);
 
     tmp_state = hswpmi->State;
-    if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
+    if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_RX))
     {
       /* Update handle */
       hswpmi->pTxBuffPtr = pData;
@@ -1021,7 +1022,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *
       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
 
       /* Check if a receive process is ongoing or not */
-      if(tmp_state == HAL_SWPMI_STATE_READY)
+      if (tmp_state == HAL_SWPMI_STATE_READY)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
 
@@ -1043,7 +1044,7 @@ HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *
       hswpmi->hdmatx->XferErrorCallback = SWPMI_DMAError;
 
       /* Enable the SWPMI transmit DMA stream */
-      if(HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
+      if (HAL_DMA_Start_IT(hswpmi->hdmatx, (uint32_t)hswpmi->pTxBuffPtr, (uint32_t)&hswpmi->Instance->TDR, Size) != HAL_OK)
       {
         hswpmi->State = tmp_state;    /* Back to previous state */
         hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
@@ -1089,7 +1090,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
   HAL_StatusTypeDef status = HAL_OK;
   HAL_SWPMI_StateTypeDef tmp_state;
 
-  if((pData == NULL ) || (Size == 0U))
+  if ((pData == NULL) || (Size == 0U))
   {
     status =  HAL_ERROR;
   }
@@ -1099,7 +1100,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
     __HAL_LOCK(hswpmi);
 
     tmp_state = hswpmi->State;
-    if((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
+    if ((tmp_state == HAL_SWPMI_STATE_READY) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX))
     {
       /* Update handle */
       hswpmi->pRxBuffPtr = pData;
@@ -1107,7 +1108,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
       hswpmi->ErrorCode = HAL_SWPMI_ERROR_NONE;
 
       /* Check if a transmit process is ongoing or not */
-      if(tmp_state == HAL_SWPMI_STATE_READY)
+      if (tmp_state == HAL_SWPMI_STATE_READY)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
 
@@ -1129,7 +1130,7 @@ HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *p
       hswpmi->hdmarx->XferErrorCallback = SWPMI_DMAError;
 
       /* Enable the DMA request */
-      if(HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
+      if (HAL_DMA_Start_IT(hswpmi->hdmarx, (uint32_t)&hswpmi->Instance->RDR, (uint32_t)hswpmi->pRxBuffPtr, Size) != HAL_OK)
       {
         hswpmi->State = tmp_state;    /* Back to previous state */
         hswpmi->ErrorCode = HAL_SWPMI_ERROR_DMA;
@@ -1179,18 +1180,18 @@ HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi)
   CLEAR_BIT(hswpmi->Instance->CR, (SWPMI_CR_TXDMA | SWPMI_CR_RXDMA));
 
   /* Abort the SWPMI DMA tx stream */
-  if(hswpmi->hdmatx != NULL)
+  if (hswpmi->hdmatx != NULL)
   {
-    if(HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
+    if (HAL_DMA_Abort(hswpmi->hdmatx) != HAL_OK)
     {
       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
       status = HAL_ERROR;
     }
   }
   /* Abort the SWPMI DMA rx stream */
-  if(hswpmi->hdmarx != NULL)
+  if (hswpmi->hdmarx != NULL)
   {
-    if(HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
+    if (HAL_DMA_Abort(hswpmi->hdmarx) != HAL_OK)
     {
       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
       status = HAL_ERROR;
@@ -1295,7 +1296,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
   uint32_t errcode = HAL_SWPMI_ERROR_NONE;
 
   /* SWPMI CRC error interrupt occurred --------------------------------------*/
-  if(((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
+  if (((regisr & SWPMI_FLAG_RXBERF) != 0U) && ((regier & SWPMI_IT_RXBERIE) != 0U))
   {
     /* Disable Receive CRC interrupt */
     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXBERIE | SWPMI_IT_RXBFIE);
@@ -1306,7 +1307,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
   }
 
   /* SWPMI Over-Run interrupt occurred -----------------------------------------*/
-  if(((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
+  if (((regisr & SWPMI_FLAG_RXOVRF) != 0U) && ((regier & SWPMI_IT_RXOVRIE) != 0U))
   {
     /* Disable Receive overrun interrupt */
     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RXOVRIE);
@@ -1317,7 +1318,7 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
   }
 
   /* SWPMI Under-Run interrupt occurred -----------------------------------------*/
-  if(((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
+  if (((regisr & SWPMI_FLAG_TXUNRF) != 0U) && ((regier & SWPMI_IT_TXUNRIE) != 0U))
   {
     /* Disable Transmit under run interrupt */
     CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TXUNRIE);
@@ -1327,27 +1328,27 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
     errcode |= HAL_SWPMI_ERROR_UDR;
   }
 
-   /* Call SWPMI Error Call back function if needed --------------------------*/
-  if(errcode != HAL_SWPMI_ERROR_NONE)
+  /* Call SWPMI Error Call back function if needed --------------------------*/
+  if (errcode != HAL_SWPMI_ERROR_NONE)
   {
     hswpmi->ErrorCode |= errcode;
 
-    if((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
+    if ((errcode & HAL_SWPMI_ERROR_UDR) != 0U)
     {
       /* Check TXDMA transfer to abort */
-      if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
+      if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_TXDMA))
       {
         /* Disable DMA TX at SWPMI level */
         CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA);
 
         /* Abort the USART DMA Tx stream */
-        if(hswpmi->hdmatx != NULL)
+        if (hswpmi->hdmatx != NULL)
         {
           /* Set the SWPMI Tx DMA Abort callback :
              will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
           hswpmi->hdmatx->XferAbortCallback = SWPMI_DMAAbortOnError;
           /* Abort DMA TX */
-          if(HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
+          if (HAL_DMA_Abort_IT(hswpmi->hdmatx) != HAL_OK)
           {
             /* Call Directly hswpmi->hdmatx->XferAbortCallback function in case of error */
             hswpmi->hdmatx->XferAbortCallback(hswpmi->hdmatx);
@@ -1380,19 +1381,19 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
     else
     {
       /* Check RXDMA transfer to abort */
-      if(HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
+      if (HAL_IS_BIT_SET(hswpmi->Instance->CR, SWPMI_CR_RXDMA))
       {
         /* Disable DMA RX at SWPMI level */
         CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
 
         /* Abort the USART DMA Rx stream */
-        if(hswpmi->hdmarx != NULL)
+        if (hswpmi->hdmarx != NULL)
         {
           /* Set the SWPMI Rx DMA Abort callback :
              will lead to call HAL_SWPMI_ErrorCallback() at end of DMA abort procedure */
           hswpmi->hdmarx->XferAbortCallback = SWPMI_DMAAbortOnError;
           /* Abort DMA RX */
-          if(HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
+          if (HAL_DMA_Abort_IT(hswpmi->hdmarx) != HAL_OK)
           {
             /* Call Directly hswpmi->hdmarx->XferAbortCallback function in case of error */
             hswpmi->hdmarx->XferAbortCallback(hswpmi->hdmarx);
@@ -1425,31 +1426,31 @@ void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi)
   }
 
   /* SWPMI in mode Receiver ---------------------------------------------------*/
-  if(((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE)  != 0U))
+  if (((regisr & SWPMI_FLAG_RXNE) != 0U) && ((regier & SWPMI_IT_RIE)  != 0U))
   {
     SWPMI_Receive_IT(hswpmi);
   }
 
   /* SWPMI in mode Transmitter ------------------------------------------------*/
-  if(((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
+  if (((regisr & SWPMI_FLAG_TXE) != 0U) && ((regier & SWPMI_IT_TIE) != 0U))
   {
     SWPMI_Transmit_IT(hswpmi);
   }
 
   /* SWPMI in mode Transmitter (Transmit buffer empty) ------------------------*/
-  if(((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
+  if (((regisr & SWPMI_FLAG_TXBEF) != 0U) && ((regier & SWPMI_IT_TXBEIE) != 0U))
   {
     SWPMI_EndTransmit_IT(hswpmi);
   }
 
   /* SWPMI in mode Receiver (Receive buffer full) -----------------------------*/
-  if(((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
+  if (((regisr & SWPMI_FLAG_RXBFF) != 0U) && ((regier & SWPMI_IT_RXBFIE) != 0U))
   {
     SWPMI_EndReceive_IT(hswpmi);
   }
 
   /* Both Transmission and reception complete ---------------------------------*/
-  if(((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
+  if (((regisr & SWPMI_FLAG_TCF) != 0U) && ((regier & SWPMI_IT_TCIE) != 0U))
   {
     SWPMI_EndTransmitReceive_IT(hswpmi);
   }
@@ -1597,14 +1598,14 @@ static void SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi)
 
   if ((tmp_state == HAL_SWPMI_STATE_BUSY_TX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
   {
-    if(hswpmi->TxXferCount == 0U)
+    if (hswpmi->TxXferCount == 0U)
     {
       /* Disable the SWPMI TXE and Underrun Interrupts */
       CLEAR_BIT(hswpmi->Instance->IER, (SWPMI_IT_TIE | SWPMI_IT_TXUNRIE));
     }
     else
     {
-      hswpmi->Instance->TDR = (uint32_t)*hswpmi->pTxBuffPtr;
+      hswpmi->Instance->TDR = (uint32_t) * hswpmi->pTxBuffPtr;
       hswpmi->pTxBuffPtr++;
       hswpmi->TxXferCount--;
     }
@@ -1628,7 +1629,7 @@ static void SWPMI_EndTransmit_IT(SWPMI_HandleTypeDef *hswpmi)
   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TIE | SWPMI_IT_TXUNRIE | SWPMI_IT_TXBEIE);
 
   /* Check if a receive Process is ongoing or not */
-  if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+  if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
   {
     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
   }
@@ -1654,13 +1655,13 @@ static void SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi)
 {
   HAL_SWPMI_StateTypeDef tmp_state = hswpmi->State;
 
-  if((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
+  if ((tmp_state == HAL_SWPMI_STATE_BUSY_RX) || (tmp_state == HAL_SWPMI_STATE_BUSY_TX_RX))
   {
     *hswpmi->pRxBuffPtr = (uint32_t)(hswpmi->Instance->RDR);
     hswpmi->pRxBuffPtr++;
 
     --hswpmi->RxXferCount;
-    if(hswpmi->RxXferCount == 0U)
+    if (hswpmi->RxXferCount == 0U)
     {
       /* Wait for RXBFF flag to update state */
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
@@ -1689,7 +1690,7 @@ static void SWPMI_EndReceive_IT(SWPMI_HandleTypeDef *hswpmi)
   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_RIE | SWPMI_IT_RXBERIE | SWPMI_IT_RXOVRIE | SWPMI_IT_RXBFIE);
 
   /* Check if a transmit Process is ongoing or not */
-  if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+  if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
   {
     hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
   }
@@ -1712,11 +1713,11 @@ static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
   CLEAR_BIT(hswpmi->Instance->IER, SWPMI_IT_TCIE);
 
   /* Check if a receive Process is ongoing or not */
-  if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+  if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
   {
     hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
   }
-  else if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
+  else if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX)
   {
     hswpmi->State = HAL_SWPMI_STATE_READY;
   }
@@ -1733,11 +1734,11 @@ static void SWPMI_EndTransmitReceive_IT(SWPMI_HandleTypeDef *hswpmi)
   */
 static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 {
-  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
   uint32_t tickstart;
 
   /* DMA Normal mode*/
-  if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
+  if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
   {
     hswpmi->TxXferCount = 0U;
 
@@ -1749,7 +1750,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
     tickstart = HAL_GetTick();
 
     /* Wait the TXBEF */
-    if(SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
+    if (SWPMI_WaitOnFlagSetUntilTimeout(hswpmi, SWPMI_FLAG_TXBEF, tickstart, SWPMI_TIMEOUT_VALUE) != HAL_OK)
     {
       /* Timeout occurred */
       hswpmi->ErrorCode |= HAL_SWPMI_ERROR_TXBEF_TIMEOUT;
@@ -1764,7 +1765,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
     {
       /* No Timeout */
       /* Check if a receive process is ongoing or not */
-      if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+      if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
       {
         hswpmi->State = HAL_SWPMI_STATE_BUSY_RX;
       }
@@ -1798,7 +1799,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
   */
 static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
   hswpmi->TxHalfCpltCallback(hswpmi);
@@ -1815,10 +1816,10 @@ static void SWPMI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 {
-  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* DMA Normal mode*/
-  if(((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
+  if (((((DMA_Stream_TypeDef *)hdma->Instance)->CR) & DMA_SxCR_CIRC) == 0U)
   {
     hswpmi->RxXferCount = 0U;
 
@@ -1827,7 +1828,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
     CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_RXDMA);
 
     /* Check if a transmit Process is ongoing or not */
-    if(hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
+    if (hswpmi->State == HAL_SWPMI_STATE_BUSY_TX_RX)
     {
       hswpmi->State = HAL_SWPMI_STATE_BUSY_TX;
     }
@@ -1850,7 +1851,7 @@ static void SWPMI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
   */
 static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
-  SWPMI_HandleTypeDef* hswpmi = (SWPMI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+  SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
   hswpmi->RxHalfCpltCallback(hswpmi);
@@ -1866,12 +1867,12 @@ static void SWPMI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
   */
 static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
 {
-  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Update handle */
   hswpmi->RxXferCount = 0U;
   hswpmi->TxXferCount = 0U;
-  hswpmi->State= HAL_SWPMI_STATE_READY;
+  hswpmi->State = HAL_SWPMI_STATE_READY;
   hswpmi->ErrorCode |= HAL_SWPMI_ERROR_DMA;
 
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
@@ -1888,12 +1889,12 @@ static void SWPMI_DMAError(DMA_HandleTypeDef *hdma)
   */
 static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 {
-  SWPMI_HandleTypeDef* hswpmi = ( SWPMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  SWPMI_HandleTypeDef *hswpmi = (SWPMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
 
   /* Update handle */
   hswpmi->RxXferCount = 0U;
   hswpmi->TxXferCount = 0U;
-  hswpmi->State= HAL_SWPMI_STATE_READY;
+  hswpmi->State = HAL_SWPMI_STATE_READY;
 
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
   hswpmi->ErrorCallback(hswpmi);
@@ -1905,7 +1906,7 @@ static void SWPMI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 /**
   * @brief  Handle SWPMI Communication Timeout.
   * @param  hswpmi SWPMI handle
-  * @param  Flag: specifies the SWPMI flag to check.
+  * @param  Flag specifies the SWPMI flag to check.
   * @param  Tickstart Tick start value
   * @param  Timeout timeout duration.
   * @retval HAL status
@@ -1915,7 +1916,7 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs
   HAL_StatusTypeDef status = HAL_OK;
 
   /* Wait until flag is set */
-  while(!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
+  while (!(HAL_IS_BIT_SET(hswpmi->Instance->ISR, Flag)))
   {
     /* Check for the Timeout */
     if ((((HAL_GetTick() - Tickstart) >  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
@@ -1945,5 +1946,3 @@ static HAL_StatusTypeDef SWPMI_WaitOnFlagSetUntilTimeout(SWPMI_HandleTypeDef *hs
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.h
index f41ac106b3..4180c713c3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,7 +21,7 @@
 #define STM32H7xx_HAL_SWPMI_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -62,7 +61,7 @@ typedef struct
   uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.
                                           This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
 
-}SWPMI_InitTypeDef;
+} SWPMI_InitTypeDef;
 
 
 /**
@@ -78,7 +77,7 @@ typedef enum
   HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
   HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
   HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */
-}HAL_SWPMI_StateTypeDef;
+} HAL_SWPMI_StateTypeDef;
 
 /**
   * @brief  SWPMI handle Structure definition
@@ -116,16 +115,16 @@ typedef struct
   __IO uint32_t                  ErrorCode;     /*!< SWPMI Error code                     */
 
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
-  void (*RxCpltCallback)     (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */
-  void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */
-  void (*TxCpltCallback)     (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */
-  void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */
-  void (*ErrorCallback)      (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */
-  void (*MspInitCallback)    (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */
-  void (*MspDeInitCallback)  (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */
+  void (*RxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi);      /*!< SWPMI receive complete callback */
+  void (*RxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi);  /*!< SWPMI receive half complete callback */
+  void (*TxCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi);      /*!< SWPMI transmit complete callback */
+  void (*TxHalfCpltCallback)(struct __SWPMI_HandleTypeDef *hswpmi);  /*!< SWPMI transmit half complete callback */
+  void (*ErrorCallback)(struct __SWPMI_HandleTypeDef *hswpmi);       /*!< SWPMI error callback */
+  void (*MspInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi);     /*!< SWPMI MSP init callback */
+  void (*MspDeInitCallback)(struct __SWPMI_HandleTypeDef *hswpmi);   /*!< SWPMI MSP de-init callback */
 #endif
 
-}SWPMI_HandleTypeDef;
+} SWPMI_HandleTypeDef;
 
 #if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)
 /**
@@ -140,7 +139,7 @@ typedef enum
   HAL_SWPMI_ERROR_CB_ID           = 0x04U, /*!< SWPMI error callback ID */
   HAL_SWPMI_MSPINIT_CB_ID         = 0x05U, /*!< SWPMI MSP init callback ID */
   HAL_SWPMI_MSPDEINIT_CB_ID       = 0x06U  /*!< SWPMI MSP de-init callback ID */
-}HAL_SWPMI_CallbackIDTypeDef;
+} HAL_SWPMI_CallbackIDTypeDef;
 
 /**
   * @brief  SWPMI callback pointer definition
@@ -298,7 +297,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi);
 
 /** @brief  Check whether the specified SWPMI flag is set or not.
   * @param  __HANDLE__ specifies the SWPMI Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg SWPMI_FLAG_RXBFF  Receive buffer full flag.
   *            @arg SWPMI_FLAG_TXBEF  Transmit buffer empty flag.
@@ -318,7 +317,7 @@ typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi);
 
 /** @brief  Clear the specified SWPMI ISR flag.
   * @param  __HANDLE__ specifies the SWPMI Handle.
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __FLAG__ specifies the flag to clear.
   *        This parameter can be one of the following values:
   *            @arg SWPMI_FLAG_RXBFF  Receive buffer full flag.
   *            @arg SWPMI_FLAG_TXBEF  Transmit buffer empty flag.
@@ -516,5 +515,3 @@ uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
 #endif
 
 #endif /* STM32H7xx_HAL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c
index 5dc8d353d1..1020295267 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c
@@ -29,6 +29,17 @@
   *           + Commutation Event configuration with Interruption and DMA
   *           + TIM OCRef clear configuration
   *           + TIM External Clock configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                       ##### TIMER Generic features #####
@@ -103,14 +114,14 @@
   allows the user to configure dynamically the driver callbacks.
 
   [..]
-  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
-  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+  Use Function HAL_TIM_RegisterCallback() to register a callback.
+  HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
   the Callback ID and a pointer to the user callback function.
 
   [..]
-  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+  Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default
   weak function.
-  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
   and the Callback ID.
 
   [..]
@@ -147,7 +158,7 @@
   [..]
 By default, after the Init and when the state is HAL_TIM_STATE_RESET
 all interrupt callbacks are set to the corresponding weak functions:
-  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+  examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback().
 
   [..]
   Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
@@ -161,7 +172,7 @@ all interrupt callbacks are set to the corresponding weak functions:
     in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
     thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
   In that case first register the MspInit/MspDeInit user callbacks
-      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+      using HAL_TIM_RegisterCallback() before calling DeInit or Init function.
 
   [..]
       When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
@@ -170,17 +181,6 @@ all interrupt callbacks are set to the corresponding weak functions:
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -205,11 +205,11 @@ all interrupt callbacks are set to the corresponding weak functions:
 /** @addtogroup TIM_Private_Functions
   * @{
   */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
+static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
                               uint32_t TIM_ICFilter);
@@ -225,7 +225,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig);
 /**
   * @}
   */
@@ -278,6 +278,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
   if (htim->State == HAL_TIM_STATE_RESET)
@@ -525,7 +526,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
   * @param  Length The length of data to be transferred from memory to peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length)
 {
   uint32_t tmpsmcr;
 
@@ -539,7 +540,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
   }
   else if (htim->State == HAL_TIM_STATE_READY)
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -561,7 +562,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
   htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
 
   /* Enable the DMA stream */
-  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
+  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR,
+                       Length) != HAL_OK)
   {
     /* Return error status */
     return HAL_ERROR;
@@ -660,6 +662,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
   if (htim->State == HAL_TIM_STATE_RESET)
@@ -881,10 +884,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Check the TIM channel state */
   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -926,34 +930,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -969,8 +977,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   switch (Channel)
   {
@@ -1003,26 +1013,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
   }
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1038,12 +1052,14 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Set the TIM channel state */
   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1052,7 +1068,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   }
   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -1078,7 +1094,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1099,7 +1116,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1120,7 +1138,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1140,7 +1159,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1151,34 +1171,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
+    /* Enable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1194,8 +1218,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   */
 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   switch (Channel)
   {
@@ -1232,26 +1258,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
+    /* Disable the Output compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
   }
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1301,6 +1331,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
   if (htim->State == HAL_TIM_STATE_RESET)
@@ -1522,9 +1553,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Check the TIM channel state */
   if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
@@ -1566,34 +1599,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1609,8 +1646,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   switch (Channel)
   {
@@ -1643,26 +1682,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
   }
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1678,12 +1721,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Set the TIM channel state */
   if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
@@ -1692,7 +1737,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
   }
   else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -1718,7 +1763,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1739,7 +1785,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1759,7 +1806,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1779,7 +1827,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1790,34 +1839,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
-  }
+    /* Enable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Enable the main output */
+      __HAL_TIM_MOE_ENABLE(htim);
+    }
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1833,8 +1886,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
   */
 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   switch (Channel)
   {
@@ -1871,26 +1926,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+  if (status == HAL_OK)
   {
-    /* Disable the Main Output */
-    __HAL_TIM_MOE_DISABLE(htim);
+    /* Disable the Capture compare channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
+    if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+    {
+      /* Disable the Main Output */
+      __HAL_TIM_MOE_DISABLE(htim);
+    }
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
   }
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1940,6 +1999,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_INSTANCE(htim->Instance));
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
   if (htim->State == HAL_TIM_STATE_RESET)
@@ -2073,7 +2133,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Check the TIM channel state */
   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2121,7 +2181,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Disable the Input Capture channel */
   TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
@@ -2150,12 +2210,14 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
+
   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   /* Check the TIM channel state */
   if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
@@ -2199,27 +2261,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  if (status == HAL_OK)
   {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    /* Enable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -2235,8 +2302,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
 
   switch (Channel)
   {
@@ -2269,21 +2338,25 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+  if (status == HAL_OK)
+  {
+    /* Disable the Input Capture channel */
+    TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
 
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -2301,12 +2374,14 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
+
   HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
   HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
 
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
 
   /* Set the TIM channel state */
@@ -2318,7 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
            && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -2333,6 +2408,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
     return HAL_ERROR;
   }
 
+  /* Enable the Input Capture channel */
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+
   switch (Channel)
   {
     case TIM_CHANNEL_1:
@@ -2345,7 +2423,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -2365,7 +2444,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -2385,7 +2465,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -2405,7 +2486,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -2416,12 +2498,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
   {
@@ -2437,7 +2517,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -2453,8 +2533,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
   */
 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
+  assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
   assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
 
   /* Disable the Input Capture channel */
@@ -2495,18 +2577,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
+  if (status == HAL_OK)
+  {
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
 
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    /* Set the TIM channel state */
+    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 /**
   * @}
@@ -2563,6 +2649,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul
   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
   assert_param(IS_TIM_OPM_MODE(OnePulseMode));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
 
   if (htim->State == HAL_TIM_STATE_RESET)
@@ -2692,8 +2779,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
   * @brief  Starts the TIM One Pulse signal generation.
   * @note Though OutputChannel parameter is deprecated and ignored by the function
   *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel See note above
   * @retval HAL status
@@ -2749,8 +2836,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu
   * @brief  Stops the TIM One Pulse signal generation.
   * @note Though OutputChannel parameter is deprecated and ignored by the function
   *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel See note above
   * @retval HAL status
@@ -2792,8 +2879,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output
   * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
   * @note Though OutputChannel parameter is deprecated and ignored by the function
   *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel See note above
   * @retval HAL status
@@ -2855,8 +2942,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou
   * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
   * @note Though OutputChannel parameter is deprecated and ignored by the function
   *        it has been kept to avoid HAL_TIM API compatibility break.
-  * @note The pulse output channel is determined when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note The pulse output channel is determined when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel See note above
   * @retval HAL status
@@ -2940,7 +3027,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
   * @param  sConfig TIM Encoder Interface configuration structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
 {
   uint32_t tmpsmcr;
   uint32_t tmpccmr1;
@@ -2966,6 +3053,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_Ini
   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
 
   if (htim->State == HAL_TIM_STATE_RESET)
   {
@@ -3475,7 +3563,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
     else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
     {
-      if ((pData1 == NULL) && (Length > 0U))
+      if ((pData1 == NULL) || (Length == 0U))
       {
         return HAL_ERROR;
       }
@@ -3500,7 +3588,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
     else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
     {
-      if ((pData2 == NULL) && (Length > 0U))
+      if ((pData2 == NULL) || (Length == 0U))
       {
         return HAL_ERROR;
       }
@@ -3529,7 +3617,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
              && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
              && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
     {
-      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
+      if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U))
       {
         return HAL_ERROR;
       }
@@ -3559,7 +3647,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -3567,11 +3656,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Enable the TIM Input Capture DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
 
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+
       /* Enable the Peripheral */
       __HAL_TIM_ENABLE(htim);
 
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
       break;
     }
 
@@ -3584,7 +3674,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Set the DMA error callback */
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -3592,15 +3683,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       /* Enable the TIM Input Capture  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
 
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
       /* Enable the Peripheral */
       __HAL_TIM_ENABLE(htim);
 
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
       break;
     }
 
-    case TIM_CHANNEL_ALL:
+    default:
     {
       /* Set the DMA capture callbacks */
       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
@@ -3610,7 +3702,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -3624,27 +3717,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
       }
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
 
       /* Enable the TIM Input Capture  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
       /* Enable the TIM Input Capture  DMA request */
       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
+
+      /* Enable the Capture compare channel */
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+
+      /* Enable the Peripheral */
+      __HAL_TIM_ENABLE(htim);
+
       break;
     }
-
-    default:
-      break;
   }
 
   /* Return function status */
@@ -3740,13 +3833,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
   */
 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
 {
+  uint32_t itsource = htim->Instance->DIER;
+  uint32_t itflag   = htim->Instance->SR;
+
   /* Capture compare 1 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
     {
       {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
         htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 
         /* Input capture event */
@@ -3774,11 +3870,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* Capture compare 2 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
       /* Input capture event */
       if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
@@ -3804,11 +3900,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* Capture compare 3 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
       /* Input capture event */
       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
@@ -3834,11 +3930,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* Capture compare 4 event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
       htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
       /* Input capture event */
       if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
@@ -3864,11 +3960,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* TIM Update event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
       htim->PeriodElapsedCallback(htim);
 #else
@@ -3877,11 +3973,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* TIM Break input event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
+  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
       htim->BreakCallback(htim);
 #else
@@ -3890,9 +3987,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* TIM Break2 input event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
+  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
     {
       __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
@@ -3903,11 +4000,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* TIM Trigger detection event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
       htim->TriggerCallback(htim);
 #else
@@ -3916,11 +4013,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
     }
   }
   /* TIM commutation event */
-  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
+  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
   {
-    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
+    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
     {
-      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
       htim->CommutationCallback(htim);
 #else
@@ -3969,9 +4066,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
-                                           TIM_OC_InitTypeDef *sConfig,
+                                           const TIM_OC_InitTypeDef *sConfig,
                                            uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_CHANNELS(Channel));
   assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
@@ -4043,12 +4142,13 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
   __HAL_UNLOCK(htim);
 
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -4064,8 +4164,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
   assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
@@ -4122,7 +4224,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
     /* Set the IC3PSC value */
     htim->Instance->CCMR2 |= sConfig->ICPrescaler;
   }
-  else
+  else if (Channel == TIM_CHANNEL_4)
   {
     /* TI4 Configuration */
     assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
@@ -4138,10 +4240,14 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
     /* Set the IC4PSC value */
     htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
   }
+  else
+  {
+    status = HAL_ERROR;
+  }
 
   __HAL_UNLOCK(htim);
 
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -4160,9 +4266,11 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
-                                            TIM_OC_InitTypeDef *sConfig,
+                                            const TIM_OC_InitTypeDef *sConfig,
                                             uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_CHANNELS(Channel));
   assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
@@ -4277,12 +4385,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
   __HAL_UNLOCK(htim);
 
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -4307,6 +4416,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,
                                                  uint32_t OutputChannel,  uint32_t InputChannel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   TIM_OC_InitTypeDef temp1;
 
   /* Check the parameters */
@@ -4337,6 +4447,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
         TIM_OC1_SetConfig(htim->Instance, &temp1);
         break;
       }
+
       case TIM_CHANNEL_2:
       {
         assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
@@ -4344,60 +4455,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
         TIM_OC2_SetConfig(htim->Instance, &temp1);
         break;
       }
+
       default:
+        status = HAL_ERROR;
         break;
     }
 
-    switch (InputChannel)
+    if (status == HAL_OK)
     {
-      case TIM_CHANNEL_1:
+      switch (InputChannel)
       {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
+        case TIM_CHANNEL_1:
+        {
+          assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
 
-        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                          sConfig->ICSelection, sConfig->ICFilter);
+          TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
 
-        /* Reset the IC1PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
+          /* Reset the IC1PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
 
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI1FP1;
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI1FP1;
 
-        /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-        break;
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        case TIM_CHANNEL_2:
+        {
+          assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+
+          TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
+                            sConfig->ICSelection, sConfig->ICFilter);
+
+          /* Reset the IC2PSC Bits */
+          htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
+
+          /* Select the Trigger source */
+          htim->Instance->SMCR &= ~TIM_SMCR_TS;
+          htim->Instance->SMCR |= TIM_TS_TI2FP2;
+
+          /* Select the Slave Mode */
+          htim->Instance->SMCR &= ~TIM_SMCR_SMS;
+          htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
+          break;
+        }
+
+        default:
+          status = HAL_ERROR;
+          break;
       }
-      case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                          sConfig->ICSelection, sConfig->ICFilter);
-
-        /* Reset the IC2PSC Bits */
-        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-        /* Select the Trigger source */
-        htim->Instance->SMCR &= ~TIM_SMCR_TS;
-        htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
-        /* Select the Slave Mode */
-        htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-        break;
-      }
-
-      default:
-        break;
     }
 
     htim->State = HAL_TIM_STATE_READY;
 
     __HAL_UNLOCK(htim);
 
-    return HAL_OK;
+    return status;
   }
   else
   {
@@ -4428,13 +4546,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
   *            @arg TIM_DMABASE_CCR3
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_CCMR3 
-  *            @arg TIM_DMABASE_CCR5 
-  *            @arg TIM_DMABASE_CCR6 
-  *            @arg TIM_DMABASE_AF1  
-  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
   *            @arg TIM_DMABASE_TISEL
-  *         
+  *
   * @param  BurstRequestSrc TIM DMA Request sources
   *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4451,10 +4569,17 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_O
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)
+                                              uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                              uint32_t  BurstLength)
 {
-  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
-                                          ((BurstLength) >> 8U) + 1U);
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                            ((BurstLength) >> 8U) + 1U);
+
+
+
+  return status;
 }
 
 /**
@@ -4480,13 +4605,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
   *            @arg TIM_DMABASE_CCR3
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_CCMR3 
-  *            @arg TIM_DMABASE_CCR5 
-  *            @arg TIM_DMABASE_CCR6 
-  *            @arg TIM_DMABASE_AF1  
-  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
   *            @arg TIM_DMABASE_TISEL
-  *         
+  *
   * @param  BurstRequestSrc TIM DMA Request sources
   *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4504,9 +4629,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
                                                    uint32_t  BurstLength,  uint32_t  DataLength)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
@@ -4533,6 +4660,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
   {
     /* nothing to do */
   }
+
   switch (BurstRequestSrc)
   {
     case TIM_DMA_UPDATE:
@@ -4546,7 +4674,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4564,7 +4692,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4582,7 +4710,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4600,7 +4728,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4618,7 +4746,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4636,7 +4764,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4654,7 +4782,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
-                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
+                           (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4662,16 +4790,20 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
       break;
     }
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Configure the DMA Burst Mode */
-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -4682,6 +4814,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
 
@@ -4724,17 +4858,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
       break;
     }
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
 
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -4760,13 +4898,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
   *            @arg TIM_DMABASE_CCR3
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_CCMR3 
-  *            @arg TIM_DMABASE_CCR5 
-  *            @arg TIM_DMABASE_CCR6 
-  *            @arg TIM_DMABASE_AF1  
-  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
   *            @arg TIM_DMABASE_TISEL
-  *         
+  *
   * @param  BurstRequestSrc TIM DMA Request sources
   *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4785,8 +4923,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)
 {
-  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
-                                         ((BurstLength) >> 8U) + 1U);
+  HAL_StatusTypeDef status;
+
+  status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+                                           ((BurstLength) >> 8U) + 1U);
+
+
+  return status;
 }
 
 /**
@@ -4812,13 +4955,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
   *            @arg TIM_DMABASE_CCR3
   *            @arg TIM_DMABASE_CCR4
   *            @arg TIM_DMABASE_BDTR
-  *            @arg TIM_DMABASE_CCMR3 
-  *            @arg TIM_DMABASE_CCR5 
-  *            @arg TIM_DMABASE_CCR6 
-  *            @arg TIM_DMABASE_AF1  
-  *            @arg TIM_DMABASE_AF2  
+  *            @arg TIM_DMABASE_CCMR3
+  *            @arg TIM_DMABASE_CCR5
+  *            @arg TIM_DMABASE_CCR6
+  *            @arg TIM_DMABASE_AF1
+  *            @arg TIM_DMABASE_AF2
   *            @arg TIM_DMABASE_TISEL
-  *         
+  *
   * @param  BurstRequestSrc TIM DMA Request sources
   *         This parameter can be one of the following values:
   *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4839,6 +4982,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
                                                   uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
                                                   uint32_t  BurstLength, uint32_t  DataLength)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
   assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
@@ -4878,7 +5023,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4896,7 +5041,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4914,7 +5059,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4932,7 +5077,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4950,7 +5095,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4968,7 +5113,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4986,7 +5131,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
 
       /* Enable the DMA stream */
       if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
-                         DataLength) != HAL_OK)
+                           DataLength) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -4994,17 +5139,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
       break;
     }
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Configure the DMA Burst Mode */
-  htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+  if (status == HAL_OK)
+  {
+    /* Configure the DMA Burst Mode */
+    htim->Instance->DCR = (BurstBaseAddress | BurstLength);
 
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+    /* Enable the TIM DMA Request */
+    __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -5015,6 +5164,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
   */
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
 
@@ -5057,17 +5208,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu
       break;
     }
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+  if (status == HAL_OK)
+  {
+    /* Disable the TIM Update DMA request */
+    __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
 
-  /* Change the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+    /* Change the DMA burst operation state */
+    htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -5131,9 +5286,11 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
-                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
                                            uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
   assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
@@ -5175,104 +5332,108 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  switch (Channel)
+  if (status == HAL_OK)
   {
-    case TIM_CHANNEL_1:
+    switch (Channel)
     {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+      case TIM_CHANNEL_1:
       {
-        /* Enable the OCREF clear feature for Channel 1 */
-        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 1 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 1 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        }
+        break;
       }
-      else
+      case TIM_CHANNEL_2:
       {
-        /* Disable the OCREF clear feature for Channel 1 */
-        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 2 */
+          SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 2 */
+          CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
+        }
+        break;
       }
-      break;
+      case TIM_CHANNEL_3:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 3 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 3 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_4:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 4 */
+          SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 4 */
+          CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_5:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 5 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 5 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
+        }
+        break;
+      }
+      case TIM_CHANNEL_6:
+      {
+        if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
+        {
+          /* Enable the OCREF clear feature for Channel 6 */
+          SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        else
+        {
+          /* Disable the OCREF clear feature for Channel 6 */
+          CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
+        }
+        break;
+      }
+      default:
+        break;
     }
-    case TIM_CHANNEL_2:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 2 */
-        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 2 */
-        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_3:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 3 */
-        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 3 */
-        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_4:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 4 */
-        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 4 */
-        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_5:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 5 */
-        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 5 */
-        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
-      }
-      break;
-    }
-    case TIM_CHANNEL_6:
-    {
-      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
-      {
-        /* Enable the OCREF clear feature for Channel 6 */
-        SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
-      }
-      else
-      {
-        /* Disable the OCREF clear feature for Channel 6 */
-        CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
-      }
-      break;
-    }
-    default:
-      break;
   }
 
   htim->State = HAL_TIM_STATE_READY;
 
   __HAL_UNLOCK(htim);
 
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -5282,8 +5443,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
   *         contains the clock source information for the TIM peripheral.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Process Locked */
@@ -5409,22 +5571,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo
     case TIM_CLOCKSOURCE_ITR6:
     case TIM_CLOCKSOURCE_ITR7:
     case TIM_CLOCKSOURCE_ITR8:
-      {
-        /* Check whether or not the timer instance supports internal trigger input */
-        assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+    {
+      /* Check whether or not the timer instance supports internal trigger input */
+      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
 
-        TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
-        break;
-      }
+      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+      break;
+    }
 
     default:
+      status = HAL_ERROR;
       break;
   }
   htim->State = HAL_TIM_STATE_READY;
 
   __HAL_UNLOCK(htim);
 
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -5471,7 +5634,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
   *         (Disable, Reset, Gated, Trigger, External clock mode 1).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig)
 {
   /* Check the parameters */
   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -5512,7 +5675,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
-                                                TIM_SlaveConfigTypeDef *sSlaveConfig)
+                                                const TIM_SlaveConfigTypeDef *sSlaveConfig)
 {
   /* Check the parameters */
   assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@@ -5554,7 +5717,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
   * @retval Captured value
   */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel)
 {
   uint32_t tmpreg = 0U;
 
@@ -5829,8 +5992,6 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call
   {
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(htim);
 
   if (htim->State == HAL_TIM_STATE_READY)
   {
@@ -5950,7 +6111,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call
 
       default :
         /* Return error status */
-        status =  HAL_ERROR;
+        status = HAL_ERROR;
         break;
     }
   }
@@ -6016,19 +6177,16 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call
 
       default :
         /* Return error status */
-        status =  HAL_ERROR;
+        status = HAL_ERROR;
         break;
     }
   }
   else
   {
     /* Return error status */
-    status =  HAL_ERROR;
+    status = HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
   return status;
 }
 
@@ -6072,128 +6230,153 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(htim);
-
   if (htim->State == HAL_TIM_STATE_READY)
   {
     switch (CallbackID)
     {
       case HAL_TIM_BASE_MSPINIT_CB_ID :
-        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;
         break;
 
       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;
         break;
 
       case HAL_TIM_IC_MSPINIT_CB_ID :
-        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;
         break;
 
       case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;
         break;
 
       case HAL_TIM_OC_MSPINIT_CB_ID :
-        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;
         break;
 
       case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;
         break;
 
       case HAL_TIM_PWM_MSPINIT_CB_ID :
-        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;
         break;
 
       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;
         break;
 
       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;
         break;
 
       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;
         break;
 
       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;
         break;
 
       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;
         break;
 
       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
-        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;
         break;
 
       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
-        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;
         break;
 
       case HAL_TIM_PERIOD_ELAPSED_CB_ID :
-        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */
+        /* Legacy weak Period Elapsed Callback */
+        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
         break;
 
       case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
-        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */
+        /* Legacy weak Period Elapsed half complete Callback */
+        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
         break;
 
       case HAL_TIM_TRIGGER_CB_ID :
-        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */
+        /* Legacy weak Trigger Callback */
+        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
         break;
 
       case HAL_TIM_TRIGGER_HALF_CB_ID :
-        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */
+        /* Legacy weak Trigger half complete Callback */
+        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
         break;
 
       case HAL_TIM_IC_CAPTURE_CB_ID :
-        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */
+        /* Legacy weak IC Capture Callback */
+        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
         break;
 
       case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
-        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */
+        /* Legacy weak IC Capture half complete Callback */
+        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
         break;
 
       case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
-        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */
+        /* Legacy weak OC Delay Elapsed Callback */
+        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
         break;
 
       case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
-        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */
+        /* Legacy weak PWM Pulse Finished Callback */
+        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
         break;
 
       case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
-        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
+        /* Legacy weak PWM Pulse Finished half complete Callback */
+        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
         break;
 
       case HAL_TIM_ERROR_CB_ID :
-        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */
+        /* Legacy weak Error Callback */
+        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
         break;
 
       case HAL_TIM_COMMUTATION_CB_ID :
-        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */
+        /* Legacy weak Commutation Callback */
+        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
         break;
 
       case HAL_TIM_COMMUTATION_HALF_CB_ID :
-        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */
+        /* Legacy weak Commutation half complete Callback */
+        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
         break;
 
       case HAL_TIM_BREAK_CB_ID :
-        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */
+        /* Legacy weak Break Callback */
+        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
         break;
 
       case HAL_TIM_BREAK2_CB_ID :
-        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2 Callback */
+        /* Legacy weak Break2 Callback */
+        htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
         break;
 
       default :
         /* Return error status */
-        status =  HAL_ERROR;
+        status = HAL_ERROR;
         break;
     }
   }
@@ -6202,76 +6385,87 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
     switch (CallbackID)
     {
       case HAL_TIM_BASE_MSPINIT_CB_ID :
-        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */
+        /* Legacy weak Base MspInit Callback */
+        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;
         break;
 
       case HAL_TIM_BASE_MSPDEINIT_CB_ID :
-        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */
+        /* Legacy weak Base Msp DeInit Callback */
+        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;
         break;
 
       case HAL_TIM_IC_MSPINIT_CB_ID :
-        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */
+        /* Legacy weak IC Msp Init Callback */
+        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;
         break;
 
       case HAL_TIM_IC_MSPDEINIT_CB_ID :
-        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */
+        /* Legacy weak IC Msp DeInit Callback */
+        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;
         break;
 
       case HAL_TIM_OC_MSPINIT_CB_ID :
-        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */
+        /* Legacy weak OC Msp Init Callback */
+        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;
         break;
 
       case HAL_TIM_OC_MSPDEINIT_CB_ID :
-        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */
+        /* Legacy weak OC Msp DeInit Callback */
+        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;
         break;
 
       case HAL_TIM_PWM_MSPINIT_CB_ID :
-        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */
+        /* Legacy weak PWM Msp Init Callback */
+        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;
         break;
 
       case HAL_TIM_PWM_MSPDEINIT_CB_ID :
-        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */
+        /* Legacy weak PWM Msp DeInit Callback */
+        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;
         break;
 
       case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
-        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */
+        /* Legacy weak One Pulse Msp Init Callback */
+        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;
         break;
 
       case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
-        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */
+        /* Legacy weak One Pulse Msp DeInit Callback */
+        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;
         break;
 
       case HAL_TIM_ENCODER_MSPINIT_CB_ID :
-        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */
+        /* Legacy weak Encoder Msp Init Callback */
+        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;
         break;
 
       case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
-        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */
+        /* Legacy weak Encoder Msp DeInit Callback */
+        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;
         break;
 
       case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
-        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */
+        /* Legacy weak Hall Sensor Msp Init Callback */
+        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;
         break;
 
       case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
-        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */
+        /* Legacy weak Hall Sensor Msp DeInit Callback */
+        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
         break;
 
       default :
         /* Return error status */
-        status =  HAL_ERROR;
+        status = HAL_ERROR;
         break;
     }
   }
   else
   {
     /* Return error status */
-    status =  HAL_ERROR;
+    status = HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
   return status;
 }
 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -6300,7 +6494,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
   * @param  htim TIM Base handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -6310,7 +6504,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
   * @param  htim TIM Output Compare handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -6320,7 +6514,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
   * @param  htim TIM handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -6330,7 +6524,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
   * @param  htim TIM IC handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -6340,7 +6534,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
   * @param  htim TIM OPM handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -6350,7 +6544,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
   * @param  htim TIM Encoder Interface handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -6360,7 +6554,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
   * @param  htim TIM handle
   * @retval Active channel
   */
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim)
 {
   return htim->Channel;
 }
@@ -6378,7 +6572,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
   *            @arg TIM_CHANNEL_6: TIM Channel 6
   * @retval TIM Channel state
   */
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel)
 {
   HAL_TIM_ChannelStateTypeDef channel_state;
 
@@ -6395,7 +6589,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  ui
   * @param  htim TIM handle
   * @retval DMA burst state
   */
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim)
 {
   /* Check the parameters */
   assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@@ -6738,7 +6932,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
   * @param  Structure TIM Base configuration structure
   * @retval None
   */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
 {
   uint32_t tmpcr1;
   tmpcr1 = TIMx->CR1;
@@ -6778,6 +6972,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
   /* Generate an update event to reload the Prescaler
      and the repetition counter (only for advanced timer) value immediately */
   TIMx->EGR = TIM_EGR_UG;
+
+  /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
+  if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
+  {
+    /* Clear the update flag */
+    CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
+  }
 }
 
 /**
@@ -6786,17 +6987,18 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
   * @param  OC_Config The output configuration structure
   * @retval None
   */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
   /* Disable the Channel 1: Reset the CC1E Bit */
   TIMx->CCER &= ~TIM_CCER_CC1E;
 
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
 
@@ -6861,17 +7063,18 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
   * @param  OC_Config The output configuration structure
   * @retval None
   */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
   /* Disable the Channel 2: Reset the CC2E Bit */
   TIMx->CCER &= ~TIM_CCER_CC2E;
 
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
 
@@ -6900,7 +7103,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
     tmpccer |= (OC_Config->OCNPolarity << 4U);
     /* Reset the Output N State */
     tmpccer &= ~TIM_CCER_CC2NE;
-
   }
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
@@ -6937,17 +7139,18 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
   * @param  OC_Config The output configuration structure
   * @retval None
   */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
   /* Disable the Channel 3: Reset the CC2E Bit */
   TIMx->CCER &= ~TIM_CCER_CC3E;
 
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
 
@@ -7011,17 +7214,18 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
   * @param  OC_Config The output configuration structure
   * @retval None
   */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
+static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
   /* Disable the Channel 4: Reset the CC4E Bit */
   TIMx->CCER &= ~TIM_CCER_CC4E;
 
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
 
@@ -7072,17 +7276,18 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
   * @retval None
   */
 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
-                              TIM_OC_InitTypeDef *OC_Config)
+                              const TIM_OC_InitTypeDef *OC_Config)
 {
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
   /* Disable the output: Reset the CCxE Bit */
   TIMx->CCER &= ~TIM_CCER_CC5E;
 
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
   /* Get the TIMx CCMR1 register value */
@@ -7125,17 +7330,18 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
   * @retval None
   */
 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
-                              TIM_OC_InitTypeDef *OC_Config)
+                              const TIM_OC_InitTypeDef *OC_Config)
 {
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
   /* Disable the output: Reset the CCxE Bit */
   TIMx->CCER &= ~TIM_CCER_CC6E;
 
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
   /* Get the TIMx CCMR1 register value */
@@ -7179,8 +7385,9 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
   * @retval None
   */
 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
-                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)
+                                                  const TIM_SlaveConfigTypeDef *sSlaveConfig)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
   uint32_t tmpccmr1;
   uint32_t tmpccer;
@@ -7287,16 +7494,18 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
     case TIM_TS_ITR11:
     case TIM_TS_ITR12:
     case TIM_TS_ITR13:
-      {
-        /* Check the parameter */
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-        break;
-      }
+    {
+      /* Check the parameter */
+      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+      break;
+    }
 
     default:
+      status = HAL_ERROR;
       break;
   }
-  return HAL_OK;
+
+  return status;
 }
 
 /**
@@ -7326,9 +7535,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
   uint32_t tmpccer;
 
   /* Disable the Channel 1: Reset the CC1E Bit */
+  tmpccer = TIMx->CCER;
   TIMx->CCER &= ~TIM_CCER_CC1E;
   tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
 
   /* Select the Input */
   if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
@@ -7416,9 +7625,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   uint32_t tmpccer;
 
   /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
   TIMx->CCER &= ~TIM_CCER_CC2E;
   tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
 
   /* Select the Input */
   tmpccmr1 &= ~TIM_CCMR1_CC2S;
@@ -7455,9 +7664,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
   uint32_t tmpccer;
 
   /* Disable the Channel 2: Reset the CC2E Bit */
+  tmpccer = TIMx->CCER;
   TIMx->CCER &= ~TIM_CCER_CC2E;
   tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
 
   /* Set the filter */
   tmpccmr1 &= ~TIM_CCMR1_IC2F;
@@ -7499,9 +7708,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   uint32_t tmpccer;
 
   /* Disable the Channel 3: Reset the CC3E Bit */
+  tmpccer = TIMx->CCER;
   TIMx->CCER &= ~TIM_CCER_CC3E;
   tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
 
   /* Select the Input */
   tmpccmr2 &= ~TIM_CCMR2_CC3S;
@@ -7547,9 +7756,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   uint32_t tmpccer;
 
   /* Disable the Channel 4: Reset the CC4E Bit */
+  tmpccer = TIMx->CCER;
   TIMx->CCER &= ~TIM_CCER_CC4E;
   tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
 
   /* Select the Input */
   tmpccmr2 &= ~TIM_CCMR2_CC4S;
@@ -7577,10 +7786,6 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   *            @arg TIM_TS_ITR1: Internal Trigger 1
   *            @arg TIM_TS_ITR2: Internal Trigger 2
   *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
   *            @arg TIM_TS_ITR4: Internal Trigger 4  (*)
   *            @arg TIM_TS_ITR5: Internal Trigger 5
   *            @arg TIM_TS_ITR6: Internal Trigger 6
@@ -7591,6 +7796,10 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
   *            @arg TIM_TS_ITR11: Internal Trigger 11 (*)
   *            @arg TIM_TS_ITR12: Internal Trigger 12 (*)
   *            @arg TIM_TS_ITR13: Internal Trigger 13 (*)
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
   *
   *       (*)  Value not defined in all devices.
   *
@@ -7685,20 +7894,20 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat
 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
 {
   /* Reset the TIM callback to the legacy weak callbacks */
-  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */
-  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */
-  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */
-  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */
-  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */
-  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */
-  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */
-  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */
-  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
-  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */
-  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */
-  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */
-  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */
-  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;                  /* Legacy weak Break2Callback                    */
+  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;
+  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;
+  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;
+  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;
+  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;
+  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;
+  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;
+  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;
+  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback;
+  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;
+  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;
+  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;
+  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;
+  htim->Break2Callback                    = HAL_TIMEx_Break2Callback;
 }
 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
 
@@ -7714,4 +7923,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h
index 2e93e31a61..8f49df2f07 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -65,8 +64,10 @@ typedef struct
                                     This means in PWM mode that (N+1) corresponds to:
                                         - the number of PWM periods in edge-aligned mode
                                         - the number of half PWM period in center-aligned mode
-                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                     Max_Data = 0xFF.
+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                     Max_Data = 0xFFFF. */
 
   uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.
                                    This parameter can be a value of @ref TIM_AutoReloadPreload */
@@ -218,7 +219,8 @@ typedef struct
   uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
                                       This parameter can be a value of @ref TIM_ClearInput_Polarity */
   uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
-                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
+                                      This parameter must be 0: When OCRef clear feature is used with ETR source,
+                                      ETR prescaler must be off */
   uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
                                       This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 } TIM_ClearInputConfigTypeDef;
@@ -268,28 +270,36 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t OffStateRunMode;      /*!< TIM off state in run mode
-                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode
-                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-  uint32_t LockLevel;            /*!< TIM Lock level
-                                      This parameter can be a value of @ref TIM_Lock_level */
-  uint32_t DeadTime;             /*!< TIM dead Time
-                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-  uint32_t BreakState;           /*!< TIM Break State
-                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-  uint32_t BreakPolarity;        /*!< TIM Break input polarity
-                                      This parameter can be a value of @ref TIM_Break_Polarity */
-  uint32_t BreakFilter;          /*!< Specifies the break input filter.
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t Break2State;          /*!< TIM Break2 State
-                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
-  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity
-                                      This parameter can be a value of @ref TIM_Break2_Polarity */
-  uint32_t Break2Filter;         /*!< TIM break2 input filter.
-                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state
-                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint32_t LockLevel;            /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
+
+  uint32_t DeadTime;             /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+
+  uint32_t BreakState;           /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint32_t BreakPolarity;        /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint32_t BreakFilter;          /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+#if defined(TIM_BDTR_BKBID)
+  uint32_t BreakAFMode;          /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
+
+#endif /* TIM_BDTR_BKBID */
+  uint32_t Break2State;          /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
+
+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
+
+  uint32_t Break2Filter;         /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
+
+#if defined(TIM_BDTR_BKBID)
+  uint32_t Break2AFMode;         /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
+
+#endif /* TIM_BDTR_BKBID */
+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+
 } TIM_BreakDeadTimeConfigTypeDef;
 
 /**
@@ -396,29 +406,28 @@ typedef struct
   */
 typedef enum
 {
-  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */
-  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */
-  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */
-  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */
-  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */
-  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */
-  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */
-  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */
-  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */
-  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */
-  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */
-  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */
-  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
-  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */
+  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                               */
+  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                             */
+  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                 */
+  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                               */
+  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                 */
+  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                               */
+  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                                */
+  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                              */
+  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                          */
+  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                        */
+  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                            */
+  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                          */
+  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
+  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                      */
   , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */
   , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */
   , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */
   , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */
-
   , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */
   , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */
   , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */
-  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */
+  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID                         */
   , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */
   , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */
   , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */
@@ -660,10 +669,8 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
   * @{
   */
-#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */
+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
 #define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
 /**
   * @}
@@ -737,6 +744,15 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @}
   */
 
+/** @defgroup TIM_CC_DMA_Request CCx DMA request selection
+  * @{
+  */
+#define TIM_CCDMAREQUEST_CC                 0x00000000U                         /*!< CCx DMA request sent when capture or compare match event occurs */
+#define TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS                        /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
 /** @defgroup TIM_Flag_definition TIM Flag Definition
   * @{
   */
@@ -777,16 +793,16 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 /** @defgroup TIM_Clock_Source TIM Clock Source
   * @{
   */
-#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
 #define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */
+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */
+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
 #define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */
 #define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */
 #define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */
 #define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */
-#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
-#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */
-#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */
-#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */
 #define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */
 #define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */
 #define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */
@@ -884,6 +900,17 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 /**
   * @}
   */
+#if  defined(TIM_BDTR_BKBID)
+
+/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
+  * @{
+  */
+#define TIM_BREAK_AFMODE_INPUT             0x00000000U                          /*!< Break input BRK in input mode */
+#define TIM_BREAK_AFMODE_BIDIRECTIONAL     TIM_BDTR_BKBID                       /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+#endif /*TIM_BDTR_BKBID */
 
 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
   * @{
@@ -902,24 +929,34 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 /**
   * @}
   */
+#if defined(TIM_BDTR_BKBID)
+
+/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
+  * @{
+  */
+#define TIM_BREAK2_AFMODE_INPUT            0x00000000U                          /*!< Break2 input BRK2 in input mode */
+#define TIM_BREAK2_AFMODE_BIDIRECTIONAL    TIM_BDTR_BK2BID                      /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+#endif /* TIM_BDTR_BKBID */
 
 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
   * @{
   */
 #define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event
-                                                                                    (if none of the break inputs BRK and BRK2 is active) */
+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
 /**
   * @}
   */
 
-/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
+/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
   * @{
   */
-#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
-#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */
-#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */
-#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */
+#define TIM_GROUPCH5_NONE                  0x00000000U                          /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /*!< OC1REFC is the logical AND of OC1REFC and OC5REF    */
+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /*!< OC2REFC is the logical AND of OC2REFC and OC5REF    */
+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /*!< OC3REFC is the logical AND of OC3REFC and OC5REF    */
 /**
   * @}
   */
@@ -999,8 +1036,8 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 #define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */
 #define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */
 #define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */
-#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
-#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
+#define TIM_OCMODE_ASYMMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */
+#define TIM_OCMODE_ASYMMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */
 /**
   * @}
   */
@@ -1012,10 +1049,6 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 #define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */
 #define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */
 #define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */
-#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
-#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
-#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
-#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
 #define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */
 #define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */
 #define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
@@ -1026,6 +1059,10 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 #define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
 #define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
 #define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */
+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */
+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */
+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */
 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
 /**
   * @}
@@ -1218,7 +1255,8 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @brief  Disable the TIM main Output.
   * @param  __HANDLE__ TIM handle
   * @retval None
-  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
+  *       disabled
   */
 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
   do { \
@@ -1385,7 +1423,8 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 
 /**
   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
-  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
   * @param  __HANDLE__ TIM handle.
   * @retval None
 mode.
@@ -1412,8 +1451,8 @@ mode.
   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
   * @param  __HANDLE__ TIM handle.
   * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
-  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
-mode.
+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
+  *       or Encoder mode.
   */
 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
 
@@ -1427,7 +1466,8 @@ mode.
 
 /**
   * @brief  Set the TIM Counter Register value on runtime.
-  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
+  *      case of 32 bits counter TIM instance.
   *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
   * @param  __HANDLE__ TIM handle.
   * @param  __COUNTER__ specifies the Counter register new value.
@@ -1489,7 +1529,8 @@ mode.
 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
 
 /**
-  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
+  *         function.
   * @param  __HANDLE__ TIM handle.
   * @param  __CHANNEL__ TIM Channels to be configured.
   *          This parameter can be one of the following values:
@@ -1711,6 +1752,17 @@ mode.
     TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
   }while(0)
 
+/** @brief  Select the Capture/compare DMA request source.
+  * @param  __HANDLE__ specifies the TIM Handle.
+  * @param  __CCDMA__ specifies Capture/compare DMA request source
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event
+  *            @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event
+  * @retval None
+  */
+#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__)    \
+  MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__))
+
 /**
   * @}
   */
@@ -1771,7 +1823,7 @@ mode.
                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
 
 #define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
-                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+                                            ((__MODE__) == TIM_UIFREMAP_ENABLE))
 
 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
@@ -1811,6 +1863,10 @@ mode.
                                             ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
                                             ((__PRESCALER__) == TIM_ICPSC_DIV8))
 
+#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
+                                                       ((__CHANNEL__) != (TIM_CHANNEL_5)) && \
+                                                       ((__CHANNEL__) != (TIM_CHANNEL_6)))
+
 #define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \
                                             ((__MODE__) == TIM_OPMODE_REPETITIVE))
 
@@ -1831,20 +1887,24 @@ mode.
 #define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \
                                             ((__CHANNEL__) == TIM_CHANNEL_2))
 
+#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
+                                               (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) :        \
+                                               ((__PERIOD__) > 0U))
+
 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
                                                     ((__CHANNEL__) == TIM_CHANNEL_2) || \
                                                     ((__CHANNEL__) == TIM_CHANNEL_3))
 
 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
                                        ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \
                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \
                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \
                                        ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \
-                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \
+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
 
 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \
                                             ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
@@ -1882,18 +1942,29 @@ mode.
 
 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
 
-
 #define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \
                                             ((__STATE__) == TIM_BREAK_DISABLE))
 
 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
                                              ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
+#if  defined(TIM_BDTR_BKBID)
+
+#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
+                                         ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
+
+#endif /* TIM_BDTR_BKBID */
 
 #define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \
                                             ((__STATE__) == TIM_BREAK2_DISABLE))
 
 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
                                               ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
+#if  defined(TIM_BDTR_BKBID)
+
+#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
+                                          ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+
+#endif /* TIM_BDTR_BKBID */
 
 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
                                                   ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
@@ -1941,8 +2012,8 @@ mode.
                                    ((__MODE__) == TIM_OCMODE_PWM2)               || \
                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \
                                    ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \
-                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \
-                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
+                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1)    || \
+                                   ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
 
 #define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \
                                    ((__MODE__) == TIM_OCMODE_ACTIVE)             || \
@@ -1953,31 +2024,31 @@ mode.
                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
                                    ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))
 
-#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR3) || \
+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR1)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR2)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR3)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR4)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR5)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR6)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR7)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR8)    || \
+                                                 ((__SELECTION__) == TIM_TS_ITR12)   || \
+                                                 ((__SELECTION__) == TIM_TS_ITR13)   || \
                                                  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
-                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \
-                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \
-                                                 ((__SELECTION__) == TIM_TS_ETRF) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR4) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR5) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR6) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR7) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR13))
+                                                 ((__SELECTION__) == TIM_TS_TI1FP1)  || \
+                                                 ((__SELECTION__) == TIM_TS_TI2FP2)  || \
+                                                 ((__SELECTION__) == TIM_TS_ETRF))
 
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR1) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR2) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR3) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR4) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR5) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR6) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR7) || \
-                                                               ((__SELECTION__) == TIM_TS_ITR8) || \
+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR1)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR2)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR3)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR4)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR5)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR6)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR7)  || \
+                                                               ((__SELECTION__) == TIM_TS_ITR8)  || \
                                                                ((__SELECTION__) == TIM_TS_ITR12) || \
                                                                ((__SELECTION__) == TIM_TS_ITR13) || \
                                                                ((__SELECTION__) == TIM_TS_NONE))
@@ -2072,13 +2143,19 @@ mode.
    ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
 
 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
-  (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[4]  = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelState[5]  = (__CHANNEL_STATE__);  \
- } while(0)
+                                                                       (__HANDLE__)->ChannelState[0]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[1]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[2]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[3]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[4]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                       (__HANDLE__)->ChannelState[5]  = \
+                                                                       (__CHANNEL_STATE__);  \
+                                                                     } while(0)
 
 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
   (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
@@ -2093,11 +2170,15 @@ mode.
    ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
 
 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \
-  (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__);  \
-  (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__);  \
- } while(0)
+                                                                         (__HANDLE__)->ChannelNState[0] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[1] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[2] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                         (__HANDLE__)->ChannelNState[3] = \
+                                                                         (__CHANNEL_STATE__);  \
+                                                                       } while(0)
 
 /**
   * @}
@@ -2128,7 +2209,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
 /**
   * @}
@@ -2150,7 +2231,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                       uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
@@ -2172,7 +2254,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                        uint16_t Length);
 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
@@ -2224,7 +2307,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
   * @{
   */
 /* Timer Encoder functions ****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
@@ -2257,31 +2340,36 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
   * @{
   */
 /* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig,
+                                            uint32_t Channel);
+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig,
+                                           uint32_t Channel);
 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
                                                  uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
+                                           const TIM_ClearInputConfigTypeDef *sClearInputConfig,
                                            uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig);
 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
+                                              uint32_t BurstRequestSrc, const uint32_t  *BurstBuffer,
+                                              uint32_t  BurstLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
-                                                   uint32_t DataLength);
+                                                   uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
+                                                   uint32_t BurstLength,  uint32_t DataLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
-                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,
-                                                  uint32_t  DataLength);
+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,
+                                                  uint32_t  BurstLength, uint32_t  DataLength);
 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
+uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
   */
@@ -2318,17 +2406,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
   * @{
   */
 /* Peripheral State functions  ************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim);
 
 /* Peripheral Channel state functions  ************************************************/
-HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);
-HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
+HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim,  uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim);
 /**
   * @}
   */
@@ -2342,9 +2430,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
 /** @defgroup TIM_Private_Functions TIM Private Functions
   * @{
   */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure);
 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config);
 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                        uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
 
@@ -2376,5 +2464,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
 #endif
 
 #endif /* STM32H7xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c
index d929a23e32..21ef06b1e8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c
@@ -11,6 +11,17 @@
   *           + Time Master and Slave synchronization configuration
   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
   *           + Timer remapping capabilities configuration
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                       ##### TIMER Extended features #####
@@ -55,24 +66,16 @@
                the commutation event).
 
      (#) Activate the TIM peripheral using one of the start functions:
-           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
-           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
+           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
+                HAL_TIMEx_OCN_Start_IT()
+           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
+                HAL_TIMEx_PWMN_Start_IT()
            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
-           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
+           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
+                HAL_TIMEx_HallSensor_Start_IT().
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -91,6 +94,19 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+#if defined(TIM_BDTR_BKBID)
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants
+  * @{
+  */
+/* Timeout for break input rearm */
+#define TIM_BREAKINPUT_REARM_TIMEOUT    5UL /* 5 milliseconds */
+/**
+  * @}
+  */
+/* End of private constants --------------------------------------------------*/
+
+#endif /* TIM_BDTR_BKBID */
 /* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -133,7 +149,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
   * @param  sConfig TIM Hall Sensor configuration structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig)
 {
   TIM_OC_InitTypeDef OC_Config;
 
@@ -149,6 +165,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen
   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
   assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
+  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
 
@@ -336,7 +353,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
   TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
 
   /* Enable the Input Capture channel 1
-  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
 
   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -368,7 +386,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
 
   /* Disable the Input Capture channels 1, 2 and 3
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
 
   /* Disable the Peripheral */
@@ -419,7 +438,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
 
   /* Enable the Input Capture channel 1
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
 
   /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
@@ -451,7 +471,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
 
   /* Disable the Input Capture channel 1
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
 
   /* Disable the capture compare Interrupts event */
@@ -495,7 +516,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
   else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
            && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -511,7 +532,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
   }
 
   /* Enable the Input Capture channel 1
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
 
   /* Set the DMA Input Capture 1 Callbacks */
@@ -558,7 +580,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
 
   /* Disable the Input Capture channel 1
-    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
+  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
+  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
 
 
@@ -698,6 +721,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
@@ -737,34 +761,38 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
 
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  if (status == HAL_OK)
   {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -780,7 +808,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpccer;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -808,30 +838,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  if (status == HAL_OK)
   {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
   }
 
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM complementary channel state */
-  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -847,8 +881,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
   * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
@@ -861,7 +897,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
   }
   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -887,7 +923,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -907,7 +944,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -927,7 +965,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -938,31 +977,35 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  if (status == HAL_OK)
   {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    /* Enable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -978,6 +1021,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
   */
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -1008,23 +1053,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the Capture compare channel N */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+  if (status == HAL_OK)
+  {
+    /* Disable the Capture compare channel N */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
 
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
 
-  /* Set the TIM complementary channel state */
-  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1046,17 +1095,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
     (+) Stop the Complementary PWM and disable interrupts.
     (+) Start the Complementary PWM and enable DMA transfers.
     (+) Stop the Complementary PWM and disable DMA transfers.
-    (+) Start the Complementary Input Capture measurement.
-    (+) Stop the Complementary Input Capture.
-    (+) Start the Complementary Input Capture and enable interrupts.
-    (+) Stop the Complementary Input Capture and disable interrupts.
-    (+) Start the Complementary Input Capture and enable DMA transfers.
-    (+) Stop the Complementary Input Capture and disable DMA transfers.
-    (+) Start the Complementary One Pulse generation.
-    (+) Stop the Complementary One Pulse.
-    (+) Start the Complementary One Pulse and enable interrupts.
-    (+) Stop the Complementary One Pulse and disable interrupts.
-
 @endverbatim
   * @{
   */
@@ -1155,6 +1193,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
@@ -1193,34 +1232,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the TIM Break interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
-
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  if (status == HAL_OK)
   {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    /* Enable the TIM Break interrupt */
+    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
+
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1236,6 +1279,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpccer;
 
   /* Check the parameters */
@@ -1265,30 +1309,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
-  /* Disable the TIM Break interrupt (only if no more channel is active) */
-  tmpccer = htim->Instance->CCER;
-  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
+  if (status == HAL_OK)
   {
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    /* Disable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+
+    /* Disable the TIM Break interrupt (only if no more channel is active) */
+    tmpccer = htim->Instance->CCER;
+    if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
+    {
+      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
+    }
+
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
+
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
+
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
   }
 
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Set the TIM complementary channel state */
-  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1304,8 +1352,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
   * @param  Length The length of data to be transferred from memory to TIM peripheral
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmpsmcr;
 
   /* Check the parameters */
@@ -1318,7 +1368,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
   }
   else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
   {
-    if ((pData == NULL) && (Length > 0U))
+    if ((pData == NULL) || (Length == 0U))
     {
       return HAL_ERROR;
     }
@@ -1344,7 +1394,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1364,7 +1415,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1384,7 +1436,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
 
       /* Enable the DMA stream */
-      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
+      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
+                           Length) != HAL_OK)
       {
         /* Return error status */
         return HAL_ERROR;
@@ -1395,31 +1448,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Enable the complementary PWM output  */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
-
-  /* Enable the Main Output */
-  __HAL_TIM_MOE_ENABLE(htim);
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+  if (status == HAL_OK)
   {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+    /* Enable the complementary PWM output  */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
+
+    /* Enable the Main Output */
+    __HAL_TIM_MOE_ENABLE(htim);
+
+    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
+    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+    {
+      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+      {
+        __HAL_TIM_ENABLE(htim);
+      }
+    }
+    else
     {
       __HAL_TIM_ENABLE(htim);
     }
   }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
-  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1435,6 +1492,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
   */
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
 {
+  HAL_StatusTypeDef status = HAL_OK;
+
   /* Check the parameters */
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
 
@@ -1465,23 +1524,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
     }
 
     default:
+      status = HAL_ERROR;
       break;
   }
 
-  /* Disable the complementary PWM output */
-  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
+  if (status == HAL_OK)
+  {
+    /* Disable the complementary PWM output */
+    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
 
-  /* Disable the Main Output */
-  __HAL_TIM_MOE_DISABLE(htim);
+    /* Disable the Main Output */
+    __HAL_TIM_MOE_DISABLE(htim);
 
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
+    /* Disable the Peripheral */
+    __HAL_TIM_DISABLE(htim);
 
-  /* Set the TIM complementary channel state */
-  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+    /* Set the TIM complementary channel state */
+    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
+  }
 
   /* Return function status */
-  return HAL_OK;
+  return status;
 }
 
 /**
@@ -1509,8 +1572,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
 /**
   * @brief  Starts the TIM One Pulse signal generation on the complementary
   *         output.
-  * @note OutputChannel must match the pulse output channel chosen when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel pulse output channel to enable
   *          This parameter can be one of the following values:
@@ -1530,7 +1593,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
   /* Check the TIM channels state */
-   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
@@ -1558,8 +1621,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou
 /**
   * @brief  Stops the TIM One Pulse signal generation on the complementary
   *         output.
-  * @note OutputChannel must match the pulse output channel chosen when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel pulse output channel to disable
   *          This parameter can be one of the following values:
@@ -1597,8 +1660,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out
 /**
   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
   *         complementary channel.
-  * @note OutputChannel must match the pulse output channel chosen when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel pulse output channel to enable
   *          This parameter can be one of the following values:
@@ -1618,7 +1681,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
 
   /* Check the TIM channels state */
-   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
       || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
       || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
       || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
@@ -1652,8 +1715,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t
 /**
   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
   *         complementary channel.
-  * @note OutputChannel must match the pulse output channel chosen when calling 
-  *       @ref HAL_TIM_OnePulse_ConfigChannel(). 
+  * @note OutputChannel must match the pulse output channel chosen when calling
+  *       @ref HAL_TIM_OnePulse_ConfigChannel().
   * @param  htim TIM One Pulse handle
   * @param  OutputChannel pulse output channel to disable
   *          This parameter can be one of the following values:
@@ -1738,6 +1801,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
   *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
   *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
   *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
   * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1794,9 +1860,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
-  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
   *            @arg TIM_TS_NONE: No trigger is needed
+  *
+  *         (*)  Value not defined in all devices.
+  *
   * @param  CommutationSource the Commutation Event source
   *          This parameter can be one of the following values:
   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
@@ -1854,8 +1923,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
-  *            @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
-  *            @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
+  *            @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
+  *            @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
   *            @arg TIM_TS_NONE: No trigger is needed
   *
   *         (*)  Value not defined in all devices.
@@ -1917,7 +1986,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig)
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig)
 {
   uint32_t tmpcr2;
   uint32_t tmpsmcr;
@@ -1990,7 +2059,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
-                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
 {
   /* Keep this variable initialized to 0 as it is used to configure BDTR register */
   uint32_t tmpbdtr = 0U;
@@ -2005,6 +2074,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
+#if defined(TIM_BDTR_BKBID)
+  assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
+#endif /* TIM_BDTR_BKBID */
 
   /* Check input state */
   __HAL_LOCK(htim);
@@ -2021,6 +2093,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+#if defined(TIM_BDTR_BKBID)
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
+#endif /* TIM_BDTR_BKBID */
 
   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
   {
@@ -2028,11 +2103,17 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
+#if defined(TIM_BDTR_BKBID)
+    assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
+#endif /* TIM_BDTR_BKBID */
 
     /* Set the BREAK2 input related BDTR bits */
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
+#if defined(TIM_BDTR_BKBID)
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
+#endif /* TIM_BDTR_BKBID */
   }
 
   /* Set TIMx_BDTR */
@@ -2056,9 +2137,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
   */
 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
                                              uint32_t BreakInput,
-                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
-
+                                             const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
 {
+  HAL_StatusTypeDef status = HAL_OK;
   uint32_t tmporx;
   uint32_t bkin_enable_mask;
   uint32_t bkin_polarity_mask;
@@ -2107,7 +2188,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
     case TIM_BREAKINPUTSOURCE_DFSDM1:
     {
       bkin_enable_mask = TIM1_AF1_BKDF1BK0E;
-      bkin_enable_bitpos = 8U;
+      bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos;
       bkin_polarity_mask = 0U;
       bkin_polarity_bitpos = 0U;
       break;
@@ -2136,10 +2217,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
 
       /* Set the break input polarity */
       if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
-        {
-          tmporx &= ~bkin_polarity_mask;
-          tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
-        }
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
 
       /* Set TIMx_AF1 */
       htim->Instance->AF1 = tmporx;
@@ -2156,22 +2237,23 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
 
       /* Set the break input polarity */
       if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
-        {
-          tmporx &= ~bkin_polarity_mask;
-          tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
-        }
+      {
+        tmporx &= ~bkin_polarity_mask;
+        tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+      }
 
       /* Set TIMx_AF2 */
       htim->Instance->AF2 = tmporx;
       break;
     }
     default:
+      status = HAL_ERROR;
       break;
   }
 
   __HAL_UNLOCK(htim);
 
-  return HAL_OK;
+  return status;
 }
 #endif /*TIM_BREAK_INPUT_SUPPORT */
 
@@ -2283,49 +2365,49 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
   *            @arg TIM_TIM5_TI1_CAN_RTP:             TIM5 TI1 is connected to CAN RTP
   *
   *         For TIM8, the parameter is one of the following values:
-  *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
-  *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
+  *            @arg TIM_TIM8_TI1_GPIO:                TIM8 TI1 is connected to GPIO
+  *            @arg TIM_TIM8_TI1_COMP2:               TIM8 TI1 is connected to COMP2 output
   *
   *         For TIM12, the parameter can have the following values: (*)
-  *            @arg TIM_TIM12_TI1_GPIO:              TIM12 TI1 is connected to GPIO
-  *            @arg TIM_TIM12_TI1_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS
+  *            @arg TIM_TIM12_TI1_GPIO:               TIM12 TI1 is connected to GPIO
+  *            @arg TIM_TIM12_TI1_SPDIF_FS:           TIM12 TI1 is connected to SPDIF FS
   *
   *         For TIM15, the parameter is one of the following values:
-  *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
-  *            @arg TIM_TIM15_TI1_TIM2:              TIM15 TI1 is connected to TIM2 CH1
-  *            @arg TIM_TIM15_TI1_TIM3:              TIM15 TI1 is connected to TIM3 CH1
-  *            @arg TIM_TIM15_TI1_TIM4:              TIM15 TI1 is connected to TIM4 CH1
-  *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
-  *            @arg TIM_TIM15_TI1_CSI:               TIM15 TI1 is connected to CSI
-  *            @arg TIM_TIM15_TI1_MCO2:              TIM15 TI1 is connected to MCO2
-  *            @arg TIM_TIM15_TI2_GPIO:              TIM15 TI2 is connected to GPIO
-  *            @arg TIM_TIM15_TI2_TIM2:              TIM15 TI2 is connected to TIM2 CH2
-  *            @arg TIM_TIM15_TI2_TIM3:              TIM15 TI2 is connected to TIM3 CH2
-  *            @arg TIM_TIM15_TI2_TIM4:              TIM15 TI2 is connected to TIM4 CH2
+  *            @arg TIM_TIM15_TI1_GPIO:               TIM15 TI1 is connected to GPIO
+  *            @arg TIM_TIM15_TI1_TIM2_CH1:           TIM15 TI1 is connected to TIM2 CH1
+  *            @arg TIM_TIM15_TI1_TIM3_CH1:           TIM15 TI1 is connected to TIM3 CH1
+  *            @arg TIM_TIM15_TI1_TIM4_CH1:           TIM15 TI1 is connected to TIM4 CH1
+  *            @arg TIM_TIM15_TI1_RCC_LSE:            TIM15 TI1 is connected to LSE
+  *            @arg TIM_TIM15_TI1_RCC_CSI:            TIM15 TI1 is connected to CSI
+  *            @arg TIM_TIM15_TI1_RCC_MCO2:           TIM15 TI1 is connected to MCO2
+  *            @arg TIM_TIM15_TI2_GPIO:               TIM15 TI2 is connected to GPIO
+  *            @arg TIM_TIM15_TI2_TIM2_CH2:           TIM15 TI2 is connected to TIM2 CH2
+  *            @arg TIM_TIM15_TI2_TIM3_CH2:           TIM15 TI2 is connected to TIM3 CH2
+  *            @arg TIM_TIM15_TI2_TIM4_CH2:           TIM15 TI2 is connected to TIM4 CH2
   *
   *         For TIM16, the parameter can have the following values:
-  *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
-  *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
-  *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
-  *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
+  *            @arg TIM_TIM16_TI1_GPIO:               TIM16 TI1 is connected to GPIO
+  *            @arg TIM_TIM16_TI1_RCC_LSI:            TIM16 TI1 is connected to LSI
+  *            @arg TIM_TIM16_TI1_RCC_LSE:            TIM16 TI1 is connected to LSE
+  *            @arg TIM_TIM16_TI1_WKUP_IT:            TIM16 TI1 is connected to RTC wakeup interrupt
   *
   *         For TIM17, the parameter can have the following values:
-  *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
-  *            @arg TIM_TIM17_TI1_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)
-  *            @arg TIM_TIM17_TI1_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz
-  *            @arg TIM_TIM17_TI1_MCO1:              TIM17 TI1 is connected to MCO1
+  *            @arg TIM_TIM17_TI1_GPIO:               TIM17 TI1 is connected to GPIO
+  *            @arg TIM_TIM17_TI1_SPDIF_FS:           TIM17 TI1 is connected to SPDIF FS (*)
+  *            @arg TIM_TIM17_TI1_RCC_HSE1MHZ:        TIM17 TI1 is connected to HSE 1MHz
+  *            @arg TIM_TIM17_TI1_RCC_MCO1:           TIM17 TI1 is connected to MCO1
   *
   *         For TIM23, the parameter can have the following values: (*)
-  *            @arg TIM_TIM23_TI4_GPIO               TIM23_TI4 is connected to GPIO
-  *            @arg TIM_TIM23_TI4_COMP1              TIM23_TI4 is connected to COMP1 output
-  *            @arg TIM_TIM23_TI4_COMP2              TIM23_TI4 is connected to COMP2 output
-  *            @arg TIM_TIM23_TI4_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output
+  *            @arg TIM_TIM23_TI4_GPIO                TIM23_TI4 is connected to GPIO
+  *            @arg TIM_TIM23_TI4_COMP1               TIM23_TI4 is connected to COMP1 output
+  *            @arg TIM_TIM23_TI4_COMP2               TIM23_TI4 is connected to COMP2 output
+  *            @arg TIM_TIM23_TI4_COMP1_COMP2         TIM23_TI4 is connected to COMP2 output
   *
   *         For TIM24, the parameter can have the following values: (*)
-  *            @arg TIM_TIM24_TI1_GPIO               TIM24_TI1 is connected to GPIO
-  *            @arg TIM_TIM24_TI1_CAN_TMP            TIM24_TI1 is connected to CAN_TMP
-  *            @arg TIM_TIM24_TI1_CAN_RTP            TIM24_TI1 is connected to CAN_RTP
-  *            @arg TIM_TIM24_TI1_CAN_SOC            TIM24_TI1 is connected to CAN_SOC
+  *            @arg TIM_TIM24_TI1_GPIO                TIM24_TI1 is connected to GPIO
+  *            @arg TIM_TIM24_TI1_CAN_TMP             TIM24_TI1 is connected to CAN_TMP
+  *            @arg TIM_TIM24_TI1_CAN_RTP             TIM24_TI1 is connected to CAN_RTP
+  *            @arg TIM_TIM24_TI1_CAN_SOC             TIM24_TI1 is connected to CAN_SOC
   *
   *         (*)  Value not defined in all devices. \n
   * @retval HAL status
@@ -2399,6 +2481,139 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
 
   return HAL_OK;
 }
+#if defined(TIM_BDTR_BKBID)
+
+/**
+  * @brief  Disarm the designated break input (when it operates in bidirectional mode).
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to disarm
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpbdtr;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Check initial conditions */
+      tmpbdtr = READ_REG(htim->Instance->BDTR);
+      if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) &&
+          (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+      {
+        /* Break input BRK is disarmed */
+        SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM);
+      }
+      break;
+    }
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Check initial conditions */
+      tmpbdtr = READ_REG(htim->Instance->BDTR);
+      if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) &&
+          (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U))
+      {
+        /* Break input BRK is disarmed */
+        SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM);
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Arm the designated break input (when it operates in bidirectional mode).
+  * @param  htim TIM handle.
+  * @param  BreakInput Break input to arm
+  *          This parameter can be one of the following values:
+  *            @arg TIM_BREAKINPUT_BRK: Timer break input
+  *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
+  * @note  Arming is possible at anytime, even if fault is present.
+  * @note  Break input is automatically armed as soon as MOE bit is set.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
+  assert_param(IS_TIM_BREAKINPUT(BreakInput));
+
+  switch (BreakInput)
+  {
+    case TIM_BREAKINPUT_BRK:
+    {
+      /* Check initial conditions */
+      if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID)
+      {
+        /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+        while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL)
+            {
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+      }
+      break;
+    }
+
+    case TIM_BREAKINPUT_BRK2:
+    {
+      /* Check initial conditions */
+      if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID)
+      {
+        /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */
+        /* Init tickstart for timeout management */
+        tickstart = HAL_GetTick();
+        while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+        {
+          if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT)
+          {
+            /* New check to avoid false timeout detection in case of preemption */
+            if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL)
+            {
+              return HAL_TIMEOUT;
+            }
+          }
+        }
+      }
+      break;
+    }
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+#endif /* TIM_BDTR_BKBID */
 
 /**
   * @}
@@ -2421,7 +2636,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan
   */
 
 /**
-  * @brief  Hall commutation changed callback in non-blocking mode
+  * @brief  Commutation callback in non-blocking mode
   * @param  htim TIM handle
   * @retval None
   */
@@ -2435,7 +2650,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
    */
 }
 /**
-  * @brief  Hall commutation changed half complete callback in non-blocking mode
+  * @brief  Commutation half complete callback in non-blocking mode
   * @param  htim TIM handle
   * @retval None
   */
@@ -2450,7 +2665,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
 }
 
 /**
-  * @brief  Hall Break detection callback in non-blocking mode
+  * @brief  Break detection callback in non-blocking mode
   * @param  htim TIM handle
   * @retval None
   */
@@ -2465,7 +2680,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
 }
 
 /**
-  * @brief  Hall Break2 detection callback in non blocking mode
+  * @brief  Break2 detection callback in non blocking mode
   * @param  htim: TIM handle
   * @retval None
   */
@@ -2502,7 +2717,7 @@ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
   * @param  htim TIM Hall Sensor handle
   * @retval HAL state
   */
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim)
 {
   return htim->State;
 }
@@ -2517,7 +2732,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
   *            @arg TIM_CHANNEL_3: TIM Channel 3
   * @retval TIM Complementary channel state
   */
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN)
 {
   HAL_TIM_ChannelStateTypeDef channel_state;
 
@@ -2537,7 +2752,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,
   */
 
 /* Private functions ---------------------------------------------------------*/
-/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
   * @{
   */
 
@@ -2616,15 +2831,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
       TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
     }
   }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
-    if (hdma->Init.Mode == DMA_NORMAL)
-    {
-      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-    }
-  }
   else
   {
     /* nothing to do */
@@ -2693,13 +2899,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
 {
   uint32_t tmp;
 
-  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+  tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
 
   /* Reset the CCxNE Bit */
   TIMx->CCER &=  ~tmp;
 
   /* Set or reset the CCxNE Bit */
-  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
 }
 /**
   * @}
@@ -2713,5 +2919,3 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.h
index 6d15c05e80..09438587d1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -73,8 +72,7 @@ typedef struct
   uint32_t Polarity;       /*!< Specifies the break input source polarity.
                                 This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
                                 Not relevant when analog watchdog output of the DFSDM1 used as break input source */
-}
-TIMEx_BreakInputConfigTypeDef;
+} TIMEx_BreakInputConfigTypeDef;
 
 #endif /* TIM_BREAK_INPUT_SUPPORT */
 /**
@@ -90,51 +88,51 @@ TIMEx_BreakInputConfigTypeDef;
 /** @defgroup TIMEx_Remap TIM Extended Remapping
   * @{
   */
-#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
-#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
-#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
-#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
-#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /*!< TIM1_ETR is connected to GPIO */
+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< TIM1_ETR is connected to COMP1 OUT */
+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< TIM1_ETR is connected to COMP2 OUT */
+#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /*!< TIM1_ETR is connected to ADC3 AWD3 */
 
-#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
-#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
-#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
-#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
-#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
-#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
-#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
-#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
-#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /*!< TIM8_ETR is connected to GPIO */
+#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /*!< TIM8_ETR is connected to COMP1 OUT */
+#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /*!< TIM8_ETR is connected to COMP2 OUT */
+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /*!< TIM8_ETR is connected to ADC3 AWD3 */
 
-#define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */
-#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */
-#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */
-#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */
-#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */
-#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */
+#define TIM_TIM2_ETR_GPIO        0x00000000U                             /*!< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to COMP1 OUT */
+#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /*!< TIM2_ETR is connected to COMP2 OUT */
+#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */
+#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /*!< TIM2_ETR is connected to SAI1 FS_A */
+#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */
 
-#define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */
-#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */
+#define TIM_TIM3_ETR_GPIO        0x00000000U          /*!< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /*!< TIM3_ETR is connected to COMP1 OUT */
 
-#define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
-#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
-#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
-#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
-#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
+#define TIM_TIM5_ETR_GPIO        0x00000000U          /*!< TIM5_ETR is connected to GPIO */
+#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /*!< TIM5_ETR is connected to SAI2 FS_A */
+#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /*!< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /*!< TIM5_ETR is connected to SAI4 FS_A */
+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /*!< TIM5_ETR is connected to SAI4 FS_B */
 
-#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
-#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
-#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
+#define TIM_TIM23_ETR_GPIO       0x00000000U          /*!< TIM23_ETR is connected to GPIO */
+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /*!< TIM23_ETR is connected to COMP1 OUT */
+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /*!< TIM23_ETR is connected to COMP2 OUT */
 
-#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
-#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
-#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
-#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
-#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /*!< TIM24_ETR is connected to GPIO */
+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /*!< TIM24_ETR is connected to SAI4 FS_A */
+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /*!< TIM24_ETR is connected to SAI4 FS_B */
+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /*!< TIM24_ETR is connected to SAI1 FS_A */
+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /*!< TIM24_ETR is connected to SAI1 FS_B */
 /**
   * @}
   */
@@ -143,8 +141,8 @@ TIMEx_BreakInputConfigTypeDef;
 /** @defgroup TIMEx_Break_Input TIM Extended Break input
   * @{
   */
-#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */
-#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */
+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /*!< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /*!< Timer break2 input */
 /**
   * @}
   */
@@ -152,10 +150,10 @@ TIMEx_BreakInputConfigTypeDef;
 /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
   * @{
   */
-#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
-#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
-#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /*!< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /*!< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /*!< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
 /**
   * @}
   */
@@ -163,8 +161,8 @@ TIMEx_BreakInputConfigTypeDef;
 /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
   * @{
   */
-#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */
-#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */
+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /*!< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /*!< Break input source is enabled */
 /**
   * @}
   */
@@ -172,8 +170,8 @@ TIMEx_BreakInputConfigTypeDef;
 /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
   * @{
   */
-#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */
-#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /*!< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /*!< Break input source is active_high */
 /**
   * @}
   */
@@ -182,61 +180,61 @@ TIMEx_BreakInputConfigTypeDef;
 /** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
   * @{
   */
-#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */
-#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */
+#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /*!< TIM1_TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM1_TI1 is connected to COMP1 OUT */
 
-#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */
-#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */
+#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /*!< TIM8_TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /*!< TIM8_TI1 is connected to COMP2 OUT */
 
-#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */
-#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */
-#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */
-#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
+#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /*!< TIM2_TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /*!< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /*!< TIM2_TI4 is connected to COMP2 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
 
-#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
-#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
-#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
-#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
+#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /*!< TIM3_TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM3_TI1 is connected to COMP1 OUT */
+#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /*!< TIM3_TI1 is connected to COMP2 OUT */
+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
 
-#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
-#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
-#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
+#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /*!< TIM5_TI1 is connected to GPIO */
+#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /*!< TIM5_TI1 is connected to CAN TMP */
+#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /*!< TIM5_TI1 is connected to CAN RTP */
 
-#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
-#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /*!< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM12 TI1 is connected to SPDIF FS */
 
-#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
-#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
-#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
-#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
-#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
-#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
-#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /*!< TIM15_TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /*!< TIM15_TI1 is connected to TIM2 CH1 */
+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /*!< TIM15_TI1 is connected to TIM3 CH1 */
+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM4 CH1 */
+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /*!< TIM15_TI1 is connected to RCC LSE  */
+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to RCC CSI  */
+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to RCC MCO2 */
 
-#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
-#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
-#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */
-#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */
+#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /*!< TIM15_TI2 is connected to GPIO */
+#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /*!< TIM15_TI2 is connected to TIM2 CH2 */
+#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /*!< TIM15_TI2 is connected to TIM3 CH2 */
+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM4 CH2 */
 
-#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */
-#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */
-#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */
-#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
+#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /*!< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /*!< TIM16 TI1 is connected to RCC LSI */
+#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /*!< TIM16 TI1 is connected to RCC LSE */
+#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to WKUP_IT */
 
-#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
-#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
-#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
-#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /*!< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /*!< TIM17 TI1 is connected to RCC HSE 1Mhz */
+#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to RCC MCO1 */
 
-#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
-#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
-#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
-#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /*!< TIM23_TI4 is connected to GPIO */
+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /*!< TIM23_TI4 is connected to COMP1 OUT */
+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /*!< TIM23_TI4 is connected to COMP2 OUT */
+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
 
-#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
-#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
-#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
-#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /*!< TIM24_TI1 is connected to GPIO */
+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /*!< TIM24_TI1 is connected to CAN TMP  */
+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /*!< TIM24_TI1 is connected to CAN RTP  */
+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24_TI1 is connected to CAN SOC */
 /**
   * @}
   */
@@ -372,7 +370,7 @@ TIMEx_BreakInputConfigTypeDef;
   * @{
   */
 /*  Timer Hall Sensor functions  **********************************************/
-HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
 
 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
@@ -405,7 +403,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                          uint16_t Length);
 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
@@ -424,7 +423,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
+                                           uint16_t Length);
 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
 /**
   * @}
@@ -458,16 +458,21 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,
                                                   uint32_t  CommutationSource);
 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
-                                                        TIM_MasterConfigTypeDef *sMasterConfig);
+                                                        const TIM_MasterConfigTypeDef *sMasterConfig);
 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
-                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+                                                const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
 #if defined(TIM_BREAK_INPUT_SUPPORT)
 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
-                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+                                             const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
 #endif /* TIM_BREAK_INPUT_SUPPORT */
 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
 HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
+#if defined(TIM_BDTR_BKBID)
+
+HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
+HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
+#endif /* TIM_BDTR_BKBID */
 /**
   * @}
   */
@@ -490,8 +495,8 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
   * @{
   */
 /* Extended Peripheral State functions  ***************************************/
-HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
+HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim,  uint32_t ChannelN);
 /**
   * @}
   */
@@ -502,7 +507,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,
 /* End of exported functions -------------------------------------------------*/
 
 /* Private functions----------------------------------------------------------*/
-/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
+/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
   * @{
   */
 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
@@ -526,5 +531,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
 
 
 #endif /* STM32H7xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c
index 218b9b598e..3465d29cca 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -76,8 +87,8 @@
     allows the user to configure dynamically the driver callbacks.
 
     [..]
-    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.
-    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
     (+) TxCpltCallback            : Tx Complete Callback.
     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
@@ -95,9 +106,9 @@
     and a pointer to the user callback function.
 
     [..]
-    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
@@ -116,16 +127,16 @@
 
     [..]
     For specific callback RxEventCallback, use dedicated registration/reset functions:
-    respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
 
     [..]
-    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
     Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()
-    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()
+    reset to the legacy weak functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
     [..]
@@ -134,28 +145,17 @@
     in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
     MspInit/DeInit callbacks can be used during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()
-    or @ref HAL_UART_Init() function.
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
 
     [..]
     When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak callbacks are used.
 
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -193,13 +193,12 @@
   */
 
 /* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
 /** @addtogroup UART_Private_Functions
   * @{
   */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
 static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
 static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
@@ -223,8 +222,8 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
   * @}
   */
 
-/* Exported Constants --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Constants
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
   * @{
   */
 const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
@@ -232,6 +231,7 @@ const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U
   * @}
   */
 
+/* Exported Constants --------------------------------------------------------*/
 /* Exported functions --------------------------------------------------------*/
 
 /** @defgroup UART_Exported_Functions UART Exported Functions
@@ -348,17 +348,19 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
 
   __HAL_UART_DISABLE(huart);
 
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
   /* Set the UART Communication parameters */
   if (UART_SetConfig(huart) == HAL_ERROR)
   {
     return HAL_ERROR;
   }
 
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
   /* In asynchronous mode, the following bits must be kept cleared:
   - LINEN and CLKEN bits in the USART_CR2 register,
   - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
@@ -413,17 +415,19 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
 
   __HAL_UART_DISABLE(huart);
 
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
   /* Set the UART Communication parameters */
   if (UART_SetConfig(huart) == HAL_ERROR)
   {
     return HAL_ERROR;
   }
 
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
   /* In half-duplex mode, the following bits must be kept cleared:
   - LINEN and CLKEN bits in the USART_CR2 register,
   - SCEN and IREN bits in the USART_CR3 register.*/
@@ -499,17 +503,19 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
 
   __HAL_UART_DISABLE(huart);
 
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
   /* Set the UART Communication parameters */
   if (UART_SetConfig(huart) == HAL_ERROR)
   {
     return HAL_ERROR;
   }
 
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
   /* In LIN mode, the following bits must be kept cleared:
   - LINEN and CLKEN bits in the USART_CR2 register,
   - SCEN and IREN bits in the USART_CR3 register.*/
@@ -583,17 +589,19 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
 
   __HAL_UART_DISABLE(huart);
 
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
   /* Set the UART Communication parameters */
   if (UART_SetConfig(huart) == HAL_ERROR)
   {
     return HAL_ERROR;
   }
 
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
   /* In multiprocessor mode, the following bits must be kept cleared:
   - LINEN and CLKEN bits in the USART_CR2 register,
   - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
@@ -656,6 +664,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_RESET;
   huart->RxState = HAL_UART_STATE_RESET;
   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
 
   __HAL_UNLOCK(huart);
 
@@ -695,7 +704,10 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User UART Callback
-  *         To be used instead of the weak predefined callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
   * @param  huart uart handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -727,8 +739,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
     return HAL_ERROR;
   }
 
-  __HAL_LOCK(huart);
-
   if (huart->gState == HAL_UART_STATE_READY)
   {
     switch (CallbackID)
@@ -818,14 +828,15 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_
     status =  HAL_ERROR;
   }
 
-  __HAL_UNLOCK(huart);
-
   return status;
 }
 
 /**
   * @brief  Unregister an UART Callback
   *         UART callaback is redirected to the weak predefined callback
+  * @note   The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
   * @param  huart uart handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -848,8 +859,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  __HAL_LOCK(huart);
-
   if (HAL_UART_STATE_READY == huart->gState)
   {
     switch (CallbackID)
@@ -941,8 +950,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR
     status =  HAL_ERROR;
   }
 
-  __HAL_UNLOCK(huart);
-
   return status;
 }
 
@@ -964,10 +971,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
     return HAL_ERROR;
   }
 
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
+  if (huart->RxState == HAL_UART_STATE_READY)
   {
     huart->RxEventCallback = pCallback;
   }
@@ -978,9 +982,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
   return status;
 }
 
@@ -994,10 +995,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
+  if (huart->RxState == HAL_UART_STATE_READY)
   {
     huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
   }
@@ -1008,8 +1006,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
   return status;
 }
 
@@ -1118,10 +1114,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
   * @param Timeout Timeout duration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
 {
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
   uint32_t tickstart;
 
   /* Check that a Tx process is not already ongoing */
@@ -1132,8 +1128,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
       return  HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->gState = HAL_UART_STATE_BUSY_TX;
 
@@ -1147,7 +1141,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
     if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
     {
       pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
+      pdata16bits = (const uint16_t *) pData;
     }
     else
     {
@@ -1155,12 +1149,13 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
       pdata16bits = NULL;
     }
 
-    __HAL_UNLOCK(huart);
-
     while (huart->TxXferCount > 0U)
     {
       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
       {
+
+        huart->gState = HAL_UART_STATE_READY;
+
         return HAL_TIMEOUT;
       }
       if (pdata8bits == NULL)
@@ -1178,6 +1173,8 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u
 
     if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
     {
+      huart->gState = HAL_UART_STATE_READY;
+
       return HAL_TIMEOUT;
     }
 
@@ -1222,8 +1219,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
       return  HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->RxState = HAL_UART_STATE_BUSY_RX;
     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1250,13 +1245,13 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
       pdata16bits = NULL;
     }
 
-    __HAL_UNLOCK(huart);
-
     /* as long as data have to be received */
     while (huart->RxXferCount > 0U)
     {
       if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
       {
+        huart->RxState = HAL_UART_STATE_READY;
+
         return HAL_TIMEOUT;
       }
       if (pdata8bits == NULL)
@@ -1293,7 +1288,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui
   * @param Size  Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
 {
   /* Check that a Tx process is not already ongoing */
   if (huart->gState == HAL_UART_STATE_READY)
@@ -1303,8 +1298,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
       return HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     huart->pTxBuffPtr  = pData;
     huart->TxXferSize  = Size;
     huart->TxXferCount = Size;
@@ -1326,10 +1319,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
         huart->TxISR = UART_TxISR_8BIT_FIFOEN;
       }
 
-      __HAL_UNLOCK(huart);
-
       /* Enable the TX FIFO threshold interrupt */
-      SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
     }
     else
     {
@@ -1343,10 +1334,8 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData
         huart->TxISR = UART_TxISR_8BIT;
       }
 
-      __HAL_UNLOCK(huart);
-
       /* Enable the Transmit Data Register Empty interrupt */
-      SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
     }
 
     return HAL_OK;
@@ -1377,8 +1366,6 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
       return HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     /* Set Reception type to Standard reception */
     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 
@@ -1388,7 +1375,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
       {
         /* Enable the UART Receiver Timeout Interrupt */
-        SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
       }
     }
 
@@ -1410,7 +1397,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData,
   * @param Size  Amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
 {
   /* Check that a Tx process is not already ongoing */
   if (huart->gState == HAL_UART_STATE_READY)
@@ -1420,8 +1407,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
       return HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     huart->pTxBuffPtr  = pData;
     huart->TxXferSize  = Size;
     huart->TxXferCount = Size;
@@ -1449,8 +1434,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
         /* Set error code to DMA */
         huart->ErrorCode = HAL_UART_ERROR_DMA;
 
-        __HAL_UNLOCK(huart);
-
         /* Restore huart->gState to ready */
         huart->gState = HAL_UART_STATE_READY;
 
@@ -1460,11 +1443,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat
     /* Clear the TC flag in the ICR register */
     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
 
-    __HAL_UNLOCK(huart);
-
     /* Enable the DMA transfer for transmit request by setting the DMAT bit
     in the UART CR3 register */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     return HAL_OK;
   }
@@ -1496,8 +1477,6 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
       return HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     /* Set Reception type to Standard reception */
     huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 
@@ -1507,7 +1486,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData
       if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
       {
         /* Enable the UART Receiver Timeout Interrupt */
-        SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
       }
     }
 
@@ -1529,27 +1508,23 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
   const HAL_UART_StateTypeDef gstate = huart->gState;
   const HAL_UART_StateTypeDef rxstate = huart->RxState;
 
-  __HAL_LOCK(huart);
-
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
       (gstate == HAL_UART_STATE_BUSY_TX))
   {
     /* Disable the UART DMA Tx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
   }
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
       (rxstate == HAL_UART_STATE_BUSY_RX))
   {
     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
     /* Disable the UART DMA Rx request */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
   }
 
-  __HAL_UNLOCK(huart);
-
   return HAL_OK;
 }
 
@@ -1560,12 +1535,10 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
   */
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
 {
-  __HAL_LOCK(huart);
-
   if (huart->gState == HAL_UART_STATE_BUSY_TX)
   {
     /* Enable the UART DMA Tx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
   }
   if (huart->RxState == HAL_UART_STATE_BUSY_RX)
   {
@@ -1573,15 +1546,16 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
     __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
 
     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the UART DMA Rx request */
-    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
   }
 
-  __HAL_UNLOCK(huart);
-
   return HAL_OK;
 }
 
@@ -1606,7 +1580,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
       (gstate == HAL_UART_STATE_BUSY_TX))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Abort the UART DMA Tx channel */
     if (huart->hdmatx != NULL)
@@ -1630,7 +1604,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
       (rxstate == HAL_UART_STATE_BUSY_RX))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the UART DMA Rx channel */
     if (huart->hdmarx != NULL)
@@ -1668,20 +1642,21 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
 {
   /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE |
-                                   USART_CR1_TCIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                          USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
 
   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
   }
 
-  /* Disable the UART DMA Tx request if enabled */
+  /* Abort the UART DMA Tx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
     if (huart->hdmatx != NULL)
@@ -1703,10 +1678,11 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
     }
   }
 
-  /* Disable the UART DMA Rx request if enabled */
+  /* Abort the UART DMA Rx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
     if (huart->hdmarx != NULL)
@@ -1769,13 +1745,14 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
 {
   /* Disable TCIE, TXEIE and TXFTIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 
-  /* Disable the UART DMA Tx request if enabled */
+  /* Abort the UART DMA Tx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
     if (huart->hdmatx != NULL)
@@ -1827,19 +1804,20 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
 {
   /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
 
   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
   }
 
-  /* Disable the UART DMA Rx request if enabled */
+  /* Abort the UART DMA Rx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
     if (huart->hdmarx != NULL)
@@ -1896,14 +1874,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
   uint32_t abortcplt = 1U;
 
   /* Disable interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
-                                   USART_CR1_TXEIE_TXFNFIE));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+                                          USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
 
   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
   }
 
   /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
@@ -1937,11 +1915,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
     }
   }
 
-  /* Disable the UART DMA Tx request if enabled */
+  /* Abort the UART DMA Tx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
   {
     /* Disable DMA Tx at UART level */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
     if (huart->hdmatx != NULL)
@@ -1961,10 +1939,11 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
     }
   }
 
-  /* Disable the UART DMA Rx request if enabled */
+  /* Abort the UART DMA Rx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
     if (huart->hdmarx != NULL)
@@ -2046,13 +2025,14 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
 {
   /* Disable interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
-  CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 
-  /* Disable the UART DMA Tx request if enabled */
+  /* Abort the UART DMA Tx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
     if (huart->hdmatx != NULL)
@@ -2136,19 +2116,20 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
 HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
 {
   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 
   /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
-    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
   }
 
-  /* Disable the UART DMA Rx request if enabled */
+  /* Abort the UART DMA Rx channel if enabled */
   if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
   {
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
     if (huart->hdmarx != NULL)
@@ -2326,10 +2307,11 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
            Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
         UART_EndRxTransfer(huart);
 
-        /* Disable the UART DMA Rx request if enabled */
+        /* Abort the UART DMA Rx channel if enabled */
         if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
         {
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+          /* Disable the UART DMA Rx request if enabled */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
           /* Abort the UART DMA Rx channel */
           if (huart->hdmarx != NULL)
@@ -2414,22 +2396,27 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
         if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
         {
           /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-          CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
           /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
              in the UART CR3 register */
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
           /* At end of Rx process, restore huart->RxState to Ready */
           huart->RxState = HAL_UART_STATE_READY;
           huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 
-          CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
 
           /* Last bytes received, so no need as the abort is immediate */
           (void)HAL_DMA_Abort(huart->hdmarx);
         }
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx Event callback*/
         huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
@@ -2450,10 +2437,10 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
           && (nb_rx_data > 0U))
       {
         /* Disable the UART Parity Error Interrupt and RXNE interrupts */
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 
         /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
-        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 
         /* Rx process is completed, restore huart->RxState to Ready */
         huart->RxState = HAL_UART_STATE_READY;
@@ -2462,7 +2449,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
         /* Clear RxISR function pointer */
         huart->RxISR = NULL;
 
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx complete callback*/
         huart->RxEventCallback(huart, nb_rx_data);
@@ -2812,7 +2804,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
 
   /* Enable USART mute mode by setting the MME bit in the CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
 
   huart->gState = HAL_UART_STATE_READY;
 
@@ -2832,7 +2824,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
 
   /* Disable USART mute mode by clearing the MME bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
 
   huart->gState = HAL_UART_STATE_READY;
 
@@ -2861,10 +2853,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
 
   /* Clear TE and RE bits */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
 
   /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
 
   huart->gState = HAL_UART_STATE_READY;
 
@@ -2884,10 +2876,10 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_BUSY;
 
   /* Clear TE and RE bits */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
 
   /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
 
   huart->gState = HAL_UART_STATE_READY;
 
@@ -2947,7 +2939,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
   *               the configuration information for the specified UART.
   * @retval HAL state
   */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
 {
   uint32_t temp1;
   uint32_t temp2;
@@ -2963,7 +2955,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
   *               the configuration information for the specified UART.
   * @retval UART Error Code
   */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
 {
   return huart->ErrorCode;
 }
@@ -3189,7 +3181,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
     /* USARTDIV must be greater than or equal to 0d16 */
     if (pclk != 0U)
     {
-      usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
       {
         brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
@@ -3245,10 +3237,10 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
     if (pclk != 0U)
     {
       /* USARTDIV must be greater than or equal to 0d16 */
-      usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
       if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
       {
-        huart->Instance->BRR = usartdiv;
+        huart->Instance->BRR = (uint16_t)usartdiv;
       }
       else
       {
@@ -3278,6 +3270,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
   /* Check whether the set of advanced features to configure is properly set */
   assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
 
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
   /* if required, configure TX pin active level inversion */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
   {
@@ -3299,13 +3298,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
     MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
   }
 
-  /* if required, configure RX/TX pins swap */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
-  {
-    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
-  }
-
   /* if required, configure RX overrun detection disabling */
   if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
   {
@@ -3363,6 +3355,13 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
     /* Wait until TEACK flag is set */
     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
     {
+      /* Disable TXE interrupt for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
       /* Timeout occurred */
       return HAL_TIMEOUT;
     }
@@ -3374,6 +3373,15 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
     /* Wait until REACK flag is set */
     if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
     {
+      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+      interrupts for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      huart->RxState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
       /* Timeout occurred */
       return HAL_TIMEOUT;
     }
@@ -3383,6 +3391,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
   huart->gState = HAL_UART_STATE_READY;
   huart->RxState = HAL_UART_STATE_READY;
   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
 
   __HAL_UNLOCK(huart);
 
@@ -3390,10 +3399,11 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
 }
 
 /**
-  * @brief  Handle UART Communication Timeout.
+  * @brief  This function handles UART Communication Timeout. It waits
+  *                  until a flag is no longer in the specified status.
   * @param huart     UART handle.
   * @param Flag      Specifies the UART flag to check
-  * @param Status    Flag status (SET or RESET)
+  * @param Status    The actual Flag status (SET or RESET)
   * @param Tickstart Tick start value
   * @param Timeout   Timeout duration
   * @retval HAL status
@@ -3409,33 +3419,39 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
     {
       if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
       {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
-           interrupts for the interrupt process */
-        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        huart->gState = HAL_UART_STATE_READY;
-        huart->RxState = HAL_UART_STATE_READY;
-
-        __HAL_UNLOCK(huart);
 
         return HAL_TIMEOUT;
       }
 
-      if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
+      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
       {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+        {
+          /* Clear Overrun Error flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+
+          huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_ERROR;
+        }
         if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
         {
           /* Clear Receiver Timeout flag*/
           __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
 
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
-             interrupts for the interrupt process */
-          CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
-          CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
 
-          huart->gState = HAL_UART_STATE_READY;
-          huart->RxState = HAL_UART_STATE_READY;
           huart->ErrorCode = HAL_UART_ERROR_RTO;
 
           /* Process Unlocked */
@@ -3474,7 +3490,7 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
   huart->RxState = HAL_UART_STATE_BUSY_RX;
 
   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
   /* Configure Rx interrupt processing */
   if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
@@ -3489,11 +3505,12 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
       huart->RxISR = UART_RxISR_8BIT_FIFOEN;
     }
 
-    __HAL_UNLOCK(huart);
-
     /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
   }
   else
   {
@@ -3507,10 +3524,15 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat
       huart->RxISR = UART_RxISR_8BIT;
     }
 
-    __HAL_UNLOCK(huart);
-
     /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
   }
   return HAL_OK;
 }
@@ -3554,25 +3576,25 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
       /* Set error code to DMA */
       huart->ErrorCode = HAL_UART_ERROR_DMA;
 
-      __HAL_UNLOCK(huart);
-
-      /* Restore huart->gState to ready */
-      huart->gState = HAL_UART_STATE_READY;
+      /* Restore huart->RxState to ready */
+      huart->RxState = HAL_UART_STATE_READY;
 
       return HAL_ERROR;
     }
   }
-  __HAL_UNLOCK(huart);
 
   /* Enable the UART Parity Error Interrupt */
-  SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
 
   /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
   /* Enable the DMA transfer for the receiver request by setting the DMAR bit
   in the UART CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
   return HAL_OK;
 }
@@ -3586,8 +3608,8 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
 {
   /* Disable TXEIE, TCIE, TXFT interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
 
   /* At end of Tx process, restore huart->gState to Ready */
   huart->gState = HAL_UART_STATE_READY;
@@ -3602,13 +3624,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
 {
   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 
   /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
   {
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
   }
 
   /* At end of Rx process, restore huart->RxState to Ready */
@@ -3636,10 +3658,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 
     /* Disable the DMA transfer for transmit request by resetting the DMAT bit
        in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
 
     /* Enable the UART Transmit Complete Interrupt */
-    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
   }
   /* DMA Circular mode */
   else
@@ -3687,12 +3709,12 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
     huart->RxXferCount = 0U;
 
     /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
     /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
        in the UART CR3 register */
-    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
 
     /* At end of Rx process, restore huart->RxState to Ready */
     huart->RxState = HAL_UART_STATE_READY;
@@ -3700,10 +3722,14 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
     /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
     if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
     {
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
     }
   }
 
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Transfer Complete */
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
   /* Check current reception Mode :
      If Reception till IDLE event has been selected : use Rx Event callback */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3738,6 +3764,10 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 {
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
 
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Half Transfer */
+  huart->RxEventType = HAL_UART_RXEVENT_HT;
+
   /* Check current reception Mode :
      If Reception till IDLE event has been selected : use Rx Event callback */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4012,10 +4042,10 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
     if (huart->TxXferCount == 0U)
     {
       /* Disable the UART Transmit Data Register Empty Interrupt */
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 
       /* Enable the UART Transmit Complete Interrupt */
-      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
     }
     else
     {
@@ -4035,7 +4065,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
   */
 static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
 {
-  uint16_t *tmp;
+  const uint16_t *tmp;
 
   /* Check that a Tx process is ongoing */
   if (huart->gState == HAL_UART_STATE_BUSY_TX)
@@ -4043,14 +4073,14 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
     if (huart->TxXferCount == 0U)
     {
       /* Disable the UART Transmit Data Register Empty Interrupt */
-      CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
 
       /* Enable the UART Transmit Complete Interrupt */
-      SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
     }
     else
     {
-      tmp = (uint16_t *) huart->pTxBuffPtr;
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
       huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
       huart->pTxBuffPtr += 2U;
       huart->TxXferCount--;
@@ -4077,10 +4107,10 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
       if (huart->TxXferCount == 0U)
       {
         /* Disable the TX FIFO threshold interrupt */
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 
         /* Enable the UART Transmit Complete Interrupt */
-        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 
         break; /* force exit loop */
       }
@@ -4107,7 +4137,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
   */
 static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
 {
-  uint16_t *tmp;
+  const uint16_t *tmp;
   uint16_t  nb_tx_data;
 
   /* Check that a Tx process is ongoing */
@@ -4118,16 +4148,16 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
       if (huart->TxXferCount == 0U)
       {
         /* Disable the TX FIFO threshold interrupt */
-        CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
 
         /* Enable the UART Transmit Complete Interrupt */
-        SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 
         break; /* force exit loop */
       }
       else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
       {
-        tmp = (uint16_t *) huart->pTxBuffPtr;
+        tmp = (const uint16_t *) huart->pTxBuffPtr;
         huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
         huart->pTxBuffPtr += 2U;
         huart->TxXferCount--;
@@ -4149,7 +4179,7 @@ static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
 static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
 {
   /* Disable the UART Transmit Complete Interrupt */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
 
   /* Tx process is ended, restore huart->gState to Ready */
   huart->gState = HAL_UART_STATE_READY;
@@ -4187,10 +4217,10 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
     if (huart->RxXferCount == 0U)
     {
       /* Disable the UART Parity Error Interrupt and RXNE interrupts */
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 
       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
       /* Rx process is completed, restore huart->RxState to Ready */
       huart->RxState = HAL_UART_STATE_READY;
@@ -4198,12 +4228,34 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
       /* Clear RxISR function pointer */
       huart->RxISR = NULL;
 
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
       /* Check current reception Mode :
          If Reception till IDLE event has been selected : */
       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
       {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
         /* Disable IDLE interrupt */
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
 
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx Event callback*/
@@ -4224,7 +4276,6 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
         HAL_UART_RxCpltCallback(huart);
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
       }
-      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
     }
   }
   else
@@ -4259,10 +4310,10 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
     if (huart->RxXferCount == 0U)
     {
       /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
-      CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
 
       /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 
       /* Rx process is completed, restore huart->RxState to Ready */
       huart->RxState = HAL_UART_STATE_READY;
@@ -4270,12 +4321,34 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
       /* Clear RxISR function pointer */
       huart->RxISR = NULL;
 
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
       /* Check current reception Mode :
          If Reception till IDLE event has been selected : */
       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
       {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
         /* Disable IDLE interrupt */
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
 
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
         /*Call registered Rx Event callback*/
@@ -4296,7 +4369,6 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
         HAL_UART_RxCpltCallback(huart);
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
       }
-      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
     }
   }
   else
@@ -4381,11 +4453,11 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
       if (huart->RxXferCount == 0U)
       {
         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 
         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
            and RX FIFO Threshold interrupt */
-        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 
         /* Rx process is completed, restore huart->RxState to Ready */
         huart->RxState = HAL_UART_STATE_READY;
@@ -4393,12 +4465,34 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
         /* Clear RxISR function pointer */
         huart->RxISR = NULL;
 
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
         /* Check current reception Mode :
            If Reception till IDLE event has been selected : */
         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
         {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
           /* Disable IDLE interrupt */
-          CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
 
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
           /*Call registered Rx Event callback*/
@@ -4419,7 +4513,6 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
           HAL_UART_RxCpltCallback(huart);
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
         }
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
       }
     }
 
@@ -4431,13 +4524,13 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
     {
       /* Disable the UART RXFT interrupt*/
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 
       /* Update the RxISR function pointer */
       huart->RxISR = UART_RxISR_8BIT;
 
       /* Enable the UART Data Register Not Empty interrupt */
-      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
     }
   }
   else
@@ -4524,11 +4617,11 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
       if (huart->RxXferCount == 0U)
       {
         /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
-        CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
 
         /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
            and RX FIFO Threshold interrupt */
-        CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
 
         /* Rx process is completed, restore huart->RxState to Ready */
         huart->RxState = HAL_UART_STATE_READY;
@@ -4536,12 +4629,34 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
         /* Clear RxISR function pointer */
         huart->RxISR = NULL;
 
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
         /* Check current reception Mode :
            If Reception till IDLE event has been selected : */
         if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
         {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
           /* Disable IDLE interrupt */
-          CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
 
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
           /*Call registered Rx Event callback*/
@@ -4562,7 +4677,6 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
           HAL_UART_RxCpltCallback(huart);
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
         }
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
       }
     }
 
@@ -4574,13 +4688,13 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
     if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
     {
       /* Disable the UART RXFT interrupt*/
-      CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
 
       /* Update the RxISR function pointer */
       huart->RxISR = UART_RxISR_16BIT;
 
       /* Enable the UART Data Register Not Empty interrupt */
-      SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
     }
   }
   else
@@ -4603,4 +4717,3 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h
index 103cb1b33f..c6fced0281 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -198,7 +197,7 @@ typedef enum
 /**
   * @brief HAL UART Reception type definition
   * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
-  *        It is expected to admit following values :
+  *        This parameter can be a value of @ref UART_Reception_Type_Values :
   *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
   *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
   *           HAL_UART_RECEPTION_TORTO            = 0x02U,
@@ -206,6 +205,17 @@ typedef enum
   */
 typedef uint32_t HAL_UART_RxTypeTypeDef;
 
+/**
+  * @brief HAL UART Rx Event type definition
+  * @note  HAL UART Rx Event type value aims to identify which type of Event has occurred
+  *        leading to call of the RxEvent callback.
+  *        This parameter can be a value of @ref UART_RxEvent_Type_Values :
+  *           HAL_UART_RXEVENT_TC                 = 0x00U,
+  *           HAL_UART_RXEVENT_HT                 = 0x01U,
+  *           HAL_UART_RXEVENT_IDLE               = 0x02U,
+  */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
 /**
   * @brief  UART handle Structure definition
   */
@@ -217,7 +227,7 @@ typedef struct __UART_HandleTypeDef
 
   UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
 
-  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+  const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
 
   uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
 
@@ -240,6 +250,8 @@ typedef struct __UART_HandleTypeDef
 
   __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
 
+  __IO HAL_UART_RxEventTypeTypeDef RxEventType;      /*!< Type of Rx Event                   */
+
   void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
 
   void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -809,7 +821,7 @@ typedef  void (*pUART_RxEventCallbackTypeDef)
   * @}
   */
 
-/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
+/** @defgroup UART_Reception_Type_Values  UART Reception type values
   * @{
   */
 #define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
@@ -820,6 +832,16 @@ typedef  void (*pUART_RxEventCallbackTypeDef)
   * @}
   */
 
+/** @defgroup UART_RxEvent_Type_Values  UART RxEvent type values
+  * @{
+  */
+#define HAL_UART_RXEVENT_TC                  (0x00000000U)             /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT                  (0x00000001U)             /*!< RxEvent linked to Half Transfer event     */
+#define HAL_UART_RXEVENT_IDLE                (0x00000002U)             /*!< RxEvent linked to IDLE event              */
+/**
+  * @}
+  */
+
 /**
   * @}
   */
@@ -1141,10 +1163,10 @@ typedef  void (*pUART_RxEventCallbackTypeDef)
   * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
+  do{                                                             \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
   } while(0U)
 
 /** @brief  Disable CTS flow control.
@@ -1160,10 +1182,10 @@ typedef  void (*pUART_RxEventCallbackTypeDef)
   * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
+  do{                                                              \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
   } while(0U)
 
 /** @brief  Enable RTS flow control.
@@ -1179,10 +1201,10 @@ typedef  void (*pUART_RxEventCallbackTypeDef)
   * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
+  do{                                                            \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
   } while(0U)
 
 /** @brief  Disable RTS flow control.
@@ -1198,10 +1220,10 @@ typedef  void (*pUART_RxEventCallbackTypeDef)
   * @param  __HANDLE__ specifies the UART Handle.
   * @retval None
   */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
+  do{                                                             \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
   } while(0U)
 /**
   * @}
@@ -1612,11 +1634,11 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
   */
 
 /* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
@@ -1670,8 +1692,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
   */
 
 /* Peripheral State and Errors functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(const UART_HandleTypeDef *huart);
 
 /**
   * @}
@@ -1707,8 +1729,6 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa
 /* Prescaler Table used in BRR computation macros.
    Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
 extern const uint16_t UARTPrescTable[12];
-
-
 /**
   * @}
   */
@@ -1727,4 +1747,3 @@ extern const uint16_t UARTPrescTable[12];
 
 #endif /* STM32H7xx_HAL_UART_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c
index bd57fecb6a..bb45995e96 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c
@@ -9,6 +9,17 @@
   *           + Peripheral Control functions
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                ##### UART peripheral extended features  #####
@@ -27,17 +38,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -211,17 +211,19 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
   /* Disable the Peripheral */
   __HAL_UART_DISABLE(huart);
 
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
   /* Set the UART Communication parameters */
   if (UART_SetConfig(huart) == HAL_ERROR)
   {
     return HAL_ERROR;
   }
 
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
-  {
-    UART_AdvFeatureConfig(huart);
-  }
-
   /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
   SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
 
@@ -483,7 +485,7 @@ HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
   __HAL_LOCK(huart);
 
   /* Set UESM bit */
-  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
 
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
@@ -502,7 +504,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
   __HAL_LOCK(huart);
 
   /* Clear UESM bit */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
 
   /* Process Unlocked */
   __HAL_UNLOCK(huart);
@@ -574,7 +576,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
   /* Disable UART */
   __HAL_UART_DISABLE(huart);
 
-  /* Enable FIFO mode */
+  /* Disable FIFO mode */
   CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
   huart->FifoMode = UART_FIFOMODE_DISABLE;
 
@@ -724,11 +726,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
       return  HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     huart->ErrorCode = HAL_UART_ERROR_NONE;
     huart->RxState = HAL_UART_STATE_BUSY_RX;
     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
 
     /* Init tickstart for timeout management */
     tickstart = HAL_GetTick();
@@ -752,8 +753,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
       pdata16bits = NULL;
     }
 
-    __HAL_UNLOCK(huart);
-
     /* Initialize output number of received elements */
     *RxLen = 0U;
 
@@ -770,6 +769,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
         /* If Set, and data has already been received, this means Idle Event is valid : End reception */
         if (*RxLen > 0U)
         {
+          huart->RxEventType = HAL_UART_RXEVENT_IDLE;
           huart->RxState = HAL_UART_STATE_READY;
 
           return HAL_OK;
@@ -835,7 +835,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
   */
 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
 {
-  HAL_StatusTypeDef status;
+  HAL_StatusTypeDef status = HAL_OK;
 
   /* Check that a Rx process is not already ongoing */
   if (huart->RxState == HAL_UART_STATE_READY)
@@ -845,29 +845,24 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
       return HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     /* Set Reception type to reception till IDLE Event*/
     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
 
-    status =  UART_Start_Receive_IT(huart, pData, Size);
+    (void)UART_Start_Receive_IT(huart, pData, Size);
 
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
     {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-        SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+    else
+    {
+      /* In case of errors already pending when reception is started,
+         Interrupts may have already been raised and lead to reception abortion.
+         (Overrun error for instance).
+         In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+      status = HAL_ERROR;
     }
 
     return status;
@@ -907,10 +902,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
       return HAL_ERROR;
     }
 
-    __HAL_LOCK(huart);
-
     /* Set Reception type to reception till IDLE Event*/
     huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
 
     status =  UART_Start_Receive_DMA(huart, pData, Size);
 
@@ -920,7 +914,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
       if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
       {
         __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
-        SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
       }
       else
       {
@@ -940,6 +934,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
   }
 }
 
+/**
+  * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+  * @note  When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+  *        of reception process is provided to application through calls of Rx Event callback (either default one
+  *        HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+  *        Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+  *        to Rx Event callback execution.
+  * @note  This function is expected to be called within the user implementation of Rx Event Callback,
+  *        in order to provide the accurate value :
+  *        In Interrupt Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one)
+  *        In DMA Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one).
+  *        In DMA mode, RxEvent callback could be called several times;
+  *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
+  *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+  * @param  huart UART handle.
+  * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+  */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
+{
+  /* Return Rx Event type value, as stored in UART handle */
+  return (huart->RxEventType);
+}
+
 /**
   * @}
   */
@@ -1016,4 +1040,3 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h
index eb437f3b00..5344695516 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -179,6 +178,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
 
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
+
 
 /**
   * @}
@@ -867,4 +868,3 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
 
 #endif /* STM32H7xx_HAL_UART_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c
index f27e32f517..85ccef27e3 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c
@@ -11,6 +11,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State and Error functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
  ===============================================================================
                         ##### How to use this driver #####
@@ -62,8 +73,8 @@
     allows the user to configure dynamically the driver callbacks.
 
     [..]
-    Use Function @ref HAL_USART_RegisterCallback() to register a user callback.
-    Function @ref HAL_USART_RegisterCallback() allows to register following callbacks:
+    Use Function HAL_USART_RegisterCallback() to register a user callback.
+    Function HAL_USART_RegisterCallback() allows to register following callbacks:
     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
     (+) TxCpltCallback            : Tx Complete Callback.
     (+) RxHalfCpltCallback        : Rx Half Complete Callback.
@@ -79,9 +90,9 @@
     and a pointer to the user callback function.
 
     [..]
-    Use function @ref HAL_USART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    @ref HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    Use function HAL_USART_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
     This function allows to reset following callbacks:
     (+) TxHalfCpltCallback        : Tx Half Complete Callback.
@@ -97,13 +108,13 @@
     (+) MspDeInitCallback         : USART MspDeInit.
 
     [..]
-    By default, after the @ref HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples @ref HAL_USART_TxCpltCallback(), @ref HAL_USART_RxHalfCpltCallback().
+    By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback().
     Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the @ref HAL_USART_Init()
-    and @ref HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the @ref HAL_USART_Init() and @ref HAL_USART_DeInit()
+    reset to the legacy weak functions in the HAL_USART_Init()
+    and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit()
     keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
 
     [..]
@@ -112,28 +123,17 @@
     in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user)
     MspInit/DeInit callbacks can be used during the Init/DeInit.
     In that case first register the MspInit/MspDeInit user callbacks
-    using @ref HAL_USART_RegisterCallback() before calling @ref HAL_USART_DeInit()
-    or @ref HAL_USART_Init() function.
+    using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit()
+    or HAL_USART_Init() function.
 
     [..]
     When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
+    and weak callbacks are used.
 
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -406,7 +406,9 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a User USART Callback
-  *         To be used instead of the weak predefined callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+  *         to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
   * @param  husart usart handle
   * @param  CallbackID ID of the callback to be registered
   *         This parameter can be one of the following values:
@@ -436,8 +438,6 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
 
     return HAL_ERROR;
   }
-  /* Process locked */
-  __HAL_LOCK(husart);
 
   if (husart->State == HAL_USART_STATE_READY)
   {
@@ -526,15 +526,14 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
   return status;
 }
 
 /**
   * @brief  Unregister an USART Callback
   *         USART callaback is redirected to the weak predefined callback
+  * @note   The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+  *         to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
   * @param  husart usart handle
   * @param  CallbackID ID of the callback to be unregistered
   *         This parameter can be one of the following values:
@@ -555,9 +554,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Process locked */
-  __HAL_LOCK(husart);
-
   if (HAL_USART_STATE_READY == husart->State)
   {
     switch (CallbackID)
@@ -645,9 +641,6 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
     status =  HAL_ERROR;
   }
 
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
   return status;
 }
 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -748,10 +741,11 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
   * @param  Timeout Timeout duration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+                                     uint32_t Timeout)
 {
-  uint8_t  *ptxdata8bits;
-  uint16_t *ptxdata16bits;
+  const uint8_t  *ptxdata8bits;
+  const uint16_t *ptxdata16bits;
   uint32_t tickstart;
 
   if (husart->State == HAL_USART_STATE_READY)
@@ -777,7 +771,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa
     if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE))
     {
       ptxdata8bits  = NULL;
-      ptxdata16bits = (uint16_t *) pTxData;
+      ptxdata16bits = (const uint16_t *) pTxData;
     }
     else
     {
@@ -957,13 +951,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat
   * @param  Timeout Timeout duration.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
                                             uint16_t Size, uint32_t Timeout)
 {
   uint8_t  *prxdata8bits;
   uint16_t *prxdata16bits;
-  uint8_t  *ptxdata8bits;
-  uint16_t *ptxdata16bits;
+  const uint8_t  *ptxdata8bits;
+  const uint16_t *ptxdata16bits;
   uint16_t uhMask;
   uint16_t rxdatacount;
   uint32_t tickstart;
@@ -998,7 +992,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
     {
       prxdata8bits  = NULL;
       ptxdata8bits  = NULL;
-      ptxdata16bits = (uint16_t *) pTxData;
+      ptxdata16bits = (const uint16_t *) pTxData;
       prxdata16bits = (uint16_t *) pRxData;
     }
     else
@@ -1104,7 +1098,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t
   * @param  Size amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
 {
   if (husart->State == HAL_USART_STATE_READY)
   {
@@ -1231,7 +1225,10 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
       __HAL_UNLOCK(husart);
 
       /* Enable the USART Parity Error interrupt and RX FIFO Threshold interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
       SET_BIT(husart->Instance->CR3, USART_CR3_RXFTIE);
     }
     else
@@ -1250,7 +1247,14 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
       __HAL_UNLOCK(husart);
 
       /* Enable the USART Parity Error and Data Register not empty Interrupts */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+      }
+      else
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+      }
     }
 
     if (husart->SlaveMode == USART_SLAVEMODE_DISABLE)
@@ -1291,7 +1295,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx
   * @param  Size amount of data elements (u8 or u16) to be sent (same amount to be received).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
                                                uint16_t Size)
 {
 
@@ -1339,8 +1343,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
-      /* Enable the USART Parity Error interrupt  */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        /* Enable the USART Parity Error interrupt  */
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
 
       /* Enable the TX and  RX FIFO Threshold interrupts */
       SET_BIT(husart->Instance->CR3, (USART_CR3_TXFTIE | USART_CR3_RXFTIE));
@@ -1365,7 +1372,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
       /* Enable the USART Parity Error and USART Data Register not empty Interrupts */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+      }
+      else
+      {
+        SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+      }
 
       /* Enable the USART Transmit Data Register Empty Interrupt */
       SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
@@ -1389,10 +1403,10 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint
   * @param  Size amount of data elements (u8 or u16) to be sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  uint32_t *tmp;
+  const uint32_t *tmp;
 
   if (husart->State == HAL_USART_STATE_READY)
   {
@@ -1423,8 +1437,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p
       husart->hdmatx->XferErrorCallback = USART_DMAError;
 
       /* Enable the USART transmit DMA channel */
-      tmp = (uint32_t *)&pTxData;
-      status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+      tmp = (const uint32_t *)&pTxData;
+      status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
     }
 
     if (status == HAL_OK)
@@ -1535,8 +1549,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
       /* Process Unlocked */
       __HAL_UNLOCK(husart);
 
-      /* Enable the USART Parity Error Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        /* Enable the USART Parity Error Interrupt */
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
 
       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1591,11 +1608,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR
   * @param  Size amount of data elements (u8 or u16) to be received/sent.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
                                                 uint16_t Size)
 {
   HAL_StatusTypeDef status;
-  uint32_t *tmp;
+  const uint32_t *tmp;
 
   if (husart->State == HAL_USART_STATE_READY)
   {
@@ -1637,13 +1654,13 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
 
       /* Enable the USART receive DMA channel */
       tmp = (uint32_t *)&pRxData;
-      status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size);
+      status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size);
 
       /* Enable the USART transmit DMA channel */
       if (status == HAL_OK)
       {
-        tmp = (uint32_t *)&pTxData;
-        status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
+        tmp = (const uint32_t *)&pTxData;
+        status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size);
       }
     }
     else
@@ -1656,8 +1673,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin
       /* Process Unlocked */
       __HAL_UNLOCK(husart);
 
-      /* Enable the USART Parity Error Interrupt */
-      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      if (husart->Init.Parity != USART_PARITY_NONE)
+      {
+        /* Enable the USART Parity Error Interrupt */
+        SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+      }
 
       /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
       SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -1774,7 +1794,10 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
     __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
 
     /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    if (husart->Init.Parity != USART_PARITY_NONE)
+    {
+      SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
+    }
     SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
 
     /* Enable the USART DMA Rx request  before the DMA Tx request */
@@ -1866,9 +1889,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
                                     USART_CR1_TCIE));
   CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
 
-  /* Disable the USART DMA Tx request if enabled */
+  /* Abort the USART DMA Tx channel if enabled */
   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
   {
+    /* Disable the USART DMA Tx request if enabled */
     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
 
     /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1891,9 +1915,10 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart)
     }
   }
 
-  /* Disable the USART DMA Rx request if enabled */
+  /* Abort the USART DMA Rx channel if enabled */
   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
   {
+    /* Disable the USART DMA Rx request if enabled */
     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1995,7 +2020,7 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
     }
   }
 
-  /* Disable the USART DMA Tx request if enabled */
+  /* Abort the USART DMA Tx channel if enabled */
   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT))
   {
     /* Disable DMA Tx at USART level */
@@ -2019,9 +2044,10 @@ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart)
     }
   }
 
-  /* Disable the USART DMA Rx request if enabled */
+  /* Abort the USART DMA Rx channel if enabled */
   if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
   {
+    /* Disable the USART DMA Rx request if enabled */
     CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
 
     /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2201,9 +2227,10 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
            Disable Interrupts, and disable DMA requests, if ongoing */
         USART_EndTransfer(husart);
 
-        /* Disable the USART DMA Rx request if enabled */
+        /* Abort the USART DMA Rx channel if enabled */
         if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR))
         {
+          /* Disable the USART DMA Rx request if enabled */
           CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR);
 
           /* Abort the USART DMA Tx channel */
@@ -2452,7 +2479,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart)
   *              the configuration information for the specified USART.
   * @retval USART handle state
   */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart)
 {
   return husart->State;
 }
@@ -2463,7 +2490,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
   *              the configuration information for the specified USART.
   * @retval USART handle Error Code
   */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
+uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart)
 {
   return husart->ErrorCode;
 }
@@ -2810,10 +2837,11 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
 
 
 /**
-  * @brief  Handle USART Communication Timeout.
+  * @brief  Handle USART Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
   * @param  husart USART handle.
   * @param  Flag Specifies the USART flag to check.
-  * @param  Status the Flag status (SET or RESET).
+  * @param  Status the actual Flag status (SET or RESET).
   * @param  Tickstart Tick start value
   * @param  Timeout timeout duration.
   * @retval HAL status
@@ -2922,7 +2950,8 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
     case USART_CLOCKSOURCE_HSI:
       if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
       {
-        usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)), husart->Init.BaudRate, husart->Init.ClockPrescaler));
+        usartdiv = (uint32_t)(USART_DIV_SAMPLING8((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)),
+                                                  husart->Init.BaudRate, husart->Init.ClockPrescaler));
       }
       else
       {
@@ -3056,7 +3085,7 @@ static void USART_TxISR_8BIT(USART_HandleTypeDef *husart)
 static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
 {
   const HAL_USART_StateTypeDef state = husart->State;
-  uint16_t *tmp;
+  const uint16_t *tmp;
 
   if ((state == HAL_USART_STATE_BUSY_TX) ||
       (state == HAL_USART_STATE_BUSY_TX_RX))
@@ -3071,7 +3100,7 @@ static void USART_TxISR_16BIT(USART_HandleTypeDef *husart)
     }
     else
     {
-      tmp = (uint16_t *) husart->pTxBuffPtr;
+      tmp = (const uint16_t *) husart->pTxBuffPtr;
       husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
       husart->pTxBuffPtr += 2U;
       husart->TxXferCount--;
@@ -3137,7 +3166,7 @@ static void USART_TxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart)
 static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
 {
   const HAL_USART_StateTypeDef state = husart->State;
-  uint16_t *tmp;
+  const uint16_t *tmp;
   uint16_t  nb_tx_data;
 
   /* Check that a Tx process is ongoing */
@@ -3158,7 +3187,7 @@ static void USART_TxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
       }
       else if (__HAL_USART_GET_FLAG(husart, USART_FLAG_TXFNF) == SET)
       {
-        tmp = (uint16_t *) husart->pTxBuffPtr;
+        tmp = (const uint16_t *) husart->pTxBuffPtr;
         husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU);
         husart->pTxBuffPtr += 2U;
         husart->TxXferCount--;
@@ -3690,4 +3719,3 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h
index 6092ebe312..518c0aa35b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -127,7 +126,7 @@ typedef struct __USART_HandleTypeDef
 
   USART_InitTypeDef             Init;                    /*!< USART communication parameters      */
 
-  uint8_t                       *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
+  const uint8_t                 *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */
 
   uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */
 
@@ -145,7 +144,7 @@ typedef struct __USART_HandleTypeDef
 
   uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */
 
-  uint32_t                      SlaveMode;               /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
+  uint32_t                      SlaveMode;               /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value
                                                               of @ref USARTEx_Slave_Mode */
 
   uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value
@@ -1113,17 +1112,18 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
   */
 
 /* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size,
+                                     uint32_t Timeout);
 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
                                             uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
                                                uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
                                                 uint16_t Size);
 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
@@ -1150,8 +1150,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
   */
 
 /* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
+HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart);
+uint32_t               HAL_USART_GetError(const USART_HandleTypeDef *husart);
 
 /**
   * @}
@@ -1175,4 +1175,3 @@ uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
 
 #endif /* STM32H7xx_HAL_USART_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c
index 2bdc87e21d..b1a916da86 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c
@@ -8,6 +8,17 @@
   *           + Peripheral Control functions
   *
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                ##### USART peripheral extended features  #####
@@ -26,17 +37,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -539,4 +539,3 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart)
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h
index 769132696f..4db656699c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -46,7 +45,7 @@ extern "C" {
   * @{
   */
 #define USART_WORDLENGTH_7B                  (USART_CR1_M1)   /*!< 7-bit long USART frame */
-#define USART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long USART frame */
+#define USART_WORDLENGTH_8B                  (0x00000000U)    /*!< 8-bit long USART frame */
 #define USART_WORDLENGTH_9B                  (USART_CR1_M0)   /*!< 9-bit long USART frame */
 /**
   * @}
@@ -281,4 +280,3 @@ HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, ui
 
 #endif /* STM32H7xx_HAL_USART_EX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c
index fbcb267b2d..4eed817e5d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c
@@ -7,6 +7,17 @@
   *          functionalities of the Window Watchdog (WWDG) peripheral:
   *           + Initialization and Configuration functions
   *           + IO operation functions
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                       ##### WWDG Specific features #####
@@ -64,7 +75,7 @@
     (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
     (+) Configure the WWDG prescaler, refresh window value, counter value and early
         interrupt status using HAL_WWDG_Init() function. This will automatically
-        enable WWDG and start its downcounter. Time reference can be taken from 
+        enable WWDG and start its downcounter. Time reference can be taken from
         function exit. Care must be taken to provide a counter value
         greater than 0x40 to prevent generation of immediate reset.
     (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is
@@ -121,17 +132,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -427,5 +427,3 @@ __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h
index 061a62fc4e..8f2e4dc190 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -192,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer t
 
 /**
   * @brief  Enable the WWDG early wakeup interrupt.
-  * @param  __HANDLE__: WWDG handle
+  * @param  __HANDLE__     WWDG handle
   * @param  __INTERRUPT__  specifies the interrupt to enable.
   *         This parameter can be one of the following values:
   *            @arg WWDG_IT_EWI: Early wakeup interrupt
@@ -305,5 +304,3 @@ void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
 #endif
 
 #endif /* STM32H7xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c
index 1ce67c4330..86ef0277a2 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -208,6 +207,7 @@
 
 /* Check of parameters for configuration of ADC hierarchical scope:           */
 /* ADC group injected                                                         */
+#if defined(STM32H745xx) || defined(STM32H745xG) || defined(STM32H742xx) || defined(STM32H743xx) || defined(STM32H747xG) || defined(STM32H747xx) || defined(STM32H750xx) || defined(STM32H753xx) || defined(STM32H755xx) || defined(STM32H757xx)
 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
   (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
@@ -232,6 +232,30 @@
    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)                \
    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)                \
   )
+#else
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
+  (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)                \
+  )
+#endif
 
 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
   (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
@@ -489,11 +513,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
   /* Disable ADC instance if not already disabled.                            */
   if (LL_ADC_IsEnabled(ADCx) == 1UL)
   {
-    /* Set ADC group regular trigger source to SW start to ensure to not      */
-    /* have an external trigger event occurring during the conversion stop    */
-    /* ADC disable process.                                                   */
-    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
-
     /* Stop potential ADC conversion on going on ADC group regular.           */
     if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
     {
@@ -503,11 +522,6 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
       }
     }
 
-    /* Set ADC group injected trigger source to SW start to ensure to not     */
-    /* have an external trigger event occurring during the conversion stop    */
-    /* ADC disable process.                                                   */
-    LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
-
     /* Stop potential ADC conversion on going on ADC group injected.          */
     if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
     {
@@ -823,6 +837,19 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
     /*    - Set ADC data resolution                                           */
     /*    - Set ADC conversion data alignment                                 */
     /*    - Set ADC low power mode                                            */
+#if defined(ADC_VER_V5_V90)
+    if(ADCx==ADC3)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC3_CFGR_RES
+                 | ADC_CFGR_AUTDLY
+                 ,
+                 ((__LL_ADC12_RESOLUTION_TO_ADC3(ADC_InitStruct->Resolution)  & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL)
+                 | ADC_InitStruct->LowPowerMode
+                );
+    }
+    else
+    {
     MODIFY_REG(ADCx->CFGR,
                ADC_CFGR_RES
                | ADC_CFGR_AUTDLY
@@ -830,6 +857,16 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
                ADC_InitStruct->Resolution
                | ADC_InitStruct->LowPowerMode
               );
+    }
+#else
+    MODIFY_REG(ADCx->CFGR,
+               ADC_CFGR_RES
+               | ADC_CFGR_AUTDLY
+               ,
+               ADC_InitStruct->Resolution
+               | ADC_InitStruct->LowPowerMode
+              );
+#endif
 
     MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LSHIFT, ADC_InitStruct->LeftBitShift);
   }
@@ -900,6 +937,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
   if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
   {
     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+    /* ADC group regular continuous mode and discontinuous mode                 */
+    /* can not be enabled simultenaeously                                       */
+    assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+                 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
   }
   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
   assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
@@ -1121,4 +1163,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h
index f12b52a703..ac75a15318 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -387,7 +386,14 @@ extern "C" {
 #endif /* ADC_VER_V5_3 */
 
 #define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#if defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) 
+#define TEMPSENSOR_CAL2_TEMP               ((((DBGMCU->IDCODE) >> 16) <= ((uint32_t)0x1003)) ? 110L : 130L)            /* Internal temperature sensor , 
+                                           temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
+                                            110 °C for revision Y and 130 °C for revision V (tolerance: +-5 DegC) (unit: DegC). */
+#else
+#define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Internal temperature sensor, temperature at which temperature sensor has been
+                                           calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#endif /* defined (STM32H742xx) || defined (STM32H743xx) || defined (STM32H753xx) */
 #define TEMPSENSOR_CAL_VREFANALOG          (3300UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
 
 /* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */
@@ -402,6 +408,14 @@ extern "C" {
   * @}
   */
 
+/** @defgroup ADC_LL_Alias_definition  ADC Alias definition
+  * @{
+  */
+#define LL_ADC_SetChannelPreSelection  LL_ADC_SetChannelPreselection    /* Alias of LL_ADC_SetChannelPreselection for backward compatibility. */
+
+/**
+  * @}
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
@@ -638,6 +652,7 @@ typedef struct
 #define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
 #define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
 #define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
+#define LL_ADC_FLAG_LDORDY                 ADC_ISR_LDORDY     /*!< ADC flag ADC LDO output voltage ready bit */
 #define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
 #define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
 #define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */
@@ -895,7 +910,7 @@ typedef struct
 /**
   * @}
   */
-#endif
+#endif /* ADC_VER_V5_V90 */
 
 #endif /* ADC_VER_V5_V90 */
 
@@ -941,7 +956,7 @@ typedef struct
 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
 #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
 #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
-#endif
+#endif /* ADC_VER_V5_V90 */
 #else
 /*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */
 #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */
@@ -1014,7 +1029,7 @@ typedef struct
                                                                                  Trigger falling edge = stop sampling and start conversion. On devices STM32H72xx and STM32H73xx */
 /**
   * @}
-  */ 
+  */
 #endif /* ADC_VER_V5_V90 */
 
 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
@@ -1048,7 +1063,7 @@ typedef struct
 /**
   * @}
   */
-#endif
+#endif /* ADC_VER_V5_V90 */
 
 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
 * @{
@@ -1141,8 +1156,10 @@ typedef struct
 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
+#if defined(HRTIM1)
 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                                   /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
+#endif /* HRTIM1 */
 #define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
@@ -1361,14 +1378,14 @@ typedef struct
 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
   * @{
   */
-#define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                                                   /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_2SAMPLES      (                                          ADC3_TR1_AWDFILT_0)   /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_3SAMPLES      (                     ADC3_TR1_AWDFILT_1                     )   /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_4SAMPLES      (                     ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)   /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC3_TR1_AWDFILT_2                                          )   /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC3_TR1_AWDFILT_2 |                      ADC3_TR1_AWDFILT_0)   /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1                     )   /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
-#define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)   /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                                                   /*!< ADC analog watchdog no filtering, one out-of-window sample is needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_2SAMPLES      (                                          ADC3_TR1_AWDFILT_0)   /*!< ADC analog watchdog 2 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_3SAMPLES      (                     ADC3_TR1_AWDFILT_1                     )   /*!< ADC analog watchdog 3 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_4SAMPLES      (                     ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)   /*!< ADC analog watchdog 4 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC3_TR1_AWDFILT_2                                          )   /*!< ADC analog watchdog 5 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC3_TR1_AWDFILT_2 |                      ADC3_TR1_AWDFILT_0)   /*!< ADC analog watchdog 6 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1                     )   /*!< ADC analog watchdog 7 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
+#define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC3_TR1_AWDFILT_2 | ADC3_TR1_AWDFILT_1 | ADC3_TR1_AWDFILT_0)   /*!< ADC analog watchdog 8 consecutives out-of-window samples are needed to raise flag or interrupt. On ADC3 of devices STM32H72xx and STM32H73xx */
 /**
   * @}
   */
@@ -2738,6 +2755,65 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx
   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
 }
 
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Add paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      VBATEN        LL_ADC_SetCommonPathInternalChAdd
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Remove paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      VBATEN        LL_ADC_SetCommonPathInternalChRem
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
 /**
   * @}
   */
@@ -2782,7 +2858,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx
   */
 __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
 {
-#if defined(ADC_VER_V5_V90)  
+#if defined(ADC_VER_V5_V90)
   MODIFY_REG(ADCx->CALFACT_RES13,
              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
@@ -2790,7 +2866,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32
   MODIFY_REG(ADCx->CALFACT,
              SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
              CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -2821,7 +2897,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui
   return (uint32_t)(READ_BIT(ADCx->CALFACT_RES13, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
 #else
   return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -2859,7 +2935,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32
       timeout_cpu_cycles--;
     }
   }
-#else /* ADC_VER_V5_V90 */
+#else
   uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;
   MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);
   MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);
@@ -2867,7 +2943,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32
   {
     timeout_cpu_cycles--;
   }
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -2898,7 +2974,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, ui
   return (uint32_t)(READ_BIT(ADCx->CALFACT2_RES14, ADC_CALFACT2_LINCALFACT));
 #else
   return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 /**
   * @brief  Set ADC resolution.
@@ -2927,7 +3003,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution
 #elif defined(ADC_VER_V5_V90)
   if (ADCx == ADC3)
   {
-    MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, (((Resolution & 0x10UL) | 0x08UL | (Resolution & 0x04UL))  & 0x00000018UL));
+    MODIFY_REG(ADCx->CFGR, ADC3_CFGR_RES, ((__LL_ADC12_RESOLUTION_TO_ADC3(Resolution)  & (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) << 1UL));
   }
   else
   {
@@ -2974,12 +3050,14 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution
   * @rmtoll CFGR     RES            LL_ADC_GetResolution
   * @param  ADCx ADC instance
   * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_ADC_RESOLUTION_16B
+  *         @arg @ref LL_ADC_RESOLUTION_16B (1)
   *         @arg @ref LL_ADC_RESOLUTION_14B
   *         @arg @ref LL_ADC_RESOLUTION_12B
   *         @arg @ref LL_ADC_RESOLUTION_10B
   *         @arg @ref LL_ADC_RESOLUTION_8B
-   *         @arg @ref LL_ADC_RESOLUTION_6B   **Value available for ADC3 on STM32H72x/3x devices only **
+  *         @arg @ref LL_ADC_RESOLUTION_6B  (2)
+  *         (1): Specific to ADC instance: ADC1, ADC2
+  *         (2): Specific to ADC instance: ADC3
   */
 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
 {
@@ -3137,15 +3215,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
   * @note   Caution: Channel selections is dependent to ADC instance and IP version:
   *         For STM32H72x/3x This is applicable only for ADC1/ADC2
   *         For Rest of STM32H7xxx This is applicable only all the ADCs instances.
-  * 
+  *
   * @param  ADCx ADC instance
   * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_ADC_CHANNEL_0           
-  *         @arg @ref LL_ADC_CHANNEL_1           
-  *         @arg @ref LL_ADC_CHANNEL_2           
-  *         @arg @ref LL_ADC_CHANNEL_3           
-  *         @arg @ref LL_ADC_CHANNEL_4           
-  *         @arg @ref LL_ADC_CHANNEL_5           
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
   *         @arg @ref LL_ADC_CHANNEL_6
   *         @arg @ref LL_ADC_CHANNEL_7
   *         @arg @ref LL_ADC_CHANNEL_8
@@ -3162,7 +3240,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
   *         @arg @ref LL_ADC_CHANNEL_19
   * @retval None
   */
-__STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t Channel)
+__STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
 {
 #if defined(ADC_VER_V5_V90)
     if (ADCx != ADC3)
@@ -3176,6 +3254,55 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C
 #endif /* ADC_VER_V5_V90 */
 }
 
+/**
+  * @brief  Gets ADC pre-selected Channel.
+  * @note   This function gets the pre-selected ADC channel.
+  * @note   Caution: Channel selections is dependent to ADC instance and IP version:
+  *         For STM32H72x/3x This is applicable only for ADC1/ADC2
+  *         For Rest of STM32H7xxx This is applicable on all the ADCs instances.
+  *
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  * @retval the preselection state of Channel (!= 0 : pre-selected, == 0 : not pre-selected)
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelPreselection(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+#if defined(ADC_VER_V5_V90)
+    if (ADCx != ADC3)
+    {
+    /* Gets preselected ADC channel */
+    return (uint32_t)(READ_BIT(ADCx->PCSEL_RES0, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
+    }
+    else
+    {
+    return 0UL;
+    }
+#else
+    /* Gets preselected ADC channel */
+    return (uint32_t)(READ_BIT(ADCx->PCSEL, 1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(Channel) & 0x1FUL)));
+#endif /* ADC_VER_V5_V90 */
+}
+
 /**
   * @brief  Set ADC selected offset number 1, 2, 3 or 4.
   * @note   This function set the 2 items of offset configuration:
@@ -3185,8 +3312,8 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C
   *         - Offset level (offset to be subtracted from the raw
   *           converted data).
   * @note   Caution: Offset format is dependent to ADC resolution:
-  *         offset has to be left-aligned on bit 11, the LSB (right bits)
-  *         are set to 0.
+  *         offset has to be left-aligned on bit 15 (handling maximum ADC resolution 16 bit),
+  *         the LSB (right bits) are set to 0.
   * @note   This function enables the offset, by default. It can be forced
   *         to disable state using function LL_ADC_SetOffsetState().
   * @note   If a channel is mapped on several offsets numbers, only the offset
@@ -3246,7 +3373,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C
   *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
   *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
   *             Other channels are slow channels (conversion rate: refer to reference manual).
-  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
   * @retval None
   */
 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
@@ -3343,8 +3470,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off
   *         Offset level (offset to be subtracted from the raw
   *         converted data).
   * @note   Caution: Offset format is dependent to ADC resolution:
-  *         offset has to be left-aligned on bit 11, the LSB (right bits)
-  *         are set to 0.
+  *         offset has to be left-aligned on bit 15 (handling maximum ADC resolution 16 bit),
+  *         the LSB (right bits) are set to 0.
   * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
   *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
   *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
@@ -3355,7 +3482,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off
   *         @arg @ref LL_ADC_OFFSET_2
   *         @arg @ref LL_ADC_OFFSET_3
   *         @arg @ref LL_ADC_OFFSET_4
-  * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
   */
 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
 {
@@ -3595,7 +3722,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset
     return (uint32_t) READ_BIT(*preg, ADC3_OFR1_OFFSETPOS);
   }
   else
-  { 
+  {
     return 0UL;
   }
 }
@@ -4395,7 +4522,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx)
     return (uint32_t)(READ_BIT(ADCx->CFGR, ADC3_CFGR_DMAEN | ADC3_CFGR_DMACFG));
   }
    else
-  { 
+  {
     return 0UL;
   }
 }
@@ -5450,7 +5577,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha
   MODIFY_REG(ADCx->DIFSEL,
              Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
              (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -5498,11 +5625,11 @@ __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Cha
   */
 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
 {
-#if defined(ADC_VER_V5_V90)  
+#if defined(ADC_VER_V5_V90)
   return (uint32_t)(READ_BIT(ADCx->DIFSEL_RES12, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
-#else  
+#else
   return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -5905,8 +6032,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
     __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
     MODIFY_REG(*preg,
-               AWDThresholdsHighLow,
-               AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+               (ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)),
+               AWDThresholdValue << (((AWDThresholdsHighLow * ADC3_TR1_HT1) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
   }
   else
   {
@@ -5961,18 +6088,31 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
 {
 #if defined(ADC_VER_V5_V90)
-  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
-                                                            + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
-                                                            + (AWDThresholdsHighLow));
+  if (ADCx == ADC3)
+  {
+    const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
+                                                     ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
-  return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
+    return (uint32_t)(READ_BIT(*preg,
+                               (ADC3_TR1_LT1 << (AWDThresholdsHighLow * ADC3_TR1_HT1_Pos)))
+                      >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
+                          & ~(AWDThresholdsHighLow & ADC3_TR1_LT1)));
+  }
+  else
+  {
+    const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+                                                                   + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+                                                                   + (AWDThresholdsHighLow));
+
+    return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
+  }
 #else
    const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
                                                                    + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
                                                                    + (AWDThresholdsHighLow));
 
   return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 #if defined(ADC_VER_V5_V90)
@@ -6030,7 +6170,8 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t
   /* containing other bits reserved for other purpose.                        */
   if (ADCx == ADC3)
   {
-    uint32_t __IO *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+    __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1_TR1,
+                                               ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
 
     MODIFY_REG(*preg,
                ADC3_TR1_HT1 | ADC3_TR1_LT1,
@@ -6242,6 +6383,15 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
   *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
   * @param  ADCx ADC instance
   * @param  Ratio This parameter can be in the range from 1 to 1024.
+  *         In the case of ADC3 can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
   * @param  Shift This parameter can be one of the following values:
   *         @arg @ref LL_ADC_OVS_SHIFT_NONE
   *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
@@ -6259,7 +6409,20 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
   */
 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
 {
+#if defined(ADC_VER_V5_V90)
+  if(ADCx==ADC3)
+  {
+    MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC3_CFGR2_OVSR), (Shift | Ratio));
+  }
+  else
+  {
+    MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
+  }
+#else
+
   MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));
+
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -6268,10 +6431,32 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint
   * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
   * @param  ADCx ADC instance
   * @retval Ratio This parameter can be in the from 1 to 1024.
+  *         In the case of ADC3 can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
 */
 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
 {
+#if defined(ADC_VER_V5_V90)
+  if(ADCx==ADC3)
+  {
+    return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC3_CFGR2_OVSR));
+  }
+  else
+  {
+    return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
+  }
+#else
+
   return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)) + (1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);
+
+#endif /* ADC_VER_V5_V90 */
 }
 
 /**
@@ -6337,7 +6522,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
   {
     MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
   }
-#endif
+#endif /* ADC_VER_V5_V90 */
 }
 
 
@@ -7356,6 +7541,17 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
   return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
 }
 
+/**
+  * @brief  Get flag ADC LDO output voltage ready bit.
+  * @rmtoll ISR      LDORDY          LL_ADC_IsActiveFlag_LDORDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_LDORDY(ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_LDORDY) == (LL_ADC_FLAG_LDORDY)) ? 1UL : 0UL);
+}
+
 /**
   * @brief  Get flag ADC analog watchdog 1 flag
   * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
@@ -8214,4 +8410,3 @@ void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
 
 #endif /* STM32H7xx_LL_ADC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.c
index d9dfcb716a..9ba6ff0fef 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -45,39 +44,45 @@
 /** @addtogroup BDMA_LL_Private_Macros
   * @{
   */
-#define IS_LL_BDMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
-                                                  ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
-                                                  ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
+#define IS_LL_BDMA_DIRECTION(__VALUE__)                      (((__VALUE__) == LL_BDMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                              ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                              ((__VALUE__) == LL_BDMA_DIRECTION_MEMORY_TO_MEMORY))
 
-#define IS_LL_BDMA_MODE(__VALUE__)               (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
-                                                  ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
+#define IS_LL_BDMA_MODE(__VALUE__)                           (((__VALUE__) == LL_BDMA_MODE_NORMAL) || \
+                                                              ((__VALUE__) == LL_BDMA_MODE_CIRCULAR))
 
-#define IS_LL_BDMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
-                                                  ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
+#define IS_LL_BDMA_PERIPHINCMODE(__VALUE__)                  (((__VALUE__) == LL_BDMA_PERIPH_INCREMENT) || \
+                                                              ((__VALUE__) == LL_BDMA_PERIPH_NOINCREMENT))
 
-#define IS_LL_BDMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
-                                                  ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
+#define IS_LL_BDMA_MEMORYINCMODE(__VALUE__)                  (((__VALUE__) == LL_BDMA_MEMORY_INCREMENT) || \
+                                                              ((__VALUE__) == LL_BDMA_MEMORY_NOINCREMENT))
 
-#define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE)      || \
-                                                  ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD)  || \
-                                                  ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
+#define IS_LL_BDMA_PERIPHDATASIZE(__VALUE__)                 (((__VALUE__) == LL_BDMA_PDATAALIGN_BYTE)      || \
+                                                              ((__VALUE__) == LL_BDMA_PDATAALIGN_HALFWORD)  || \
+                                                              ((__VALUE__) == LL_BDMA_PDATAALIGN_WORD))
 
-#define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE)      || \
-                                                  ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD)  || \
-                                                  ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
+#define IS_LL_BDMA_MEMORYDATASIZE(__VALUE__)                 (((__VALUE__) == LL_BDMA_MDATAALIGN_BYTE)      || \
+                                                              ((__VALUE__) == LL_BDMA_MDATAALIGN_HALFWORD)  || \
+                                                              ((__VALUE__) == LL_BDMA_MDATAALIGN_WORD))
 
-#define IS_LL_BDMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+#define IS_LL_BDMA_NBDATA(__VALUE__)                        ((__VALUE__)  <= 0x0000FFFFU)
 
 #if defined(ADC3)
-#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
+#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)                 ((__VALUE__) <= LL_DMAMUX2_REQ_ADC3)
 #else
-#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
+#define IS_LL_BDMA_PERIPHREQUEST(__VALUE__)                 ((__VALUE__) <= LL_DMAMUX2_REQ_DFSDM2_FLT0)
 #endif /* ADC3 */
 
-#define IS_LL_BDMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_BDMA_PRIORITY_LOW)    || \
-                                                  ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
-                                                  ((__VALUE__) == LL_BDMA_PRIORITY_HIGH)   || \
-                                                  ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
+#define IS_LL_BDMA_PRIORITY(__VALUE__)                       (((__VALUE__) == LL_BDMA_PRIORITY_LOW)    || \
+                                                              ((__VALUE__) == LL_BDMA_PRIORITY_MEDIUM) || \
+                                                              ((__VALUE__) == LL_BDMA_PRIORITY_HIGH)   || \
+                                                              ((__VALUE__) == LL_BDMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_BDMA_DOUBLEBUFFER_MODE(__VALUE__)              (((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_DISABLE) || \
+                                                              ((__VALUE__) == LL_BDMA_DOUBLEBUFFER_MODE_ENABLE))
+
+#define IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(__VALUE__)         (((__VALUE__) == LL_BDMA_CURRENTTARGETMEM0)    || \
+                                                              ((__VALUE__) == LL_BDMA_CURRENTTARGETMEM1))
 
 #define IS_LL_BDMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == BDMA) && \
                                                              (((CHANNEL) == LL_BDMA_CHANNEL_0) || \
@@ -254,26 +259,33 @@ uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef
   assert_param(IS_LL_BDMA_NBDATA(BDMA_InitStruct->NbData));
   assert_param(IS_LL_BDMA_PERIPHREQUEST(BDMA_InitStruct->PeriphRequest));
   assert_param(IS_LL_BDMA_PRIORITY(BDMA_InitStruct->Priority));
+  assert_param(IS_LL_BDMA_DOUBLEBUFFER_MODE(BDMA_InitStruct->DoubleBufferMode));
+  assert_param(IS_LL_BDMA_DOUBLEBUFFER_TARGETMEM(BDMA_InitStruct->TargetMemInDoubleBufferMode));
 
   /*---------------------------- DMAx CCR Configuration ------------------------
    * Configure DMAx_Channely: data transfer direction, data transfer mode,
    *                          peripheral and memory increment mode,
    *                          data size alignment and  priority level with parameters :
-   * - Direction:      BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
-   * - Mode:           BDMA_CCR_CIRC bit
-   * - PeriphOrM2MSrcIncMode:  BDMA_CCR_PINC bit
-   * - MemoryOrM2MDstIncMode:  BDMA_CCR_MINC bit
-   * - PeriphOrM2MSrcDataSize: BDMA_CCR_PSIZE[1:0] bits
-   * - MemoryOrM2MDstDataSize: BDMA_CCR_MSIZE[1:0] bits
-   * - Priority:               BDMA_CCR_PL[1:0] bits
+   * - Direction:                   BDMA_CCR_DIR and BDMA_CCR_MEM2MEM bits
+   * - Mode:                        BDMA_CCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:       BDMA_CCR_PINC bit
+   * - MemoryOrM2MDstIncMode:       BDMA_CCR_MINC bit
+   * - PeriphOrM2MSrcDataSize:      BDMA_CCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize:      BDMA_CCR_MSIZE[1:0] bits
+   * - Priority:                    BDMA_CCR_PL[1:0] bits
+   * - DoubleBufferMode:            BDMA_CCR_DBM bit
+   * - TargetMemInDoubleBufferMode: BDMA_CCR_CT bit
    */
-  LL_BDMA_ConfigTransfer(BDMAx, Channel, BDMA_InitStruct->Direction              | \
+  LL_BDMA_ConfigTransfer(BDMAx, Channel,
+                         BDMA_InitStruct->Direction              | \
                          BDMA_InitStruct->Mode                   | \
                          BDMA_InitStruct->PeriphOrM2MSrcIncMode  | \
                          BDMA_InitStruct->MemoryOrM2MDstIncMode  | \
                          BDMA_InitStruct->PeriphOrM2MSrcDataSize | \
                          BDMA_InitStruct->MemoryOrM2MDstDataSize | \
-                         BDMA_InitStruct->Priority);
+                         BDMA_InitStruct->Priority               | \
+                         BDMA_InitStruct->DoubleBufferMode       | \
+                         BDMA_InitStruct->TargetMemInDoubleBufferMode);
 
   /*-------------------------- DMAx CMAR Configuration -------------------------
    * Configure the memory or destination base address with parameter :
@@ -310,17 +322,19 @@ uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef
 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
 {
   /* Set BDMA_InitStruct fields to default values */
-  BDMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
-  BDMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
-  BDMA_InitStruct->Direction              = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
-  BDMA_InitStruct->Mode                   = LL_BDMA_MODE_NORMAL;
-  BDMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_BDMA_PERIPH_NOINCREMENT;
-  BDMA_InitStruct->MemoryOrM2MDstIncMode  = LL_BDMA_MEMORY_NOINCREMENT;
-  BDMA_InitStruct->PeriphOrM2MSrcDataSize = LL_BDMA_PDATAALIGN_BYTE;
-  BDMA_InitStruct->MemoryOrM2MDstDataSize = LL_BDMA_MDATAALIGN_BYTE;
-  BDMA_InitStruct->NbData                 = 0x00000000U;
-  BDMA_InitStruct->PeriphRequest          = LL_DMAMUX2_REQ_MEM2MEM;
-  BDMA_InitStruct->Priority               = LL_BDMA_PRIORITY_LOW;
+  BDMA_InitStruct->PeriphOrM2MSrcAddress       = 0x00000000U;
+  BDMA_InitStruct->MemoryOrM2MDstAddress       = 0x00000000U;
+  BDMA_InitStruct->Direction                   = LL_BDMA_DIRECTION_PERIPH_TO_MEMORY;
+  BDMA_InitStruct->Mode                        = LL_BDMA_MODE_NORMAL;
+  BDMA_InitStruct->PeriphOrM2MSrcIncMode       = LL_BDMA_PERIPH_NOINCREMENT;
+  BDMA_InitStruct->MemoryOrM2MDstIncMode       = LL_BDMA_MEMORY_NOINCREMENT;
+  BDMA_InitStruct->PeriphOrM2MSrcDataSize      = LL_BDMA_PDATAALIGN_BYTE;
+  BDMA_InitStruct->MemoryOrM2MDstDataSize      = LL_BDMA_MDATAALIGN_BYTE;
+  BDMA_InitStruct->NbData                      = 0x00000000U;
+  BDMA_InitStruct->PeriphRequest               = LL_DMAMUX2_REQ_MEM2MEM;
+  BDMA_InitStruct->Priority                    = LL_BDMA_PRIORITY_LOW;
+  BDMA_InitStruct->DoubleBufferMode            = LL_BDMA_DOUBLEBUFFER_MODE_DISABLE;
+  BDMA_InitStruct->TargetMemInDoubleBufferMode = LL_BDMA_CURRENTTARGETMEM0;
 }
 
 /**
@@ -343,4 +357,3 @@ void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h
index 36910f2772..8db1b7cc6f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -62,10 +61,15 @@ static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
 
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
+/** @defgroup BDMA_LL_Private_Macros BDMA Private Macros
+  * @{
+  */
 #if !defined(UNUSED)
 #define UNUSED(x) ((void)(x))
 #endif
-
+/**
+  * @}
+  */
 /* Exported types ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure
@@ -73,70 +77,79 @@ static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
   */
 typedef struct
 {
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for BDMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
+  uint32_t PeriphOrM2MSrcAddress;       /*!< Specifies the peripheral base address for BDMA transfer
+                                             or as Source base address in case of memory to memory transfer direction.
 
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+                                             This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
 
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
+  uint32_t MemoryOrM2MDstAddress;       /*!< Specifies the memory base address for DMA transfer
+                                             or as Destination base address in case of memory to memory transfer direction.
 
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+                                             This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
 
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
+  uint32_t Direction;                   /*!< Specifies if the data will be transferred from memory to peripheral,
+                                             from memory to memory or from peripheral to memory.
+                                             This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
 
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref BDMA_LL_EC_MODE
-                                        @note: The circular buffer mode cannot be used if the memory to memory
-                                               data transfer direction is configured on the selected Channel
+  uint32_t Mode;                        /*!< Specifies the normal or circular operation mode.
+                                             This parameter can be a value of @ref BDMA_LL_EC_MODE
+                                             @note: The circular buffer mode cannot be used if the memory to memory
+                                                    data transfer direction is configured on the selected Channel
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
 
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref BDMA_LL_EC_PERIPH
+  uint32_t PeriphOrM2MSrcIncMode;       /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                             is incremented or not.
+                                             This parameter can be a value of @ref BDMA_LL_EC_PERIPH
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
 
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref BDMA_LL_EC_MEMORY
+  uint32_t MemoryOrM2MDstIncMode;       /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                             is incremented or not.
+                                             This parameter can be a value of @ref BDMA_LL_EC_MEMORY
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
 
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
+  uint32_t PeriphOrM2MSrcDataSize;      /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                             in case of memory to memory transfer direction.
+                                             This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
 
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
+  uint32_t MemoryOrM2MDstDataSize;      /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                             in case of memory to memory transfer direction.
+                                             This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
 
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+  uint32_t NbData;                      /*!< Specifies the number of data to transfer, in data unit.
+                                             The data unit is equal to the source buffer configuration set in PeripheralSize
+                                             or MemorySize parameters depending in the transfer direction.
+                                             This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
 
-  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
-                                        This parameter can be a value of @ref DMAMUX2_Request_selection
+  uint32_t PeriphRequest;               /*!< Specifies the peripheral request.
+                                             This parameter can be a value of @ref DMAMUX2_Request_selection
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
 
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
+  uint32_t Priority;                    /*!< Specifies the channel priority level.
+                                             This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
 
-                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
 
+  uint32_t DoubleBufferMode;            /*!< Specifies the double buffer mode.
+                                             This parameter can be a value of @ref BDMA_LL_EC_DOUBLEBUFFER_MODE
+
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_EnableDoubleBufferMode() & LL_BDMA_DisableDoubleBufferMode(). */
+
+  uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
+                                             This parameter can be a value of @ref BDMA_LL_EC_CURRENTTARGETMEM
+
+                                             This feature can be modified afterwards using unitary function @ref LL_BDMA_SetCurrentTargetMem(). */
 } LL_BDMA_InitTypeDef;
 /**
   * @}
@@ -271,7 +284,7 @@ typedef struct
   * @}
   */
 
-/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
+/** @defgroup BDMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
   * @{
   */
 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U              /*!< Disable double buffering mode        */
@@ -280,6 +293,15 @@ typedef struct
   * @}
   */
 
+/** @defgroup BDMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_BDMA_CURRENTTARGETMEM0          0x00000000U              /*!< Set CurrentTarget Memory to Memory 0 */
+#define LL_BDMA_CURRENTTARGETMEM1          BDMA_CCR_CT              /*!< Set CurrentTarget Memory to Memory 1 */
+/**
+  * @}
+  */
+
 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
   * @{
   */
@@ -329,15 +351,10 @@ typedef struct
   * @}
   */
 
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
-  * @{
-  */
-#define LL_BDMA_CURRENTTARGETMEM0          0x00000000U              /*!< Set CurrentTarget Memory to Memory 0 */
-#define LL_BDMA_CURRENTTARGETMEM1          BDMA_CCR_CT              /*!< Set CurrentTarget Memory to Memory 1 */
+
 /**
   * @}
   */
-
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros
   * @{
@@ -542,7 +559,9 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t
   *         CCR          MINC          LL_BDMA_ConfigTransfer\n
   *         CCR          PSIZE         LL_BDMA_ConfigTransfer\n
   *         CCR          MSIZE         LL_BDMA_ConfigTransfer\n
-  *         CCR          PL            LL_BDMA_ConfigTransfer
+  *         CCR          PL            LL_BDMA_ConfigTransfer\n
+  *         CCR          DBM           LL_BDMA_ConfigTransfer\n
+  *         CCR          CT            LL_BDMA_ConfigTransfer
   * @param  BDMAx BDMA Instance
   * @param  Channel This parameter can be one of the following values:
   *         @arg @ref LL_BDMA_CHANNEL_0
@@ -561,6 +580,8 @@ __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t
   *         @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
   *         @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
   *         @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
+  *         @arg @ref LL_BDMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_BDMA_DOUBLEBUFFER_MODE_ENABLE
+  *         @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1
   * @retval None
   */
 __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
@@ -568,8 +589,8 @@ __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channe
   uint32_t bdma_base_addr = (uint32_t)BDMAx;
 
   MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
-             BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,
-             Configuration);
+             BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL | \
+             BDMA_CCR_DBM | BDMA_CCR_CT, Configuration);
 }
 
 /**
@@ -1087,6 +1108,28 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32
   CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
 }
 
+/**
+  * @brief  Check if double buffer mode is enabled or not.
+  * @rmtoll CCR          DBM           LL_BDMA_IsEnabledDoubleBufferMode
+  * @param  BDMAx BDMAx Instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_BDMA_CHANNEL_0
+  *         @arg @ref LL_BDMA_CHANNEL_1
+  *         @arg @ref LL_BDMA_CHANNEL_2
+  *         @arg @ref LL_BDMA_CHANNEL_3
+  *         @arg @ref LL_BDMA_CHANNEL_4
+  *         @arg @ref LL_BDMA_CHANNEL_5
+  *         @arg @ref LL_BDMA_CHANNEL_6
+  *         @arg @ref LL_BDMA_CHANNEL_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)
+{
+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;
+
+  return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM) == (BDMA_CCR_DBM)) ? 1UL : 0UL);
+}
+
 /**
   * @brief  Configure the Source and Destination addresses.
   * @note   This API must not be called when the BDMA channel is enabled.
@@ -1817,6 +1860,10 @@ __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 0 global interrupt flag.
+  * @note Do not Clear Channel 0 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0,
+    LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF0         LL_BDMA_ClearFlag_GI0
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1828,6 +1875,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 1 global interrupt flag.
+  * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
+    LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF1         LL_BDMA_ClearFlag_GI1
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1839,6 +1890,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 2 global interrupt flag.
+  * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
+    LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF2         LL_BDMA_ClearFlag_GI2
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1850,6 +1905,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 3 global interrupt flag.
+  * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
+    LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF3         LL_BDMA_ClearFlag_GI3
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1861,6 +1920,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 4 global interrupt flag.
+  * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
+    LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF4         LL_BDMA_ClearFlag_GI4
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1872,6 +1935,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 5 global interrupt flag.
+  * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
+    LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF5         LL_BDMA_ClearFlag_GI5
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1883,6 +1950,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 6 global interrupt flag.
+  * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
+    LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF6         LL_BDMA_ClearFlag_GI6
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -1894,6 +1965,10 @@ __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
 
 /**
   * @brief  Clear Channel 7 global interrupt flag.
+  * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
+    Instead clear specific flags transfer complete, half transfer & transfer
+    error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
+    LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
   * @rmtoll IFCR         CGIF7         LL_BDMA_ClearFlag_GI7
   * @param  BDMAx BDMA Instance
   * @retval None
@@ -2403,18 +2478,9 @@ void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
   * @}
   */
 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* STM32H7xx_LL_BDMA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bus.h
index 022cf6d230..4f15c6efa6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bus.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bus.h
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32h7xx_ll_bus.h
   * @author  MCD Application Team
-  * @version $VERSION$
-  * @date    $DATE$
   * @brief   Header file of BUS LL module.
 
   @verbatim
@@ -25,14 +23,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -249,7 +245,7 @@ extern "C" {
 #define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN
 #if defined(RCC_APB3ENR_WWDGEN)
 #define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/
-#endif
+#endif /* RCC_APB3ENR_WWDGEN */
 /**
   * @}
   */
@@ -538,7 +534,7 @@ extern "C" {
   *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)
   *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)
   *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)
-  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)
+  *         AHB3ENR      GFXMMUEN      LL_AHB3_GRP1_EnableClock\n  (*)
   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n
   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)
   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)
@@ -588,7 +584,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
   *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMUEN      LL_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n
   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)
@@ -619,7 +615,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -634,7 +630,7 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
   *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMUEN      LL_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)
@@ -673,7 +669,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
   * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n
   *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n
   *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n
-  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n 
+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
   *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)
   *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)
   *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)
@@ -848,6 +844,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n
   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n
   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_EnableClock\n (*)
   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)
   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)
   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)
@@ -860,6 +857,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
   *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12
   *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)
@@ -913,7 +911,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -922,6 +920,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
   *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n
   *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n
   *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)
+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_DisableClock\n (*)
   *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)
   *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)
   *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)
@@ -1164,7 +1163,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -1211,9 +1210,9 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
   *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)
   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n
   *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset\n   (*)
   *         AHB2RSTR     FMACRST       LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ForceReset 
+  *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ForceReset
   * @param  Periphs This parameter can be a combination of the following values:
   *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI
   *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)
@@ -1241,7 +1240,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
   *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)
   *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n
   *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)
+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset\n (*)
   *         AHB2RSTR     FMACRST       LL_AHB2_GRP1_ReleaseReset\n
   *         AHB2RSTR     CORDICRST     LL_AHB2_GRP1_ReleaseReset
   * @param  Periphs This parameter can be a combination of the following values:
@@ -1434,7 +1433,7 @@ __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -1700,7 +1699,7 @@ __STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -1930,7 +1929,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -2302,7 +2301,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -2530,7 +2529,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -2860,7 +2859,7 @@ __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -3116,7 +3115,7 @@ __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
   *         @arg @ref LL_CLKAM_PERIPH_COMP12
   *         @arg @ref LL_CLKAM_PERIPH_VREF
   *         @arg @ref LL_CLKAM_PERIPH_RTC
-  *         @arg @ref LL_CLKAM_PERIPH_CRC (*) 
+  *         @arg @ref LL_CLKAM_PERIPH_CRC (*)
   *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
   *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
   *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
@@ -3178,7 +3177,7 @@ __STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)
   *         @arg @ref LL_CLKAM_PERIPH_COMP12
   *         @arg @ref LL_CLKAM_PERIPH_VREF
   *         @arg @ref LL_CLKAM_PERIPH_RTC
-  *         @arg @ref LL_CLKAM_PERIPH_CRC (*) 
+  *         @arg @ref LL_CLKAM_PERIPH_CRC (*)
   *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)
   *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)
   *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)
@@ -3211,8 +3210,49 @@ __STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)
 
 /**
   * @brief  Enable clock gating for AXI bus peripherals.
-  * @rmtoll
-  * @param :
+  * @rmtoll CKGAENR      AXICKG          LL_CKGA_Enable\n
+  *         CKGAENR      AHBCKG          LL_CKGA_Enable\n
+  *         CKGAENR      CPUCKG          LL_CKGA_Enable\n
+  *         CKGAENR      SDMMCCKG        LL_CKGA_Enable\n
+  *         CKGAENR      MDMACKG         LL_CKGA_Enable\n 
+  *         CKGAENR      DMA2DCKG        LL_CKGA_Enable\n 
+  *         CKGAENR      LTDCCKG         LL_CKGA_Enable\n 
+  *         CKGAENR      GFXMMUMCKG      LL_CKGA_Enable\n 
+  *         CKGAENR      AHB12CKG        LL_CKGA_Enable\n 
+  *         CKGAENR      AHB34CKG        LL_CKGA_Enable\n 
+  *         CKGAENR      FLIFTCKG        LL_CKGA_Enable\n 
+  *         CKGAENR      OCTOSPI2CKG     LL_CKGA_Enable\n
+  *         CKGAENR      FMCCKG          LL_CKGA_Enable\n
+  *         CKGAENR      OCTOSPI1CKG     LL_CKGA_Enable\n
+  *         CKGAENR      AXIRAM1CKG      LL_CKGA_Enable\n
+  *         CKGAENR      AXIRAM2CKG      LL_CKGA_Enable\n
+  *         CKGAENR      AXIRAM3CKG      LL_CKGA_Enable\n
+  *         CKGAENR      GFXMMUSCKG      LL_CKGA_Enable\n
+  *         CKGAENR      ECCRAMCKG       LL_CKGA_Enable\n
+  *         CKGAENR      EXTICKG         LL_CKGA_Enable\n
+  *         CKGAENR      JTAGCKG         LL_CKGA_Enable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CKGA_PERIPH_AXI
+  *         @arg @ref LL_CKGA_PERIPH_AHB
+  *         @arg @ref LL_CKGA_PERIPH_CPU
+  *         @arg @ref LL_CKGA_PERIPH_SDMMC
+  *         @arg @ref LL_CKGA_PERIPH_MDMA     
+  *         @arg @ref LL_CKGA_PERIPH_DMA2D   
+  *         @arg @ref LL_CKGA_PERIPH_LTDC   
+  *         @arg @ref LL_CKGA_PERIPH_GFXMMUM  
+  *         @arg @ref LL_CKGA_PERIPH_AHB12 
+  *         @arg @ref LL_CKGA_PERIPH_AHB34 
+  *         @arg @ref LL_CKGA_PERIPH_FLIFT  
+  *         @arg @ref LL_CKGA_PERIPH_OCTOSPI2
+  *         @arg @ref LL_CKGA_PERIPH_FMC 
+  *         @arg @ref LL_CKGA_PERIPH_OCTOSPI1
+  *         @arg @ref LL_CKGA_PERIPH_AXIRAM1 
+  *         @arg @ref LL_CKGA_PERIPH_AXIRAM2
+  *         @arg @ref LL_CKGA_PERIPH_AXIRAM3 
+  *         @arg @ref LL_CKGA_PERIPH_GFXMMUS
+  *         @arg @ref LL_CKGA_PERIPH_ECCRAM
+  *         @arg @ref LL_CKGA_PERIPH_EXTI
+  *         @arg @ref LL_CKGA_PERIPH_JTAG
   * @retval None
 */
 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
@@ -3230,8 +3270,49 @@ __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)
 
 /**
   * @brief  Disable  clock gating for AXI bus peripherals.
-  * @rmtoll
-  * @param :
+  * @rmtoll CKGAENR      AXICKG          LL_CKGA_Enable\n
+  *         CKGAENR      AHBCKG          LL_CKGA_Enable\n
+  *         CKGAENR      CPUCKG          LL_CKGA_Enable\n
+  *         CKGAENR      SDMMCCKG        LL_CKGA_Enable\n
+  *         CKGAENR      MDMACKG         LL_CKGA_Enable\n 
+  *         CKGAENR      DMA2DCKG        LL_CKGA_Enable\n 
+  *         CKGAENR      LTDCCKG         LL_CKGA_Enable\n 
+  *         CKGAENR      GFXMMUMCKG      LL_CKGA_Enable\n 
+  *         CKGAENR      AHB12CKG        LL_CKGA_Enable\n 
+  *         CKGAENR      AHB34CKG        LL_CKGA_Enable\n 
+  *         CKGAENR      FLIFTCKG        LL_CKGA_Enable\n 
+  *         CKGAENR      OCTOSPI2CKG     LL_CKGA_Enable\n
+  *         CKGAENR      FMCCKG          LL_CKGA_Enable\n
+  *         CKGAENR      OCTOSPI1CKG     LL_CKGA_Enable\n
+  *         CKGAENR      AXIRAM1CKG      LL_CKGA_Enable\n
+  *         CKGAENR      AXIRAM2CKG      LL_CKGA_Enable\n
+  *         CKGAENR      AXIRAM3CKG      LL_CKGA_Enable\n
+  *         CKGAENR      GFXMMUSCKG      LL_CKGA_Enable\n
+  *         CKGAENR      ECCRAMCKG       LL_CKGA_Enable\n
+  *         CKGAENR      EXTICKG         LL_CKGA_Enable\n
+  *         CKGAENR      JTAGCKG         LL_CKGA_Enable
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_CKGA_PERIPH_AXI
+  *         @arg @ref LL_CKGA_PERIPH_AHB
+  *         @arg @ref LL_CKGA_PERIPH_CPU
+  *         @arg @ref LL_CKGA_PERIPH_SDMMC
+  *         @arg @ref LL_CKGA_PERIPH_MDMA     
+  *         @arg @ref LL_CKGA_PERIPH_DMA2D   
+  *         @arg @ref LL_CKGA_PERIPH_LTDC   
+  *         @arg @ref LL_CKGA_PERIPH_GFXMMUM  
+  *         @arg @ref LL_CKGA_PERIPH_AHB12 
+  *         @arg @ref LL_CKGA_PERIPH_AHB34 
+  *         @arg @ref LL_CKGA_PERIPH_FLIFT  
+  *         @arg @ref LL_CKGA_PERIPH_OCTOSPI2
+  *         @arg @ref LL_CKGA_PERIPH_FMC 
+  *         @arg @ref LL_CKGA_PERIPH_OCTOSPI1
+  *         @arg @ref LL_CKGA_PERIPH_AXIRAM1 
+  *         @arg @ref LL_CKGA_PERIPH_AXIRAM2
+  *         @arg @ref LL_CKGA_PERIPH_AXIRAM3 
+  *         @arg @ref LL_CKGA_PERIPH_GFXMMUS
+  *         @arg @ref LL_CKGA_PERIPH_ECCRAM
+  *         @arg @ref LL_CKGA_PERIPH_EXTI
+  *         @arg @ref LL_CKGA_PERIPH_JTAG
   * @retval None
 */
 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
@@ -3262,7 +3343,7 @@ __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)
   *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)
   *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
   *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)
+  *         AHB3ENR      GFXMMUEN      LL_C1_AHB3_GRP1_EnableClock\n (*)
   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock
   * @param  Periphs This parameter can be a combination of the following values:
   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
@@ -3302,7 +3383,7 @@ __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
   *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
+  *         AHB3ENR      GFXMMUEN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)
   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock
   * @param  Periphs This parameter can be a combination of the following values:
   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
@@ -3323,7 +3404,7 @@ __STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -3338,7 +3419,7 @@ __STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
   *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)
-  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)
+  *         AHB3ENR      GFXMMUEN      LL_C1_AHB3_GRP1_DisableClock\n (*)
   *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock
   * @param  Periphs This parameter can be a combination of the following values:
   *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA
@@ -3537,7 +3618,7 @@ __STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -3725,7 +3806,7 @@ __STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -3925,7 +4006,7 @@ __STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -4107,7 +4188,7 @@ __STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -4302,7 +4383,7 @@ __STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -4544,7 +4625,7 @@ __STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -4724,7 +4805,7 @@ __STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -4958,7 +5039,7 @@ __STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -5158,7 +5239,7 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -5293,7 +5374,7 @@ __STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
   *
-  *         (*) value not defined in all devices.  
+  *         (*) value not defined in all devices.
   * @retval None
 */
 __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
@@ -5331,12 +5412,12 @@ __STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)
   *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)
   *
-  *         (*) value not defined in all devices.  
+  *         (*) value not defined in all devices.
   * @retval uint32_t
 */
 __STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -5498,7 +5579,7 @@ __STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -5684,7 +5765,7 @@ __STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -5866,7 +5947,7 @@ __STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -6060,7 +6141,7 @@ __STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -6302,7 +6383,7 @@ __STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -6475,7 +6556,7 @@ __STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -6689,7 +6770,7 @@ __STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)
 */
 __STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)
 {
-  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);
+  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs) ? 1U : 0U);
 }
 
 /**
@@ -6830,4 +6911,4 @@ __STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)
 
 #endif /* STM32H7xx_LL_BUS_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c
index ad5d4d50f3..f14b2e71a6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -293,4 +292,3 @@ void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h
index beedbac038..0d342c580e 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -53,6 +52,12 @@ extern "C" {
   */
 
 /* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Macros COMP Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
 /* Exported types ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
@@ -814,6 +819,91 @@ __STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
   * @}
   */
 
+/** @defgroup COMP_LL_EF_FLAG_Management Comparator flag Management
+  * @{
+  */
+
+/**
+  * @brief  Get comparator output trigger flag (latched)
+  * @rmtoll SR       C1IF           LL_COMP_IsActiveFlag_OutputTrig
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsActiveFlag_OutputTrig(COMP_TypeDef *COMPx)
+{
+   if (COMPx == COMP1)
+  {
+    return ((READ_BIT(COMP12->SR, COMP_SR_C1IF) == (COMP_SR_C1IF)) ? 1UL : 0UL);
+  }
+  else
+  {
+    return ((READ_BIT(COMP12->SR, COMP_SR_C2IF) == (COMP_SR_C2IF)) ? 1UL : 0UL);
+  }
+}
+
+/**
+  * @brief  Clear comparator comparator output trigger flag (latched)
+  * @rmtoll ICFR     CC1IF          LL_COMP_ClearFlag_OutputTrig
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_ClearFlag_OutputTrig(COMP_TypeDef *COMPx)
+{
+  if (COMPx == COMP1)
+  {
+    SET_BIT(COMP12->ICFR, COMP_ICFR_C1IF);
+  }
+  else
+  {
+    SET_BIT(COMP12->ICFR, COMP_ICFR_C2IF);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_IT_Management Comparartor IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable comparator output trigger interrupt
+  * @rmtoll ICFR     ITEN           LL_COMP_EnableIT_OutputTrig
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_EnableIT_OutputTrig(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CFGR, COMP_CFGRx_ITEN);
+}
+
+/**
+  * @brief  Disable comparator output trigger interrupt
+  * @rmtoll ICFR     ITEN           LL_COMP_DisableIT_OutputTrig
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_DisableIT_OutputTrig(COMP_TypeDef *COMPx)
+{
+  CLEAR_BIT(COMPx->CFGR, COMP_CFGRx_ITEN);
+}
+
+/**
+  * @brief  Get comparator output trigger interrupt state
+  * @rmtoll ICFR     ITEN           LL_COMP_IsEnabledIT_OutputTrig
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabledIT_OutputTrig(COMP_TypeDef *COMPx)
+{
+  return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_ITEN) == (COMP_CFGRx_ITEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+  
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
   * @{
@@ -848,4 +938,4 @@ void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
 
 #endif /* __STM32H7xx_LL_COMP_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c
index 7166551051..ceb3247647 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -59,7 +58,7 @@
   *          - SUCCESS: CORDIC registers are de-initialized
   *          - ERROR: CORDIC registers are not de-initialized
   */
-ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx)
+ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx)
 {
   ErrorStatus status = SUCCESS;
 
@@ -101,5 +100,3 @@ ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h
index 848a5dcf8d..fe1f6f9efc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -242,13 +241,13 @@ extern "C" {
   *         - @ref LL_CORDIC_SetNbRead()
   *         - @ref LL_CORDIC_SetInSize()
   *         - @ref LL_CORDIC_SetOutSize()
-  * @rmtoll CSR          FUNC          LL_CORDIC_Configure\n
-  *         CSR          PRECISION     LL_CORDIC_Configure\n
-  *         CSR          SCALE         LL_CORDIC_Configure\n
-  *         CSR          NARGS         LL_CORDIC_Configure\n
-  *         CSR          NRES          LL_CORDIC_Configure\n
-  *         CSR          ARGSIZE       LL_CORDIC_Configure\n
-  *         CSR          RESIZE        LL_CORDIC_Configure
+  * @rmtoll CSR          FUNC          LL_CORDIC_Config\n
+  *         CSR          PRECISION     LL_CORDIC_Config\n
+  *         CSR          SCALE         LL_CORDIC_Config\n
+  *         CSR          NARGS         LL_CORDIC_Config\n
+  *         CSR          NRES          LL_CORDIC_Config\n
+  *         CSR          ARGSIZE       LL_CORDIC_Config\n
+  *         CSR          RESIZE        LL_CORDIC_Config
   * @param  CORDICx CORDIC instance
   * @param  Function parameter can be one of the following values:
   *         @arg @ref LL_CORDIC_FUNCTION_COSINE
@@ -348,7 +347,7 @@ __STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Fun
   *         @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
   *         @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC));
 }
@@ -401,7 +400,7 @@ __STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Pr
   *         @arg @ref LL_CORDIC_PRECISION_14CYCLES
   *         @arg @ref LL_CORDIC_PRECISION_15CYCLES
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION));
 }
@@ -440,7 +439,7 @@ __STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
   *         @arg @ref LL_CORDIC_SCALE_6
   *         @arg @ref LL_CORDIC_SCALE_7
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetScale(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE));
 }
@@ -467,7 +466,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWr
   *         @arg @ref LL_CORDIC_NBWRITE_1
   *         @arg @ref LL_CORDIC_NBWRITE_2
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS));
 }
@@ -494,7 +493,7 @@ __STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRea
   *         @arg @ref LL_CORDIC_NBREAD_1
   *         @arg @ref LL_CORDIC_NBREAD_2
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES));
 }
@@ -521,7 +520,7 @@ __STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSiz
   *         @arg @ref LL_CORDIC_INSIZE_32BITS
   *         @arg @ref LL_CORDIC_INSIZE_16BITS
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE));
 }
@@ -548,7 +547,7 @@ __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutS
   *         @arg @ref LL_CORDIC_OUTSIZE_32BITS
   *         @arg @ref LL_CORDIC_OUTSIZE_16BITS
   */
-__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE));
 }
@@ -589,7 +588,7 @@ __STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
   * @param  CORDICx CORDIC Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(const CORDIC_TypeDef *CORDICx)
 {
   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U);
 }
@@ -630,7 +629,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
   * @param  CORDICx CORDIC Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(const CORDIC_TypeDef *CORDICx)
 {
   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U);
 }
@@ -663,7 +662,7 @@ __STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
   * @param  CORDICx CORDIC Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(const CORDIC_TypeDef *CORDICx)
 {
   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U);
 }
@@ -678,7 +677,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
   *         @arg @ref LL_CORDIC_DMA_REG_DATA_OUT
   * @retval Address of data register
   */
-__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(const CORDIC_TypeDef *CORDICx, uint32_t Direction)
 {
   uint32_t data_reg_addr;
 
@@ -710,7 +709,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint3
   * @param  CORDICx CORDIC Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(const CORDIC_TypeDef *CORDICx)
 {
   return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U);
 }
@@ -741,7 +740,7 @@ __STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InDat
   * @param  CORDICx CORDIC Instance
   * @retval 32-bit output data of CORDIC processing.
   */
-__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
+__STATIC_INLINE uint32_t LL_CORDIC_ReadData(const CORDIC_TypeDef *CORDICx)
 {
   return (uint32_t)(READ_REG(CORDICx->RDATA));
 }
@@ -756,7 +755,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
 /** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
   * @{
   */
-ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);
+ErrorStatus LL_CORDIC_DeInit(const CORDIC_TypeDef *CORDICx);
 
 /**
   * @}
@@ -782,5 +781,3 @@ ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);
 #endif
 
 #endif /* STM32H7xx_LL_CORDIC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cortex.h
index 4313732b79..2b63e8f33d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cortex.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cortex.h
@@ -10,7 +10,7 @@
     [..]
     The LL CORTEX driver contains a set of generic APIs that can be
     used by user:
-      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
           functions
       (+) Low power mode configuration (SCB register of Cortex-MCU)
       (+) MPU API to configure and enable regions
@@ -21,13 +21,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -175,6 +174,8 @@ extern "C" {
 #define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
 #define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
 #define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+
+/* Legacy Define */
 #define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
 /**
   * @}
@@ -593,7 +594,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2
   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
@@ -666,4 +667,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
 
 #endif /* STM32H7xx_LL_CORTEX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.c
index 17cdb6464e..34f0dd117d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -26,7 +25,7 @@
 #include "stm32_assert.h"
 #else
 #define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
 
 /** @addtogroup STM32H7xx_LL_Driver
   * @{
@@ -60,7 +59,7 @@
   *          - SUCCESS: CRC registers are de-initialized
   *          - ERROR: CRC registers are not de-initialized
   */
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx)
 {
   ErrorStatus status = SUCCESS;
 
@@ -81,7 +80,7 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
 
     /* Release CRC reset */
     LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
-#endif/*LL_AHB4_GRP1_PERIPH_CRC)*/
+#endif /*LL_AHB4_GRP1_PERIPH_CRC)*/
   }
   else
   {
@@ -110,6 +109,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.h
index d55593f3c3..7c5aa20c6c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -185,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi
   *         @arg @ref LL_CRC_POLYLENGTH_8B
   *         @arg @ref LL_CRC_POLYLENGTH_7B
   */
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
 }
@@ -216,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
   *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
   *         @arg @ref LL_CRC_INDATA_REVERSE_WORD
   */
-__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
 }
@@ -236,14 +235,14 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t
 }
 
 /**
-  * @brief  Configure the reversal of the bit order of the Output data
+  * @brief  Return type of reversal of the bit order of the Output data
   * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode
   * @param  CRCx CRC Instance
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
   *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
   */
-__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
 }
@@ -271,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
   * @param  CRCx CRC Instance
   * @retval Value programmed in Programmable initial CRC value register
   */
-__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_REG(CRCx->INIT));
 }
@@ -302,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno
   * @param  CRCx CRC Instance
   * @retval Value programmed in Programmable Polynomial value register
   */
-__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_REG(CRCx->POL));
 }
@@ -360,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
   * @param  CRCx CRC Instance
   * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
   */
-__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_REG(CRCx->DR));
 }
@@ -372,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
   * @param  CRCx CRC Instance
   * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
   */
-__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx)
 {
   return (uint16_t)READ_REG(CRCx->DR);
 }
@@ -384,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
   * @param  CRCx CRC Instance
   * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
   */
-__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx)
 {
   return (uint8_t)READ_REG(CRCx->DR);
 }
@@ -396,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
   * @param  CRCx CRC Instance
   * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
   */
-__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx)
 {
   return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
 }
@@ -408,7 +407,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
   * @param  CRCx CRC Instance
   * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
   */
-__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx)
 {
   return (uint32_t)(READ_REG(CRCx->IDR));
 }
@@ -434,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
   * @{
   */
 
-ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
+ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx);
 
 /**
   * @}
@@ -460,5 +459,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
 #endif
 
 #endif /* STM32H7xx_LL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.c
index e6553d6e6d..e2977e445b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -82,5 +81,3 @@ ErrorStatus LL_CRS_DeInit(void)
   */
   
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h
index 85e0fe7c87..86ce84783b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -779,5 +778,3 @@ ErrorStatus LL_CRS_DeInit(void);
 #endif
 
 #endif /* STM32H7xx_LL_CRS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c
index c27d64b452..aedbc6645a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -47,13 +46,13 @@
   * @{
   */
 #define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__)        \
-  (  ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)      \
-     || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)   \
+  (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1)      \
+   || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2)   \
   )
 
 #if defined (HRTIM1)
 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
-  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
+  (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                              \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
@@ -70,7 +69,7 @@
   )
 #elif defined (DAC2)
 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
-  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
+  (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                              \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
@@ -86,7 +85,7 @@
   )
 #else
 #define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__)                           \
-  (   ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                           \
+  (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE)                              \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM1_TRGO)                      \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO)                      \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO)                      \
@@ -101,58 +100,58 @@
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM23_TRGO)                     \
    || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM24_TRGO)                     \
   )
-#endif
+#endif /* HRTIM1 */
 
 #define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__)              \
-  (   ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)        \
-      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)    \
-      || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
+  (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE)           \
+   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)       \
+   || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)    \
   )
 
 #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__)  \
   ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE)                               \
-     && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                           \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                     \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                    \
-           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                   \
+     && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0)                             \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0)                       \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0)                      \
+         || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0))                     \
     )                                                                                                     \
     ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)                          \
-       && (  ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                           \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                        \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                        \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                       \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                       \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                       \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                      \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                      \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                      \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                     \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                     \
-             || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                    \
+       && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1)                             \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3)                          \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7)                          \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15)                         \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31)                         \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63)                         \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127)                        \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255)                        \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511)                        \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023)                       \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047)                       \
+           || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095))                      \
       )                                                                                                   \
   )
 
 #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__)                             \
-  (   ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                     \
-      || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                 \
+  (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE)                        \
+   || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE)                    \
   )
 
 #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__)                     \
-  (   ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                  \
-      || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)           \
+  (((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO)                     \
+   || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL)              \
   )
 
 #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__)                                 \
-  (   ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                         \
-      || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)             \
+  (((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL)                            \
+   || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD)                \
   )
 
 /**
@@ -179,19 +178,19 @@
   *          - SUCCESS: DAC registers are de-initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx)
 {
   /* Check the parameters */
   assert_param(IS_DAC_ALL_INSTANCE(DACx));
 
-  if(DACx == DAC1)
+  if (DACx == DAC1)
   {
     /* Force reset of DAC clock */
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC12);
 
     /* Release reset of DAC clock */
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC12);
- }
+  }
 #if defined (DAC2)
   else
   {
@@ -201,8 +200,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
     /* Release reset of DAC clock */
     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_DAC2);
   }
-#endif
-
+#endif /* DAC2 */
 
   return SUCCESS;
 }
@@ -232,7 +230,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
   *          - SUCCESS: DAC registers are initialized
   *          - ERROR: DAC registers are not initialized
   */
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct)
 {
   ErrorStatus status = SUCCESS;
 
@@ -344,5 +342,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h
index d0c74210bf..0059a34df7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -68,12 +67,14 @@ extern "C" {
                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
 #define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
+
 #define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
                                                                   DHR12Rx channel 1 (shifted left of 28 bits)   */
 #define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
                                                                   DHR12Rx channel 1 (shifted left of 20 bits)   */
 #define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
                                                                   DHR12Rx channel 1 (shifted left of 24 bits)   */
+
 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
 #define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
@@ -81,9 +82,11 @@ extern "C" {
                                         | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
 
 #define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
+
 #define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus
                                                                   DORx channel 2 (shifted left of 5 bits)    */
 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+
 #define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */
 #define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus
                                                                   SHSRx channel 2 (shifted left of 6 bits)    */
@@ -229,6 +232,7 @@ typedef struct
 #define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
 #define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
 #define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
+
 /**
   * @}
   */
@@ -238,7 +242,9 @@ typedef struct
   * @{
   */
 #define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+
 #define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+
 /**
   * @}
   */
@@ -276,19 +282,19 @@ typedef struct
 #if defined (HRTIM1)
 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1        (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */
 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */
-#endif
+#endif /* HRTIM1 */
 #define LL_DAC_TRIG_EXT_LPTIM1_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */
 #define LL_DAC_TRIG_EXT_LPTIM2_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_2                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */
 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */
 #if defined(TIM23)
 #define LL_DAC_TRIG_EXT_TIM23_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */
-#endif
+#endif /* TIM23 */
 #if defined(TIM24)
 #define LL_DAC_TRIG_EXT_TIM24_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */
-#endif
+#endif /* TIM24 */
 #if defined (DAC2)
 #define LL_DAC_TRIG_EXT_LPTIM3_OUT         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */
-#endif
+#endif /* DAC2 */
 /**
   * @}
   */
@@ -551,12 +557,10 @@ typedef struct
   *         @arg @ref LL_DAC_RESOLUTION_8B
   * @retval DAC conversion data (unit: digital value)
   */
-#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
-                                      __DAC_VOLTAGE__,\
-                                      __DAC_RESOLUTION__)                      \
-((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \
- / (__VREFANALOG_VOLTAGE__)                                                  \
-)
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)     \
+  ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                                      \
+   / (__VREFANALOG_VOLTAGE__)                                                                          \
+  )
 
 /**
   * @}
@@ -571,6 +575,7 @@ typedef struct
 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
   * @{
   */
+
 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
   * @{
   */
@@ -609,7 +614,7 @@ __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uin
   *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
   *         @arg @ref LL_DAC_MODE_CALIBRATION
   */
-__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -648,7 +653,7 @@ __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Cha
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
   */
-__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -743,7 +748,7 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha
   *         (4) On this STM32 series, parameter not available on all devices.
   *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)
   */
-__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -786,7 +791,7 @@ __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DA
   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
   *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
   */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -852,7 +857,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha
   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
   *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
   */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -919,7 +924,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t
   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
   *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
   */
-__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1017,7 +1022,7 @@ __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channe
   *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
   *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
   */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1060,7 +1065,7 @@ __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Chan
   *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
   *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
   */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1119,7 +1124,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_
   *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
   *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
   */
-__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1161,7 +1166,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
   */
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
                                                    & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
@@ -1199,7 +1204,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
   */
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1236,7 +1241,7 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint3
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
                     >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
@@ -1298,7 +1303,7 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return ((READ_BIT(DACx->CR,
                     DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1337,7 +1342,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_
   *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
   * @retval DAC register address
   */
-__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
 {
   /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
   /* DAC channel selected.                                                    */
@@ -1398,7 +1403,7 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return ((READ_BIT(DACx->CR,
                     DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1456,7 +1461,7 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   return ((READ_BIT(DACx->CR,
                     DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
@@ -1629,7 +1634,7 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint
   *         @arg @ref LL_DAC_CHANNEL_2
   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
   */
-__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
 {
   __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
                                                    & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
@@ -1644,13 +1649,14 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D
 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
   * @{
   */
+
 /**
   * @brief  Get DAC calibration offset flag for DAC channel 1
   * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
 }
@@ -1662,7 +1668,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
 }
@@ -1674,19 +1680,18 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
 }
 
-
 /**
   * @brief  Get DAC busy writing sample time flag for DAC channel 2
   * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
 }
@@ -1698,7 +1703,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
 }
@@ -1710,7 +1715,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
 }
@@ -1802,7 +1807,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
 }
@@ -1814,7 +1819,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
   * @param  DACx DAC instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
 {
   return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
 }
@@ -1829,8 +1834,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
   * @{
   */
 
-ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
-ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
 void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
 
 /**
@@ -1857,5 +1862,3 @@ void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
 #endif
 
 #endif /* STM32H7xx_LL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.c
index 5021dde64b..edaf5b799f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.c
@@ -8,7 +8,18 @@
   *          functionalities of the Delay Block peripheral:
   *           + input clock frequency range 25MHz to 208MHz
   *           + up to 12 oversampling phases
-  *         
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                        ##### DelayBlock peripheral features #####
@@ -34,19 +45,7 @@
       
   
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */ 
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal.h"
@@ -60,11 +59,17 @@
   * @{
   */
 
-#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)
+#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_QSPI_MODULE_ENABLED)|| defined(HAL_OSPI_MODULE_ENABLED)
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
+/** @defgroup DelayBlock_LL_Private_Defines Delay Block Low Layer Private Defines
+  * @{
+  */
 #define DLYB_TIMEOUT 0xFFU
+/**
+  * @}
+  */
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
@@ -207,4 +212,3 @@ HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx,uint32_t PhaseSel, ui
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.h
index 78b7bb163b..4733bc736b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_delayblock.h
@@ -6,16 +6,15 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef STM32H7xx_LL_DLYB_H
@@ -57,10 +56,14 @@
 
 /**
   * @}
-  */ 
+  */
+
+/** @addtogroup DelayBlock_LL_Exported_Functions
+  * @{
+  */
  
 /* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions
+/** @addtogroup HAL_DELAY_LL_Group1
   * @{
   */
 HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx);
@@ -71,7 +74,10 @@ HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, u
   * @}
   */
   
-  
+/**
+  * @}
+  */
+   
 /**
   * @}
   */
@@ -85,4 +91,3 @@ HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, u
 
 #endif /* STM32H7xx_LL_DLYB_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.c
index 9db91e9dc5..183cd743ee 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -44,42 +43,48 @@
 /** @addtogroup DMA_LL_Private_Macros
   * @{
   */
-#define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
-                                                 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
+#define IS_LL_DMA_DIRECTION(__VALUE__)                     (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
+                                                            ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
+                                                            ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
 
-#define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
-                                                 ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
-                                                 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
+#define IS_LL_DMA_MODE(__VALUE__)                          (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
+                                                            ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
+                                                            ((__VALUE__) == LL_DMA_MODE_PFCTRL))
 
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
+#define IS_LL_DMA_PERIPHINCMODE(__VALUE__)                 (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
+                                                            ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
 
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
-                                                 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
+#define IS_LL_DMA_MEMORYINCMODE(__VALUE__)                 (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
+                                                            ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
 
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
+#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)                (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
+                                                            ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
+                                                            ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
 
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
-                                                 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
+#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)                (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
+                                                            ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
+                                                            ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
 
-#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
+#define IS_LL_DMA_NBDATA(__VALUE__)                        ((__VALUE__)  <= 0x0000FFFFU)
 
 #if defined(TIM24)
-#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_TIM24_TRIG))
+#define IS_LL_DMA_REQUEST(REQUEST)                         (((REQUEST)   <= LL_DMAMUX1_REQ_TIM24_TRIG))
 #elif defined(ADC3)
-#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
+#define IS_LL_DMA_REQUEST(REQUEST)                         (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
 #else
-#define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
+#define IS_LL_DMA_REQUEST(REQUEST)                         (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
 #endif /* TIM24 */
 
-#define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
-                                                 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+#define IS_LL_DMA_PRIORITY(__VALUE__)                      (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
+                                                            ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
+                                                            ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
+                                                            ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
+
+#define IS_LL_DMA_DOUBLEBUFFER_MODE(__VALUE__)             (((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_DISABLE) || \
+                                                            ((__VALUE__) == LL_DMA_DOUBLEBUFFER_MODE_ENABLE))
+
+#define IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(__VALUE__)        (((__VALUE__) == LL_DMA_CURRENTTARGETMEM0)    || \
+                                                            ((__VALUE__) == LL_DMA_CURRENTTARGETMEM1))
 
 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
@@ -102,23 +107,23 @@
                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
                                                             ((STREAM) == LL_DMA_STREAM_ALL))))
 
-#define IS_LL_DMA_FIFO_MODE_STATE(STATE)    (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
-                                             ((STATE) == LL_DMA_FIFOMODE_ENABLE))
+#define IS_LL_DMA_FIFO_MODE_STATE(STATE)                   (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
+                                                            ((STATE) == LL_DMA_FIFOMODE_ENABLE))
 
-#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
-                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
-                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
-                                             ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
+#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD)                (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
+                                                            ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
+                                                            ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
+                                                            ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
 
-#define IS_LL_DMA_MEMORY_BURST(BURST)       (((BURST) == LL_DMA_MBURST_SINGLE) || \
-                                             ((BURST) == LL_DMA_MBURST_INC4)   || \
-                                             ((BURST) == LL_DMA_MBURST_INC8)   || \
-                                             ((BURST) == LL_DMA_MBURST_INC16))
+#define IS_LL_DMA_MEMORY_BURST(BURST)                      (((BURST) == LL_DMA_MBURST_SINGLE) || \
+                                                            ((BURST) == LL_DMA_MBURST_INC4)   || \
+                                                            ((BURST) == LL_DMA_MBURST_INC8)   || \
+                                                            ((BURST) == LL_DMA_MBURST_INC16))
 
-#define IS_LL_DMA_PERIPHERAL_BURST(BURST)  (((BURST) == LL_DMA_PBURST_SINGLE) || \
-                                            ((BURST) == LL_DMA_PBURST_INC4)   || \
-                                            ((BURST) == LL_DMA_PBURST_INC8)   || \
-                                            ((BURST) == LL_DMA_PBURST_INC16))
+#define IS_LL_DMA_PERIPHERAL_BURST(BURST)                  (((BURST) == LL_DMA_PBURST_SINGLE) || \
+                                                            ((BURST) == LL_DMA_PBURST_INC4)   || \
+                                                            ((BURST) == LL_DMA_PBURST_INC8)   || \
+                                                            ((BURST) == LL_DMA_PBURST_INC16))
 
 /**
   * @}
@@ -297,6 +302,8 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA
   assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
   assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
+  assert_param(IS_LL_DMA_DOUBLEBUFFER_MODE(DMA_InitStruct->DoubleBufferMode));
+  assert_param(IS_LL_DMA_DOUBLEBUFFER_TARGETMEM(DMA_InitStruct->TargetMemInDoubleBufferMode));
 
   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
      when FIFO mode is enabled */
@@ -311,22 +318,26 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA
    * Configure DMAx_Streamy: data transfer direction, data transfer mode,
    *                          peripheral and memory increment mode,
    *                          data size alignment and  priority level with parameters :
-   * - Direction:      DMA_SxCR_DIR[1:0] bits
-   * - Mode:           DMA_SxCR_CIRC bit
-   * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
-   * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
-   * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
-   * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
-   * - Priority:               DMA_SxCR_PL[1:0] bits
+   * - Direction:                   DMA_SxCR_DIR[1:0] bits
+   * - Mode:                        DMA_SxCR_CIRC bit
+   * - PeriphOrM2MSrcIncMode:       DMA_SxCR_PINC bit
+   * - MemoryOrM2MDstIncMode:       DMA_SxCR_MINC bit
+   * - PeriphOrM2MSrcDataSize:      DMA_SxCR_PSIZE[1:0] bits
+   * - MemoryOrM2MDstDataSize:      DMA_SxCR_MSIZE[1:0] bits
+   * - Priority:                    DMA_SxCR_PL[1:0] bits
+   * - DoubleBufferMode:            DMA_SxCR_DBM bit
+   * - TargetMemInDoubleBufferMode: DMA_SxCR_CT bit
    */
-  LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
+  LL_DMA_ConfigTransfer(DMAx, Stream,
+                        DMA_InitStruct->Direction               | \
                         DMA_InitStruct->Mode                    | \
                         DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
                         DMA_InitStruct->MemoryOrM2MDstIncMode   | \
                         DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
                         DMA_InitStruct->MemoryOrM2MDstDataSize  | \
-                        DMA_InitStruct->Priority
-                       );
+                        DMA_InitStruct->Priority                | \
+                        DMA_InitStruct->DoubleBufferMode        | \
+                        DMA_InitStruct->TargetMemInDoubleBufferMode);
 
   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
   {
@@ -385,21 +396,23 @@ uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA
 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 {
   /* Set DMA_InitStruct fields to default values */
-  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
-  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
-  DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
-  DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
-  DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
-  DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
-  DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
-  DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
-  DMA_InitStruct->NbData                 = 0x00000000U;
-  DMA_InitStruct->PeriphRequest          = LL_DMAMUX1_REQ_MEM2MEM;
-  DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
-  DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
-  DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
-  DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
-  DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
+  DMA_InitStruct->PeriphOrM2MSrcAddress       = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress       = 0x00000000U;
+  DMA_InitStruct->Direction                   = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
+  DMA_InitStruct->Mode                        = LL_DMA_MODE_NORMAL;
+  DMA_InitStruct->PeriphOrM2MSrcIncMode       = LL_DMA_PERIPH_NOINCREMENT;
+  DMA_InitStruct->MemoryOrM2MDstIncMode       = LL_DMA_MEMORY_NOINCREMENT;
+  DMA_InitStruct->PeriphOrM2MSrcDataSize      = LL_DMA_PDATAALIGN_BYTE;
+  DMA_InitStruct->MemoryOrM2MDstDataSize      = LL_DMA_MDATAALIGN_BYTE;
+  DMA_InitStruct->NbData                      = 0x00000000U;
+  DMA_InitStruct->PeriphRequest               = LL_DMAMUX1_REQ_MEM2MEM;
+  DMA_InitStruct->Priority                    = LL_DMA_PRIORITY_LOW;
+  DMA_InitStruct->FIFOMode                    = LL_DMA_FIFOMODE_DISABLE;
+  DMA_InitStruct->FIFOThreshold               = LL_DMA_FIFOTHRESHOLD_1_4;
+  DMA_InitStruct->MemBurst                    = LL_DMA_MBURST_SINGLE;
+  DMA_InitStruct->PeriphBurst                 = LL_DMA_PBURST_SINGLE;
+  DMA_InitStruct->DoubleBufferMode            = LL_DMA_DOUBLEBUFFER_MODE_DISABLE;
+  DMA_InitStruct->TargetMemInDoubleBufferMode = LL_DMA_CURRENTTARGETMEM0;
 }
 
 /**
@@ -422,4 +435,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.h
index 5dae9e13d3..bed596d7b7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -63,7 +62,9 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
   */
 
 /* Private macros ------------------------------------------------------------*/
-
+/** @defgroup DMA_LL_Private_Macros DMA LL Private Macros
+  * @{
+  */
 /**
   * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel
   * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
@@ -73,6 +74,9 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
   */
 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \
 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
+/**
+  * @}
+  */
 
 /* Exported types ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
@@ -81,98 +85,107 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
   */
 typedef struct
 {
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
+  uint32_t PeriphOrM2MSrcAddress;       /*!< Specifies the peripheral base address for DMA transfer
+                                             or as Source base address in case of memory to memory transfer direction.
 
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+                                             This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
 
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
+  uint32_t MemoryOrM2MDstAddress;       /*!< Specifies the memory base address for DMA transfer
+                                             or as Destination base address in case of memory to memory transfer direction.
 
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+                                             This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
 
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+  uint32_t Direction;                   /*!< Specifies if the data will be transferred from memory to peripheral,
+                                             from memory to memory or from peripheral to memory.
+                                             This parameter can be a value of @ref DMA_LL_EC_DIRECTION
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
 
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref DMA_LL_EC_MODE
-                                        @note The circular buffer mode cannot be used if the memory to memory
-                                              data transfer direction is configured on the selected Stream
+  uint32_t Mode;                        /*!< Specifies the normal or circular operation mode.
+                                             This parameter can be a value of @ref DMA_LL_EC_MODE
+                                             @note The circular buffer mode cannot be used if the memory to memory
+                                                   data transfer direction is configured on the selected Stream
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
 
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+  uint32_t PeriphOrM2MSrcIncMode;       /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                             is incremented or not.
+                                             This parameter can be a value of @ref DMA_LL_EC_PERIPH
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
 
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+  uint32_t MemoryOrM2MDstIncMode;       /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                             is incremented or not.
+                                             This parameter can be a value of @ref DMA_LL_EC_MEMORY
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
 
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+  uint32_t PeriphOrM2MSrcDataSize;      /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                             in case of memory to memory transfer direction.
+                                             This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
 
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+  uint32_t MemoryOrM2MDstDataSize;      /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                             in case of memory to memory transfer direction.
+                                             This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
 
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+  uint32_t NbData;                      /*!< Specifies the number of data to transfer, in data unit.
+                                             The data unit is equal to the source buffer configuration set in PeripheralSize
+                                             or MemorySize parameters depending in the transfer direction.
+                                             This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
 
-  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.
-                                        This parameter can be a value of @ref DMAMUX1_Request_selection
+  uint32_t PeriphRequest;               /*!< Specifies the peripheral request.
+                                             This parameter can be a value of @ref DMAMUX1_Request_selection
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
 
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+  uint32_t Priority;                    /*!< Specifies the channel priority level.
+                                             This parameter can be a value of @ref DMA_LL_EC_PRIORITY
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
 
-  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
-                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
-                                        @note The Direct mode (FIFO mode disabled) cannot be used if the
-                                        memory-to-memory data transfer is configured on the selected stream
+  uint32_t FIFOMode;                    /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                             This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                             @note The Direct mode (FIFO mode disabled) cannot be used if the
+                                             memory-to-memory data transfer is configured on the selected stream
 
-                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+                                             This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
 
-  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
-                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+  uint32_t FIFOThreshold;               /*!< Specifies the FIFO threshold level.
+                                             This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
 
-  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.
-                                        It specifies the amount of data to be transferred in a single non interruptible
-                                        transaction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MBURST
-                                        @note The burst mode is possible only if the address Increment mode is enabled.
+  uint32_t MemBurst;                    /*!< Specifies the Burst transfer configuration for the memory transfers.
+                                             It specifies the amount of data to be transferred in a single non interruptible
+                                             transaction.
+                                             This parameter can be a value of @ref DMA_LL_EC_MBURST
+                                             @note The burst mode is possible only if the address Increment mode is enabled.
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
 
-  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.
-                                        It specifies the amount of data to be transferred in a single non interruptible
-                                        transaction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
-                                        @note The burst mode is possible only if the address Increment mode is enabled.
+  uint32_t PeriphBurst;                 /*!< Specifies the Burst transfer configuration for the peripheral transfers.
+                                             It specifies the amount of data to be transferred in a single non interruptible
+                                             transaction.
+                                             This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                             @note The burst mode is possible only if the address Increment mode is enabled.
 
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
 
+  uint32_t DoubleBufferMode;            /*!< Specifies the double buffer mode.
+                                             This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE
+
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */
+
+  uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
+                                             This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM
+
+                                             This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */
 } LL_DMA_InitTypeDef;
 /**
   * @}
@@ -229,6 +242,15 @@ typedef struct
   * @}
   */
 
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
 /** @defgroup DMA_LL_EC_PERIPH PERIPH
   * @{
   */
@@ -343,15 +365,6 @@ typedef struct
   * @}
   */
 
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
-  * @{
-  */
-#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
-#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
-/**
-  * @}
-  */
-
 /**
   * @}
   */
@@ -533,7 +546,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre
   *         CR          PSIZE         LL_DMA_ConfigTransfer\n
   *         CR          MSIZE         LL_DMA_ConfigTransfer\n
   *         CR          PL            LL_DMA_ConfigTransfer\n
-  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer\n
+  *         CR          DBM           LL_DMA_ConfigTransfer\n
+  *         CR          CT            LL_DMA_ConfigTransfer
   * @param  DMAx DMAx Instance
   * @param  Stream This parameter can be one of the following values:
   *         @arg @ref LL_DMA_STREAM_0
@@ -552,6 +567,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre
   *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
   *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
   *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *         @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1
   *@retval None
   */
 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
@@ -559,8 +576,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u
   uint32_t dma_base_addr = (uint32_t)DMAx;
 
   MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
-             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
-             Configuration);
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \
+             DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration);
 }
 
 /**
@@ -1583,6 +1600,28 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t
   CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
 }
 
+/**
+  * @brief  Check if double buffer mode is enabled or not.
+  * @rmtoll CR          DBM           LL_DMA_IsEnabledDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  uint32_t dma_base_addr = (uint32_t)DMAx;
+
+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL);
+}
+
 /**
   * @brief Get FIFO status.
   * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
@@ -3134,7 +3173,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
 }
 
 /**
-  * @brief Check if Half transfer interrup is enabled.
+  * @brief Check if Half transfer interrupt is enabled.
   * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
   * @param  DMAx DMAx Instance
   * @param  Stream This parameter can be one of the following values:
@@ -3178,7 +3217,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea
 }
 
 /**
-  * @brief Check if Transfer complete interrup is enabled.
+  * @brief Check if Transfer complete interrupt is enabled.
   * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
   * @param  DMAx DMAx Instance
   * @param  Stream This parameter can be one of the following values:
@@ -3222,7 +3261,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre
 }
 
 /**
-  * @brief Check if FIFO error interrup is enabled.
+  * @brief Check if FIFO error interrupt is enabled.
   * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
   * @param  DMAx DMAx Instance
   * @param  Stream This parameter can be one of the following values:
@@ -3281,4 +3320,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
 
 #endif /* __STM32H7xx_LL_DMA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c
index 0805f0075f..e79d451964 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -633,6 +632,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h
index 583a04ea29..daea475843 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -2230,5 +2229,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb
 #endif
 
 #endif /* STM32H7xx_LL_DMA2D_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h
index 9592307d5f..bf4cffa0bc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -2435,4 +2434,3 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMU
 
 #endif /* __STM32H7xx_LL_DMAMUX_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c
index b9ecde5e08..5e3a19848f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -455,4 +454,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.h
index 1e25e01092..885f22d9f1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -3284,4 +3283,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
 
 #endif /* __STM32H7xx_LL_EXTI_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.c
index 337d4f75d7..eab7ae8ca0 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.c
@@ -2,17 +2,16 @@
   ******************************************************************************
   * @file    stm32h7xx_ll_fmac.c
   * @author  MCD Application Team
-  * @brief   FMAC LL module driver.
+  * @brief   Header for stm32h7xx_ll_fmac.c module
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -37,41 +36,13 @@
   * @{
   */
 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
-/** @addtogroup FMAC_LL_Private_Macros
-  * @{
-  */
-
-/** @brief  Check if the watermark value is a valid one.
-  * @param  __VALUE__ Watermak value.
-  * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
-  */
-#define IS_LL_FMAC_WM(__VALUE__) (((__VALUE__) == LL_FMAC_WM_0_THRESHOLD_1) \
-                                  || ((__VALUE__) == LL_FMAC_WM_1_THRESHOLD_2) \
-                                  || ((__VALUE__) == LL_FMAC_WM_2_THRESHOLD_4) \
-                                  || ((__VALUE__) == LL_FMAC_WM_3_THRESHOLD_8))
-
-/** @brief  Check if the function ID is a valid one.
-  * @param  __VALUE__ Function ID.
-  * @retval SET (__VALUE__ is a valid value) or RESET (__VALUE__ is invalid)
-  */
-#define IS_LL_FMAC_FUNC(__VALUE__) (((__VALUE__) == LL_FMAC_FUNC_LOAD_X1) \
-                                    || ((__VALUE__) == LL_FMAC_FUNC_LOAD_X2) \
-                                    || ((__VALUE__) == LL_FMAC_FUNC_LOAD_Y) \
-                                    || ((__VALUE__) == LL_FMAC_FUNC_CONVO_FIR) \
-                                    || ((__VALUE__) == LL_FMAC_FUNC_IIR_DIRECT_FORM_1))
-
-
-/**
-  * @}
-  */
-
+/* Private variables ---------------------------------------------------------*/
+/* Global variables ----------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
+/* Functions Definition ------------------------------------------------------*/
 /** @addtogroup FMAC_LL_Exported_Functions
   * @{
   */
@@ -83,7 +54,7 @@
 /**
   * @brief  Initialize FMAC peripheral registers to their default reset values.
   * @param  FMACx FMAC Instance
-  * @retval An ErrorStatus enumeration value:
+  * @retval ErrorStatus enumeration value:
   *          - SUCCESS: FMAC registers are initialized
   *          - ERROR: FMAC registers are not initialized
   */
@@ -119,7 +90,7 @@ ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx)
   *          - SUCCESS: FMAC registers are de-initialized
   *          - ERROR: FMAC registers are not de-initialized
   */
-ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx)
+ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx)
 {
   ErrorStatus status = SUCCESS;
 
@@ -163,5 +134,3 @@ ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.h
index 4bc018c33b..8e92c3d4d1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmac.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -38,20 +37,6 @@ extern "C" {
   * @{
   */
 
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup FMAC_LL_Private_Macros FMAC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
 /* Exported types ------------------------------------------------------------*/
 
 /* Exported constants --------------------------------------------------------*/
@@ -63,11 +48,12 @@ extern "C" {
   * @brief    Flag defines which can be used with LL_FMAC_ReadReg function
   * @{
   */
-#define LL_FMAC_SR_SAT                     FMAC_SR_SAT
-#define LL_FMAC_SR_UNFL                    FMAC_SR_UNFL
-#define LL_FMAC_SR_OVFL                    FMAC_SR_OVFL
-#define LL_FMAC_SR_X1FULL                  FMAC_SR_X1FULL
-#define LL_FMAC_SR_YEMPTY                  FMAC_SR_YEMPTY
+#define LL_FMAC_SR_SAT                     FMAC_SR_SAT    /*!< Saturation Error Flag
+                                                               (this helps in debugging a filter)                     */
+#define LL_FMAC_SR_UNFL                    FMAC_SR_UNFL   /*!< Underflow Error Flag                                   */
+#define LL_FMAC_SR_OVFL                    FMAC_SR_OVFL   /*!< Overflow Error Flag                                    */
+#define LL_FMAC_SR_X1FULL                  FMAC_SR_X1FULL /*!< X1 Buffer Full Flag                                    */
+#define LL_FMAC_SR_YEMPTY                  FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag                                    */
 /**
   * @}
   */
@@ -76,11 +62,12 @@ extern "C" {
   * @brief    IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
   * @{
   */
-#define LL_FMAC_CR_SATIEN                  FMAC_CR_SATIEN
-#define LL_FMAC_CR_UNFLIEN                 FMAC_CR_UNFLIEN
-#define LL_FMAC_CR_OVFLIEN                 FMAC_CR_OVFLIEN
-#define LL_FMAC_CR_WIEN                    FMAC_CR_WIEN
-#define LL_FMAC_CR_RIEN                    FMAC_CR_RIEN
+#define LL_FMAC_CR_SATIEN                  FMAC_CR_SATIEN  /*!< Saturation Error Interrupt Enable
+                                                                (this helps in debugging a filter)                    */
+#define LL_FMAC_CR_UNFLIEN                 FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable                      */
+#define LL_FMAC_CR_OVFLIEN                 FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable                       */
+#define LL_FMAC_CR_WIEN                    FMAC_CR_WIEN    /*!< Write Interrupt Enable                                */
+#define LL_FMAC_CR_RIEN                    FMAC_CR_RIEN    /*!< Read Interrupt Enable                                 */
 /**
   * @}
   */
@@ -89,10 +76,14 @@ extern "C" {
   * @brief    Watermark defines that can be used for buffer full (input) or buffer empty (output)
   * @{
   */
-#define LL_FMAC_WM_0_THRESHOLD_1           0x00000000UL /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
-#define LL_FMAC_WM_1_THRESHOLD_2           0x01000000UL /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
-#define LL_FMAC_WM_2_THRESHOLD_4           0x02000000UL /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
-#define LL_FMAC_WM_3_THRESHOLD_8           0x03000000UL /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
+#define LL_FMAC_WM_0_THRESHOLD_1           0x00000000U /*!< Buffer full/empty flag set if there
+                                                            is less than 1 free/unread space.                         */
+#define LL_FMAC_WM_1_THRESHOLD_2           0x01000000U /*!< Buffer full/empty flag set if there
+                                                            are less than 2 free/unread spaces.                       */
+#define LL_FMAC_WM_2_THRESHOLD_4           0x02000000U /*!< Buffer full/empty flag set if there
+                                                            are less than 4 free/unread spaces.                       */
+#define LL_FMAC_WM_3_THRESHOLD_8           0x03000000U /*!< Buffer full/empty flag set if there
+                                                            are less than 8 free/empty spaces.                        */
 /**
   * @}
   */
@@ -100,11 +91,20 @@ extern "C" {
 /** @defgroup FMAC_LL_EC_FUNC FMAC functions
   * @{
   */
-#define LL_FMAC_FUNC_LOAD_X1               ((uint32_t)(FMAC_PARAM_FUNC_0))                                         /*!< Load X1 buffer */
-#define LL_FMAC_FUNC_LOAD_X2               ((uint32_t)(FMAC_PARAM_FUNC_1))                                         /*!< Load X2 buffer */
-#define LL_FMAC_FUNC_LOAD_Y                ((uint32_t)(FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0))                     /*!< Load Y buffer */
-#define LL_FMAC_FUNC_CONVO_FIR             ((uint32_t)(FMAC_PARAM_FUNC_3))                                         /*!< Convolution (FIR filter) */
-#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1     ((uint32_t)(FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0))                     /*!< IIR filter (direct form 1) */
+#define LL_FMAC_FUNC_LOAD_X1               (FMAC_PARAM_FUNC_0)                        /*!< Load X1 buffer             */
+#define LL_FMAC_FUNC_LOAD_X2               (FMAC_PARAM_FUNC_1)                        /*!< Load X2 buffer             */
+#define LL_FMAC_FUNC_LOAD_Y                (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0)    /*!< Load Y buffer              */
+#define LL_FMAC_FUNC_CONVO_FIR             (FMAC_PARAM_FUNC_3)                        /*!< Convolution (FIR filter)   */
+#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1     (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0)    /*!< IIR filter (direct form 1) */
+/**
+  * @}
+  */
+
+/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
+  * @{
+  */
+#define LL_FMAC_PROCESSING_STOP            0x00U /*!< Stop FMAC Processing                                            */
+#define LL_FMAC_PROCESSING_START           0x01U /*!< Start FMAC Processing                                           */
 /**
   * @}
   */
@@ -113,7 +113,8 @@ extern "C" {
   * @}
   */
 
-/* Exported macro ------------------------------------------------------------*/
+/* External variables --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
 /** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
   * @{
   */
@@ -177,13 +178,13 @@ __STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Wa
   * @brief  Return X1 full watermark.
   * @rmtoll X1BUFCFG     FULL_WM       LL_FMAC_GetX1FullWatermark
   * @param  FMACx FMAC instance
-  * @retval Returned value can be one of the following values:
+  * @retval uint32_t Returned value can be one of the following values:
   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
   */
-__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(const FMAC_TypeDef *FMACx)
 {
   return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
 }
@@ -192,7 +193,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
   * @brief  Configure X1 buffer size.
   * @rmtoll X1BUFCFG     X1_BUF_SIZE   LL_FMAC_SetX1BufferSize
   * @param  FMACx FMAC instance
-  * @param  BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+  * @param  BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+  *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -204,9 +206,10 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer
   * @brief  Return X1 buffer size.
   * @rmtoll X1BUFCFG     X1_BUF_SIZE   LL_FMAC_GetX1BufferSize
   * @param  FMACx FMAC instance
-  * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+  * @retval uint8_t Number of 16-bit words allocated to the input buffer
+  *                 (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
 }
@@ -215,7 +218,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
   * @brief  Configure X1 base.
   * @rmtoll X1BUFCFG     X1_BASE       LL_FMAC_SetX1Base
   * @param  FMACx FMAC instance
-  * @param  Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+  * @param  Base Base address of the input buffer (X1) within the internal memory.
+  *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -227,9 +231,10 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
   * @brief  Return X1 base.
   * @rmtoll X1BUFCFG     X1_BASE       LL_FMAC_GetX1Base
   * @param  FMACx FMAC instance
-  * @retval 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
+  * @retval uint8_t Base address of the input buffer (X1) within the internal memory
+  *                      (value between Min_Data=0x00 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
 }
@@ -238,7 +243,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
   * @brief  Configure X2 buffer size.
   * @rmtoll X2BUFCFG     X2_BUF_SIZE   LL_FMAC_SetX2BufferSize
   * @param  FMACx FMAC instance
-  * @param  BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+  * @param  BufferSize Number of 16-bit words allocated to the coefficient buffer.
+  *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -250,9 +256,10 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer
   * @brief  Return X2 buffer size.
   * @rmtoll X2BUFCFG     X2_BUF_SIZE   LL_FMAC_GetX2BufferSize
   * @param  FMACx FMAC instance
-  * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+  * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
+  *                 (value between Min_Data=0x01 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
 }
@@ -261,7 +268,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
   * @brief  Configure X2 base.
   * @rmtoll X2BUFCFG     X2_BASE       LL_FMAC_SetX2Base
   * @param  FMACx FMAC instance
-  * @param  Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+  * @param  Base Base address of the coefficient buffer (X2) within the internal memory.
+  *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -273,9 +281,10 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
   * @brief  Return X2 base.
   * @rmtoll X2BUFCFG     X2_BASE       LL_FMAC_GetX2Base
   * @param  FMACx FMAC instance
-  * @retval 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
+  * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
+  *                      (value between Min_Data=0x00 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
 }
@@ -300,13 +309,13 @@ __STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Wa
   * @brief  Return Y empty watermark.
   * @rmtoll YBUFCFG      EMPTY_WM      LL_FMAC_GetYEmptyWatermark
   * @param  FMACx FMAC instance
-  * @retval Returned value can be one of the following values:
+  * @retval uint32_t Returned value can be one of the following values:
   *         @arg @ref LL_FMAC_WM_0_THRESHOLD_1
   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
   */
-__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(const FMAC_TypeDef *FMACx)
 {
   return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
 }
@@ -315,7 +324,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
   * @brief  Configure Y buffer size.
   * @rmtoll YBUFCFG      Y_BUF_SIZE    LL_FMAC_SetYBufferSize
   * @param  FMACx FMAC instance
-  * @param  BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+  * @param  BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+  *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
@@ -327,9 +337,10 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS
   * @brief  Return Y buffer size.
   * @rmtoll YBUFCFG      Y_BUF_SIZE    LL_FMAC_GetYBufferSize
   * @param  FMACx FMAC instance
-  * @retval 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+  * @retval uint8_t Number of 16-bit words allocated to the output buffer
+  *                (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
 }
@@ -338,7 +349,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
   * @brief  Configure Y base.
   * @rmtoll YBUFCFG      Y_BASE        LL_FMAC_SetYBase
   * @param  FMACx FMAC instance
-  * @param  Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+  * @param  Base Base address of the output buffer (Y) within the internal memory.
+  *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
@@ -350,9 +362,10 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
   * @brief  Return Y base.
   * @rmtoll YBUFCFG      Y_BASE        LL_FMAC_GetYBase
   * @param  FMACx FMAC instance
-  * @retval 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
+  * @retval uint8_t Base address of the output buffer (Y) within the internal memory
+  *                      (value between Min_Data=0x00 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetYBase(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
 }
@@ -383,9 +396,9 @@ __STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
   * @brief  Check the state of FMAC processing.
   * @rmtoll PARAM        START         LL_FMAC_IsEnabledStart
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
 }
@@ -411,14 +424,14 @@ __STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
   * @brief  Return function.
   * @rmtoll PARAM        FUNC          LL_FMAC_GetFunction
   * @param  FMACx FMAC instance
-  * @retval Returned value can be one of the following values:
+  * @retval uint32_t Returned value can be one of the following values:
   *         @arg @ref LL_FMAC_FUNC_LOAD_X1
   *         @arg @ref LL_FMAC_FUNC_LOAD_X2
   *         @arg @ref LL_FMAC_FUNC_LOAD_Y
   *         @arg @ref LL_FMAC_FUNC_CONVO_FIR
   *         @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
   */
-__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_GetFunction(const FMAC_TypeDef *FMACx)
 {
   return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
 }
@@ -427,7 +440,8 @@ __STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
   * @brief  Configure input parameter R.
   * @rmtoll PARAM        R             LL_FMAC_SetParamR
   * @param  FMACx FMAC instance
-  * @param  Param 0x00 .. 0xFF: Parameter R (gain, etc.).
+  * @param  Param Parameter R (gain, etc.).
+  *               This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
@@ -439,9 +453,9 @@ __STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
   * @brief  Return input parameter R.
   * @rmtoll PARAM        R             LL_FMAC_GetParamR
   * @param  FMACx FMAC instance
-  * @retval 0x00 .. 0xFF: Parameter R (gain, etc.).
+  * @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetParamR(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
 }
@@ -450,7 +464,8 @@ __STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
   * @brief  Configure input parameter Q.
   * @rmtoll PARAM        Q             LL_FMAC_SetParamQ
   * @param  FMACx FMAC instance
-  * @param  Param 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+  * @param  Param Parameter Q (vector length, etc.).
+  *               This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
@@ -462,9 +477,9 @@ __STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
   * @brief  Return input parameter Q.
   * @rmtoll PARAM        Q             LL_FMAC_GetParamQ
   * @param  FMACx FMAC instance
-  * @retval 0x00 .. 0xFF: Parameter Q (vector length, etc.).
+  * @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(const FMAC_TypeDef *FMACx)
 {
   return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
 }
@@ -473,23 +488,25 @@ __STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
   * @brief  Configure input parameter P.
   * @rmtoll PARAM        P             LL_FMAC_SetParamP
   * @param  FMACx FMAC instance
-  * @param  Param 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+  * @param  Param Parameter P (vector length, number of filter taps, etc.).
+  *               This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
 {
-  MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param) << FMAC_PARAM_P_Pos);
+  MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
 }
 
 /**
   * @brief  Return input parameter P.
   * @rmtoll PARAM        P             LL_FMAC_GetParamP
   * @param  FMACx FMAC instance
-  * @retval 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
+  * @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
+  *                 (value between Min_Data=0x00 and Max_Data=0xFF).
   */
-__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint8_t LL_FMAC_GetParamP(const FMAC_TypeDef *FMACx)
 {
-  return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P) >> FMAC_PARAM_P_Pos);
+  return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
 }
 
 /**
@@ -511,24 +528,13 @@ __STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
   SET_BIT(FMACx->CR, FMAC_CR_RESET);
 }
 
-/**
-  * @brief  Interrupt the FMAC reset.
-  * @rmtoll CR           RESET         LL_FMAC_DisableReset
-  * @param  FMACx FMAC instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_FMAC_DisableReset(FMAC_TypeDef *FMACx)
-{
-  CLEAR_BIT(FMACx->CR, FMAC_CR_RESET);
-}
-
 /**
   * @brief  Check the state of the FMAC reset.
   * @rmtoll CR           RESET         LL_FMAC_IsEnabledReset
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
 }
@@ -567,9 +573,9 @@ __STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
   * @brief  Check Clipping State.
   * @rmtoll CR           CLIPEN        LL_FMAC_IsEnabledClipping
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
 }
@@ -608,9 +614,9 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC DMA write channel request state.
   * @rmtoll CR           DMAWEN        LL_FMAC_IsEnabledDMAReq_WRITE
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
 }
@@ -641,9 +647,9 @@ __STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC DMA read channel request state.
   * @rmtoll CR           DMAREN        LL_FMAC_IsEnabledDMAReq_READ
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
 }
@@ -682,9 +688,9 @@ __STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC saturation error interrupt state.
   * @rmtoll CR           SATIEN        LL_FMAC_IsEnabledIT_SAT
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
 }
@@ -715,9 +721,9 @@ __STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC underflow error interrupt state.
   * @rmtoll CR           UNFLIEN       LL_FMAC_IsEnabledIT_UNFL
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
 }
@@ -748,9 +754,9 @@ __STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC overflow error interrupt state.
   * @rmtoll CR           OVFLIEN       LL_FMAC_IsEnabledIT_OVFL
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
 }
@@ -781,9 +787,9 @@ __STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC write interrupt state.
   * @rmtoll CR           WIEN          LL_FMAC_IsEnabledIT_WR
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
 }
@@ -814,9 +820,9 @@ __STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC read interrupt state.
   * @rmtoll CR           RIEN          LL_FMAC_IsEnabledIT_RD
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
 }
@@ -833,9 +839,9 @@ __STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC saturation error flag state.
   * @rmtoll SR           SAT           LL_FMAC_IsActiveFlag_SAT
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
 }
@@ -844,9 +850,9 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC underflow error flag state.
   * @rmtoll SR           UNFL          LL_FMAC_IsActiveFlag_UNFL
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
 }
@@ -855,9 +861,9 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC overflow error flag state.
   * @rmtoll SR           OVFL          LL_FMAC_IsActiveFlag_OVFL
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
 }
@@ -866,9 +872,9 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC X1 buffer full flag state.
   * @rmtoll SR           X1FULL        LL_FMAC_IsActiveFlag_X1FULL
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
 }
@@ -877,9 +883,9 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
   * @brief  Check FMAC Y buffer empty flag state.
   * @rmtoll SR           YEMPTY        LL_FMAC_IsActiveFlag_YEMPTY
   * @param  FMACx FMAC instance
-  * @retval State of bit (1 or 0).
+  * @retval uint32_t State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(const FMAC_TypeDef *FMACx)
 {
   return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
 }
@@ -896,7 +902,8 @@ __STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
   * @brief  Write 16-bit input data for the FMAC processing.
   * @rmtoll WDATA        WDATA         LL_FMAC_WriteData
   * @param  FMACx FMAC instance
-  * @param  InData 0x0000 .. 0xFFFF: 16-bit value to be provided as input data for FMAC processing.
+  * @param  InData 16-bit value to be provided as input data for FMAC processing.
+  *                This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
@@ -908,9 +915,9 @@ __STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
   * @brief  Return 16-bit output data of FMAC processing.
   * @rmtoll RDATA        RDATA         LL_FMAC_ReadData
   * @param  FMACx FMAC instance
-  * @retval 0x0000 .. 0xFFFF: 16-bit output data of FMAC processing.
+  * @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
   */
-__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
+__STATIC_INLINE uint16_t LL_FMAC_ReadData(const FMAC_TypeDef *FMACx)
 {
   return (uint16_t)(READ_REG(FMACx->RDATA));
 }
@@ -934,14 +941,17 @@ __STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
-  * @param  Base 0x00 .. 0xFF: Base address of the input buffer (X1) within the internal memory.
-  * @param  BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the input buffer (including the optional "headroom").
+  * @param  Base Base address of the input buffer (X1) within the internal memory.
+  *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @param  BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
+  *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
 {
   MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
-             Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
+             Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
+             (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
 }
 
 /**
@@ -949,14 +959,17 @@ __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, u
   * @rmtoll X2BUFCFG     X2_BASE       LL_FMAC_ConfigX2\n
   *         X2BUFCFG     X2_BUF_SIZE   LL_FMAC_ConfigX2
   * @param  FMACx FMAC instance
-  * @param  Base 0x00 .. 0xFF: Base address of the coefficient buffer (X2) within the internal memory.
-  * @param  BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the coefficient buffer.
+  * @param  Base Base address of the coefficient buffer (X2) within the internal memory.
+  *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @param  BufferSize Number of 16-bit words allocated to the coefficient buffer.
+  *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
 {
   MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
-             (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
+             (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
+             (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
 }
 
 /**
@@ -970,14 +983,17 @@ __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t
   *         @arg @ref LL_FMAC_WM_1_THRESHOLD_2
   *         @arg @ref LL_FMAC_WM_2_THRESHOLD_4
   *         @arg @ref LL_FMAC_WM_3_THRESHOLD_8
-  * @param  Base 0x00 .. 0xFF: Base address of the output buffer (Y) within the internal memory.
-  * @param  BufferSize 0x01 .. 0xFF: Number of 16-bit addresses allocated to the output buffer (including the optional "headroom").
+  * @param  Base Base address of the output buffer (Y) within the internal memory.
+  *              This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @param  BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
+  *                    This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
 {
   MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
-             Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
+             Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
+             (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
 }
 
 /**
@@ -988,23 +1004,29 @@ __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, ui
   *         PARAM        Q             LL_FMAC_ConfigFunc\n
   *         PARAM        R             LL_FMAC_ConfigFunc
   * @param  FMACx FMAC instance
-  * @param  Start 0x00 .. 0x01: Enable or disable FMAC processing.
+  * @param  Start This parameter can be one of the following values:
+  *         @arg @ref LL_FMAC_PROCESSING_STOP
+  *         @arg @ref LL_FMAC_PROCESSING_START
   * @param  Function This parameter can be one of the following values:
   *         @arg @ref LL_FMAC_FUNC_LOAD_X1
   *         @arg @ref LL_FMAC_FUNC_LOAD_X2
   *         @arg @ref LL_FMAC_FUNC_LOAD_Y
   *         @arg @ref LL_FMAC_FUNC_CONVO_FIR
   *         @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
-  * @param  ParamP 0x00 .. 0xFF: Parameter P (vector length, number of filter taps, etc.).
-  * @param  ParamQ 0x00 .. 0xFF: Parameter Q (vector length, etc.).
-  * @param  ParamR 0x00 .. 0xFF: Parameter R (gain, etc.).
+  * @param  ParamP Parameter P (vector length, number of filter taps, etc.).
+  *                This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @param  ParamQ Parameter Q (vector length, etc.).
+  *                This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
+  * @param  ParamR Parameter R (gain, etc.).
+  *                This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
   * @retval None
   */
 __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
                                         uint8_t ParamQ, uint8_t ParamR)
 {
   MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
-             (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
+             (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
+             (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
 }
 
 /**
@@ -1018,7 +1040,7 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint
   * @{
   */
 ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
-ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
+ErrorStatus LL_FMAC_DeInit(const FMAC_TypeDef *FMACx);
 
 
 /**
@@ -1045,5 +1067,3 @@ ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
 #endif
 
 #endif /* STM32H7xx_LL_FMAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c
index 452d5e965b..b9fa468f1a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c
@@ -10,6 +10,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                         ##### FMC peripheral features #####
@@ -41,17 +52,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -60,7 +60,8 @@
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
-#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
+#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
+ || defined(HAL_SRAM_MODULE_ENABLED)
 
 /** @defgroup FMC_LL  FMC Low Layer
   * @brief FMC driver modules
@@ -988,10 +989,10 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
   assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
 
   /* Set command register */
-  MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | 
-             FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) | 
-             (Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
-             ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
+  MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
+             ((Command->CommandMode) | (Command->CommandTarget) |
+              (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
+              ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
   /* Prevent unused argument(s) compilation warning */
   UNUSED(Timeout);
   return HAL_OK;
@@ -1043,7 +1044,7 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
   *         FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
   *         FMC_SDRAM_POWER_DOWN_MODE.
   */
-uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
+uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 {
   uint32_t tmpreg;
 
@@ -1089,5 +1090,3 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h
index 687775a585..3d34898e39 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -598,11 +597,13 @@ typedef struct
   * @}
   */
 
+#if defined(FMC_BCR1_WFDIS)
 /** @defgroup FMC_Write_FIFO FMC Write FIFO
   * @{
   */
 #define FMC_WRITE_FIFO_DISABLE                  FMC_BCR1_WFDIS
 #define FMC_WRITE_FIFO_ENABLE                   (0x00000000U)
+#endif /* FMC_BCR1_WFDIS */
 /**
   * @}
   */
@@ -1134,7 +1135,7 @@ HAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
 HAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
 HAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
                                                   uint32_t AutoRefreshNumber);
-uint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
+uint32_t           FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
 /**
   * @}
   */
@@ -1159,5 +1160,3 @@ uint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B
 #endif
 
 #endif /* STM32H7xx_LL_FMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.c
index 5a809dbab6..f48c3465b2 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -303,5 +302,4 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h
index cf032aa297..b51f9d3bf9 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -983,4 +982,3 @@ void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
 
 #endif /* STM32H7xx_LL_GPIO_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.c
index 47adce6449..1ee8c0a112 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -79,5 +78,3 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h
index 36a12353f7..d3f3608fe1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -377,10 +376,10 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] =
   * @{
   * @brief Constants defining the source and event to be sent on the synchronization output.
   */
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_START  0x00000000U                        /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
-#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
-#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START  0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
 /**
   * @}
   */
@@ -1440,7 +1439,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncI
   *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
   *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
   */
-__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx)
 {
   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
 }
@@ -1491,7 +1490,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t S
   *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
   *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx)
 {
   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
 }
@@ -1522,7 +1521,7 @@ __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t Sync
   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
   *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
   */
-__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx)
 {
   return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
 }
@@ -1712,7 +1711,7 @@ __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outp
   *         @arg @ref LL_HRTIM_OUTPUT_TE2
   * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
 }
@@ -1743,7 +1742,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_
   *         @arg @ref LL_HRTIM_OUTPUT_TE2
   * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
 }
@@ -2028,7 +2027,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t A
   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
   *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
   */
-__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
 {
   const uint32_t shift = ((3U * ADCTrig) & 0x1FU);
   return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);
@@ -2462,7 +2461,7 @@ __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCT
   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
   *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
   */
-__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
 {
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
                                                                     REG_OFFSET_TAB_ADCxR[ADCTrig]));
@@ -2543,7 +2542,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
 }
@@ -2592,7 +2591,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
   *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -2645,7 +2644,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
   *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -2711,7 +2710,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -2774,7 +2773,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -2838,7 +2837,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval None
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -2890,7 +2889,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
   *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -2956,7 +2955,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -3041,7 +3040,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
   *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -3116,7 +3115,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_
   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
   *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
@@ -3175,7 +3174,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uin
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
@@ -3235,7 +3234,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
   *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
@@ -3287,7 +3286,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval Counter Value between 0 and 0xFFFF
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
@@ -3332,7 +3331,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Time
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval Period Value between 0 and 0xFFFF
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
@@ -3377,7 +3376,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval Repetition Value between 0 and 0xFF
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
@@ -3426,7 +3425,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Ti
   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
@@ -3475,7 +3474,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Ti
   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
@@ -3524,7 +3523,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Ti
   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
@@ -3573,7 +3572,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Ti
   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
@@ -3740,7 +3739,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
   *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
@@ -3760,7 +3759,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval Captured value
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
@@ -3780,7 +3779,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval Captured value
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
@@ -3954,7 +3953,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
   *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
@@ -4014,7 +4013,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -4100,7 +4099,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
   *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -4162,7 +4161,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -4252,7 +4251,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_FAULT_5
   * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
@@ -4330,7 +4329,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint
   *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
   *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
@@ -4439,7 +4438,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
   *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -4461,7 +4460,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HR
   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
   *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -4577,7 +4576,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
   *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
@@ -4666,7 +4665,7 @@ __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uin
   *         @arg @ref LL_HRTIM_EELATCH_DISABLED
   *         @arg @ref LL_HRTIM_EELATCH_ENABLED
   */
-__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
@@ -4758,7 +4757,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Ti
   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
   *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
   */
-__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
@@ -4799,7 +4798,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval RisingValue Value between 0 and 0x1FF
   */
-__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
@@ -4844,7 +4843,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
   *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
@@ -4885,7 +4884,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval FallingValue Value between 0 and 0x1FF
   */
-__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
@@ -4930,7 +4929,7 @@ __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
   *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
@@ -4950,7 +4949,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint3
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval None
   */
-__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
@@ -5122,7 +5121,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
   *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
   */
-__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
@@ -5182,7 +5181,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
   *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
   */
-__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
@@ -5257,7 +5256,7 @@ __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
   *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
   */
-__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
@@ -5506,7 +5505,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_
   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
@@ -5747,7 +5746,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint3
   *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10
   *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
@@ -5848,7 +5847,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Ou
   *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
   *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -5906,7 +5905,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Ou
   *         @arg @ref LL_HRTIM_OUT_NO_IDLE
   *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -5965,7 +5964,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t O
   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
   *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -6028,7 +6027,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
   *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -6086,7 +6085,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
   *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -6144,7 +6143,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
   *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
@@ -6173,7 +6172,7 @@ __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint
   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
@@ -6239,7 +6238,7 @@ __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Out
   *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
   *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
 {
   uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
@@ -6398,7 +6397,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, u
   *         @arg External event source 3
   *         @arg External event source 4
   */
-__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
 {
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
@@ -6473,7 +6472,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Eve
   *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
   *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
   */
-__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
 {
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
@@ -6551,7 +6550,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
   *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
   */
-__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
 {
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
@@ -6615,7 +6614,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Eve
   *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
   *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
   */
-__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
 {
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
@@ -6695,7 +6694,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event
   *         @arg @ref LL_HRTIM_EE_FILTER_14
   *         @arg @ref LL_HRTIM_EE_FILTER_15
   */
-__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
 {
   uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
   return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
@@ -6730,7 +6729,7 @@ __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Pr
   *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
   */
 
-__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
 {
   return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
 }
@@ -6822,7 +6821,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault,
   *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
   *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
   */
-__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
 {
   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
@@ -6876,7 +6875,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fa
   *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
   *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
   */
-__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
 {
   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
@@ -6958,7 +6957,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Faul
   *         @arg @ref LL_HRTIM_FLT_FILTER_14
   *         @arg @ref LL_HRTIM_FLT_FILTER_15
   */
-__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
 {
   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
@@ -6993,7 +6992,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t P
   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
   *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
   */
-__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
 {
   return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
 }
@@ -7086,7 +7085,7 @@ __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
   *         @arg @ref LL_HRTIM_FAULT_5
   * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
 {
   uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
@@ -7142,7 +7141,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
   *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
   *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx)
 {
   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
 }
@@ -7196,7 +7195,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t Clo
   *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
   *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx)
 {
   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
 }
@@ -7251,7 +7250,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Pr
   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
   *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
 {
   return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
 }
@@ -7284,7 +7283,7 @@ __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx)
 {
   uint32_t temp; /* MISRAC-2012 compliance */
   temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
@@ -7436,7 +7435,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
   *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx)
 {
   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
 }
@@ -7463,7 +7462,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t Comp
   *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
   *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx)
 {
   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
 }
@@ -7490,7 +7489,7 @@ __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Perio
   *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
   *         The maximum value is 0x0000 FFDF.
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx)
 {
   return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
 }
@@ -7523,7 +7522,7 @@ __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
 }
@@ -7559,7 +7558,7 @@ __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
   *         @arg @ref LL_HRTIM_BM_STATUS_NORMAL
   *         @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
   */
-__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx)
 {
   return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
 }
@@ -7589,7 +7588,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
 }
@@ -7611,7 +7610,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
 }
@@ -7633,7 +7632,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
 }
@@ -7655,7 +7654,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
 }
@@ -7677,7 +7676,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
 }
@@ -7699,7 +7698,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
 }
@@ -7721,7 +7720,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
 }
@@ -7743,7 +7742,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of SYNC bit in HRTIM_MISR register  (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
 }
@@ -7784,7 +7783,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -7830,7 +7829,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -7875,7 +7874,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -7920,7 +7919,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -7965,7 +7964,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8010,7 +8009,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8051,7 +8050,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8092,7 +8091,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8133,7 +8132,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8174,7 +8173,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8215,7 +8214,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8256,7 +8255,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8297,7 +8296,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8338,7 +8337,7 @@ __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
@@ -8383,7 +8382,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
 }
@@ -8416,7 +8415,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
 }
@@ -8449,7 +8448,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
 }
@@ -8482,7 +8481,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
 }
@@ -8515,7 +8514,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
 }
@@ -8548,7 +8547,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
 }
@@ -8581,7 +8580,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
 }
@@ -8614,7 +8613,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
 }
@@ -8677,7 +8676,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -8744,7 +8743,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Time
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -8811,7 +8810,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -8878,7 +8877,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -8945,7 +8944,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9012,7 +9011,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9073,7 +9072,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9134,7 +9133,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9195,7 +9194,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9256,7 +9255,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9317,7 +9316,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9378,7 +9377,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Tim
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9439,7 +9438,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Time
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9500,7 +9499,7 @@ __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t T
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9545,7 +9544,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
   * @param  HRTIMx High Resolution Timer instance
   * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx)
 {
   return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
 }
@@ -9608,7 +9607,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9675,7 +9674,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9742,7 +9741,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9809,7 +9808,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9876,7 +9875,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -9943,7 +9942,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10004,7 +10003,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10065,7 +10064,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10126,7 +10125,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10187,7 +10186,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10248,7 +10247,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10309,7 +10308,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10370,7 +10369,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10431,7 +10430,7 @@ __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32
   *         @arg @ref LL_HRTIM_TIMER_E
   * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
 {
   uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
@@ -10474,6 +10473,4 @@ ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
 
 #endif /* STM32H7xx_LL_HRTIM_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
 
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hsem.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hsem.h
index 1e5953c502..cff88b5cd5 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hsem.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hsem.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -63,6 +62,7 @@ extern "C" {
   * @}
   */
 
+
 /** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines
   * @brief    Flags defines which can be used with LL_HSEM_ReadReg function
   * @{
@@ -238,7 +238,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho
   */
 __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
 {
-  return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
+  return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
 }
 
 /**
@@ -292,6 +292,8 @@ __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
 /**
   * @brief  Release all semaphore with the same core id.
   * @rmtoll CR           KEY           LL_HSEM_ResetAllLock
+  * @rmtoll CR           SEC           LL_HSEM_ResetAllLock
+  * @rmtoll CR           PRIV          LL_HSEM_ResetAllLock
   * @param  HSEMx HSEM Instance.
   * @param  key Key value.
   * @param  core This parameter can be one of the following values:
@@ -898,5 +900,3 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32
 #endif
 
 #endif /* __STM32H7xx_LL_HSEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.c
index 09e20cb4fb..69f7923c66 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -25,7 +24,7 @@
 #include "stm32_assert.h"
 #else
 #define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
 
 /** @addtogroup STM32H7xx_LL_Driver
   * @{
@@ -84,7 +83,7 @@
   *          - SUCCESS: I2C registers are de-initialized
   *          - ERROR: I2C registers are not de-initialized
   */
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx)
 {
   ErrorStatus status = SUCCESS;
 
@@ -133,7 +132,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
     /* Release reset of I2C clock */
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C5);
   }
-#endif
+#endif /* I2C5 */
   else
   {
     status = ERROR;
@@ -150,7 +149,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
   *          - SUCCESS: I2C registers are initialized
   *          - ERROR: Not applicable
   */
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct)
 {
   /* Check the I2C Instance I2Cx */
   assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
@@ -249,5 +248,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h
index c698b7ae3a..6400400661 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -69,38 +68,46 @@ typedef struct
   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
 
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetMode(). */
 
   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
                                      This parameter must be set by referring to the STM32CubeMX Tool and
                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
 
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetTiming(). */
 
   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
 
-                                     This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
+                                     This feature can be modified afterwards using unitary functions
+                                     @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
 
   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
 
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetDigitalFilter(). */
 
   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
 
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
 
-  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
+                                     match code or next received byte.
                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
 
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_AcknowledgeNextData(). */
 
   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
 
-                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
+                                     This feature can be modified afterwards using unitary function
+                                     @ref LL_I2C_SetOwnAddress1(). */
 } LL_I2C_InitTypeDef;
 /**
   * @}
@@ -170,10 +177,11 @@ typedef struct
 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
   * @{
   */
-#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */
-#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
-#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */
-#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                 */
+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge           */
+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode
+                                                                         (Default address not acknowledge)        */
+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge */
 /**
   * @}
   */
@@ -208,14 +216,15 @@ typedef struct
 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
   * @{
   */
-#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
-#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
-#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
-#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
-#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
-#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
-#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
-#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                 */
+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared. */
+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.   */
+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done.
+                                                                         All Address2 are acknowledged.        */
 /**
   * @}
   */
@@ -250,14 +259,21 @@ typedef struct
 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
   * @{
   */
-#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
-#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
-#define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
-#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
-#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD           /*!< Enable I2C Reload mode.     */
+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND          /*!< Enable I2C Automatic end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SOFTEND                 0x00000000U              /*!< Enable I2C Software end mode
+                                                                          with no HW PEC comparison.  */
+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD       /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND      /*!< Enable SMBUS Automatic end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND      /*!< Enable SMBUS Software end mode
+                                                                          with HW PEC comparison.     */
+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
+/*!< Enable SMBUS Software end mode with HW PEC comparison.    */
 /**
   * @}
   */
@@ -265,14 +281,23 @@ typedef struct
 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
   * @{
   */
-#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                                /*!< Don't Generate Stop and Start condition.                */
-#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)                                     /*!< Generate Stop condition (Size should be set to 0).      */
-#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
-#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Start for write request.                       */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U
+/*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)
+/*!< Generate Stop condition (Size should be set to 0).      */
+#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+/*!< Generate Restart for read request, slave 7Bit address.  */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | \
+                                                       I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
+/*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
+/*!< Generate Restart for write request, slave 10Bit address.*/
 /**
   * @}
   */
@@ -280,8 +305,10 @@ typedef struct
 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
   * @{
   */
-#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */
-#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master,
+                                                                          slave enters receiver mode.  */
+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master,
+                                                                          slave enters transmitter mode.*/
 /**
   * @}
   */
@@ -289,8 +316,10 @@ typedef struct
 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
   * @{
   */
-#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */
-#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */
+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for
+                                                                          transmission */
+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for
+                                                                          reception */
 /**
   * @}
   */
@@ -298,8 +327,10 @@ typedef struct
 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
   * @{
   */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */
-#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect
+                                                                          SCL low level timeout.              */
+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect
+                                                                          both SCL and SDA high level timeout.*/
 /**
   * @}
   */
@@ -307,9 +338,12 @@ typedef struct
 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
   * @{
   */
-#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
-#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
-#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                 /*!< TimeoutA enable bit          */
+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                   /*!< TimeoutB (extended clock)
+                                                                                       enable bit                   */
+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
+                                                       I2C_TIMEOUTR_TEXTEN)       /*!< TimeoutA and TimeoutB
+(extended clock) enable bits */
 /**
   * @}
   */
@@ -353,18 +387,22 @@ typedef struct
 /**
   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
   * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.
-  * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
-  * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
-  * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
-  * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
+  * @param  __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tscldel = (SCLDEL+1)xtpresc)
+  * @param  __HOLD_TIME__  This parameter must be a value between Min_Data=0 and Max_Data=0xF.
+                           (tsdadel = SDADELxtpresc)
+  * @param  __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
+                            (tsclh = (SCLH+1)xtpresc)
+  * @param  __SCLL_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF.
+                            (tscll = (SCLL+1)xtpresc)
   * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
   */
-#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
-  ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
-   (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
-   (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
-   (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
-   (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
+  ((((uint32_t)(__PRESCALER__)    << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \
+   (((uint32_t)(__SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \
+   (((uint32_t)(__HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \
+   (((uint32_t)(__SCLH_PERIOD__)  << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \
+   (((uint32_t)(__SCLL_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))
 /**
   * @}
   */
@@ -413,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
 }
@@ -428,7 +466,8 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
   * @param  AnalogFilter This parameter can be one of the following values:
   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
   * @retval None
@@ -444,7 +483,8 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt
   *         This filter can only be programmed when the I2C is disabled (PE = 0).
   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
   * @param  I2Cx I2C Instance.
-  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
+                          and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
   * @retval None
@@ -460,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x0 and Max_Data=0xF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
 }
@@ -495,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
 }
@@ -528,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
 }
@@ -561,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
 }
@@ -576,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
   * @retval Address of data register
   */
-__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
 {
   uint32_t data_reg_addr;
 
@@ -624,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
 }
@@ -657,14 +697,14 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Enable Wakeup from STOP.
-  * @note   Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
   *         WakeUpFromStop feature is supported by the I2Cx Instance.
   * @note   This bit can only be programmed when Digital Filter is disabled.
   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
@@ -678,7 +718,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Disable Wakeup from STOP.
-  * @note   Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
   *         WakeUpFromStop feature is supported by the I2Cx Instance.
   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
   * @param  I2Cx I2C Instance.
@@ -691,13 +731,13 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Check if Wakeup from STOP is enabled or disabled.
-  * @note   Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
   *         WakeUpFromStop feature is supported by the I2Cx Instance.
   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
 }
@@ -732,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
 }
@@ -760,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
   */
-__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
 }
@@ -809,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
 }
@@ -865,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
 }
@@ -890,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x0 and Max_Data=0xF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
 }
@@ -901,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
 }
@@ -912,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
 }
@@ -923,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x0 and Max_Data=0xF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
 }
@@ -934,14 +974,14 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x0 and Max_Data=0xF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
 }
 
 /**
   * @brief  Configure peripheral mode.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
   *         CR1          SMBDEN        LL_I2C_SetMode
@@ -960,7 +1000,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
 
 /**
   * @brief  Get peripheral mode.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
   *         CR1          SMBDEN        LL_I2C_GetMode
@@ -971,14 +1011,14 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
   */
-__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
 }
 
 /**
   * @brief  Enable SMBus alert (Host or Device mode)
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   SMBus Device mode:
   *         - SMBus Alert pin is drived low and
@@ -996,7 +1036,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Disable SMBus alert (Host or Device mode)
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   SMBus Device mode:
   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
@@ -1014,20 +1054,20 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Enable SMBus Packet Error Calculation (PEC).
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
   * @param  I2Cx I2C Instance.
@@ -1040,7 +1080,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Disable SMBus Packet Error Calculation (PEC).
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
   * @param  I2Cx I2C Instance.
@@ -1053,20 +1093,20 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Configure the SMBus Clock Timeout.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
@@ -1089,7 +1129,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo
 
 /**
   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   These bits can only be programmed when TimeoutA is disabled.
   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
@@ -1104,20 +1144,20 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
 
 /**
   * @brief  Get the SMBus Clock TimeoutA setting.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0 and Max_Data=0xFFF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
 }
 
 /**
   * @brief  Set the SMBus Clock TimeoutA mode.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   This bit can only be programmed when TimeoutA is disabled.
   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
@@ -1134,7 +1174,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
 
 /**
   * @brief  Get the SMBus Clock TimeoutA mode.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
   * @param  I2Cx I2C Instance.
@@ -1142,14 +1182,14 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
   */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
 }
 
 /**
   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   These bits can only be programmed when TimeoutB is disabled.
   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
@@ -1164,20 +1204,20 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
 
 /**
   * @brief  Get the SMBus Extended Cumulative Clock TimeoutB setting.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0 and Max_Data=0xFFF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
 }
 
 /**
   * @brief  Enable the SMBus Clock Timeout.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
@@ -1195,7 +1235,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock
 
 /**
   * @brief  Disable the SMBus Clock Timeout.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
@@ -1213,7 +1253,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
 
 /**
   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
@@ -1224,9 +1264,10 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
 {
-  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
+  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
+           (ClockTimeout)) ? 1UL : 0UL);
 }
 
 /**
@@ -1265,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
 }
@@ -1298,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
 }
@@ -1331,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
 }
@@ -1364,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
 }
@@ -1397,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
 }
@@ -1436,14 +1477,14 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Enable Error interrupts.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   Any of these errors will generate interrupt :
   *         Arbitration Loss (ARLO)
@@ -1463,7 +1504,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Disable Error interrupts.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   Any of these errors will generate interrupt :
   *         Arbitration Loss (ARLO)
@@ -1487,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
 }
@@ -1508,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
 }
@@ -1521,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
 }
@@ -1534,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
 }
@@ -1547,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
 }
@@ -1560,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
 }
@@ -1573,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
 }
@@ -1586,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
 }
@@ -1599,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
 }
@@ -1612,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
 }
@@ -1625,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
 }
@@ -1638,14 +1679,14 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Indicate the status of SMBus PEC error flag in reception.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   RESET: Clear default value.
   *         SET: When the received PEC does not match with the PEC register content.
@@ -1653,14 +1694,14 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Indicate the status of SMBus Timeout detection flag.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   RESET: Clear default value.
   *         SET: When a timeout or extended clock timeout occurs.
@@ -1668,14 +1709,14 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Indicate the status of SMBus alert flag.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @note   RESET: Clear default value.
   *         SET: When SMBus host configuration, SMBus alert enabled and
@@ -1684,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
 }
@@ -1697,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
 }
@@ -1782,7 +1823,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Clear SMBus PEC error flag.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
   * @param  I2Cx I2C Instance.
@@ -1795,7 +1836,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Clear SMBus Timeout detection flag.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
   * @param  I2Cx I2C Instance.
@@ -1808,7 +1849,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Clear SMBus Alert flag.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
   * @param  I2Cx I2C Instance.
@@ -1858,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
 }
@@ -1893,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
 }
@@ -1917,13 +1958,14 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
 }
 
 /**
-  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
+            or next received byte.
   * @note   Usage in Slave mode only.
   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
   * @param  I2Cx I2C Instance.
@@ -1964,7 +2006,8 @@ __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
 /**
   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
   * @note   The master sends the complete 10bit slave address read sequence :
-  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
+            in Read direction.
   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
   * @param  I2Cx I2C Instance.
   * @retval None
@@ -1992,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
 }
@@ -2020,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
   *         @arg @ref LL_I2C_REQUEST_WRITE
   *         @arg @ref LL_I2C_REQUEST_READ
   */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
 }
@@ -2044,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
   */
-__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
 }
@@ -2090,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
 {
+  /* Declaration of tmp to prevent undefined behavior of volatile usage */
+  uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
+                             ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
+                             (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
+                             (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
+
+  /* update CR2 register */
   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
              (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
              I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
-             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+             tmp);
 }
 
 /**
@@ -2107,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
   *         @arg @ref LL_I2C_DIRECTION_WRITE
   *         @arg @ref LL_I2C_DIRECTION_READ
   */
-__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
 }
@@ -2118,16 +2168,17 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
   */
-__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
 }
 
 /**
   * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
-  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
+            or an Address Matched is received.
   *         This bit has no effect when RELOAD bit is set.
   *         This bit has no effect in device mode when SBC bit is not set.
   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
@@ -2141,26 +2192,26 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
 
 /**
   * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
   * @param  I2Cx I2C Instance.
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
 {
   return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
 }
 
 /**
   * @brief  Get the SMBus Packet Error byte calculated.
-  * @note   Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+  * @note   The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
   *         SMBus feature is supported by the I2Cx Instance.
   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
 {
   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
 }
@@ -2171,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
   * @param  I2Cx I2C Instance.
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
 {
   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
 }
@@ -2197,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
   * @{
   */
 
-ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
-ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
+ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
 
 
@@ -2226,5 +2277,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
 #endif
 
 #endif /* STM32H7xx_LL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h
index 8e22e3d7f5..d34acc2622 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -337,5 +336,3 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
 #endif
 
 #endif /* STM32H7xx_LL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c
index bf08c4620c..54dc528488 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -28,7 +27,7 @@
 #include "stm32_assert.h"
 #else
 #define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
 
 /** @addtogroup STM32H7xx_LL_Driver
   * @{
@@ -93,7 +92,7 @@
   *          - SUCCESS: LPTIMx registers are de-initialized
   *          - ERROR: invalid LPTIMx instance
   */
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx)
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx)
 {
   ErrorStatus result = SUCCESS;
 
@@ -164,7 +163,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
   *          - SUCCESS: LPTIMx instance has been initialized
   *          - ERROR: LPTIMx instance hasn't been initialized
   */
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct)
 {
   ErrorStatus result = SUCCESS;
   /* Check the parameters */
@@ -215,12 +214,15 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
   uint32_t tmpCFGR;
   uint32_t tmpCMP;
   uint32_t tmpARR;
+  uint32_t primask_bit;
   uint32_t tmpCFGR2;
 
   /* Check the parameters */
   assert_param(IS_LPTIM_INSTANCE(LPTIMx));
 
-  __disable_irq();
+  /* Enter critical section */
+  primask_bit = __get_PRIMASK();
+  __set_PRIMASK(1) ;
 
   /********** Save LPTIM Config *********/
   /* Save LPTIM source clock */
@@ -311,8 +313,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
       do
       {
         rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
-      }
-      while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+      } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
 
       LL_LPTIM_ClearFlag_ARROK(LPTIMx);
     }
@@ -328,7 +329,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
   LPTIMx->CFGR = tmpCFGR;
   LPTIMx->CFGR2 = tmpCFGR2;
 
-  __enable_irq();
+  /* Exit critical section: restore previous priority mask */
+  __set_PRIMASK(primask_bit);
 }
 
 /**
@@ -350,5 +352,3 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h
index a2ee75c665..033e7b25b4 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -67,22 +66,26 @@ typedef struct
   uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.
                                 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
 
-                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
+                                This feature can be modified afterwards using unitary
+                                function @ref LL_LPTIM_SetClockSource().*/
 
   uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.
                                 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
 
-                                This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
+                                This feature can be modified afterwards using using unitary
+                                function @ref LL_LPTIM_SetPrescaler().*/
 
   uint32_t Waveform;       /*!< Specifies the waveform shape.
                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
 
-                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+                                This feature can be modified afterwards using unitary
+                                function @ref LL_LPTIM_ConfigOutput().*/
 
   uint32_t Polarity;       /*!< Specifies waveform polarity.
                                 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
 
-                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
+                                This feature can be modified afterwards using unitary
+                                function @ref LL_LPTIM_ConfigOutput().*/
 } LL_LPTIM_InitTypeDef;
 
 /**
@@ -199,14 +202,14 @@ typedef struct
 #define LL_LPTIM_TRIG_SOURCE_LPTIM2           0x00000000U                                                          /*!<External input trigger is connected to LPTIM2 output*/
 #define LL_LPTIM_TRIG_SOURCE_LPTIM3           LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to LPTIM3 output*/
 #define LL_LPTIM_TRIG_SOURCE_LPTIM4           LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to LPTIM4 output*/
-#define LL_LPTIM_TRIG_SOURCE_LPTIM5           (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to LPTIM5 output*/
+#define LL_LPTIM_TRIG_SOURCE_LPTIM5           (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to LPTIM5 output*/
 #define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI1 FS A output*/
-#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B        (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI1 FS B output*/
+#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B        (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to SAI1 FS B output*/
 #define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI2 FS A output*/
-#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B        (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI2 FS B output*/
-#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A        (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI4 FS A output*/
+#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B        (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to SAI2 FS B output*/
+#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A        (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to SAI4 FS A output*/
 #define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI4 FS B output*/
-#define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK       (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_1)                          /*!<External input trigger is connected to DFSDM2_BRK[0] */
+#define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK       (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to DFSDM2_BRK[0] */
 /**
   * @}
   */
@@ -336,14 +339,27 @@ typedef struct
   * @{
   */
 
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_LPTIM_ClearFLAG_CMPM  LL_LPTIM_ClearFlag_CMPM
+#define LL_LPTIM_ClearFLAG_CC1   LL_LPTIM_ClearFlag_CC1
+#define LL_LPTIM_ClearFLAG_CC2   LL_LPTIM_ClearFlag_CC2
+#define LL_LPTIM_ClearFLAG_CC1O  LL_LPTIM_ClearFlag_CC1O
+#define LL_LPTIM_ClearFLAG_CC2O  LL_LPTIM_ClearFlag_CC2O
+#define LL_LPTIM_ClearFLAG_ARRM  LL_LPTIM_ClearFlag_ARRM
+/**
+@endcond
+  */
+
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
   * @{
   */
 
-ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
+ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx);
 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
-ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
 /**
   * @}
@@ -373,7 +389,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
 }
@@ -426,7 +442,7 @@ __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
 }
@@ -469,7 +485,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda
   *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
   *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
 }
@@ -484,7 +500,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
   * @note autoreload value be strictly greater than the compare value.
   * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload
   * @param  LPTIMx Low-Power Timer instance
-  * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @param  AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
   * @retval None
   */
 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
@@ -496,9 +512,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto
   * @brief  Get actual auto reload value
   * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload
   * @param  LPTIMx Low-Power Timer instance
-  * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
+  * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
 }
@@ -525,7 +541,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare
   * @param  LPTIMx Low-Power Timer instance
   * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
 }
@@ -540,7 +556,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval Counter value
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
 }
@@ -568,7 +584,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou
   *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
   *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
 }
@@ -617,7 +633,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo
   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
   *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
 }
@@ -644,7 +660,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari
   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
   *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
 }
@@ -688,7 +704,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc
   *         @arg @ref LL_LPTIM_PRESCALER_DIV64
   *         @arg @ref LL_LPTIM_PRESCALER_DIV128
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
 }
@@ -770,7 +786,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
 }
@@ -863,7 +879,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour
   *         (*)  Value not defined in all devices. \n
   *
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
 }
@@ -878,7 +894,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
   *         @arg @ref LL_LPTIM_TRIG_FILTER_4
   *         @arg @ref LL_LPTIM_TRIG_FILTER_8
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
 }
@@ -892,7 +908,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
   *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
   *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
 }
@@ -928,13 +944,14 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo
   *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
   *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
 }
 
 /**
-  * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
+  * @brief  Configure the active edge or edges used by the counter when
+            the LPTIM is clocked by an external clock source.
   * @note This function must be called when the LPTIM instance is disabled.
   * @note When both external clock signal edges are considered active ones,
   *       the LPTIM must also be clocked by an internal clock source with a
@@ -969,7 +986,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF
   *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
   *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
 }
@@ -984,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
   *         @arg @ref LL_LPTIM_CLK_FILTER_4
   *         @arg @ref LL_LPTIM_CLK_FILTER_8
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
 }
@@ -1022,7 +1039,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc
   *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
   *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
   */
-__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx)
 {
   return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
 }
@@ -1061,7 +1078,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
 }
@@ -1074,13 +1091,14 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
   * @{
   */
 
+
 /**
   * @brief  Clear the compare match flag (CMPMCF)
-  * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM
+  * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFlag_CMPM
   * @param  LPTIMx Low-Power Timer instance
   * @retval None
   */
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
 {
   SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
 }
@@ -1091,18 +1109,18 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
 }
 
 /**
   * @brief  Clear the autoreload match flag (ARRMCF)
-  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM
+  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFlag_ARRM
   * @param  LPTIMx Low-Power Timer instance
   * @retval None
   */
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
 {
   SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
 }
@@ -1113,7 +1131,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
 }
@@ -1135,7 +1153,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
 }
@@ -1152,12 +1170,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
 }
 
 /**
-  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
+            completed. If so, a new one can be initiated.
   * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
 }
@@ -1174,12 +1193,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
 }
 
 /**
-  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
+            completed. If so, a new one can be initiated.
   * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
 }
@@ -1196,12 +1216,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
 }
 
 /**
-  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
+  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
+            operates in encoder mode).
   * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
 }
@@ -1218,12 +1239,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
 }
 
 /**
-  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
+  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
+            operates in encoder mode).
   * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
 }
@@ -1264,7 +1286,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
 }
@@ -1297,7 +1319,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
 }
@@ -1330,7 +1352,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
 }
@@ -1363,7 +1385,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
 }
@@ -1396,7 +1418,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit(1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
 }
@@ -1429,7 +1451,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit(1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx)
 {
   return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
 }
@@ -1462,7 +1484,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
   * @param  LPTIMx Low-Power Timer instance
   * @retval State of bit(1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx)
 {
   return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
 }
@@ -1490,5 +1512,3 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
 #endif
 
 #endif /* STM32H7xx_LL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.c
index 7ff544123e..739cb1a632 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -45,6 +44,9 @@
   * @{
   */
 
+/* Definition of default baudrate value used for LPUART initialisation */
+#define LPUART_DEFAULT_BAUDRATE          (9600U)
+
 /**
   * @}
   */
@@ -127,7 +129,7 @@
   *          - SUCCESS: LPUART registers are de-initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx)
 {
   ErrorStatus status = SUCCESS;
 
@@ -165,7 +167,7 @@ ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
   *          - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
   *          - ERROR: Problem occurred during LPUART Registers initialization
   */
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct)
 {
   ErrorStatus status = ERROR;
   uint32_t periphclk;
@@ -254,7 +256,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
 {
   /* Set LPUART_InitStruct fields to default values */
   LPUART_InitStruct->PrescalerValue      = LL_LPUART_PRESCALER_DIV1;
-  LPUART_InitStruct->BaudRate            = 9600U;
+  LPUART_InitStruct->BaudRate            = LPUART_DEFAULT_BAUDRATE;
   LPUART_InitStruct->DataWidth           = LL_LPUART_DATAWIDTH_8B;
   LPUART_InitStruct->StopBits            = LL_LPUART_STOPBITS_1;
   LPUART_InitStruct->Parity              = LL_LPUART_PARITY_NONE ;
@@ -281,6 +283,3 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h
index 64e17f9c70..fe66becb5b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -159,7 +158,6 @@ typedef struct
 #define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
 #define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
 #define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
-#define LL_LPUART_ICR_TXFECF               USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
 #define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
 #define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
 #define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
@@ -524,7 +522,7 @@ __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
 }
@@ -557,7 +555,7 @@ __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
 }
@@ -577,7 +575,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
 {
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
 }
 
 /**
@@ -592,7 +590,7 @@ __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32
   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 }
@@ -612,7 +610,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
 {
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
 }
 
 /**
@@ -627,7 +625,7 @@ __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32
   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
   *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
 }
@@ -655,8 +653,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
 {
-  MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
-             (RXThreshold << USART_CR3_RXFTCFG_Pos));
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
 }
 
 /**
@@ -669,7 +667,7 @@ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint
   */
 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
 }
 
 /**
@@ -681,7 +679,7 @@ __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
 }
 
 /**
@@ -691,7 +689,7 @@ __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
 }
@@ -704,7 +702,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
 }
 
 /**
@@ -715,7 +713,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
 }
 
 /**
@@ -726,7 +724,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
 }
 
 /**
@@ -737,7 +735,7 @@ __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
 }
 
 /**
@@ -755,7 +753,7 @@ __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
 {
-  MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
 }
 
 /**
@@ -769,7 +767,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint
   *         @arg @ref LL_LPUART_DIRECTION_TX
   *         @arg @ref LL_LPUART_DIRECTION_TX_RX
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
 }
@@ -803,7 +801,7 @@ __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity
   *         @arg @ref LL_LPUART_PARITY_EVEN
   *         @arg @ref LL_LPUART_PARITY_ODD
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
 }
@@ -830,7 +828,7 @@ __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t
   *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
   *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
 }
@@ -859,7 +857,7 @@ __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t Dat
   *         @arg @ref LL_LPUART_DATAWIDTH_8B
   *         @arg @ref LL_LPUART_DATAWIDTH_9B
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
 }
@@ -872,7 +870,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
 }
 
 /**
@@ -883,7 +881,7 @@ __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
 }
 
 /**
@@ -892,7 +890,7 @@ __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
 }
@@ -939,7 +937,7 @@ __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t Pre
   *         @arg @ref LL_LPUART_PRESCALER_DIV128
   *         @arg @ref LL_LPUART_PRESCALER_DIV256
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
 }
@@ -966,7 +964,7 @@ __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_
   *         @arg @ref LL_LPUART_STOPBITS_1
   *         @arg @ref LL_LPUART_STOPBITS_2
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
 }
@@ -1024,7 +1022,7 @@ __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t Swap
   *         @arg @ref LL_LPUART_TXRX_STANDARD
   *         @arg @ref LL_LPUART_TXRX_SWAPPED
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
 }
@@ -1051,7 +1049,7 @@ __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi
   *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
   *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
 }
@@ -1078,7 +1076,7 @@ __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t Pi
   *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
   *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
 }
@@ -1108,7 +1106,7 @@ __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32
   *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
   *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
 }
@@ -1139,7 +1137,7 @@ __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint3
   *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
   *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
 }
@@ -1183,7 +1181,7 @@ __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_
   * @param  LPUARTx LPUART Instance
   * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
 }
@@ -1196,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
   *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
   *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
 }
@@ -1273,7 +1271,7 @@ __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t Ha
   *         @arg @ref LL_LPUART_HWCONTROL_CTS
   *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
 }
@@ -1306,7 +1304,7 @@ __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
 }
@@ -1335,7 +1333,7 @@ __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type
   *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
   *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
 }
@@ -1400,7 +1398,8 @@ __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t Peri
   *         @arg @ref LL_LPUART_PRESCALER_DIV256
   * @retval Baud Rate
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
+                                               uint32_t PrescalerValue)
 {
   uint32_t lpuartdiv;
   uint32_t brrresult;
@@ -1456,7 +1455,7 @@ __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
 }
@@ -1487,7 +1486,7 @@ __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint
   * @param  LPUARTx LPUART Instance
   * @retval Time value expressed on 5 bits ([4:0] bits) : c
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
 }
@@ -1510,7 +1509,7 @@ __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32
   * @param  LPUARTx LPUART Instance
   * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
 }
@@ -1543,7 +1542,7 @@ __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
 }
@@ -1570,7 +1569,7 @@ __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint3
   *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
   *         @arg @ref LL_LPUART_DE_POLARITY_LOW
   */
-__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
 {
   return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
 }
@@ -1589,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
 }
@@ -1600,7 +1599,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
 }
@@ -1611,7 +1610,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
 }
@@ -1622,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
 }
@@ -1633,13 +1632,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE
+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
@@ -1647,7 +1645,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
 }
@@ -1658,13 +1656,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUART
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF
+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
@@ -1672,7 +1669,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
 }
@@ -1683,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
 }
@@ -1694,7 +1691,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
 }
@@ -1705,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
 }
@@ -1716,7 +1713,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
 }
@@ -1727,7 +1724,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
 }
@@ -1738,7 +1735,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
 }
@@ -1749,7 +1746,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
 }
@@ -1760,7 +1757,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
 }
@@ -1771,7 +1768,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
 }
@@ -1782,7 +1779,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
 }
@@ -1793,7 +1790,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
 }
@@ -1804,7 +1801,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
 }
@@ -1815,7 +1812,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
 }
@@ -1875,17 +1872,6 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
   WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
 }
 
-/**
-  * @brief  Clear TX FIFO Empty Flag
-  * @rmtoll ICR          TXFECF        LL_LPUART_ClearFlag_TXFE
-  * @param  LPUARTx LPUART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)
-{
-  WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);
-}
-
 /**
   * @brief  Clear Transmission Complete Flag
   * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
@@ -1946,11 +1932,10 @@ __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
 }
 
-/* Legacy define */
-#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE
+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
@@ -1960,7 +1945,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
 }
 
 /**
@@ -1971,11 +1956,10 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
 }
 
-/* Legacy define */
-#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF
+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
@@ -1985,7 +1969,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
 }
 
 /**
@@ -1996,7 +1980,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
 }
 
 /**
@@ -2007,7 +1991,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
 }
 
 /**
@@ -2018,7 +2002,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
 }
 
 /**
@@ -2029,7 +2013,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
 }
 
 /**
@@ -2044,7 +2028,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
 }
 
 /**
@@ -2055,7 +2039,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
 }
 
 /**
@@ -2066,7 +2050,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
 }
 
 /**
@@ -2077,7 +2061,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
 }
 
 /**
@@ -2088,7 +2072,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
 }
 
 /**
@@ -2099,11 +2083,10 @@ __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
 }
 
-/* Legacy define */
-#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE
+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
@@ -2113,7 +2096,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
 }
 
 /**
@@ -2124,11 +2107,10 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
 }
 
-/* Legacy define */
-#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF
+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
@@ -2138,7 +2120,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
 }
 
 /**
@@ -2149,7 +2131,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
 }
 
 /**
@@ -2160,7 +2142,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
 }
 
 /**
@@ -2171,7 +2153,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
 }
 
 /**
@@ -2182,7 +2164,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
 }
 
 /**
@@ -2197,7 +2179,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
 }
 
 /**
@@ -2208,7 +2190,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
 }
 
 /**
@@ -2219,7 +2201,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
 }
 
 /**
@@ -2230,7 +2212,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
 }
 
 /**
@@ -2241,7 +2223,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
 }
 
 /**
@@ -2250,13 +2232,12 @@ __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
@@ -2264,7 +2245,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
 }
@@ -2275,13 +2256,12 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
@@ -2289,7 +2269,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
 }
@@ -2300,7 +2280,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
 }
@@ -2311,7 +2291,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
 }
@@ -2322,7 +2302,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
 }
@@ -2333,7 +2313,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
 }
@@ -2344,7 +2324,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
 }
@@ -2355,7 +2335,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
 }
@@ -2366,7 +2346,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
 }
@@ -2377,7 +2357,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
 }
@@ -2388,7 +2368,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
 }
@@ -2409,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
 }
 
 /**
@@ -2420,7 +2400,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
 }
 
 /**
@@ -2429,7 +2409,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
 }
@@ -2442,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
 {
-  SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
 }
 
 /**
@@ -2453,7 +2433,7 @@ __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
   */
 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
 {
-  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
 }
 
 /**
@@ -2462,7 +2442,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
 }
@@ -2495,7 +2475,7 @@ __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
 {
   return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
 }
@@ -2510,7 +2490,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUAR
   *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
   * @retval Address of data register
   */
-__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
 {
   uint32_t data_reg_addr;
 
@@ -2542,7 +2522,7 @@ __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32
   * @param  LPUARTx LPUART Instance
   * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
 {
   return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
 }
@@ -2553,7 +2533,7 @@ __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
   * @param  LPUARTx LPUART Instance
   * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
   */
-__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
 {
   return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
 }
@@ -2633,8 +2613,8 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
   * @{
   */
-ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
-ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
 void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
 /**
   * @}
@@ -2661,4 +2641,3 @@ void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
 
 #endif /* STM32H7xx_LL_LPUART_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.c
index 1c33f828a7..c57e98d3a2 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -806,4 +805,3 @@ void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h
index 38d08f2e91..8b80c7d811 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -4357,4 +4356,3 @@ void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode);
 
 #endif /* STM32H7xx_LL_MDMA_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.c
index 5b8937bf10..ffbb5487dc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -227,4 +226,3 @@ void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h
index b6d4d3eb88..abc4d301d8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -255,7 +254,7 @@ typedef struct
   */
 
 /** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays
-  * @note   Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
+  * @note   Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver,
   *         not timeout values.
   *         For details on delays values, refer to descriptions in source code
   *         above each literal definition.
@@ -822,4 +821,4 @@ void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
 
 #endif /* __STM32H7xx_LL_OPAMP_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.c
index 28ce161867..86b029ada0 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -83,4 +82,3 @@ ErrorStatus LL_PWR_DeInit(void)
 
 #endif /* defined (USE_FULL_LL_DRIVER) */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h
index a7f82057c2..be137a46fc 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -2300,4 +2299,3 @@ ErrorStatus LL_PWR_DeInit(void);
 
 #endif /* STM32H7xx_LL_PWR_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c
index 68ed42ac55..e7b85d92d6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c
@@ -6,14 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 #if defined(USE_FULL_LL_DRIVER)
@@ -22,9 +20,9 @@
 #include "stm32h7xx_ll_rcc.h"
 #include "stm32h7xx_ll_bus.h"
 #ifdef  USE_FULL_ASSERT
-  #include "stm32_assert.h"
+#include "stm32_assert.h"
 #else
-  #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
 #endif
 
 /** @addtogroup STM32H7xx_LL_Driver
@@ -39,7 +37,14 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
+/** @addtogroup RCC_LL_Private_Variables
+  * @{
+  */
 const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
 /** @addtogroup RCC_LL_Private_Macros
@@ -119,8 +124,8 @@ static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
   */
 void LL_RCC_DeInit(void)
 {
-   /* Increasing the CPU frequency */
-  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+  /* Increasing the CPU frequency */
+  if (FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
@@ -130,26 +135,26 @@ void LL_RCC_DeInit(void)
   SET_BIT(RCC->CR, RCC_CR_HSION);
 
   /* Wait for HSI READY bit */
-  while(LL_RCC_HSI_IsReady() == 0U)
+  while (LL_RCC_HSI_IsReady() == 0U)
   {}
 
   /* Reset CFGR register */
   CLEAR_REG(RCC->CFGR);
 
   /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
-  |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
+            | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
 
   /* Wait for PLL1 READY bit to be reset */
-  while(LL_RCC_PLL1_IsReady() != 0U)
+  while (LL_RCC_PLL1_IsReady() != 0U)
   {}
 
   /* Wait for PLL2 READY bit to be reset */
-  while(LL_RCC_PLL2_IsReady() != 0U)
+  while (LL_RCC_PLL2_IsReady() != 0U)
   {}
 
   /* Wait for PLL3 READY bit to be reset */
-  while(LL_RCC_PLL3_IsReady() != 0U)
+  while (LL_RCC_PLL3_IsReady() != 0U)
   {}
 
 #if defined(RCC_D1CFGR_HPRE)
@@ -174,7 +179,7 @@ void LL_RCC_DeInit(void)
 #endif /* RCC_D1CFGR_HPRE */
 
   /* Reset PLLCKSELR register to default value */
-  RCC->PLLCKSELR= RCC_PLLCKSELR_DIVM1_5|RCC_PLLCKSELR_DIVM2_5|RCC_PLLCKSELR_DIVM3_5;
+  RCC->PLLCKSELR = RCC_PLLCKSELR_DIVM1_5 | RCC_PLLCKSELR_DIVM2_5 | RCC_PLLCKSELR_DIVM3_5;
 
   /* Reset PLLCFGR register to default value */
   LL_RCC_WriteReg(PLLCFGR, 0x01FF0000U);
@@ -205,14 +210,14 @@ void LL_RCC_DeInit(void)
 
   /* Clear all interrupts */
   SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC
-                   | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
-                   | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
+          | RCC_CICR_CSIRDYC | RCC_CICR_HSI48RDYC | RCC_CICR_PLLRDYC | RCC_CICR_PLL2RDYC
+          | RCC_CICR_PLL3RDYC | RCC_CICR_LSECSSC | RCC_CICR_HSECSSC);
 
   /* Clear reset source flags */
   SET_BIT(RCC->RSR, RCC_RSR_RMVF);
-  
-   /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if (FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
     MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
@@ -298,7 +303,7 @@ void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
     case LL_RCC_PLLSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -372,7 +377,7 @@ void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
     case LL_RCC_PLLSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -446,7 +451,7 @@ void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks)
     case LL_RCC_PLLSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -516,9 +521,9 @@ uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N,
 {
   float_t freq;
 
-  freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN/(float_t)0x2000));
+  freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
 
-  freq = freq/(float_t)PQR;
+  freq = freq / (float_t)PQR;
 
   return (uint32_t)freq;
 }
@@ -542,11 +547,11 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
   switch (LL_RCC_GetUSARTClockSource(USARTxSource))
   {
     case LL_RCC_USART16_CLKSOURCE_PCLK2:
-      usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_USART234578_CLKSOURCE_PCLK1:
-      usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_USART16_CLKSOURCE_PLL2Q:
@@ -571,7 +576,7 @@ uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
     case LL_RCC_USART234578_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        usart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -614,7 +619,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
   {
     case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
-      lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      lpuart_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_LPUART1_CLKSOURCE_PLL2Q:
@@ -636,7 +641,7 @@ uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
     case LL_RCC_LPUART1_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        lpuart_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -681,11 +686,11 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
   switch (LL_RCC_GetI2CClockSource(I2CxSource))
   {
     case LL_RCC_I2C123_CLKSOURCE_PCLK1:
-      i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_I2C4_CLKSOURCE_PCLK4:
-      i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      i2c_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_I2C123_CLKSOURCE_PLL3R:
@@ -701,7 +706,7 @@ uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
     case LL_RCC_I2C4_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        i2c_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -741,12 +746,12 @@ uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
   switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
   {
     case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
-      lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
     case LL_RCC_LPTIM345_CLKSOURCE_PCLK4:
-      lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      lptim_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_LPTIM1_CLKSOURCE_PLL2P:
@@ -836,7 +841,7 @@ uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
 #if defined (RCC_CDCCIP1R_SAI2ASEL) || defined(RCC_CDCCIP1R_SAI2BSEL)
     case LL_RCC_SAI2A_CLKSOURCE_PLL1Q:
     case LL_RCC_SAI2B_CLKSOURCE_PLL1Q:
-#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */ 
+#endif /* RCC_CDCCIP1R_SAI2ASEL || RCC_CDCCIP1R_SAI2BSEL */
       if (LL_RCC_PLL1_IsReady() != 0U)
       {
         LL_RCC_GetPLL1ClockFreq(&PLL_Clocks);
@@ -1157,7 +1162,7 @@ uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
       break;
 
     case LL_RCC_DFSDM1_CLKSOURCE_PCLK2:
-      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     default:
@@ -1189,7 +1194,7 @@ uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource)
       break;
 
     case LL_RCC_DFSDM2_CLKSOURCE_PCLK4:
-      dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      dfsdm_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     default:
@@ -1279,7 +1284,7 @@ uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource)
     case LL_RCC_SPDIF_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        spdif_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -1346,11 +1351,11 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
       break;
 
     case LL_RCC_SPI45_CLKSOURCE_PCLK2:
-      spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      spi_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_SPI6_CLKSOURCE_PCLK4:
-      spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      spi_frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_SPI45_CLKSOURCE_PLL2Q:
@@ -1375,7 +1380,7 @@ uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
     case LL_RCC_SPI6_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        spi_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -1417,13 +1422,13 @@ uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource)
   switch (LL_RCC_GetSWPClockSource(SWPxSource))
   {
     case LL_RCC_SWP_CLKSOURCE_PCLK1:
-      swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler())));
+      swp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler())));
       break;
 
     case LL_RCC_SWP_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        swp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -1495,7 +1500,7 @@ uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
   switch (LL_RCC_GetFMCClockSource(FMCxSource))
   {
     case LL_RCC_FMC_CLKSOURCE_HCLK:
-      fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      fmc_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
       break;
 
     case LL_RCC_FMC_CLKSOURCE_PLL1Q:
@@ -1542,7 +1547,7 @@ uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource)
   switch (LL_RCC_GetQSPIClockSource(QSPIxSource))
   {
     case LL_RCC_QSPI_CLKSOURCE_HCLK:
-      qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      qspi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
       break;
 
     case LL_RCC_QSPI_CLKSOURCE_PLL1Q:
@@ -1591,7 +1596,7 @@ uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource)
   switch (LL_RCC_GetOSPIClockSource(OSPIxSource))
   {
     case LL_RCC_OSPI_CLKSOURCE_HCLK:
-      ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(),LL_RCC_GetSysPrescaler()));
+      ospi_frequency = RCC_GetHCLKClockFreq(LL_RCC_CALC_SYSCLK_FREQ(RCC_GetSystemClockFreq(), LL_RCC_GetSysPrescaler()));
       break;
 
     case LL_RCC_OSPI_CLKSOURCE_PLL1Q:
@@ -1639,7 +1644,7 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
     case LL_RCC_CLKP_CLKSOURCE_HSI:
       if (LL_RCC_HSI_IsReady() != 0U)
       {
-        clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+        clkp_frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       }
       break;
 
@@ -1691,7 +1696,7 @@ static uint32_t RCC_GetSystemClockFreq(void)
   {
     /* No check on Ready: Won't be selected by hardware if not */
     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
-      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider()>> RCC_CR_HSIDIV_Pos);
+      frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos);
       break;
 
     case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
@@ -1786,4 +1791,3 @@ static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h
index 2ab40eb0f6..bd700dc2b8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h
@@ -2,20 +2,16 @@
   ******************************************************************************
   * @file    stm32h7xx_ll_rcc.h
   * @author  MCD Application Team
-  * @version $VERSION$
-  * @date    $DATE$
   * @brief   Header file of RCC LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   ******************************************************************************
   */
 
@@ -53,6 +49,9 @@ extern const uint8_t LL_RCC_PrescTable[16];
   */
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
 #if !defined(UNUSED)
 #define UNUSED(x) ((void)(x))
 #endif
@@ -94,15 +93,9 @@ extern const uint8_t LL_RCC_PrescTable[16];
                                                                      (( __POS__              ) << LL_RCC_POS_SHIFT)  | \
                                                                      (( __REG__              ) << LL_RCC_REG_SHIFT)  | \
                                                                      (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
-  * @{
-  */
 /**
   * @}
   */
-#endif /*USE_FULL_LL_DRIVER*/
 /* Exported types ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
@@ -1692,7 +1685,7 @@ __STATIC_INLINE void LL_RCC_HSE_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -1730,7 +1723,7 @@ __STATIC_INLINE void LL_RCC_HSI_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -1740,7 +1733,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL);
 }
 
 /**
@@ -1827,7 +1820,7 @@ __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
     MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
   }
 #else
-    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
+  MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
 #endif /* RCC_VER_X */
 }
 
@@ -1850,7 +1843,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
     return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
   }
 #else
-    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
 #endif /* RCC_VER_X */
 }
 
@@ -1889,7 +1882,7 @@ __STATIC_INLINE void LL_RCC_CSI_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -1933,7 +1926,7 @@ __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
   }
 #else
-    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
+  return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
 #endif /* RCC_VER_X */
 }
 
@@ -1960,7 +1953,7 @@ __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
     MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
   }
 #else
-    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
+  MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
 #endif /* RCC_VER_X */
 }
 
@@ -1983,7 +1976,7 @@ __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
     return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
   }
 #else
-    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
+  return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
 #endif /* RCC_VER_X */
 }
 
@@ -2022,7 +2015,7 @@ __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -2053,7 +2046,7 @@ __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -2072,9 +2065,9 @@ __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL);
 }
- /* alias */
+/* alias */
 #define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady
 /**
   * @}
@@ -2094,7 +2087,7 @@ __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL);
 }
 /**
   * @}
@@ -2112,7 +2105,7 @@ __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL);
 }
 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
 /**
@@ -2142,7 +2135,7 @@ __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
 {
-  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL);
 }
 #endif  /* RCC_GCR_WW1RSC */
 
@@ -2164,7 +2157,7 @@ __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
 {
-  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);
+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL);
 }
 #endif  /*DUAL_CORE*/
 /**
@@ -2193,7 +2186,7 @@ __STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
 {
-  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL);
 }
 
 /**
@@ -2213,7 +2206,7 @@ __STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
 {
-  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);
+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL);
 }
 
 /**
@@ -2244,7 +2237,7 @@ __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
 {
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
 }
 
 /**
@@ -2350,7 +2343,7 @@ __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
 {
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -2388,7 +2381,7 @@ __STATIC_INLINE void LL_RCC_LSI_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
 {
-  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -2789,7 +2782,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
   */
 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
 {
-  MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
+  MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
 }
 
 /**
@@ -2850,7 +2843,7 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale
   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
   *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*) 
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
@@ -2902,9 +2895,9 @@ __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescale
 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
 {
 #if defined(RCC_D1CCIPR_FMCSEL)
-  uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
+  uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
 #else
-  uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
+  uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
 #endif /*  */
   MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
 }
@@ -3020,7 +3013,7 @@ __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
-  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*) 
+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
   *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
   *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)
@@ -3153,9 +3146,9 @@ __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
 {
 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
-   MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
 #else
-   MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
 }
 
@@ -3170,7 +3163,7 @@ __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
   */
 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
 {
-   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
 }
 #endif /* DFSDM2_BASE */
 
@@ -3477,7 +3470,7 @@ __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
 #else
   const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
 #endif /* RCC_D1CCIPR_FMCSEL */
-  return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );
+  return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
 }
 
 /**
@@ -4040,7 +4033,7 @@ __STATIC_INLINE void LL_RCC_DisableRTC(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
 {
-  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);
+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
 }
 
 /**
@@ -4349,7 +4342,7 @@ __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -4402,7 +4395,7 @@ __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL);
 }
 
 /**
@@ -4412,7 +4405,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL);
 }
 
 /**
@@ -4422,7 +4415,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL);
 }
 
 /**
@@ -4432,7 +4425,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL);
 }
 
 /**
@@ -4576,7 +4569,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
   */
 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
 {
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos);
 }
 
 /**
@@ -4600,7 +4593,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
   */
 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
 {
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos);
 }
 
 /**
@@ -4611,7 +4604,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
   */
 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
 {
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos);
 }
 
 /**
@@ -4622,7 +4615,7 @@ __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
   */
 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
 {
-  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);
+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos);
 }
 
 /**
@@ -4663,7 +4656,7 @@ __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -4716,7 +4709,7 @@ __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL);
 }
 
 /**
@@ -4726,7 +4719,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL);
 }
 
 /**
@@ -4736,7 +4729,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL);
 }
 
 /**
@@ -4746,7 +4739,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL);
 }
 
 /**
@@ -4890,7 +4883,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
   */
 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
 {
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos);
 }
 
 /**
@@ -4912,7 +4905,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
   */
 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
 {
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos);
 }
 
 /**
@@ -4923,7 +4916,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
   */
 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
 {
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos);
 }
 
 /**
@@ -4934,7 +4927,7 @@ __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
   */
 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
 {
-  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);
+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos);
 }
 
 /**
@@ -4975,7 +4968,7 @@ __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
 {
-  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);
+  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL);
 }
 
 /**
@@ -5028,7 +5021,7 @@ __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL);
 }
 
 /**
@@ -5038,7 +5031,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL);
 }
 
 /**
@@ -5048,7 +5041,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL);
 }
 
 /**
@@ -5058,7 +5051,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
 {
-  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);
+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL);
 }
 
 /**
@@ -5202,7 +5195,7 @@ __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
   */
 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
 {
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos);
 }
 
 /**
@@ -5224,7 +5217,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
   */
 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
 {
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos);
 }
 
 /**
@@ -5235,7 +5228,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
   */
 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
 {
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos);
 }
 
 /**
@@ -5246,7 +5239,7 @@ __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
   */
 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
 {
-  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);
+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos);
 }
 
 /**
@@ -5386,7 +5379,7 @@ __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5396,7 +5389,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5406,7 +5399,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5416,7 +5409,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5426,7 +5419,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5436,7 +5429,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5446,7 +5439,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5456,7 +5449,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5466,7 +5459,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5476,7 +5469,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5486,7 +5479,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
 {
-  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);
+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5501,9 +5494,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
 {
 #if defined(DUAL_CORE)
-  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
 #else
-  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL);
 #endif /*DUAL_CORE*/
 }
 
@@ -5515,7 +5508,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
 }
 #endif  /*DUAL_CORE*/
 
@@ -5526,7 +5519,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
 }
 
 #if defined(DUAL_CORE)
@@ -5537,7 +5530,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
 }
 #endif  /*DUAL_CORE*/
 
@@ -5548,7 +5541,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
 }
 
 #if defined(DUAL_CORE)
@@ -5559,7 +5552,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
 }
 #endif  /*DUAL_CORE*/
 
@@ -5575,9 +5568,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
 {
 #if defined(DUAL_CORE)
-  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
 #else
-  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL);
 #endif  /*DUAL_CORE*/
 }
 
@@ -5589,7 +5582,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
 }
 #endif  /*DUAL_CORE*/
 
@@ -5600,7 +5593,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5610,7 +5603,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5620,7 +5613,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
 }
 
 #if defined(RCC_RSR_D1RSTF)
@@ -5631,7 +5624,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
 }
 #endif /* RCC_RSR_D1RSTF */
 
@@ -5643,7 +5636,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL);
 }
 #endif /* RCC_RSR_CDRSTF */
 
@@ -5655,7 +5648,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
 }
 #endif /* RCC_RSR_D2RSTF */
 
@@ -5672,9 +5665,9 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
 {
 #if defined(DUAL_CORE)
-  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
 #else
-  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL);
 #endif/*DUAL_CORE*/
 }
 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
@@ -5687,7 +5680,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
 {
-  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
 }
 #endif  /*DUAL_CORE*/
 
@@ -5709,7 +5702,7 @@ __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5719,7 +5712,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5729,7 +5722,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5739,7 +5732,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5749,7 +5742,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5759,7 +5752,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5769,7 +5762,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5779,7 +5772,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5789,7 +5782,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5799,7 +5792,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5809,7 +5802,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5819,7 +5812,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5829,7 +5822,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5839,7 +5832,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5849,7 +5842,7 @@ __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
   */
 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
 {
-  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5869,7 +5862,7 @@ __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5879,7 +5872,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5889,7 +5882,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5899,7 +5892,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5909,7 +5902,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5919,7 +5912,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5929,7 +5922,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5939,7 +5932,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5949,7 +5942,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5959,7 +5952,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5969,7 +5962,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5979,7 +5972,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5989,7 +5982,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -5999,7 +5992,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -6009,7 +6002,7 @@ __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
   */
 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
 {
-  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);
+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
 }
 
 /**
@@ -6238,7 +6231,7 @@ __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6248,7 +6241,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6258,7 +6251,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6268,7 +6261,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6278,7 +6271,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6288,7 +6281,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6298,7 +6291,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6308,7 +6301,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6318,7 +6311,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
 }
 
 /**
@@ -6328,7 +6321,7 @@ __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
   */
 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
 {
-  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);
+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
 }
 /**
   * @}
@@ -6409,4 +6402,3 @@ uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
 
 #endif /* STM32H7xx_LL_RCC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c
index a98addf20e..02981e2c45 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -42,7 +41,7 @@
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
-/** @addtogroup RNG_LL_Private_Macros
+/** @defgroup RNG_LL_Private_Macros RNG Private Macros
   * @{
   */
 #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \
@@ -60,7 +59,7 @@
 #define IS_LL_RNG_CONFIG2 (__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
 
 #define IS_LL_RNG_CONFIG3 (__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
-#endif /* RNG_CR_CONDRST*/
+#endif /* RNG_CR_CONDRST */
 /**
   * @}
   */
@@ -82,16 +81,26 @@
   *          - SUCCESS: RNG registers are de-initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx)
 {
+  ErrorStatus status = SUCCESS;
+
   /* Check the parameters */
   assert_param(IS_RNG_ALL_INSTANCE(RNGx));
-  /* Enable RNG reset state */
-  LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
+  if (RNGx == RNG)
+  {
+    /* Enable RNG reset state */
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
 
-  /* Release RNG from reset state */
-  LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
-  return (SUCCESS);
+    /* Release RNG from reset state */
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  return status;
 }
 
 /**
@@ -154,5 +163,3 @@ void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h
index 1b98dd0fb7..62039d0e6b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -39,6 +38,15 @@ extern "C" {
   */
 
 /* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_LL_Private_Defines RNG Private Defines
+  * @{
+  */
+/*  Health test control register information to use in CCM algorithm */
+#define LL_RNG_HTCFG   0x17590ABCU /*!< Magic number */
+/**
+  * @}
+  */
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
 /* Private macros ------------------------------------------------------------*/
@@ -211,7 +219,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
 }
@@ -224,7 +232,12 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
 {
+#if defined(RNG_CR_CONDRST)
+  MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+#else
   CLEAR_BIT(RNGx->CR, RNG_CR_CED);
+#endif /* RNG_CR_CONDRST*/
 }
 
 /**
@@ -235,7 +248,12 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
 {
+#if defined(RNG_CR_CONDRST)
+  MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
+#else
   SET_BIT(RNGx->CR, RNG_CR_CED);
+#endif /* RNG_CR_CONDRST*/
 }
 
 /**
@@ -244,7 +262,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
 }
@@ -278,7 +296,7 @@ __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);
 }
@@ -300,7 +318,7 @@ __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);
 }
@@ -313,7 +331,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
 {
-  CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
+  MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 }
 
 /**
@@ -324,7 +343,8 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
 {
-  SET_BIT(RNGx->CR, RNG_CR_NISTC);
+  MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 }
 
 /**
@@ -333,7 +353,7 @@ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);
 }
@@ -347,7 +367,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
 {
-  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);
+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 }
 
 /**
@@ -356,7 +377,7 @@ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)
   * @param  RNGx RNG Instance
   * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F
   */
-__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx)
 {
   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);
 }
@@ -370,7 +391,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
 {
-  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);
+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 }
 
 /**
@@ -379,7 +401,7 @@ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)
   * @param  RNGx RNG Instance
   * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7
   */
-__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx)
 {
   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
 }
@@ -393,7 +415,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
 {
-  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);
+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 }
 
 /**
@@ -402,7 +425,7 @@ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)
   * @param  RNGx RNG Instance
   * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF
   */
-__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx)
 {
   return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
 }
@@ -432,7 +455,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
 {
-  MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);
+  MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST);
+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);
 }
 
 /**
@@ -457,7 +481,7 @@ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)
   *         @arg @ref LL_RNG_CLKDIV_BY_16384
   *         @arg @ref LL_RNG_CLKDIV_BY_32768
   */
-__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx)
 {
   return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);
 }
@@ -476,7 +500,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
 }
@@ -487,7 +511,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
 }
@@ -498,7 +522,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
 }
@@ -509,7 +533,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
 }
@@ -520,7 +544,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
 }
@@ -586,7 +610,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx)
 {
   return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
 }
@@ -605,7 +629,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
   * @param  RNGx RNG Instance
   * @retval Generated 32-bit random value
   */
-__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx)
 {
   return (uint32_t)(READ_REG(RNGx->DR));
 }
@@ -628,6 +652,9 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
   */
 __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
 {
+  /*!< magic number must be written immediately before to RNG_HTCRG */
+  WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
+
   WRITE_REG(RNGx->HTCR, HTCFG);
 }
 
@@ -639,6 +666,9 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)
   */
 __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
 {
+  /*!< magic number must be written immediately before reading RNG_HTCRG */
+  WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG);
+
   return (uint32_t)READ_REG(RNGx->HTCR);
 }
 
@@ -652,7 +682,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)
   */
 ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
 void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
-ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
+ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx);
 
 /**
   * @}
@@ -679,4 +709,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
 
 #endif /* __STM32H7xx_LL_RNG_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.c
index 613cd55b98..0e516e75d1 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -87,18 +86,7 @@
 
 #define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
 
-#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_MARCH) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_APRIL) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_MAY) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_JUNE) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_JULY) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
-                                 || ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
+#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U))
 
 #define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
 
@@ -175,24 +163,19 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
     LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
     LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
 
-#if defined(RTC_ICSR_ALRAWF)
+#if defined(TAMP)
     /* Reset ICSR register and exit initialization mode */
-    LL_RTC_WriteReg(RTCx, ICSR,      0x00000000U);
-#endif /* RTC_ICSR_ALRAWF */
-#if defined(RTC_ISR_ALRAWF)
+    LL_RTC_WriteReg(RTCx, ICSR,   0x00000000U);
+#else
     /* Reset ISR register and exit initialization mode */
-    LL_RTC_WriteReg(RTCx, ISR,      0x00000000U);
-#endif /* RTC_ISR_ALRAWF */
+    LL_RTC_WriteReg(RTCx, ISR,    0x00000000U);
 
-#if defined(RTC_TAMPCR_TAMP1E)
     /* Reset Tamper and alternate functions configuration register */
     LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U);
-#endif /* RTC_TAMPCR_TAMP1E */
 
-#if defined(RTC_OR_ALARMOUTTYPE)
     /* Reset Option register */
-    LL_RTC_WriteReg(RTCx, OR, 0x00000000U);
-#endif /* RTC_OR_ALARMOUTTYPE */
+    LL_RTC_WriteReg(RTCx, OR,     0x00000000U);
+#endif /* TAMP */
 
     /* Wait till the RTC RSF flag is set */
     status = LL_RTC_WaitForSynchro(RTCx);
@@ -201,14 +184,14 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
   /* Enable the write protection for RTC registers */
   LL_RTC_EnableWriteProtection(RTCx);
 
-#if defined (TAMP_CR1_TAMP1E)
+#if defined(TAMP)
   /* DeInitialization of the TAMP */
   LL_RTC_WriteReg(TAMP, CR1,      0xFFFF0000U);
   LL_RTC_WriteReg(TAMP, FLTCR,    0x00000000U);
   LL_RTC_WriteReg(TAMP, ATCR1,    0x00000000U);
   LL_RTC_WriteReg(TAMP, IER,      0x00000000U);
   LL_RTC_WriteReg(TAMP, SCR,      0xFFFFFFFFU);
-#endif /* TAMP_CR1_TAMP1E */
+#endif /* TAMP */
 
   return status;
 }
@@ -343,7 +326,7 @@ ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Time
     }
 
     /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTC);
+    LL_RTC_DisableInitMode(RTCx);
 
     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
@@ -431,7 +414,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date
     }
 
     /* Exit Initialization mode */
-    LL_RTC_DisableInitMode(RTC);
+    LL_RTC_DisableInitMode(RTCx);
 
     /* If  RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
     if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
@@ -891,4 +874,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.h
index 230b1e3c7b..85e6fadda7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rtc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -235,24 +234,21 @@ typedef struct
   * @brief    Flags defines which can be used with LL_RTC_ReadReg function
   * @{
   */
-#if defined(RTC_SCR_CALRAF)
+#if defined(TAMP)
 #define LL_RTC_SCR_ITSF                    RTC_SCR_CITSF
 #define LL_RTC_SCR_TSOVF                   RTC_SCR_CTSOVF
 #define LL_RTC_SCR_TSF                     RTC_SCR_CTSF
 #define LL_RTC_SCR_WUTF                    RTC_SCR_CWUTF
 #define LL_RTC_SCR_ALRBF                   RTC_SCR_CALRBF
 #define LL_RTC_SCR_ALRAF                   RTC_SCR_CALRAF
-#endif /* RTC_SCR_CALRAF */
 
-#if defined(RTC_ICSR_ALRAWF)
 #define LL_RTC_ICSR_RECALPF                RTC_ICSR_RECALPF
 #define LL_RTC_ICSR_INITF                  RTC_ICSR_INITF
 #define LL_RTC_ICSR_RSF                    RTC_ICSR_RSF
 #define LL_RTC_ICSR_INITS                  RTC_ICSR_INITS
 #define LL_RTC_ICSR_SHPF                   RTC_ICSR_SHPF
 #define LL_RTC_ICSR_WUTWF                  RTC_ICSR_WUTWF
-#endif /* RTC_ICSR_ALRAWF */
-#if defined(RTC_ISR_ALRAWF)
+#else
 #define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF
 #define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF
 #define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F
@@ -270,7 +266,7 @@ typedef struct
 #define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF
 #define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF
 #define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF
-#endif /* RTC_ISR_ALRAWF */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -283,18 +279,12 @@ typedef struct
 #define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE
 #define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE
 #define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE
-#if defined(RTC_TAMPCR_TAMP3E)
+#if !defined(TAMP)
 #define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE
-#endif /* RTC_TAMPCR_TAMP3E */
-#if defined(RTC_TAMPCR_TAMP2E)
 #define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined(RTC_TAMPCR_TAMP1E)
 #define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined(RTC_TAMPCR_TAMPIE)
 #define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE
-#endif /* RTC_TAMPCR_TAMPIE */
+#endif /* !TAMP */
 /**
   * @}
   */
@@ -355,14 +345,13 @@ typedef struct
 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
   * @{
   */
-#if defined(RTC_CR_TAMPALRM_TYPE)
+#if defined(TAMP)
 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  RTC_CR_TAMPALRM_TYPE   /*!< RTC_ALARM is open-drain output */
 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   0x00000000U            /*!< RTC_ALARM is push-pull output */
-#endif /* RTC_CR_TAMPALRM_TYPE */
-#if defined(RTC_OR_ALARMOUTTYPE)
+#else
 #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U            /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE    /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
-#endif /* RTC_OR_ALARMOUTTYPE */
+#endif /* TAMP */
 /**
   * @}
   */
@@ -456,18 +445,13 @@ typedef struct
   * @}
   */
 
+#if defined(TAMP)
 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
   * @{
   */
-#if defined(TAMP_CR1_TAMP1E)
 #define LL_RTC_TAMPER_1                    TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(TAMP_CR1_TAMP2E)
 #define LL_RTC_TAMPER_2                    TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(TAMP_CR1_TAMP3E)
 #define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
-#endif /* TAMP_CR1_TAMP3E */
 /**
   * @}
   */
@@ -475,15 +459,9 @@ typedef struct
 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
   * @{
   */
-#if defined(TAMP_CR1_TAMP1E)
 #define LL_RTC_TAMPER_MASK_TAMPER1         TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(TAMP_CR1_TAMP2E)
 #define LL_RTC_TAMPER_MASK_TAMPER2         TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(TAMP_CR1_TAMP3E)
 #define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* TAMP_CR1_TAMP3E */
 /**
   * @}
   */
@@ -491,20 +469,13 @@ typedef struct
 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
   * @{
   */
-#if defined(TAMP_CR1_TAMP1E)
 #define LL_RTC_TAMPER_NOERASE_TAMPER1      TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(TAMP_CR1_TAMP2E)
 #define LL_RTC_TAMPER_NOERASE_TAMPER2      TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(TAMP_CR1_TAMP3E)
 #define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* TAMP_CR1_TAMP3E */
 /**
   * @}
   */
 
-#if defined(TAMP_FLTCR_TAMPPRCH)
 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
   * @{
   */
@@ -515,9 +486,7 @@ typedef struct
 /**
   * @}
   */
-#endif /* TAMP_FLTCR_TAMPPRCH */
 
-#if defined(TAMP_FLTCR_TAMPFLT)
 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
   * @{
   */
@@ -528,9 +497,7 @@ typedef struct
 /**
   * @}
   */
-#endif /* TAMP_FLTCR_TAMPFLT */
 
-#if defined(TAMP_FLTCR_TAMPFREQ)
 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
   * @{
   */
@@ -545,36 +512,23 @@ typedef struct
 /**
   * @}
   */
-#endif /* TAMP_FLTCR_TAMPFREQ */
 
 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
   * @{
   */
-#if defined(TAMP_CR1_TAMP1E)
 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
-#endif /* TAMP_CR1_TAMP1E */
-#if defined(TAMP_CR1_TAMP2E)
 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
-#endif /* TAMP_CR1_TAMP2E */
-#if defined(TAMP_CR1_TAMP3E)
 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
-#endif /* TAMP_CR1_TAMP3E */
 /**
   * @}
   */
-
+#else
 /** @defgroup RTC_LL_EC_TAMPER  TAMPER
   * @{
   */
-#if defined (RTC_TAMPCR_TAMP1E)
 #define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined (RTC_TAMPCR_TAMP2E)
 #define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined (RTC_TAMPCR_TAMP3E)
 #define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
-#endif /* RTC_TAMPCR_TAMP3E */
 /**
   * @}
   */
@@ -582,15 +536,9 @@ typedef struct
 /** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK
   * @{
   */
-#if defined (RTC_TAMPCR_TAMP1E)
 #define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined (RTC_TAMPCR_TAMP2E)
 #define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined (RTC_TAMPCR_TAMP3E)
 #define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */
-#endif /* RTC_TAMPCR_TAMP3E */
 /**
   * @}
   */
@@ -598,20 +546,13 @@ typedef struct
 /** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE
   * @{
   */
-#if defined (RTC_TAMPCR_TAMP1E)
 #define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined (RTC_TAMPCR_TAMP2E)
 #define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined (RTC_TAMPCR_TAMP3E)
 #define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
-#endif /* RTC_TAMPCR_TAMP3E */
 /**
   * @}
   */
 
-#if defined(RTC_TAMPCR_TAMPPRCH)
 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
   * @{
   */
@@ -622,9 +563,7 @@ typedef struct
 /**
   * @}
   */
-#endif /* RTC_TAMPCR_TAMPPRCH */
 
-#if defined(RTC_TAMPCR_TAMPFLT)
 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
   * @{
   */
@@ -635,9 +574,7 @@ typedef struct
 /**
   * @}
   */
-#endif /* RTC_TAMPCR_TAMPFLT */
 
-#if defined(RTC_TAMPCR_TAMPFREQ)
 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
   * @{
   */
@@ -652,41 +589,29 @@ typedef struct
 /**
   * @}
   */
-#endif /* RTC_TAMPCR_TAMPFREQ */
 
 /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL
   * @{
   */
-#if defined (RTC_TAMPCR_TAMP1E)
 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPCR_TAMP1E */
-#if defined (RTC_TAMPCR_TAMP2E)
 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPCR_TAMP2E */
-#if defined (RTC_TAMPCR_TAMP3E)
 #define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/
-#endif /* RTC_TAMPCR_TAMP3E */
 /**
   * @}
   */
+#endif /* TAMP */
 
+#if defined(TAMP)
 /** @defgroup RTC_LL_EC_ACTIVE_MODE   ACTIVE TAMPER MODE
   * @{
   */
-#if defined(TAMP_ATCR1_TAMP1AM)
 #define LL_RTC_TAMPER_ATAMP_TAMP1AM               TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */
-#endif /* TAMP_ATCR1_TAMP1AM */
-#if defined(TAMP_ATCR1_TAMP2AM)
 #define LL_RTC_TAMPER_ATAMP_TAMP2AM               TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */
-#endif /* TAMP_ATCR1_TAMP2AM */
-#if defined(TAMP_ATCR1_TAMP3AM)
 #define LL_RTC_TAMPER_ATAMP_TAMP3AM               TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */
-#endif /* TAMP_ATCR1_TAMP3AM */
 /**
   * @}
   */
 
-#if defined(TAMP_ATCR1_ATCKSEL)
 /** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER   ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK
   * @{
   */
@@ -701,31 +626,25 @@ typedef struct
 /**
   * @}
   */
-#endif /* TAMP_ATCR1_ATCKSEL */
 
 /** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION   ACTIVE TAMPER OUTPUT SELECTION
   * @{
   */
-#if defined(TAMP_ATCR1_TAMP1AM)
 #define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL1_Pos)
 #define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL1_Pos)
 #define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL1_Pos)
-#endif /* TAMP_ATCR1_TAMP1AM */
 
-#if defined(TAMP_ATCR1_TAMP2AM)
 #define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL2_Pos)
 #define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL2_Pos)
 #define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL2_Pos)
-#endif /* TAMP_ATCR1_TAMP2AM */
 
-#if defined(TAMP_ATCR1_TAMP3AM)
 #define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL3_Pos)
 #define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL3_Pos)
 #define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL3_Pos)
-#endif /* TAMP_ATCR1_TAMP3AM */
 /**
   * @}
   */
+#endif /* TAMP */
 
 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
   * @{
@@ -1021,7 +940,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
 }
 
-#if defined(RTC_CR_TAMPALRM_TYPE)
+#if defined(TAMP)
 /**
   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
   * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType
@@ -1048,39 +967,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
 {
   return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
 }
-#endif /* RTC_CR_TAMPALRM_TYPE */
-
-#if defined(RTC_ICSR_INIT)
-/**
-  * @brief  Enable initialization mode
-  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
-  *         and prescaler register (RTC_PRER).
-  *         Counters are stopped and start counting from the new value when INIT is reset.
-  * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
-{
-  /* Set the Initialization mode */
-  WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
-}
-
-/**
-  * @brief  Disable initialization mode (Free running mode)
-  * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode
-  * @param  RTCx RTC Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
-{
-  /* Exit Initialization mode */
-  WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
-}
-
-#endif /* RTC_ICSR_INIT */
-
-#if defined(RTC_OR_ALARMOUTTYPE)
+#else
 /**
   * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
   * @note   Used only when RTC_ALARM is mapped on PC13
@@ -1109,9 +996,37 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
 {
   return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
 }
-#endif /* RTC_OR_ALARMOUTTYPE */
+#endif /* TAMP */
 
-#if defined(RTC_ISR_INIT)
+#if defined(TAMP)
+/**
+  * @brief  Enable initialization mode
+  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
+  *         and prescaler register (RTC_PRER).
+  *         Counters are stopped and start counting from the new value when INIT is reset.
+  * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Set the Initialization mode */
+  WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
+}
+
+/**
+  * @brief  Disable initialization mode (Free running mode)
+  * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode
+  * @param  RTCx RTC Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
+{
+  /* Exit Initialization mode */
+  WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
+}
+
+#else
 /**
   * @brief  Enable initialization mode
   * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
@@ -1138,7 +1053,7 @@ __STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
   /* Exit Initialization mode */
   WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);
 }
-#endif /* RTC_ISR_INIT */
+#endif /* TAMP */
 
 /**
   * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
@@ -1297,7 +1212,7 @@ __STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
   WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
 }
 
-#if defined(RTC_CR_TAMPOE)
+#if defined(TAMP)
 /**
   * @brief  Enable tamper output.
   * @note When the tamper output is enabled, all external and internal tamper flags
@@ -1332,9 +1247,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL);
 }
-#endif /* RTC_CR_TAMPOE */
 
-#if defined(RTC_CR_TAMPALRM_PU)
 /**
   * @brief  Enable internal pull-up in output mode.
   * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp
@@ -1367,9 +1280,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL);
 }
-#endif /* RTC_CR_TAMPALRM_PU */
 
-#if defined(RTC_CR_OUT2EN)
 /**
   * @brief  Enable RTC_OUT2 output
   * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
@@ -1405,10 +1316,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL);
 }
-
-#endif /* RTC_CR_OUT2EN */
-
-#if defined(RTC_OR_OUT_RMP)
+#else
 /**
   * @brief  Enable RTC_OUT remap
   * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap
@@ -1430,7 +1338,7 @@ __STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);
 }
-#endif /* RTC_OR_OUT_RMP */
+#endif /* TAMP */
 
 /**
   * @}
@@ -1458,7 +1366,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma
 
 /**
   * @brief  Get time format (AM or PM notation)
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1492,7 +1400,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
 
 /**
   * @brief  Get Hours in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1527,7 +1435,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
 
 /**
   * @brief  Get Minutes in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1562,7 +1470,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
 
 /**
   * @brief  Get Seconds in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1612,7 +1520,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24,
 
 /**
   * @brief  Get time (hour, minute and second) in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
   *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1758,7 +1666,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
 
 /**
   * @brief  Get Year in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
   * @rmtoll RTC_DR           YT            LL_RTC_DATE_GetYear
@@ -1792,7 +1700,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
 
 /**
   * @brief  Get Week day
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @rmtoll RTC_DR           WDU           LL_RTC_DATE_GetWeekDay
   * @param  RTCx RTC Instance
@@ -1839,7 +1747,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
 
 /**
   * @brief  Get Month in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
   * @rmtoll RTC_DR           MT            LL_RTC_DATE_GetMonth
@@ -1881,7 +1789,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
 
 /**
   * @brief  Get Day in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
   * @rmtoll RTC_DR           DT            LL_RTC_DATE_GetDay
@@ -1943,7 +1851,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin
 
 /**
   * @brief  Get date (WeekDay, Day, Month and Year) in BCD format
-  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+  * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
   *       before reading this bit
   * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
   * and __LL_RTC_GET_DAY are available to get independently each parameter.
@@ -2949,7 +2857,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
   * @{
   */
 
-#if defined(RTC_TAMPCR_TAMPTS)
+#if !defined(TAMP)
 /**
   * @brief  Activate timestamp on tamper detection event
   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
@@ -2971,9 +2879,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);
 }
-#endif /* RTC_TAMPCR_TAMPTS */
-
-#if defined(RTC_CR_TAMPTS)
+#else
 /**
   * @brief  Activate timestamp on tamper detection event
   * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper
@@ -2996,7 +2902,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
 }
-#endif /* RTC_CR_TAMPTS */
+#endif /* !TAMP */
 
 /**
   * @}
@@ -3006,7 +2912,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
   * @{
   */
 
-#if defined(RTC_TAMPCR_TAMP1E)
+#if !defined(TAMP)
 /**
   * @brief  Enable RTC_TAMPx input detection
   * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable
@@ -3115,9 +3021,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t T
 {
   SET_BIT(RTCx->TAMPCR, Tamper);
 }
-#endif /* RTC_TAMPCR_TAMP1E */
 
-#if defined(RTC_TAMPCR_TAMPPUDIS)
 /**
   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
   * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
@@ -3139,9 +3043,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);
 }
-#endif /* RTC_TAMPCR_TAMPPUDIS */
 
-#if defined(RTC_TAMPCR_TAMPPRCH)
 /**
   * @brief  Set RTC_TAMPx precharge duration
   * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge
@@ -3172,9 +3074,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
 {
   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));
 }
-#endif /* RTC_TAMPCR_TAMPPRCH */
 
-#if defined(RTC_TAMPCR_TAMPFLT)
 /**
   * @brief  Set RTC_TAMPx filter count
   * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount
@@ -3205,9 +3105,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
 {
   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));
 }
-#endif /* RTC_TAMPCR_TAMPFLT */
 
-#if defined(RTC_TAMPCR_TAMPFREQ)
 /**
   * @brief  Set Tamper sampling frequency
   * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq
@@ -3246,9 +3144,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
 {
   return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));
 }
-#endif /* RTC_TAMPCR_TAMPFREQ */
 
-#if defined(RTC_TAMPCR_TAMP1E)
 /**
   * @brief  Enable Active level for Tamper input
   * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel
@@ -3284,9 +3180,9 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_
 {
   CLEAR_BIT(RTCx->TAMPCR, Tamper);
 }
-#endif /* RTC_TAMPCR_TAMP1E */
+#endif /* !TAMP */
 
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Enable TAMPx input detection
   * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Enable
@@ -3322,9 +3218,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper)
 {
   CLEAR_BIT(TAMPx->CR1, Tamper);
 }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR2_TAMP1MSK)
 /**
   * @brief  Enable Tamper mask flag
   * @note Associated Tamper IT must not enabled when tamper mask is set.
@@ -3433,9 +3327,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint3
 {
   CLEAR_BIT(TAMPx->CR2, Tamper);
 }
-#endif /* TAMP_CR2_TAMP1MSK */
 
-#if defined(TAMP_FLTCR_TAMPPUDIS)
 /**
   * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
   * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp
@@ -3558,7 +3450,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx)
 {
   return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ));
 }
-#endif /* TAMP_FLTCR_TAMPPUDIS */
+#endif /* TAMP */
 
 /**
   * @}
@@ -3673,7 +3565,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
   * @{
   */
 
-#if defined(RTC_BKP0R)
+#if !defined(TAMP)
 /**
   * @brief  Writes a data in a specified RTC Backup data register.
   * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister
@@ -3774,9 +3666,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back
   /* Read the specified register */
   return (*(__IO uint32_t *)tmp);
 }
-#endif /* RTC_BKP0R */
-
-#if defined(TAMP_BKP0R_BKP)
+#else
 /**
   * @brief  Writes a data in a specified Backup data register.
   * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_SetRegister
@@ -3819,7 +3709,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back
   */
 __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)
 {
-  uint32_t tmp = 0U;
+  uint32_t tmp;
 
   tmp = (uint32_t)(&(TAMPx->BKP0R));
   tmp += (BackupRegister * 4U);
@@ -3869,7 +3759,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t Backup
   */
 __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)
 {
-  uint32_t tmp = 0U;
+  uint32_t tmp;
 
   tmp = (uint32_t)(&(TAMPx->BKP0R));
   tmp += (BackupRegister * 4U);
@@ -3877,7 +3767,7 @@ __STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t Ba
   /* Read the specified register */
   return (*(__IO uint32_t *)tmp);
 }
-#endif /* TAMP_BKP0R_BKP */
+#endif /* !TAMP */
 
 /**
   * @}
@@ -4014,7 +3904,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
   * @{
   */
 
-#if defined(RTC_ISR_ITSF)
+#if !defined(TAMP)
 /**
   * @brief  Get Internal Time-stamp flag
   * @rmtoll RTC_ISR          ITSF          LL_RTC_IsActiveFlag_ITS
@@ -4311,9 +4201,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);
 }
-#endif /* RTC_ISR_ITSF */
+#endif /* !TAMP */
 
-#if defined(RTC_SR_ITSF)
+#if defined(TAMP)
 /**
   * @brief  Get Internal Time-stamp flag
   * @rmtoll RTC_SR          ITSF          LL_RTC_IsActiveFlag_ITS
@@ -4379,9 +4269,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);
 }
-#endif /* RTC_SR_ITSF */
 
-#if defined(RTC_SCR_CITSF)
 /**
   * @brief  Clear Internal Time-stamp flag
   * @rmtoll RTC_SCR          CITSF          LL_RTC_ClearFlag_ITS
@@ -4447,9 +4335,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
 {
   SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
 }
-#endif /* RTC_SCR_CITSF */
 
-#if defined(RTC_ICSR_RECALPF)
 /**
   * @brief  Get Recalibration pending Flag
   * @rmtoll RTC_ICSR          RECALPF       LL_RTC_IsActiveFlag_RECALP
@@ -4548,9 +4434,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);
 }
-#endif /* RTC_ICSR_RECALPF */
 
-#if defined(RTC_MISR_ALRAMF)
 /**
   * @brief  Get Alarm A masked flag.
   * @rmtoll RTC_MISR          ALRAMF        LL_RTC_IsActiveFlag_ALRAM
@@ -4616,9 +4500,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);
 }
-#endif /* RTC_MISR_ALRAMF */
 
-#if defined(TAMP_CR1_TAMP1E)
 /**
   * @brief  Get tamper 1 detection flag.
   * @rmtoll TAMP_SR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1
@@ -4629,9 +4511,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR1_TAMP2E)
 /**
   * @brief  Get tamper 2 detection flag.
   * @rmtoll TAMP_SR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2
@@ -4642,9 +4522,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP2E */
 
-#if defined(TAMP_CR1_TAMP3E)
 /**
   * @brief  Get tamper 3 detection flag.
   * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3
@@ -4655,9 +4533,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP3E */
 
-#if defined(TAMP_CR1_TAMP1E)
 /**
   * @brief  Get tamper 1 interrupt masked flag.
   * @rmtoll TAMP_MISR          TAMP1MF        LL_RTC_IsActiveFlag_TAMP1M
@@ -4668,9 +4544,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR1_TAMP2E)
 /**
   * @brief  Get tamper 2 interrupt masked flag.
   * @rmtoll TAMP_MISR          TAMP2MF        LL_RTC_IsActiveFlag_TAMP2M
@@ -4681,9 +4555,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP2E */
 
-#if defined(TAMP_CR1_TAMP3E)
 /**
   * @brief  Get tamper 3 interrupt masked flag.
   * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M
@@ -4694,9 +4566,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP3E */
 
-#if defined(TAMP_CR1_TAMP1E)
 /**
   * @brief  Clear tamper 1 detection flag.
   * @rmtoll TAMP_SCR          CTAMP1F         LL_RTC_ClearFlag_TAMP1
@@ -4707,9 +4577,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx)
 {
   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F);
 }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR1_TAMP2E)
 /**
   * @brief  Clear tamper 2 detection flag.
   * @rmtoll TAMP_SCR          CTAMP2F         LL_RTC_ClearFlag_TAMP2
@@ -4720,9 +4588,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx)
 {
   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F);
 }
-#endif /* TAMP_CR1_TAMP2E */
 
-#if defined(TAMP_CR1_TAMP3E)
 /**
   * @brief  Clear tamper 3 detection flag.
   * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3
@@ -4733,7 +4599,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx)
 {
   SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F);
 }
-#endif /* TAMP_CR1_TAMP3E */
+#endif /* TAMP */
 
 /**
   * @}
@@ -4839,7 +4705,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
   CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
 }
 
-#if defined(RTC_TAMPCR_TAMP3E)
+#if !defined(TAMP)
 /**
   * @brief  Enable Tamper 3 interrupt
   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3
@@ -4861,9 +4727,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);
 }
-#endif /* RTC_TAMPCR_TAMP3E */
 
-#if defined(RTC_TAMPCR_TAMP2E)
 /**
   * @brief  Enable Tamper 2 interrupt
   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2
@@ -4885,9 +4749,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);
 }
-#endif /* RTC_TAMPCR_TAMP2E */
 
-#if defined(RTC_TAMPCR_TAMP1E)
 /**
   * @brief  Enable Tamper 1 interrupt
   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1
@@ -4909,9 +4771,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);
 }
-#endif /* RTC_TAMPCR_TAMP1E */
 
-#if defined(RTC_TAMPCR_TAMPIE)
 /**
   * @brief  Enable all Tamper Interrupt
   * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP
@@ -4933,7 +4793,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)
 {
   CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);
 }
-#endif /* RTC_TAMPCR_TAMPIE */
+#endif /* !TAMP */
 
 /**
   * @brief  Check if  Time-stamp interrupt is enabled or not
@@ -4979,7 +4839,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
   return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);
 }
 
-#if defined(RTC_TAMPCR_TAMP3E)
+#if !defined(TAMP)
 /**
   * @brief  Check if  Tamper 3 interrupt is enabled or not
   * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3
@@ -4990,9 +4850,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);
 }
-#endif /* RTC_TAMPCR_TAMP3E */
 
-#if defined(RTC_TAMPCR_TAMP2E)
 /**
   * @brief  Check if  Tamper 2 interrupt is enabled or not
   * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2
@@ -5004,9 +4862,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);
 
 }
-#endif /* RTC_TAMPCR_TAMP2E */
 
-#if defined(RTC_TAMPCR_TAMP1E)
 /**
   * @brief  Check if  Tamper 1 interrupt is enabled or not
   * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1
@@ -5017,9 +4873,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);
 }
-#endif /* RTC_TAMPCR_TAMP1E */
 
-#if defined(RTC_TAMPCR_TAMPIE)
 /**
   * @brief  Check if all the TAMPER interrupts are enabled or not
   * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP
@@ -5030,9 +4884,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)
 {
   return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);
 }
-#endif /* RTC_TAMPCR_TAMPIE */
+#endif /* !TAMP */
 
-#if defined(TAMP_CR1_TAMP1E)
+#if defined(TAMP)
 /**
   * @brief  Enable tamper 1 interrupt.
   * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_EnableIT_TAMP1
@@ -5054,9 +4908,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx)
 {
   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);
 }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR1_TAMP2E)
 /**
   * @brief  Enable tamper 2 interrupt.
   * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_EnableIT_TAMP2
@@ -5078,9 +4930,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx)
 {
   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);
 }
-#endif /* TAMP_CR1_TAMP2E */
 
-#if defined(TAMP_CR1_TAMP3E)
 /**
   * @brief  Enable tamper 3 interrupt.
   * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3
@@ -5102,9 +4952,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx)
 {
   CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);
 }
-#endif /* TAMP_CR1_TAMP3E */
 
-#if defined(TAMP_CR1_TAMP1E)
 /**
   * @brief  Check if tamper 1 interrupt is enabled or not.
   * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP1
@@ -5115,9 +4963,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP1E */
 
-#if defined(TAMP_CR1_TAMP2E)
 /**
   * @brief  Check if tamper 2 interrupt is enabled or not.
   * @rmtoll TAMP_IER           TAMP2IE        LL_RTC_IsEnabledIT_TAMP2
@@ -5128,9 +4974,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP2E */
 
-#if defined(TAMP_CR1_TAMP3E)
 /**
   * @brief  Check if tamper 3 interrupt is enabled or not.
   * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3
@@ -5141,13 +4985,11 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx)
 {
   return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);
 }
-#endif /* TAMP_CR1_TAMP3E */
 
 /**
   * @}
   */
 
-#if defined (TAMP_ATCR1_TAMP1AM)
 /** @defgroup RTC_LL_EF_Active_Tamper Active Tamper
   * @{
   */
@@ -5288,9 +5130,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)
 {
   return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3)));
 }
-#endif /* TAMP_ATCR1_TAMP1AM */
 
-#if defined(ATSEEDR)
 /**
   * @brief  Write active tamper seed.
   * @rmtoll TAMP_ATSEEDR   SEED          LL_RTC_TAMPER_ATAMP_WriteSeed
@@ -5301,9 +5141,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)
 {
   WRITE_REG(TAMP->ATSEEDR, Seed);
 }
-#endif /* ATSEEDR */
 
-#if defined(TAMP_ATOR_INITS)
 /**
   * @brief  Get active tamper initialization status flag.
   * @rmtoll TAMP_ATOR      INITS         LL_RTC_IsActiveFlag_ATAMP_INITS
@@ -5323,7 +5161,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)
 {
   return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);
 }
-#endif /* TAMP_ATOR_INITS */
+#endif /* TAMP */
 
 /**
   * @}
@@ -5375,4 +5213,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
 
 #endif /* STM32H7xx_LL_RTC_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c
index 36c52c328d..38e7697ed6 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c
@@ -11,6 +11,17 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                        ##### SDMMC peripheral features #####
@@ -137,17 +148,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Includes ------------------------------------------------------------------*/
@@ -1059,6 +1059,31 @@ uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
   return errorstate;
 }
 
+/**
+  * @brief  Send the Sleep command to MMC card (not SD card).
+  * @param  SDMMCx Pointer to SDMMC register base
+  * @param  Argument Argument of the command (RCA and Sleep/Awake)
+  * @retval HAL status
+  */
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
+{
+  SDMMC_CmdInitTypeDef  sdmmc_cmdinit;
+  uint32_t errorstate;
+
+  /* Send CMD5 SDMMC_CMD_MMC_SLEEP_AWAKE */
+  sdmmc_cmdinit.Argument         = Argument;
+  sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_MMC_SLEEP_AWAKE;
+  sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
+  sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+  sdmmc_cmdinit.CPSM             = SDMMC_CPSM_ENABLE;
+  (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+  /* Check for error conditions */
+  errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_MMC_SLEEP_AWAKE, SDMMC_CMDTIMEOUT);
+
+  return errorstate;
+}
+
 /**
   * @brief  Send the Status command and check the response.
   * @param  SDMMCx: Pointer to SDMMC register base
@@ -1144,7 +1169,7 @@ uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
 
   /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */
   /* CMD Response: R1 */
-  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN;*/
+  sdmmc_cmdinit.Argument         = Argument; /* SDMMC_SDR25_SWITCH_PATTERN*/
   sdmmc_cmdinit.CmdIndex         = SDMMC_CMD_HS_SWITCH;
   sdmmc_cmdinit.Response         = SDMMC_RESPONSE_SHORT;
   sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
@@ -1542,7 +1567,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
 
   if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT))
   {
-    /* Card is SD V2.0 compliant */
+    /* Card is not SD V2.0 compliant */
     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT);
 
     return SDMMC_ERROR_CMD_RSP_TIMEOUT;
@@ -1550,7 +1575,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
 
   else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL))
   {
-    /* Card is SD V2.0 compliant */
+    /* Card is not SD V2.0 compliant */
     __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL);
 
     return SDMMC_ERROR_CMD_CRC_FAIL;
@@ -1617,5 +1642,3 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h
index fd210d3885..6e12084e4b 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -135,13 +134,11 @@ typedef struct
 #define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */
 #define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */
 #define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */
-#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the   */
-                                                                       /*!< number of transferred bytes does not match the block length   */
+#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length   */
 #define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */
 #define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */
 #define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */
-#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock        */
-                                                                       /*!< command or if there was an attempt to access a locked card    */
+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card    */
 #define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */
 #define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */
 #define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */
@@ -152,8 +149,7 @@ typedef struct
 #define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */
 #define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */
 #define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */
-#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out    */
-                                                                       /*!< of erase sequence command was received                        */
+#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out of erase sequence command was received                        */
 #define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */
 #define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */
 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */
@@ -172,12 +168,10 @@ typedef struct
 #define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
 #define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */
 #define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */
-#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its     */
-                                                                      /*!< operating condition register (OCR) content in the response on the CMD line.              */
+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/
 #define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
 #define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */
-                                                                      /*!<  and asks the card whether card supports voltage.                                        */
+#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information  and asks the card whether card supports voltage.                      */
 #define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
 #define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
 #define SDMMC_CMD_VOLTAGE_SWITCH                      ((uint8_t)11U)  /*!< SD card Voltage switch to 1.8V mode.                                                     */
@@ -185,18 +179,14 @@ typedef struct
 #define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */
 #define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */
 #define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands               */
-                                                                      /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective           */
+#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective        */
 /*!< for SDHS and SDXC.                                                                       */
-#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of      */
-                                                                      /*!<  fixed 512 bytes in case of SDHC and SDXC.                                               */
-#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by                */
-                                                                      /*!< STOP_TRANSMISSION command.                                                               */
+#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                    */
+#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by  STOP_TRANSMISSION command.                                                            */
 #define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */
 #define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of     */
-                                                                      /*!< fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC.                                   */
 #define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
 #define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */
 #define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */
@@ -205,37 +195,34 @@ typedef struct
 #define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */
 #define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
 #define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command        */
-                                                                      /*!< system set by switch function command (CMD6).                                            */
-#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-                                                                      /*!<  Reserved for each command system set by switch function command (CMD6).                 */
+#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6).                                  */
+#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6).           */
 #define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */
 #define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */
 #define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by   */
-                                                                      /*!< the SET_BLOCK_LEN command.                                                               */
-#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather    */
-                                                                      /*!< than a standard command.                                                                 */
-#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card    */
-                                                                      /*!< for general purpose/application specific commands.                                       */
+#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.                                                */
+#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather than a standard command.                                                   */
+#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands.                         */
 #define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */
 
 /**
   * @brief Following commands are SD Card Specific commands.
   *        SDMMC_APP_CMD should be sent before sending these commands.
   */
-#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus    */
-                                                                      /*!<  widths are given in SCR register.                                                       */
+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register.                                                   */
 #define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */
-#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with    */
-                                                                      /*!< 32bit+CRC data block.                                                                    */
-#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to     */
-                                                                      /*!< send its operating condition register (OCR) content in the response on the CMD line.     */
+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block.                                                               */
+#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */
 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */
 #define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */
 #define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */
 #define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */
 
+/**
+  * @brief Following commands are MMC Specific commands.
+  */
+#define SDMMC_CMD_MMC_SLEEP_AWAKE                     ((uint8_t)5U)   /*!< Toggle the device between Sleep state and Standby state.                                 */
+
 /**
   * @brief Following commands are SD Card Specific security commands.
   *        SDMMC_CMD_APP_CMD should be sent before sending these commands.
@@ -292,6 +279,7 @@ typedef struct
 #define SDMMC_SDR104_SWITCH_PATTERN        ((uint32_t)0x80FF1F03U)
 #define SDMMC_SDR50_SWITCH_PATTERN         ((uint32_t)0x80FF1F02U)
 #define SDMMC_SDR25_SWITCH_PATTERN         ((uint32_t)0x80FFFF01U)
+#define SDMMC_SDR12_SWITCH_PATTERN         ((uint32_t)0x80FFFF00U)
 
 #define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)
 
@@ -303,8 +291,9 @@ typedef struct
 #define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)
 #define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)
 
+#ifndef SDMMC_DATATIMEOUT
 #define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
-
+#endif /* SDMMC_DATATIMEOUT */
 #define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)
 #define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)
 #define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)
@@ -368,12 +357,15 @@ typedef struct
 #define SDMMC_SPEED_MODE_DEFAULT               ((uint32_t)0x00000001U)
 #define SDMMC_SPEED_MODE_HIGH                  ((uint32_t)0x00000002U)
 #define SDMMC_SPEED_MODE_ULTRA                 ((uint32_t)0x00000003U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR104          SDMMC_SPEED_MODE_ULTRA
 #define SDMMC_SPEED_MODE_DDR                   ((uint32_t)0x00000004U)
+#define SDMMC_SPEED_MODE_ULTRA_SDR50           ((uint32_t)0x00000005U)
 
-#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO)    || \
-                                   ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
-                                   ((MODE) == SDMMC_SPEED_MODE_HIGH)    || \
-                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA)   || \
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO)         || \
+                                   ((MODE) == SDMMC_SPEED_MODE_DEFAULT)      || \
+                                   ((MODE) == SDMMC_SPEED_MODE_HIGH)         || \
+                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA)        || \
+                                   ((MODE) == SDMMC_SPEED_MODE_ULTRA_SDR50)  || \
                                    ((MODE) == SDMMC_SPEED_MODE_DDR))
 
 /**
@@ -702,10 +694,10 @@ typedef struct
 #define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)
 
 /* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/
-#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4)
+#define SDMMC_NSPEED_CLK_DIV ((uint8_t)0x4)
 
 /* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/
-#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)
+#define SDMMC_HSPEED_CLK_DIV ((uint8_t)0x2)
 /**
   * @}
   */
@@ -1074,6 +1066,7 @@ uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
 uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
+uint32_t SDMMC_CmdSleepMmc(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
@@ -1122,5 +1115,3 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
 #endif
 
 #endif /* STM32H7xx_LL_SDMMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c
index 57f63a7cdd..570569978a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -22,14 +21,11 @@
 #include "stm32h7xx_ll_spi.h"
 #include "stm32h7xx_ll_bus.h"
 #include "stm32h7xx_ll_rcc.h"
-#ifdef GENERATOR_I2S_PRESENT
-#include "stm32h7xx_ll_rcc.h"
-#endif /* GENERATOR_I2S_PRESENT*/
 #ifdef  USE_FULL_ASSERT
 #include "stm32_assert.h"
 #else
 #define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
 
 /** @addtogroup STM32H7xx_LL_Driver
   * @{
@@ -49,172 +45,172 @@
   * @{
   */
 
-#define IS_LL_SPI_MODE(__VALUE__)                   (((__VALUE__) == LL_SPI_MODE_MASTER)                 \
-                                                  || ((__VALUE__) == LL_SPI_MODE_SLAVE))
+#define IS_LL_SPI_MODE(__VALUE__)                   (((__VALUE__) == LL_SPI_MODE_MASTER)         || \
+                                                     ((__VALUE__) == LL_SPI_MODE_SLAVE))
 
-#define IS_LL_SPI_SS_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
+#define IS_LL_SPI_SS_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_SS_IDLENESS_00CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_01CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_02CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_03CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_04CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_05CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_06CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_07CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_08CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_09CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_10CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_11CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_12CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_13CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_14CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_SS_IDLENESS_15CYCLE))
 
-#define IS_LL_SPI_ID_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE)         \
-                                                  || ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
+#define IS_LL_SPI_ID_IDLENESS(__VALUE__)            (((__VALUE__) == LL_SPI_ID_IDLENESS_00CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_01CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_02CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_03CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_04CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_05CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_06CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_07CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_08CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_09CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_10CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_11CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_12CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_13CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_14CYCLE) || \
+                                                     ((__VALUE__) == LL_SPI_ID_IDLENESS_15CYCLE))
 
-#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN)  \
-                                                  || ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
+#define IS_LL_SPI_TXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN) || \
+                                                     ((__VALUE__) == LL_SPI_TXCRCINIT_ALL_ONES_PATTERN))
 
-#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN)  \
-                                                  || ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
+#define IS_LL_SPI_RXCRCINIT_PATTERN(__VALUE__)      (((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN) || \
+                                                     ((__VALUE__) == LL_SPI_RXCRCINIT_ALL_ONES_PATTERN))
 
-#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__)    (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) \
-                                                  || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED)    \
-                                                  || ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
+#define IS_LL_SPI_UDR_CONFIG_REGISTER(__VALUE__)    (((__VALUE__) == LL_SPI_UDR_CONFIG_REGISTER_PATTERN) || \
+                                                     ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_RECEIVED)    || \
+                                                     ((__VALUE__) == LL_SPI_UDR_CONFIG_LAST_TRANSMITTED))
 
-#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__)  (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) \
-                                                  || ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME)   \
-                                                  || ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
+#define IS_LL_SPI_UDR_DETECT_BEGIN_DATA(__VALUE__)  (((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME) || \
+                                                     ((__VALUE__) == LL_SPI_UDR_DETECT_END_DATA_FRAME)   || \
+                                                     ((__VALUE__) == LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS))
 
-#define IS_LL_SPI_PROTOCOL(__VALUE__)               (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA)           \
-                                                  || ((__VALUE__) == LL_SPI_PROTOCOL_TI))
+#define IS_LL_SPI_PROTOCOL(__VALUE__)               (((__VALUE__) == LL_SPI_PROTOCOL_MOTOROLA)           || \
+                                                     ((__VALUE__) == LL_SPI_PROTOCOL_TI))
 
-#define IS_LL_SPI_PHASE(__VALUE__)                  (((__VALUE__) == LL_SPI_PHASE_1EDGE)                 \
-                                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
+#define IS_LL_SPI_PHASE(__VALUE__)                  (((__VALUE__) == LL_SPI_PHASE_1EDGE)                 || \
+                                                     ((__VALUE__) == LL_SPI_PHASE_2EDGE))
 
-#define IS_LL_SPI_POLARITY(__VALUE__)               (((__VALUE__) == LL_SPI_POLARITY_LOW)                \
-                                                  || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
+#define IS_LL_SPI_POLARITY(__VALUE__)               (((__VALUE__) == LL_SPI_POLARITY_LOW)                || \
+                                                     ((__VALUE__) == LL_SPI_POLARITY_HIGH))
 
-#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__)      (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)      \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)      \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)     \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)     \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)     \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128)    \
-                                                  || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
+#define IS_LL_SPI_BAUDRATEPRESCALER(__VALUE__)      (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)      || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)      || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)     || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)     || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)     || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128)    || \
+                                                     ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
 
-#define IS_LL_SPI_BITORDER(__VALUE__)               (((__VALUE__) == LL_SPI_LSB_FIRST)                   \
-                                                  || ((__VALUE__) == LL_SPI_MSB_FIRST))
+#define IS_LL_SPI_BITORDER(__VALUE__)               (((__VALUE__) == LL_SPI_LSB_FIRST)                   || \
+                                                     ((__VALUE__) == LL_SPI_MSB_FIRST))
 
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)     (((__VALUE__) == LL_SPI_FULL_DUPLEX)                 \
-                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_TX)                  \
-                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)                  \
-                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX)              \
-                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
+#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__)     (((__VALUE__) == LL_SPI_FULL_DUPLEX)                 || \
+                                                     ((__VALUE__) == LL_SPI_SIMPLEX_TX)                  || \
+                                                     ((__VALUE__) == LL_SPI_SIMPLEX_RX)                  || \
+                                                     ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX)              || \
+                                                     ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
 
-#define IS_LL_SPI_DATAWIDTH(__VALUE__)              (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)              \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)              \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)              \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)              \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)              \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)              \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT)             \
-                                                  || ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
+#define IS_LL_SPI_DATAWIDTH(__VALUE__)              (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)              || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_17BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_18BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_19BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_20BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_21BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_22BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_23BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_24BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_25BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_26BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_27BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_28BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_29BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_30BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_31BIT)             || \
+                                                     ((__VALUE__) == LL_SPI_DATAWIDTH_32BIT))
 
-#define IS_LL_SPI_FIFO_TH(__VALUE__)                (((__VALUE__) == LL_SPI_FIFO_TH_01DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_02DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_03DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_04DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_05DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_06DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_07DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_08DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_09DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_10DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_11DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_12DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_13DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_14DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_15DATA)              \
-                                                  || ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
+#define IS_LL_SPI_FIFO_TH(__VALUE__)                (((__VALUE__) == LL_SPI_FIFO_TH_01DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_02DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_03DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_04DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_05DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_06DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_07DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_08DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_09DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_10DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_11DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_12DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_13DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_14DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_15DATA)              || \
+                                                     ((__VALUE__) == LL_SPI_FIFO_TH_16DATA))
 
-#define IS_LL_SPI_CRC(__VALUE__)                    (((__VALUE__) == LL_SPI_CRC_4BIT)                    \
-                                                  || ((__VALUE__) == LL_SPI_CRC_5BIT)                    \
-                                                  || ((__VALUE__) == LL_SPI_CRC_6BIT)                    \
-                                                  || ((__VALUE__) == LL_SPI_CRC_7BIT)                    \
-                                                  || ((__VALUE__) == LL_SPI_CRC_8BIT)                    \
-                                                  || ((__VALUE__) == LL_SPI_CRC_9BIT)                    \
-                                                  || ((__VALUE__) == LL_SPI_CRC_10BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_11BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_12BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_13BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_14BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_15BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_16BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_17BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_18BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_19BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_20BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_21BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_22BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_23BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_24BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_25BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_26BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_27BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_28BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_29BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_30BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_31BIT)                   \
-                                                  || ((__VALUE__) == LL_SPI_CRC_32BIT))
+#define IS_LL_SPI_CRC(__VALUE__)                    (((__VALUE__) == LL_SPI_CRC_4BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_5BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_6BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_7BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_8BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_9BIT)                    || \
+                                                     ((__VALUE__) == LL_SPI_CRC_10BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_11BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_12BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_13BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_14BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_15BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_16BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_17BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_18BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_19BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_20BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_21BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_22BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_23BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_24BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_25BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_26BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_27BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_28BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_29BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_30BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_31BIT)                   || \
+                                                     ((__VALUE__) == LL_SPI_CRC_32BIT))
 
-#define IS_LL_SPI_NSS(__VALUE__)                    (((__VALUE__) == LL_SPI_NSS_SOFT)                    \
-                                                  || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT)              \
-                                                  || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
+#define IS_LL_SPI_NSS(__VALUE__)                    (((__VALUE__) == LL_SPI_NSS_SOFT)                    || \
+                                                     ((__VALUE__) == LL_SPI_NSS_HARD_INPUT)              || \
+                                                     ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
 
-#define IS_LL_SPI_RX_FIFO(__VALUE__)                (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET)             \
-                                                  || ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET)             \
-                                                  || ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET)             \
-                                                  || ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
+#define IS_LL_SPI_RX_FIFO(__VALUE__)                (((__VALUE__) == LL_SPI_RX_FIFO_0PACKET)             || \
+                                                     ((__VALUE__) == LL_SPI_RX_FIFO_1PACKET)             || \
+                                                     ((__VALUE__) == LL_SPI_RX_FIFO_2PACKET)             || \
+                                                     ((__VALUE__) == LL_SPI_RX_FIFO_3PACKET))
 
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__)         (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE)       \
-                                                  || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
+#define IS_LL_SPI_CRCCALCULATION(__VALUE__)         (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE)       || \
+                                                     ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
 
 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__)          ((__VALUE__) >= 0x1UL)
 
@@ -240,7 +236,7 @@
   *          - SUCCESS: SPI registers are de-initialized
   *          - ERROR: SPI registers are not de-initialized
   */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
 {
   ErrorStatus status = ERROR;
 
@@ -256,6 +252,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
     /* Release reset of SPI clock */
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
 
+    /* Update the return status */
     status = SUCCESS;
   }
 #endif /* SPI1 */
@@ -268,6 +265,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
     /* Release reset of SPI clock */
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
 
+    /* Update the return status */
     status = SUCCESS;
   }
 #endif /* SPI2 */
@@ -280,6 +278,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
     /* Release reset of SPI clock */
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
 
+    /* Update the return status */
     status = SUCCESS;
   }
 #endif /* SPI3 */
@@ -292,6 +291,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
     /* Release reset of SPI clock */
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
 
+    /* Update the return status */
     status = SUCCESS;
   }
 #endif /* SPI4 */
@@ -304,6 +304,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
     /* Release reset of SPI clock */
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
 
+    /* Update the return status */
     status = SUCCESS;
   }
 #endif /* SPI5 */
@@ -316,6 +317,7 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
     /* Release reset of SPI clock */
     LL_APB4_GRP1_ReleaseReset(LL_APB4_GRP1_PERIPH_SPI6);
 
+    /* Update the return status */
     status = SUCCESS;
   }
 #endif /* SPI6 */
@@ -325,8 +327,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
 
 /**
   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
-  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled
+  *         (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
   * @param  SPIx SPI Instance
   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
@@ -336,6 +339,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
   ErrorStatus status = ERROR;
   uint32_t tmp_nss;
   uint32_t tmp_mode;
+  uint32_t tmp_nss_polarity;
 
   /* Check the SPI Instance SPIx*/
   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
@@ -351,6 +355,7 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
 
+  /* Check the SPI instance is not enabled */
   if (LL_SPI_IsEnabled(SPIx) == 0x00000000UL)
   {
     /*---------------------------- SPIx CFG1 Configuration ------------------------
@@ -359,20 +364,18 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
        * - CRC Computation Enable : SPI_CFG1_CRCEN bit
        * - Length of data frame   : SPI_CFG1_DSIZE[4:0] bits
        */
-    MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR              | SPI_CFG1_CRCEN                 | SPI_CFG1_DSIZE,
+    MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR | SPI_CFG1_CRCEN | SPI_CFG1_DSIZE,
                SPI_InitStruct->BaudRate  | SPI_InitStruct->CRCCalculation | SPI_InitStruct->DataWidth);
 
     tmp_nss  = SPI_InitStruct->NSS;
     tmp_mode = SPI_InitStruct->Mode;
+    tmp_nss_polarity = LL_SPI_GetNSSPolarity(SPIx);
 
     /* Checks to setup Internal SS signal level and avoid a MODF Error */
-    if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_LOW) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_MASTER))
-    {
-      LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
-    }
-
-    /* Checks to setup Internal SS signal to the active level in Slave Mode */
-    if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_SLAVE))
+    if ((tmp_nss == LL_SPI_NSS_SOFT) && (((tmp_nss_polarity == LL_SPI_NSS_POLARITY_LOW)  && \
+                                          (tmp_mode == LL_SPI_MODE_MASTER))              || \
+                                         ((tmp_nss_polarity == LL_SPI_NSS_POLARITY_HIGH) && \
+                                          (tmp_mode == LL_SPI_MODE_SLAVE))))
     {
       LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH);
     }
@@ -389,8 +392,8 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
     MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM   | SPI_CFG2_SSOE    |
                SPI_CFG2_CPOL              | SPI_CFG2_CPHA    |
                SPI_CFG2_LSBFRST           | SPI_CFG2_MASTER  | SPI_CFG2_COMM,
-               SPI_InitStruct->NSS        |   SPI_InitStruct->ClockPolarity                    |
-               SPI_InitStruct->ClockPhase |   SPI_InitStruct->BitOrder                         |
+               SPI_InitStruct->NSS        | SPI_InitStruct->ClockPolarity                    |
+               SPI_InitStruct->ClockPhase | SPI_InitStruct->BitOrder                         |
                SPI_InitStruct->Mode       | (SPI_InitStruct->TransferDirection & SPI_CFG2_COMM));
 
     /*---------------------------- SPIx CR1 Configuration ------------------------
@@ -442,15 +445,14 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
 /**
   * @}
   */
-  
-/**
-  * @}
-  */
-  
+
 /**
   * @}
   */
 
+/**
+  * @}
+  */
 /** @addtogroup I2S_LL
   * @{
   */
@@ -475,54 +477,54 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
   * @{
   */
 
-#define IS_LL_I2S_DATAFORMAT(__VALUE__)            (((__VALUE__) == LL_I2S_DATAFORMAT_16B)              \
-                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED)     \
-                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)              \
-                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) \
-                                                 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
+#define IS_LL_I2S_DATAFORMAT(__VALUE__)            (((__VALUE__) == LL_I2S_DATAFORMAT_16B)              || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED)     || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_24B)              || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED) || \
+                                                    ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
 
-#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__)  (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH)    \
-                                                 || ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
+#define IS_LL_I2S_CHANNEL_LENGTH_TYPE (__VALUE__)  (((__VALUE__) == LL_I2S_SLAVE_VARIABLE_CH_LENGTH)    || \
+                                                    ((__VALUE__) == LL_I2S_SLAVE_FIXED_CH_LENGTH))
 
-#define IS_LL_I2S_CKPOL(__VALUE__)                  (((__VALUE__) == LL_I2S_POLARITY_LOW)               \
-                                                 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
+#define IS_LL_I2S_CKPOL(__VALUE__)                  (((__VALUE__) == LL_I2S_POLARITY_LOW)               || \
+                                                     ((__VALUE__) == LL_I2S_POLARITY_HIGH))
 
-#define IS_LL_I2S_STANDARD(__VALUE__)              (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)            \
-                                                 || ((__VALUE__) == LL_I2S_STANDARD_MSB)                \
-                                                 || ((__VALUE__) == LL_I2S_STANDARD_LSB)                \
-                                                 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT)          \
-                                                 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
+#define IS_LL_I2S_STANDARD(__VALUE__)              (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)            || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_MSB)                || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_LSB)                || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT)          || \
+                                                    ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
 
-#define IS_LL_I2S_MODE(__VALUE__)                  (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)               \
-                                                 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)               \
-                                                 || ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX)      \
-                                                 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX)              \
-                                                 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)              \
-                                                 || ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
+#define IS_LL_I2S_MODE(__VALUE__)                  (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)               || \
+                                                    ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)               || \
+                                                    ((__VALUE__) == LL_I2S_MODE_SLAVE_FULL_DUPLEX)      || \
+                                                    ((__VALUE__) == LL_I2S_MODE_MASTER_TX)              || \
+                                                    ((__VALUE__) == LL_I2S_MODE_MASTER_RX)              || \
+                                                    ((__VALUE__) == LL_I2S_MODE_MASTER_FULL_DUPLEX))
 
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__)           (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE)          \
-                                                 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
+#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__)           (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE)          || \
+                                                    ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
 
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__)           ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)                \
-                                                 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K))             \
-                                                 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
+#define IS_LL_I2S_AUDIO_FREQ(__VALUE__)           ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)                && \
+                                                    ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K))             || \
+                                                   ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
 
 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)       ((__VALUE__) <= 0xFFUL)
 
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__)      (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN)       \
-                                                 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
+#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__)      (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN)       || \
+                                                    ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
 
-#define IS_LL_I2S_FIFO_TH (__VALUE__)              (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA)       \
-                                                 || ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
+#define IS_LL_I2S_FIFO_TH (__VALUE__)              (((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_01DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_02DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_03DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_04DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_05DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_06DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_07DATA)       || \
+                                                    ((__VALUE__) == LL_I2S_LL_I2S_FIFO_TH_08DATA))
 
-#define IS_LL_I2S_BIT_ORDER(__VALUE__)             (((__VALUE__) == LL_I2S_LSB_FIRST)                   \
-                                                 || ((__VALUE__) == LL_I2S_MSB_FIRST))
+#define IS_LL_I2S_BIT_ORDER(__VALUE__)             (((__VALUE__) == LL_I2S_LSB_FIRST)                   || \
+                                                    ((__VALUE__) == LL_I2S_MSB_FIRST))
 /**
   * @}
   */
@@ -545,29 +547,38 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
   *          - SUCCESS: SPI registers are de-initialized
   *          - ERROR: SPI registers are not de-initialized
   */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_DeInit(SPIx);
 }
 
 /**
   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
-  * @note   As some bits in I2S configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
-  *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
-  * @note   I2S (SPI) source clock must be ready before calling this function. Otherwise will results in wrong programming.
+  * @note   As some bits in I2S configuration registers can only be written when the SPI is disabled
+  *         (SPI_CR1_SPE bit =0), SPI IP should be in disabled state prior calling this function.
+  *         Otherwise, ERROR result will be returned.
+  * @note   I2S (SPI) source clock must be ready before calling this function. Otherwise will results
+  *         in wrong programming.
   * @param  SPIx SPI Instance
   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: SPI registers are Initialized
   *          - ERROR: SPI registers are not Initialized
   */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct)
 {
-  uint32_t i2sdiv = 0UL, i2sodd = 0UL, packetlength = 1UL, ispcm = 0UL;
+  uint32_t i2sdiv = 0UL;
+  uint32_t i2sodd = 0UL;
+  uint32_t packetlength = 1UL;
+  uint32_t ispcm = 0UL;
   uint32_t tmp;
-  uint32_t sourceclock;
+  uint32_t sourceclock = 0UL;
+
   ErrorStatus status = ERROR;
 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(sourceclock);
+
   /* Check the I2S parameters */
   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
@@ -638,7 +649,7 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
       }
 #else
       sourceclock = LL_RCC_GetSPIClockFreq(LL_RCC_SPI123_CLKSOURCE);
-#endif
+#endif /* SPI_SPI6I2S_SUPPORT */
 
       /* Compute the Real divider depending on the MCLK output state with a fixed point */
       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
@@ -740,5 +751,3 @@ void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_
   * @}
   */
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h
index 4dd1c2d92b..e382453558 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -43,10 +42,18 @@ extern "C" {
 /* Private constants ---------------------------------------------------------*/
 
 /* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
   * @{
   */
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup SPI_LL_Exported_Types SPI Exported Types
+  * @{
+  */
 
 /**
   * @brief  SPI Init structures definition
@@ -56,53 +63,68 @@ typedef struct
   uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.
                                          This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetTransferDirection().*/
 
   uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).
                                          This parameter can be a value of @ref SPI_LL_EC_MODE.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetMode().*/
 
   uint32_t DataWidth;               /*!< Specifies the SPI data width.
                                          This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetDataWidth().*/
 
   uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.
                                          This parameter can be a value of @ref SPI_LL_EC_POLARITY.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetClockPolarity().*/
 
   uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.
                                          This parameter can be a value of @ref SPI_LL_EC_PHASE.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetClockPhase().*/
+
+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
+                                         or by software using the SSI bit.
 
-  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
                                          This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetNSSMode().*/
 
-  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure
+                                         the transmit and receive SCK clock.
                                          This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
-                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.
+                                         @note The communication clock is derived from the master clock.
+                                         The slave clock does not need to be set.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetBaudRatePrescaler().*/
 
   uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.
                                          This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetTransferBitOrder().*/
 
   uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.
                                          This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
 
-                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
+                                         This feature can be modified afterwards using unitary functions
+                                         @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
 
   uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.
-                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.
+                                         This parameter must be a number between Min_Data = 0x00
+                                         and Max_Data = 0xFFFFFFFF.
 
-                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_SPI_SetCRCPolynomial().*/
 
 } LL_SPI_InitTypeDef;
 
@@ -195,7 +217,8 @@ typedef struct
 #define LL_SPI_SS_IDLENESS_12CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
 #define LL_SPI_SS_IDLENESS_13CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
 #define LL_SPI_SS_IDLENESS_14CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
-#define LL_SPI_SS_IDLENESS_15CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
+#define LL_SPI_SS_IDLENESS_15CYCLE                 (SPI_CFG2_MSSI_3\
+                                                    | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
 /**
   * @}
   */
@@ -218,7 +241,8 @@ typedef struct
 #define LL_SPI_ID_IDLENESS_12CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
 #define LL_SPI_ID_IDLENESS_13CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
 #define LL_SPI_ID_IDLENESS_14CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
-#define LL_SPI_ID_IDLENESS_15CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
+#define LL_SPI_ID_IDLENESS_15CYCLE                 (SPI_CFG2_MIDI_3\
+                                                    | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
 /**
   * @}
   */
@@ -348,7 +372,8 @@ typedef struct
 #define LL_SPI_DATAWIDTH_13BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
 #define LL_SPI_DATAWIDTH_14BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_15BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_16BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_16BIT                     (SPI_CFG1_DSIZE_3\
+                                                    | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_17BIT                     (SPI_CFG1_DSIZE_4)
 #define LL_SPI_DATAWIDTH_18BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_19BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
@@ -356,15 +381,20 @@ typedef struct
 #define LL_SPI_DATAWIDTH_21BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
 #define LL_SPI_DATAWIDTH_22BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_23BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_24BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_24BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_25BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
 #define LL_SPI_DATAWIDTH_26BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_27BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_28BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_28BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
 #define LL_SPI_DATAWIDTH_29BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
-#define LL_SPI_DATAWIDTH_30BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
-#define LL_SPI_DATAWIDTH_31BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
-#define LL_SPI_DATAWIDTH_32BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_30BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
+#define LL_SPI_DATAWIDTH_31BIT                     (SPI_CFG1_DSIZE_4\
+                                                    | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
+#define LL_SPI_DATAWIDTH_32BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
+                                                    | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
 /**
   * @}
   */
@@ -387,7 +417,8 @@ typedef struct
 #define LL_SPI_FIFO_TH_13DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
 #define LL_SPI_FIFO_TH_14DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
 #define LL_SPI_FIFO_TH_15DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
-#define LL_SPI_FIFO_TH_16DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
+#define LL_SPI_FIFO_TH_16DATA                      (SPI_CFG1_FTHLV_3\
+                                                    | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
 /**
   * @}
   */
@@ -419,7 +450,8 @@ typedef struct
 #define LL_SPI_CRC_13BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
 #define LL_SPI_CRC_14BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_15BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_16BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_16BIT                           (SPI_CFG1_CRCSIZE_3\
+                                                    | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_17BIT                           (SPI_CFG1_CRCSIZE_4)
 #define LL_SPI_CRC_18BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_19BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
@@ -427,15 +459,20 @@ typedef struct
 #define LL_SPI_CRC_21BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
 #define LL_SPI_CRC_22BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_23BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_24BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_24BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_25BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
 #define LL_SPI_CRC_26BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_27BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_28BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_28BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
 #define LL_SPI_CRC_29BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
-#define LL_SPI_CRC_30BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
-#define LL_SPI_CRC_31BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
-#define LL_SPI_CRC_32BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_30BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
+#define LL_SPI_CRC_31BIT                           (SPI_CFG1_CRCSIZE_4\
+                                                    | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
+#define LL_SPI_CRC_32BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
+                                                    | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
 /**
   * @}
   */
@@ -453,10 +490,10 @@ typedef struct
 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
   * @{
   */
-#define LL_SPI_RX_FIFO_0PACKET                     (0x00000000UL)                      /* 0 or multiple of 4 packet available is the RxFIFO */
-#define LL_SPI_RX_FIFO_1PACKET                     (SPI_SR_RXPLVL_0)
-#define LL_SPI_RX_FIFO_2PACKET                     (SPI_SR_RXPLVL_1)
-#define LL_SPI_RX_FIFO_3PACKET                     (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
+#define LL_SPI_RX_FIFO_0PACKET               (0x00000000UL)    /* 0 or multiple of 4 packet available is the RxFIFO */
+#define LL_SPI_RX_FIFO_1PACKET               (SPI_SR_RXPLVL_0)
+#define LL_SPI_RX_FIFO_2PACKET               (SPI_SR_RXPLVL_1)
+#define LL_SPI_RX_FIFO_3PACKET               (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
 /**
   * @}
   */
@@ -538,7 +575,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
 }
@@ -573,7 +610,7 @@ __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
 }
@@ -608,7 +645,7 @@ __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
 }
@@ -636,7 +673,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
   *         @arg @ref LL_SPI_MODE_MASTER
   *         @arg @ref LL_SPI_MODE_SLAVE
   */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
 }
@@ -691,7 +728,7 @@ __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t Mast
   *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
   *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
   */
-__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
 }
@@ -746,7 +783,7 @@ __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t Mas
   *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
   *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
   */
-__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
 }
@@ -771,7 +808,7 @@ __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
 }
@@ -796,7 +833,7 @@ __STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
 }
@@ -820,7 +857,7 @@ __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
 }
@@ -836,7 +873,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
   */
 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
 {
-  MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
+  MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll);
 }
 
 /**
@@ -847,7 +884,7 @@ __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCR
   *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
   *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
   */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
 }
@@ -874,7 +911,7 @@ __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCR
   *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
   *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
   */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
 }
@@ -902,7 +939,7 @@ __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLev
   *         @arg @ref LL_SPI_SS_LEVEL_HIGH
   *         @arg @ref LL_SPI_SS_LEVEL_LOW
   */
-__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
 }
@@ -935,7 +972,7 @@ __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
 }
@@ -968,7 +1005,7 @@ __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
 }
@@ -1001,7 +1038,7 @@ __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
 }
@@ -1031,7 +1068,7 @@ __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRC
   *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
   *         @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
   */
-__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
 }
@@ -1061,7 +1098,7 @@ __STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetec
   *         @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
   *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
   */
-__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
 }
@@ -1089,7 +1126,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
   *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA
   *         @arg @ref LL_SPI_PROTOCOL_TI
   */
-__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
 }
@@ -1118,7 +1155,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase
   *         @arg @ref LL_SPI_PHASE_1EDGE
   *         @arg @ref LL_SPI_PHASE_2EDGE
   */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
 }
@@ -1147,7 +1184,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
   *         @arg @ref LL_SPI_POLARITY_LOW
   *         @arg @ref LL_SPI_POLARITY_HIGH
   */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
 }
@@ -1176,7 +1213,7 @@ __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolari
   *         @arg @ref LL_SPI_NSS_POLARITY_LOW
   *         @arg @ref LL_SPI_NSS_POLARITY_HIGH
   */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
 }
@@ -1217,7 +1254,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau
   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
   *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
   */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
 }
@@ -1246,14 +1283,15 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
   *         @arg @ref LL_SPI_LSB_FIRST
   *         @arg @ref LL_SPI_MSB_FIRST
   */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
 }
 
 /**
   * @brief  Set Transfer Mode
-  * @note   This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.
+  * @note   This configuration can not be changed when SPI is enabled except for half duplex direction
+  *         using LL_SPI_SetHalfDuplexDirection.
   * @rmtoll CR1          HDDIR         LL_SPI_SetTransferDirection\n
   *         CFG2         COMM          LL_SPI_SetTransferDirection
   * @param  SPIx SPI Instance
@@ -1283,7 +1321,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra
   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
   */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
 {
   uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
   uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
@@ -1314,7 +1352,7 @@ __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t H
   *         @arg @ref LL_SPI_HALF_DUPLEX_RX
   *         @arg @ref LL_SPI_HALF_DUPLEX_TX
   */
-__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
 }
@@ -1396,7 +1434,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
   *         @arg @ref LL_SPI_DATAWIDTH_31BIT
   *         @arg @ref LL_SPI_DATAWIDTH_32BIT
   */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
 }
@@ -1452,7 +1490,7 @@ __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thresho
   *         @arg @ref LL_SPI_FIFO_TH_15DATA
   *         @arg @ref LL_SPI_FIFO_TH_16DATA
   */
-__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
 }
@@ -1486,7 +1524,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
 }
@@ -1568,7 +1606,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
   *         @arg @ref LL_SPI_CRC_31BIT
   *         @arg @ref LL_SPI_CRC_32BIT
   */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
 }
@@ -1601,7 +1639,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
   *         @arg @ref LL_SPI_NSS_HARD_INPUT
   *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
   */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
 }
@@ -1638,7 +1676,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
 }
@@ -1657,7 +1695,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
 }
@@ -1668,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
 }
@@ -1679,7 +1717,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
 }
@@ -1690,7 +1728,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
 }
@@ -1701,7 +1739,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
 }
@@ -1712,7 +1750,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
 }
@@ -1723,7 +1761,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
 }
@@ -1734,7 +1772,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
 }
@@ -1745,7 +1783,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
 }
@@ -1756,7 +1794,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
 }
@@ -1767,7 +1805,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
 }
@@ -1778,7 +1816,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
 }
@@ -1789,7 +1827,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
 }
@@ -1800,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
 }
@@ -1811,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
 }
@@ -1826,7 +1864,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
   *         @arg @ref LL_SPI_RX_FIFO_2PACKET
   *         @arg @ref LL_SPI_RX_FIFO_3PACKET
   */
-__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
 }
@@ -2186,7 +2224,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
 }
@@ -2197,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
 }
@@ -2208,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
 }
@@ -2219,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
 }
@@ -2230,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
 }
@@ -2241,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
 }
@@ -2252,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
 }
@@ -2263,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
 }
@@ -2274,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
 }
@@ -2285,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
 }
@@ -2296,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
 }
@@ -2337,7 +2375,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
 }
@@ -2370,11 +2408,31 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
 }
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll TXDR           TXDR            LL_SPI_DMA_GetTxRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t) &(SPIx->TXDR);
+}
 
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RXDR           RXDR            LL_SPI_DMA_GetRxRegAddr
+  * @param  SPIx SPI Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx)
+{
+  return (uint32_t) &(SPIx->RXDR);
+}
 /**
   * @}
   */
@@ -2389,7 +2447,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval 0..0xFF
   */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
 {
   return (*((__IO uint8_t *)&SPIx->RXDR));
 }
@@ -2400,9 +2458,14 @@ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFF
   */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
 {
-  return (uint16_t)(READ_REG(SPIx->RXDR));
+#if defined (__GNUC__)
+  __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
+  return (*spirxdr);
+#else
+  return (*((__IO uint16_t *)&SPIx->RXDR));
+#endif /* __GNUC__ */
 }
 
 /**
@@ -2411,7 +2474,7 @@ __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval  0..0xFFFFFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
 {
   return (*((__IO uint32_t *)&SPIx->RXDR));
 }
@@ -2441,8 +2504,8 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
   __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
   *spitxdr = TxData;
 #else
-  SPIx->TXDR = TxData;
-#endif
+  *((__IO uint16_t *)&SPIx->TXDR) = TxData;
+#endif /* __GNUC__ */
 }
 
 /**
@@ -2475,7 +2538,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFFFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_REG(SPIx->CRCPOLY));
 }
@@ -2498,7 +2561,7 @@ __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFFFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_REG(SPIx->UDRDR));
 }
@@ -2509,7 +2572,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFFFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_REG(SPIx->RXCRC));
 }
@@ -2520,7 +2583,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFFFFFF
   */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_REG(SPIx->TXCRC));
 }
@@ -2534,7 +2597,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
   * @{
   */
 
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
+ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
 void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
 
@@ -2545,6 +2608,9 @@ void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
 /**
   * @}
   */
+/**
+  * @}
+  */
 
 /** @defgroup I2S_LL I2S
   * @{
@@ -2569,37 +2635,44 @@ typedef struct
   uint32_t Mode;                    /*!< Specifies the I2S operating mode.
                                          This parameter can be a value of @ref I2S_LL_EC_MODE
 
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetTransferMode().*/
 
   uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.
                                          This parameter can be a value of @ref I2S_LL_EC_STANDARD
 
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetStandard().*/
 
 
   uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.
                                          This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
 
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetDataFormat().*/
 
 
   uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.
                                          This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
 
-                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
+                                         This feature can be modified afterwards using unitary functions
+                                         @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
 
 
   uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.
                                          This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
 
-                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
-                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
+                                         Audio Frequency can be modified afterwards using Reference manual formulas
+                                         to calculate Prescaler Linear, Parity and unitary functions
+                                         @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
+                                         to set it.*/
 
 
   uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.
                                          This parameter can be a value of @ref I2S_LL_EC_POLARITY
 
-                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
+                                         This feature can be modified afterwards using unitary function
+                                         @ref LL_I2S_SetClockPolarity().*/
 
 } LL_I2S_InitTypeDef;
 
@@ -2671,8 +2744,8 @@ typedef struct
 /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
   * @{
   */
-#define LL_I2S_PRESCALER_PARITY_EVEN        (0x00000000UL)           /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
-#define LL_I2S_PRESCALER_PARITY_ODD         (0x00000001UL)           /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
+#define LL_I2S_PRESCALER_PARITY_EVEN        (0x00000000UL)   /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
+#define LL_I2S_PRESCALER_PARITY_ODD         (0x00000001UL)   /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
 /**
   * @}
   */
@@ -2811,7 +2884,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength
   *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
   *         @arg @ref LL_I2S_DATAFORMAT_32B
   */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
 }
@@ -2840,7 +2913,7 @@ __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t Cha
   *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
   *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
   */
-__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
 }
@@ -2873,7 +2946,7 @@ __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Handle
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
 }
@@ -2900,7 +2973,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo
   *         @arg @ref LL_I2S_POLARITY_LOW
   *         @arg @ref LL_I2S_POLARITY_HIGH
   */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
 }
@@ -2935,7 +3008,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
   *         @arg @ref LL_I2S_STANDARD_PCM_SHORT
   *         @arg @ref LL_I2S_STANDARD_PCM_LONG
   */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
 }
@@ -2970,7 +3043,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard
   *         @arg @ref LL_I2S_MODE_MASTER_RX
   *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
   */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
 }
@@ -3031,7 +3104,7 @@ __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIOSwap(SPIx);
 }
@@ -3066,7 +3139,7 @@ __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledGPIOControl(SPIx);
 }
@@ -3090,7 +3163,7 @@ __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIOLock(SPIx);
 }
@@ -3117,7 +3190,7 @@ __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO
   *         @arg @ref LL_I2S_LSB_FIRST
   *         @arg @ref LL_I2S_MSB_FIRST
   */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_GetTransferBitOrder(SPIx);
 }
@@ -3135,11 +3208,11 @@ __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
 
 /**
   * @brief  Check if there is an unfinished transfer
-  * @rmtoll CR1          CSTART        LL_I2S_IsTransferActive
+  * @rmtoll CR1          CSTART        LL_I2S_IsActiveTransfer
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsActiveMasterTransfer(SPIx);
 }
@@ -3179,7 +3252,7 @@ __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thresho
   *         @arg @ref LL_I2S_FIFO_TH_07DATA
   *         @arg @ref LL_I2S_FIFO_TH_08DATA
   */
-__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_GetFIFOThreshold(SPIx);
 }
@@ -3203,7 +3276,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t Presc
   * @param  SPIx SPI Instance
   * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
 }
@@ -3230,7 +3303,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc
   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
   */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
 {
   return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
 }
@@ -3263,7 +3336,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
 {
   return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
 }
@@ -3283,7 +3356,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsActiveFlag_RXP(SPIx);
 }
@@ -3294,7 +3367,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsActiveFlag_TXP(SPIx);
 }
@@ -3305,7 +3378,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsActiveFlag_UDR(SPIx);
 }
@@ -3316,7 +3389,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsActiveFlag_OVR(SPIx);
 }
@@ -3327,7 +3400,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsActiveFlag_FRE(SPIx);
 }
@@ -3489,7 +3562,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIT_RXP(SPIx);
 }
@@ -3500,7 +3573,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIT_TXP(SPIx);
 }
@@ -3511,7 +3584,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIT_UDR(SPIx);
 }
@@ -3522,7 +3595,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIT_OVR(SPIx);
 }
@@ -3533,7 +3606,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledIT_FRE(SPIx);
 }
@@ -3574,7 +3647,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledDMAReq_RX(SPIx);
 }
@@ -3607,7 +3680,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0)
   */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
 {
   return LL_SPI_IsEnabledDMAReq_TX(SPIx);
 }
@@ -3626,7 +3699,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval 0..0xFFFF
   */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
 {
   return LL_SPI_ReceiveData16(SPIx);
 }
@@ -3637,7 +3710,7 @@ __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
   * @param  SPIx SPI Instance
   * @retval  0..0xFFFFFFFF
   */
-__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
+__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */
 {
   return LL_SPI_ReceiveData32(SPIx);
 }
@@ -3666,18 +3739,19 @@ __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
   LL_SPI_TransmitData32(SPIx, TxData);
 }
 
+
 /**
   * @}
   */
 
 
 #if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
+/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
   * @{
   */
 
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
+ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, const LL_I2S_InitTypeDef *I2S_InitStruct);
 void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
 void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
 
@@ -3700,13 +3774,8 @@ void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear,
   * @}
   */
 
-/**
-  * @}
-  */
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* STM32H7xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.c
index e2b38b5b77..20c2c5e1a0 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -99,8 +98,9 @@ ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx)
 
 /**
   * @brief  Initialize the SWPMI peripheral according to the specified parameters in the SWPMI_InitStruct.
-  * @note   As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated (SWPMI_CR_SWPACT bit = 0),
-  *         SWPMI IP should be in deactivated state prior calling this function. Otherwise, ERROR result will be returned.
+  * @note   As some bits in SWPMI configuration registers can only be written when the SWPMI is deactivated
+  *         (SWPMI_CR_SWPACT bit = 0), the SWPMI peripheral should be in deactivated state prior calling
+  *         this function. Otherwise, ERROR result will be returned.
   * @param  SWPMIx           SWPMI Instance
   * @param  SWPMI_InitStruct pointer to a @ref LL_SWPMI_InitTypeDef structure that contains
   *                          the configuration information for the SWPMI peripheral.
@@ -130,8 +130,8 @@ ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_Ini
 
     /* Set the new configuration of the SWPMI peripheral */
     MODIFY_REG(SWPMIx->CR,
-              (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
-              (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
+               (SWPMI_CR_RXMODE | SWPMI_CR_TXMODE),
+               (SWPMI_InitStruct->TxBufferingMode | SWPMI_InitStruct->RxBufferingMode));
   }
   /* Else (SWPMI not in deactivated state => return ERROR) */
   else
@@ -175,5 +175,3 @@ void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct)
   */
 
 #endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.h
index efe1daa9d2..c2b31d604f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_swpmi.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -1238,5 +1237,3 @@ void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
 #endif
 
 #endif /* STM32H7xx_LL_SWPMI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h
index b4326b5d60..aa5149abfd 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h
@@ -3,6 +3,18 @@
   * @file    stm32h7xx_ll_system.h
   * @author  MCD Application Team
   * @brief   Header file of SYSTEM LL module.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -16,17 +28,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
@@ -541,8 +542,8 @@ __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5(*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C5 (*)
   *
   *         (*) value not defined in all devices
   * @retval None
@@ -2439,4 +2440,3 @@ __STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)
 
 #endif /* __STM32H7xx_LL_SYSTEM_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.c
index 688f0c1979..89ccf5f0e2 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -67,8 +66,8 @@
                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
-                                     || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \
+                                     || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2))
 
 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
@@ -149,6 +148,11 @@
                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
+#if defined(TIM_BDTR_BKBID)
+
+#define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
+                                           || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
+#endif /* TIM_BDTR_BKBID */
 
 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
@@ -172,6 +176,11 @@
                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
+#if   defined(TIM_BDTR_BKBID)
+
+#define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
+                                            || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
+#endif /*TIM_BDTR_BKBID */
 
 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
@@ -184,16 +193,16 @@
 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
   * @{
   */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 /**
   * @}
   */
@@ -214,7 +223,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: invalid TIMx instance
   */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
 {
   ErrorStatus result = SUCCESS;
 
@@ -232,91 +241,91 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
   }
-#endif
+#endif /* TIM2 */
 #if defined(TIM3)
   else if (TIMx == TIM3)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
   }
-#endif
+#endif /* TIM3 */
 #if defined(TIM4)
   else if (TIMx == TIM4)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
   }
-#endif
+#endif /* TIM4 */
 #if defined(TIM5)
   else if (TIMx == TIM5)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
   }
-#endif
+#endif /* TIM5 */
 #if defined(TIM6)
   else if (TIMx == TIM6)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
   }
-#endif
+#endif /* TIM6 */
 #if defined (TIM7)
   else if (TIMx == TIM7)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
   }
-#endif
+#endif /* TIM7 */
 #if defined(TIM8)
   else if (TIMx == TIM8)
   {
     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
   }
-#endif
+#endif /* TIM8 */
 #if defined(TIM12)
   else if (TIMx == TIM12)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
   }
-#endif
+#endif /* TIM12 */
 #if defined(TIM13)
   else if (TIMx == TIM13)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
   }
-#endif
+#endif /* TIM13 */
 #if defined(TIM14)
   else if (TIMx == TIM14)
   {
     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
   }
-#endif
+#endif /* TIM14 */
 #if defined(TIM15)
   else if (TIMx == TIM15)
   {
     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
   }
-#endif
+#endif /* TIM15 */
 #if defined(TIM16)
   else if (TIMx == TIM16)
   {
     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
   }
-#endif
+#endif /* TIM16 */
 #if defined(TIM17)
   else if (TIMx == TIM17)
   {
     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
   }
-#endif
+#endif /* TIM17 */
   else
   {
     result = ERROR;
@@ -344,12 +353,13 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 /**
   * @brief  Configure the TIMx time base unit.
   * @param  TIMx Timer Instance
-  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
+  * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
+  *         (TIMx time base unit configuration data structure)
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
 {
   uint32_t tmpcr1;
 
@@ -397,7 +407,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 /**
   * @brief  Set the fields of the TIMx output channel configuration data
   *         structure to their default values.
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
+  *         (the output channel configuration data structure)
   * @retval None
   */
 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
@@ -423,12 +434,13 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
   *         @arg @ref LL_TIM_CHANNEL_CH4
   *         @arg @ref LL_TIM_CHANNEL_CH5
   *         @arg @ref LL_TIM_CHANNEL_CH6
-  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
+  * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
+  *         data structure)
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: TIMx output channel is initialized
   *          - ERROR: TIMx output channel is not initialized
   */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 {
   ErrorStatus result = ERROR;
 
@@ -462,7 +474,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy
 /**
   * @brief  Set the fields of the TIMx input channel configuration data
   *         structure to their default values.
-  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
+  * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
+  *         data structure)
   * @retval None
   */
 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
@@ -482,12 +495,13 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
   *         @arg @ref LL_TIM_CHANNEL_CH2
   *         @arg @ref LL_TIM_CHANNEL_CH3
   *         @arg @ref LL_TIM_CHANNEL_CH4
-  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
+  * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
+  *         structure)
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: TIMx output channel is initialized
   *          - ERROR: TIMx output channel is not initialized
   */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 {
   ErrorStatus result = ERROR;
 
@@ -514,7 +528,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy
 
 /**
   * @brief  Fills each TIM_EncoderInitStruct field with its default value
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
+  *         configuration data structure)
   * @retval None
   */
 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
@@ -534,12 +549,13 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct
 /**
   * @brief  Configure the encoder interface of the timer instance.
   * @param  TIMx Timer Instance
-  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
+  * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
+  *         configuration data structure)
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 {
   uint32_t tmpccmr1;
   uint32_t tmpccer;
@@ -598,7 +614,8 @@ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *T
 /**
   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
   *         structure to their default values.
-  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface
+  *         configuration data structure)
   * @retval None
   */
 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
@@ -625,12 +642,13 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI
   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
   *       when TIMx operates in Hall sensor interface mode.
   * @param  TIMx Timer Instance
-  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
+  * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor
+  *         interface configuration data structure)
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 {
   uint32_t tmpcr2;
   uint32_t tmpccmr1;
@@ -705,7 +723,8 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType
 /**
   * @brief  Set the fields of the Break and Dead Time configuration data structure
   *         to their default values.
-  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+  *         data structure)
   * @retval None
   */
 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
@@ -718,9 +737,15 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
+#if defined(TIM_BDTR_BKBID)
+  TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
+#endif /* TIM_BDTR_BKBID */
   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
+#if defined(TIM_BDTR_BKBID)
+  TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
+#endif /*TIM_BDTR_BKBID */
   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 }
 
@@ -735,12 +760,13 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
   *       a timer instance provides a second break input.
   * @param  TIMx Timer Instance
-  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
+  * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration
+  *         data structure)
   * @retval An ErrorStatus enumeration value:
   *          - SUCCESS: Break and Dead Time is initialized
   *          - ERROR: not applicable
   */
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 {
   uint32_t tmpbdtr = 0;
 
@@ -752,6 +778,10 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
+  assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+#if defined(TIM_BDTR_BKBID)
+  assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+#endif /*TIM_BDTR_BKBID */
 
   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
   the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -764,23 +794,27 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
-  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
-  if (IS_TIM_ADVANCED_INSTANCE(TIMx))
-  {
-    assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
-    MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
-  }
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+#if defined(TIM_BDTR_BKBID)
+  MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
+#endif /*TIM_BDTR_BKBID */
 
   if (IS_TIM_BKIN2_INSTANCE(TIMx))
   {
     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
+#if defined(TIM_BDTR_BKBID)
+    assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
+#endif /*TIM_BDTR_BKBID */
 
     /* Set the BREAK2 input related BDTR bit-fields */
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
+#if defined(TIM_BDTR_BKBID)
+    MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
+#endif /*TIM_BDTR_BKBID */
   }
 
   /* Set TIMx_BDTR */
@@ -808,7 +842,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 {
   uint32_t tmpccmr1;
   uint32_t tmpccer;
@@ -819,8 +853,6 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 
   /* Disable the Channel 1: Reset the CC1E Bit */
   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
@@ -848,8 +880,10 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
   {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 
     /* Set the complementary output Polarity */
     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
@@ -887,7 +921,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 {
   uint32_t tmpccmr1;
   uint32_t tmpccer;
@@ -898,8 +932,6 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 
   /* Disable the Channel 2: Reset the CC2E Bit */
   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
@@ -927,8 +959,10 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
   {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 
     /* Set the complementary output Polarity */
     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
@@ -966,7 +1000,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 {
   uint32_t tmpccmr2;
   uint32_t tmpccer;
@@ -977,8 +1011,6 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 
   /* Disable the Channel 3: Reset the CC3E Bit */
   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
@@ -1006,8 +1038,10 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
   {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
+    assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
+    assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
+    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 
     /* Set the complementary output Polarity */
     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
@@ -1045,7 +1079,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 {
   uint32_t tmpccmr2;
   uint32_t tmpccer;
@@ -1056,8 +1090,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
-  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 
   /* Disable the Channel 4: Reset the CC4E Bit */
   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
@@ -1085,7 +1117,6 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
   {
-    assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 
     /* Set the Output Idle state */
@@ -1115,7 +1146,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 {
   uint32_t tmpccmr3;
   uint32_t tmpccer;
@@ -1176,7 +1207,7 @@ static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
+static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 {
   uint32_t tmpccmr3;
   uint32_t tmpccer;
@@ -1236,7 +1267,7 @@ static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
@@ -1269,7 +1300,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
@@ -1302,7 +1333,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
@@ -1335,7 +1366,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni
   *          - SUCCESS: TIMx registers are de-initialized
   *          - ERROR: not applicable
   */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
+static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 {
   /* Check the parameters */
   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
@@ -1352,7 +1383,7 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni
              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
 
-  /* Select the Polarity and set the CC2E Bit */
+  /* Select the Polarity and set the CC4E Bit */
   MODIFY_REG(TIMx->CCER,
              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
@@ -1377,4 +1408,3 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h
index 4ec1297f69..050f73853c 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -201,24 +200,29 @@ typedef struct
   uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
                                    This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
 
-                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
 
   uint32_t CounterMode;       /*!< Specifies the counter mode.
                                    This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
 
-                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
 
   uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
                                    Auto-Reload Register at the next update event.
                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-                                   Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
 
-                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
 
   uint32_t ClockDivision;     /*!< Specifies the clock division.
                                    This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
 
-                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
 
   uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
                                    reaches zero, an update event is generated and counting restarts
@@ -226,10 +230,13 @@ typedef struct
                                    This means in PWM mode that (N+1) corresponds to:
                                       - the number of PWM periods in edge-aligned mode
                                       - the number of half PWM period in center-aligned mode
-                                   GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
 
-                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
 } LL_TIM_InitTypeDef;
 
 /**
@@ -240,43 +247,51 @@ typedef struct
   uint32_t OCMode;        /*!< Specifies the output mode.
                                This parameter can be a value of @ref TIM_LL_EC_OCMODE.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
 
   uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
 
-                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
 
   uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
                                This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
 
-                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
 
   uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
                                This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
 
-                               This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
 
   uint32_t OCPolarity;    /*!< Specifies the output polarity.
                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
 
   uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
                                This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
 
 
   uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
 
   uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
                                This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
 } LL_TIM_OC_InitTypeDef;
 
 /**
@@ -289,22 +304,26 @@ typedef struct
   uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
                                This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
 
   uint32_t ICActiveInput; /*!< Specifies the input.
                                This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
 
   uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
                                This parameter can be a value of @ref TIM_LL_EC_ICPSC.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
 
   uint32_t ICFilter;      /*!< Specifies the input capture filter.
                                This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
 
-                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
 } LL_TIM_IC_InitTypeDef;
 
 
@@ -316,47 +335,56 @@ typedef struct
   uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
                                  This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
 
   uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
 
   uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
 
   uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
 
   uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
 
   uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
                                  This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
 
   uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
                                  This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
 
   uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
                                  This parameter can be a value of @ref TIM_LL_EC_ICPSC.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
 
   uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
                                  This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
 
-                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
 
 } LL_TIM_ENCODER_InitTypeDef;
 
@@ -369,26 +397,31 @@ typedef struct
   uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
                                     This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
 
-                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
 
   uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
                                     Prescaler must be set to get a maximum counter period longer than the
                                     time interval between 2 consecutive changes on the Hall inputs.
                                     This parameter can be a value of @ref TIM_LL_EC_ICPSC.
 
-                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
 
   uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
-                                    This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
 
-                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
 
   uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
                                     A positive pulse (TRGO event) is generated with a programmable delay every time
                                     a change occurs on the Hall inputs.
                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
 
-                                    This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
 } LL_TIM_HALLSENSOR_InitTypeDef;
 
 /**
@@ -399,79 +432,125 @@ typedef struct
   uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
                                       This parameter can be a value of @ref TIM_LL_EC_OSSR
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
 
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
 
   uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
                                       This parameter can be a value of @ref TIM_LL_EC_OSSI
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
 
-                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
 
   uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
                                       This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
 
-                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
-                                            has been written, their content is frozen until the next reset.*/
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
 
   uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
                                       switching-on of the outputs.
                                       This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
 
   uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
 
-                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 
   uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 
   uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
                                       This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 
+#if defined(TIM_BDTR_BKBID)
+  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#endif /*TIM_BDTR_BKBID */
   uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
 
-                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 
   uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 
   uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
                                       This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
 
-                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 
+#if defined(TIM_BDTR_BKBID)
+  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+#endif /*TIM_BDTR_BKBID */
   uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
                                       This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
 
-                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
 
-                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
 } LL_TIM_BDTR_InitTypeDef;
 
 /**
@@ -574,10 +653,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
   * @{
   */
-#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
 #define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
 #define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
 /**
   * @}
@@ -658,6 +737,15 @@ typedef struct
   */
 #endif /* USE_FULL_LL_DRIVER */
 
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+  */
+
 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
   * @{
   */
@@ -673,8 +761,8 @@ typedef struct
 #define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
 #define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
 #define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
-#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
 /**
   * @}
   */
@@ -839,10 +927,6 @@ typedef struct
 #define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
 #define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
 #define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
 #define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
 #define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
 #define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
@@ -853,6 +937,10 @@ typedef struct
 #define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
 #define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
 #define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
 /**
   * @}
   */
@@ -888,11 +976,11 @@ typedef struct
 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
 #define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
@@ -900,51 +988,51 @@ typedef struct
   * @}
   */
 
-#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */
-#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */
-#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */
+#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM1_ETR is connected to GPIO */
+#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< TIM1_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< TIM1_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< TIM1_ETR is connected to ADC1 AWD3 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< TIM1_ETR is connected to ADC3 AWD1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /*!< TIM1_ETR is connected to ADC3 AWD3 */
 
-#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
-#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
-#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
+#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM8_ETR is connected to GPIO */
+#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /*!< TIM8_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /*!< TIM8_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /*!< TIM8_ETR is connected to ADC2 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM8_ETR is connected to ADC2 AWD3 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /*!< TIM8_ETR is connected to ADC3 AWD1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /*!< TIM8_ETR is connected to ADC3 AWD3 */
 
-#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM2_ETR is connected to GPIO */
-#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /* !< TIM2_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /* !< TIM2_ETR is connected to COMP2 OUT */
-#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to RCC LSE */
-#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /* !< TIM2_ETR is connected to SAI1 FS_A */
-#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to SAI1 FS_B */
+#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM2_ETR is connected to GPIO */
+#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /*!< TIM2_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /*!< TIM2_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to RCC LSE */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /*!< TIM2_ETR is connected to SAI1 FS_A */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /*!< TIM2_ETR is connected to SAI1 FS_B */
 
-#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM3_ETR is connected to GPIO */
-#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /* !< TIM3_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM3_ETR is connected to GPIO */
+#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /*!< TIM3_ETR is connected to COMP1 OUT */
 
-#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM5_ETR is connected to GPIO */
-#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI2 FS_A */
-#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI2 FS_B */
-#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI4 FS_A */
-#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI4 FS_B */
+#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /*!< TIM5_ETR is connected to GPIO */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /*!< TIM5_ETR is connected to SAI2 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /*!< TIM5_ETR is connected to SAI2 FS_B */
+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /*!< TIM5_ETR is connected to SAI4 FS_A */
+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /*!< TIM5_ETR is connected to SAI4 FS_B */
 
-#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /* !< TIM23_ETR is connected to GPIO */
-#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /* !< TIM23_ETR is connected to COMP1 OUT */
-#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /* !< TIM23_ETR is connected to COMP2 OUT */
+#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /*!< TIM23_ETR is connected to GPIO */
+#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /*!< TIM23_ETR is connected to COMP1 OUT */
+#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /*!< TIM23_ETR is connected to COMP2 OUT */
 
-#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /* !< TIM24_ETR is connected to GPIO */
-#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /* !< TIM24_ETR is connected to SAI4 FS_A */
-#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /* !< TIM24_ETR is connected to SAI4 FS_B */
-#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /* !< TIM24_ETR is connected to SAI1 FS_A */
-#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /* !< TIM24_ETR is connected to SAI1 FS_B */
+#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /*!< TIM24_ETR is connected to GPIO */
+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /*!< TIM24_ETR is connected to SAI4 FS_A */
+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /*!< TIM24_ETR is connected to SAI4 FS_B */
+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /*!< TIM24_ETR is connected to SAI1 FS_A */
+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /*!< TIM24_ETR is connected to SAI1 FS_B */
 
 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
   * @{
@@ -1059,6 +1147,35 @@ typedef struct
   */
 #endif /* TIM_BREAK_INPUT_SUPPORT */
 
+#if defined(TIM_BDTR_BKBID)
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_ReArmBRK(_PARAM_)
+#define LL_TIM_ReArmBRK2(_PARAM_)
+/**
+@endcond
+  */
+
+#endif /*TIM_BDTR_BKBID */
 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
   * @{
   */
@@ -1083,10 +1200,10 @@ typedef struct
 #define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
-#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)
+#if defined(TIM1_AF1_BKINE)&&defined(TIM1_AF2_BKINE)
 #define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
-#endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */
+#endif /* TIM1_AF1_BKINE && TIM1_AF2_BKINE */
 #define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
 /**
   * @}
@@ -1120,8 +1237,8 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM1 input 1 is connected to GPIO */
-#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1 input 1 is connected to COMP1 OUT */
+#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM1 input 1 is connected to GPIO */
+#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM1 input 1 is connected to COMP1 OUT */
 /**
   * @}
   */
@@ -1129,8 +1246,8 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM8 input 1 is connected to GPIO */
-#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8 input 1 is connected to COMP2 OUT */
+#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM8 input 1 is connected to GPIO */
+#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /*!< TIM8 input 1 is connected to COMP2 OUT */
 /**
   * @}
   */
@@ -1138,10 +1255,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap
   * @{
   */
-#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /* !< TIM2 input 4 is connected to GPIO */
-#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2 input 4 is connected to COMP1 OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2 input 4 is connected to COMP2 OUT */
-#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
+#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /*!< TIM2 input 4 is connected to GPIO */
+#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /*!< TIM2 input 4 is connected to COMP1 OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /*!< TIM2 input 4 is connected to COMP2 OUT */
+#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */
 /**
   * @}
   */
@@ -1149,10 +1266,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM3 input 1 is connected to GPIO */
-#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3 input 1 is connected to COMP1 OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3 input 1 is connected to COMP2 OUT */
-#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
+#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM3 input 1 is connected to GPIO */
+#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /*!< TIM3 input 1 is connected to COMP1 OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /*!< TIM3 input 1 is connected to COMP2 OUT */
+#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */
 /**
   * @}
   */
@@ -1160,9 +1277,9 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM5 input 1 is connected to GPIO */
-#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5 input 1 is connected to CAN TMP */
-#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5 input 1 is connected to CAN RTP */
+#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /*!< TIM5 input 1 is connected to GPIO */
+#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /*!< TIM5 input 1 is connected to CAN TMP */
+#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /*!< TIM5 input 1 is connected to CAN RTP */
 /**
   * @}
   */
@@ -1170,8 +1287,8 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM12 input 1 is connected to GPIO */
-#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 input 1 is connected to SPDIF FS */
+#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM12 input 1 is connected to GPIO */
+#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM12 input 1 is connected to SPDIF FS */
 /**
   * @}
   */
@@ -1179,13 +1296,13 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 1 is connected to GPIO */
-#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15 input 1 is connected to TIM2 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15 input 1 is connected to TIM3 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */
-#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15 input 1 is connected to RCC LSE  */
-#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI  */
-#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */
+#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM15 input 1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /*!< TIM15 input 1 is connected to TIM2 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /*!< TIM15 input 1 is connected to TIM3 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to TIM4 CH1 */
+#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /*!< TIM15 input 1 is connected to RCC LSE  */
+#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to RCC CSI  */
+#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15 input 1 is connected to RCC MCO2 */
 /**
   * @}
   */
@@ -1193,10 +1310,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap
   * @{
   */
-#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 2 is connected to GPIO */
-#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15 input 2 is connected to TIM2 CH2 */
-#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15 input 2 is connected to TIM3 CH2 */
-#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /*!< TIM15 input 2 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /*!< TIM15 input 2 is connected to TIM2 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /*!< TIM15 input 2 is connected to TIM3 CH2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15 input 2 is connected to TIM4 CH2 */
 /**
   * @}
   */
@@ -1204,10 +1321,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM16 input 1 is connected to GPIO */
-#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 input 1 is connected to RCC LSI */
-#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 input 1 is connected to RCC LSE */
-#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */
+#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM16 input 1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /*!< TIM16 input 1 is connected to RCC LSI */
+#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /*!< TIM16 input 1 is connected to RCC LSE */
+#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to WKUP_IT */
 /**
   * @}
   */
@@ -1215,10 +1332,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM17 input 1 is connected to GPIO */
-#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 input 1 is connected to SPDIF FS */
-#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */
-#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */
+#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM17 input 1 is connected to GPIO */
+#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /*!< TIM17 input 1 is connected to SPDIF FS */
+#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /*!< TIM17 input 1 is connected to RCC HSE 1Mhz */
+#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to RCC MCO1 */
 /**
   * @}
   */
@@ -1226,10 +1343,10 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap
   * @{
   */
-#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /* !< TIM23 input 4 is connected to GPIO */
-#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23 input 4 is connected to COMP1 OUT */
-#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23 input 4 is connected to COMP2 OUT */
-#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
+#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /*!< TIM23 input 4 is connected to GPIO */
+#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /*!< TIM23 input 4 is connected to COMP1 OUT */
+#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /*!< TIM23 input 4 is connected to COMP2 OUT */
+#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */
 /**
   * @}
   */
@@ -1237,10 +1354,13 @@ typedef struct
 /** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap
   * @{
   */
-#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM24 input 1 is connected to GPIO */
-#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24 input 1 is connected to CAN TMP  */
-#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24 input 1 is connected to CAN RTP  */
-#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */
+#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /*!< TIM24 input 1 is connected to GPIO */
+#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /*!< TIM24 input 1 is connected to CAN TMP  */
+#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /*!< TIM24 input 1 is connected to CAN RTP  */
+#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
+/**
+  * @}
+  */
 
 #if defined(TIM_BREAK_INPUT_SUPPORT)
 /** Legacy definitions for compatibility purpose
@@ -1251,6 +1371,7 @@ typedef struct
 @endcond
   */
 #endif /* TIM_BREAK_INPUT_SUPPORT */
+
 /**
   * @}
   */
@@ -1283,10 +1404,6 @@ typedef struct
   * @}
   */
 
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
-  * @{
-  */
-
 /**
   * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
   * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
@@ -1310,10 +1427,17 @@ typedef struct
   * @retval DTG[0:7]
   */
 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
-  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \
-    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
-    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
     0U)
 
 /**
@@ -1324,7 +1448,7 @@ typedef struct
   * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
   */
 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
-  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
 
 /**
   * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
@@ -1338,7 +1462,8 @@ typedef struct
   ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
 
 /**
-  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
   * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
   * @param  __TIMCLK__ timer input clock frequency (in Hz)
   * @param  __PSC__ prescaler
@@ -1350,7 +1475,8 @@ typedef struct
               / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
 
 /**
-  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
   * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
   * @param  __TIMCLK__ timer input clock frequency (in Hz)
   * @param  __PSC__ prescaler
@@ -1376,11 +1502,6 @@ typedef struct
   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
 
 
-/**
-  * @}
-  */
-
-
 /**
   * @}
   */
@@ -1421,7 +1542,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
 }
@@ -1454,7 +1575,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval Inverted state of bit (0 or 1).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
 }
@@ -1488,7 +1609,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo
   *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
   *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
   */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
 }
@@ -1515,7 +1636,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse
   *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
   *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
   */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
 }
@@ -1559,7 +1680,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo
   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
   *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
   */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
 {
   uint32_t counter_mode;
 
@@ -1601,13 +1722,14 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
 }
 
 /**
-  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
   *       whether or not the clock division feature is supported by the timer
   *       instance.
@@ -1625,7 +1747,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
 }
 
 /**
-  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
   * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
   *       whether or not the clock division feature is supported by the timer
   *       instance.
@@ -1636,7 +1759,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
   *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
   */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
 }
@@ -1663,7 +1786,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
   * @param  TIMx Timer instance
   * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
   */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CNT));
 }
@@ -1676,7 +1799,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
   *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
   *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
   */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
 }
@@ -1703,7 +1826,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
   * @param  TIMx Timer instance
   * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
   */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->PSC));
 }
@@ -1732,7 +1855,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload
   * @param  TIMx Timer instance
   * @retval Auto-reload value
   */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->ARR));
 }
@@ -1760,14 +1883,15 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep
   * @param  TIMx Timer instance
   * @retval Repetition counter value
   */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->RCR));
 }
 
 /**
   * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
-  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
   * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
   * @param  TIMx Timer instance
   * @retval None
@@ -1793,7 +1917,7 @@ __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
   * @param  Counter Counter value
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
 {
   return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
 }
@@ -1834,6 +1958,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
   CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
 }
 
+/**
+  * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
 /**
   * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
   * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
@@ -1872,7 +2007,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR
   *         @arg @ref LL_TIM_CCDMAREQUEST_CC
   *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
   */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
 }
@@ -1978,7 +2113,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
   *         @arg @ref LL_TIM_CHANNEL_CH6
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
 {
   return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
 }
@@ -2064,15 +2199,15 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
   * @retval None
   */
 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
 }
 
 /**
@@ -2104,14 +2239,14 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
   *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
   *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
-  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
-  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
 }
 
 /**
@@ -2173,7 +2308,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
   *         @arg @ref LL_TIM_OCPOLARITY_HIGH
   *         @arg @ref LL_TIM_OCPOLARITY_LOW
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
@@ -2242,7 +2377,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel,
   *         @arg @ref LL_TIM_OCIDLESTATE_LOW
   *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
@@ -2319,7 +2454,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
   *         @arg @ref LL_TIM_CHANNEL_CH6
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2395,7 +2530,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
   *         @arg @ref LL_TIM_CHANNEL_CH6
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2480,7 +2615,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
   *         @arg @ref LL_TIM_CHANNEL_CH6
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2489,7 +2624,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch
 }
 
 /**
-  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
   *       dead-time insertion feature is supported by a timer instance.
   * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
@@ -2610,7 +2746,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t Compare
   * @param  TIMx Timer instance
   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR1));
 }
@@ -2626,7 +2762,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR2));
 }
@@ -2642,7 +2778,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR3));
 }
@@ -2658,7 +2794,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR4));
 }
@@ -2671,7 +2807,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
 }
@@ -2684,7 +2820,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR6));
 }
@@ -2756,7 +2892,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
   MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
-             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
   MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
              (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
 }
@@ -2803,7 +2940,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe
   *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
   *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2854,7 +2991,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel,
   *         @arg @ref LL_TIM_ICPSC_DIV4
   *         @arg @ref LL_TIM_ICPSC_DIV8
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2929,7 +3066,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui
   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
   *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
@@ -2986,7 +3123,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel,
   *         @arg @ref LL_TIM_IC_POLARITY_FALLING
   *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
 {
   uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
   return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
@@ -3027,7 +3164,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
 }
@@ -3043,7 +3180,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR1));
 }
@@ -3059,7 +3196,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR2));
 }
@@ -3075,7 +3212,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR3));
 }
@@ -3091,7 +3228,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
   */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
 {
   return (uint32_t)(READ_REG(TIMx->CCR4));
 }
@@ -3138,7 +3275,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
 }
@@ -3273,10 +3410,6 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
   *         @arg @ref LL_TIM_TS_ITR1
   *         @arg @ref LL_TIM_TS_ITR2
   *         @arg @ref LL_TIM_TS_ITR3
-  *         @arg @ref LL_TIM_TS_TI1F_ED
-  *         @arg @ref LL_TIM_TS_TI1FP1
-  *         @arg @ref LL_TIM_TS_TI2FP2
-  *         @arg @ref LL_TIM_TS_ETRF
   *         @arg @ref LL_TIM_TS_ITR4
   *         @arg @ref LL_TIM_TS_ITR5
   *         @arg @ref LL_TIM_TS_ITR6
@@ -3287,6 +3420,10 @@ __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
   *         @arg @ref LL_TIM_TS_ITR11 (*)
   *         @arg @ref LL_TIM_TS_ITR12 (*)
   *         @arg @ref LL_TIM_TS_ITR13 (*)
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
   *
   *      (*)  Value not defined in all devices.
   * @retval None
@@ -3330,7 +3467,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
 }
@@ -3477,6 +3614,56 @@ __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
 }
 
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+  *       LL_TIM_BREAK_AFMODE_INPUT.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK\n
+  *         BDTR         BKBID         LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @param  BreakAFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+                                      uint32_t BreakAFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+#else
 /**
   * @brief  Configure the break input.
   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
@@ -3512,6 +3699,24 @@ __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,
   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
 }
 
+#endif /* TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Disarm the break input (when it operates in bidirectional mode).
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
 /**
   * @brief  Enable the break 2 function.
   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
@@ -3538,6 +3743,56 @@ __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
   CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
 }
 
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break 2 input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+  *       LL_TIM_BREAK2_AFMODE_INPUT.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @param  Break2AFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+                                       uint32_t Break2AFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+#else
 /**
   * @brief  Configure the break 2 input.
   * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
@@ -3572,6 +3827,24 @@ __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarit
   MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
 }
 
+#endif /*TIM_BDTR_BKBID */
+#if defined(TIM_BDTR_BKBID)
+/**
+  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
+  * @note  The break 2 input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+#endif /*TIM_BDTR_BKBID */
 /**
   * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
   * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
@@ -3626,7 +3899,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
 }
@@ -3669,7 +3942,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
 }
@@ -3796,13 +4069,13 @@ __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint3
   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
   *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
   *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  
-  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
   *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
-  *         
+  *
   * @param  DMABurstLength This parameter can be one of the following values:
   *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
   *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
@@ -3938,7 +4211,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
 }
@@ -3960,7 +4233,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
 }
@@ -3982,7 +4255,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
 }
@@ -4004,7 +4277,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
 }
@@ -4026,7 +4299,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
 }
@@ -4048,7 +4321,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
 }
@@ -4070,7 +4343,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
 }
@@ -4092,7 +4365,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
 }
@@ -4114,7 +4387,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
 }
@@ -4136,7 +4409,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
 }
@@ -4158,7 +4431,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
 }
@@ -4175,12 +4448,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
 }
 
 /**
-  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
   * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
 }
@@ -4197,12 +4471,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
 }
 
 /**
-  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
   * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
 }
@@ -4219,12 +4494,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
 }
 
 /**
-  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
   * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
 }
@@ -4241,12 +4517,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
 }
 
 /**
-  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
   * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
 }
@@ -4268,7 +4545,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
 }
@@ -4308,7 +4585,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
 }
@@ -4341,7 +4618,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
 }
@@ -4374,7 +4651,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
 }
@@ -4407,7 +4684,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
 }
@@ -4440,7 +4717,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
 }
@@ -4473,7 +4750,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
 }
@@ -4506,7 +4783,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
 }
@@ -4539,7 +4816,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
 }
@@ -4548,7 +4825,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
   * @}
   */
 
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
   * @{
   */
 /**
@@ -4579,7 +4856,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
 }
@@ -4612,7 +4889,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
 }
@@ -4645,7 +4922,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
 }
@@ -4678,7 +4955,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
 }
@@ -4711,7 +4988,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
 }
@@ -4744,7 +5021,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
 }
@@ -4777,7 +5054,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
   * @param  TIMx Timer instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
 {
   return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
 }
@@ -4897,19 +5174,19 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
   * @{
   */
 
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
 /**
   * @}
   */
@@ -4934,4 +5211,3 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT
 #endif
 
 #endif /* __STM32H7xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c
index 2dc28f06bc..d4b8d2880f 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -32,7 +31,8 @@
   * @{
   */
 
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+ || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
 
 /** @addtogroup USART_LL
   * @{
@@ -41,6 +41,17 @@
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
+/** @addtogroup USART_LL_Private_Constants
+  * @{
+  */
+
+/* Definition of default baudrate value used for USART initialisation */
+#define USART_DEFAULT_BAUDRATE          (9600U)
+
+/**
+  * @}
+  */
+
 /* Private macros ------------------------------------------------------------*/
 /** @addtogroup USART_LL_Private_Macros
   * @{
@@ -126,7 +137,7 @@
   *          - SUCCESS: USART registers are de-initialized
   *          - ERROR: USART registers are not de-initialized
   */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx)
 {
   ErrorStatus status = SUCCESS;
 
@@ -239,7 +250,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
   *          - SUCCESS: USART registers are initialized according to USART_InitStruct content
   *          - ERROR: Problem occurred during USART Registers initialization
   */
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct)
 {
   ErrorStatus status = ERROR;
   uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
@@ -379,7 +390,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
 {
   /* Set USART_InitStruct fields to default values */
   USART_InitStruct->PrescalerValue      = LL_USART_PRESCALER_DIV1;
-  USART_InitStruct->BaudRate            = 9600U;
+  USART_InitStruct->BaudRate            = USART_DEFAULT_BAUDRATE;
   USART_InitStruct->DataWidth           = LL_USART_DATAWIDTH_8B;
   USART_InitStruct->StopBits            = LL_USART_STOPBITS_1;
   USART_InitStruct->Parity              = LL_USART_PARITY_NONE ;
@@ -402,7 +413,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
   *                     to USART_ClockInitStruct content
   *          - ERROR: Problem occurred during USART Registers initialization
   */
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
 {
   ErrorStatus status = SUCCESS;
 
@@ -481,5 +492,4 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
 
 #endif /* USE_FULL_LL_DRIVER */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h
index 4a164ba3f1..d1242ebde2 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -32,7 +31,8 @@ extern "C" {
   * @{
   */
 
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \
+ || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10)
 
 /** @defgroup USART_LL USART
   * @{
@@ -64,6 +64,12 @@ static const uint32_t USART_PRESCALER_TAB[] =
   */
 
 /* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
 /* Private macros ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup USART_LL_Private_Macros USART Private Macros
@@ -651,7 +657,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
 }
@@ -690,7 +696,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
 }
@@ -712,7 +718,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
 {
-  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
 }
 
 /**
@@ -729,7 +735,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t
   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
   */
-__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
 }
@@ -751,7 +757,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
 {
-  MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
 }
 
 /**
@@ -768,7 +774,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t
   *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
   *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
   */
-__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
 }
@@ -798,8 +804,8 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
 {
-  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
-             (RXThreshold << USART_CR3_RXFTCFG_Pos));
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
 }
 
 /**
@@ -814,7 +820,7 @@ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32
   */
 __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_UESM);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
 }
 
 /**
@@ -828,7 +834,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
 }
 
 /**
@@ -839,7 +845,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
 }
@@ -852,7 +858,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_RE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
 }
 
 /**
@@ -863,7 +869,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
 }
 
 /**
@@ -874,7 +880,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_TE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
 }
 
 /**
@@ -885,7 +891,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
 }
 
 /**
@@ -903,7 +909,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
 {
-  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
 }
 
 /**
@@ -917,7 +923,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32
   *         @arg @ref LL_USART_DIRECTION_TX
   *         @arg @ref LL_USART_DIRECTION_TX_RX
   */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
 }
@@ -951,7 +957,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
   *         @arg @ref LL_USART_PARITY_EVEN
   *         @arg @ref LL_USART_PARITY_ODD
   */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
 }
@@ -978,7 +984,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me
   *         @arg @ref LL_USART_WAKEUP_IDLELINE
   *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
   */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
 }
@@ -1009,7 +1015,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW
   *         @arg @ref LL_USART_DATAWIDTH_8B
   *         @arg @ref LL_USART_DATAWIDTH_9B
   */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
 }
@@ -1022,7 +1028,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_MME);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
 }
 
 /**
@@ -1033,7 +1039,7 @@ __STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
 }
 
 /**
@@ -1042,7 +1048,7 @@ __STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
 }
@@ -1069,7 +1075,7 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov
   *         @arg @ref LL_USART_OVERSAMPLING_16
   *         @arg @ref LL_USART_OVERSAMPLING_8
   */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
 }
@@ -1101,7 +1107,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3
   *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
   *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
   */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
 }
@@ -1132,7 +1138,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc
   *         @arg @ref LL_USART_PHASE_1EDGE
   *         @arg @ref LL_USART_PHASE_2EDGE
   */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
 }
@@ -1163,7 +1169,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C
   *         @arg @ref LL_USART_POLARITY_LOW
   *         @arg @ref LL_USART_POLARITY_HIGH
   */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
 }
@@ -1242,7 +1248,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc
   *         @arg @ref LL_USART_PRESCALER_DIV128
   *         @arg @ref LL_USART_PRESCALER_DIV256
   */
-__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
 }
@@ -1281,7 +1287,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
 }
@@ -1312,7 +1318,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t
   *         @arg @ref LL_USART_STOPBITS_1_5
   *         @arg @ref LL_USART_STOPBITS_2
   */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
 }
@@ -1373,7 +1379,7 @@ __STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapCo
   *         @arg @ref LL_USART_TXRX_STANDARD
   *         @arg @ref LL_USART_TXRX_SWAPPED
   */
-__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
 }
@@ -1400,7 +1406,7 @@ __STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinI
   *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
   *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
   */
-__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
 }
@@ -1427,7 +1433,7 @@ __STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinI
   *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
   *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
   */
-__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
 }
@@ -1456,7 +1462,7 @@ __STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t
   *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
   *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
   */
-__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
 }
@@ -1487,7 +1493,7 @@ __STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_
   *         @arg @ref LL_USART_BITORDER_LSBFIRST
   *         @arg @ref LL_USART_BITORDER_MSBFIRST
   */
-__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
 }
@@ -1526,7 +1532,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
 }
@@ -1561,7 +1567,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
   *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
   */
-__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
 }
@@ -1594,7 +1600,7 @@ __STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
 }
@@ -1638,7 +1644,7 @@ __STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t
   * @param  USARTx USART Instance
   * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
   */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
 }
@@ -1651,7 +1657,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
   *         @arg @ref LL_USART_ADDRESS_DETECT_4B
   *         @arg @ref LL_USART_ADDRESS_DETECT_7B
   */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
 }
@@ -1740,7 +1746,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard
   *         @arg @ref LL_USART_HWCONTROL_CTS
   *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
   */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
 }
@@ -1773,7 +1779,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
 }
@@ -1806,7 +1812,7 @@ __STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
 }
@@ -1839,7 +1845,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
   *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
   *         @arg @ref LL_USART_WAKEUP_ON_RXNE
   */
-__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
 }
@@ -1927,7 +1933,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph
   *         @arg @ref LL_USART_OVERSAMPLING_8
   * @retval Baud Rate
   */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
                                               uint32_t OverSampling)
 {
   uint32_t usartdiv;
@@ -1976,7 +1982,7 @@ __STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeo
   * @param  USARTx USART Instance
   * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
   */
-__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
 }
@@ -1999,7 +2005,7 @@ __STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t Blo
   * @param  USARTx USART Instance
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
 }
@@ -2046,7 +2052,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
 }
@@ -2077,7 +2083,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P
   *         @arg @ref LL_USART_IRDA_POWER_NORMAL
   *         @arg @ref LL_USART_PHASE_2EDGE
   */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
 }
@@ -2094,7 +2100,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
 {
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
 }
 
 /**
@@ -2106,7 +2112,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P
   * @param  USARTx USART Instance
   * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
   */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
 }
@@ -2153,7 +2159,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
 }
@@ -2192,7 +2198,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
 }
@@ -2224,7 +2230,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx,
   * @param  USARTx USART Instance
   * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
   */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
 }
@@ -2241,7 +2247,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR
   */
 __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
 {
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
 }
 
 /**
@@ -2253,7 +2259,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3
   * @param  USARTx USART Instance
   * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
   */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
 }
@@ -2270,7 +2276,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
 {
-  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
 }
 
 /**
@@ -2282,7 +2288,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3
   * @param  USARTx USART Instance
   * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
   */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
 }
@@ -2329,7 +2335,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
 }
@@ -2375,7 +2381,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
 }
@@ -2417,7 +2423,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
 }
@@ -2456,7 +2462,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3
   *         @arg @ref LL_USART_LINBREAK_DETECT_10B
   *         @arg @ref LL_USART_LINBREAK_DETECT_11B
   */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
 }
@@ -2495,7 +2501,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
 }
@@ -2530,7 +2536,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32
   * @param  USARTx USART Instance
   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
   */
-__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
 }
@@ -2557,7 +2563,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t
   * @param  USARTx USART Instance
   * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
   */
-__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
 }
@@ -2596,7 +2602,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
 }
@@ -2627,7 +2633,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_
   *         @arg @ref LL_USART_DE_POLARITY_HIGH
   *         @arg @ref LL_USART_DE_POLARITY_LOW
   */
-__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
 {
   return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
 }
@@ -2930,7 +2936,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
 }
@@ -2941,7 +2947,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
 }
@@ -2952,7 +2958,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
 }
@@ -2963,7 +2969,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
 }
@@ -2974,13 +2980,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
@@ -2990,7 +2995,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
 }
@@ -3001,13 +3006,12 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
@@ -3017,7 +3021,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
 }
@@ -3030,7 +3034,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
 }
@@ -3043,7 +3047,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
 }
@@ -3056,7 +3060,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
 }
@@ -3067,7 +3071,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
 }
@@ -3080,7 +3084,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
 }
@@ -3093,7 +3097,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
 }
@@ -3106,7 +3110,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
 }
@@ -3119,7 +3123,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
 }
@@ -3130,7 +3134,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
 }
@@ -3141,7 +3145,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
 }
@@ -3152,7 +3156,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
 }
@@ -3163,7 +3167,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
 }
@@ -3176,7 +3180,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
 }
@@ -3187,7 +3191,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
 }
@@ -3198,7 +3202,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
 }
@@ -3211,7 +3215,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
 }
@@ -3224,7 +3228,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
 }
@@ -3235,7 +3239,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
 }
@@ -3248,7 +3252,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
 }
@@ -3261,7 +3265,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
 }
@@ -3459,11 +3463,10 @@ __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
 }
 
-/* Legacy define */
-#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
@@ -3475,7 +3478,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
 }
 
 /**
@@ -3486,11 +3489,10 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
 }
 
-/* Legacy define */
-#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
@@ -3502,7 +3504,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
 }
 
 /**
@@ -3513,7 +3515,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
 }
 
 /**
@@ -3524,7 +3526,7 @@ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
 }
 
 /**
@@ -3535,7 +3537,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
 }
 
 /**
@@ -3548,7 +3550,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
 }
 
 /**
@@ -3561,7 +3563,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
 }
 
 /**
@@ -3572,7 +3574,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
 }
 
 /**
@@ -3600,7 +3602,7 @@ __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_EIE);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
 }
 
 /**
@@ -3613,7 +3615,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
 }
 
 /**
@@ -3626,7 +3628,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
 }
 
 /**
@@ -3639,7 +3641,7 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
 }
 
 /**
@@ -3652,7 +3654,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
 }
 
 /**
@@ -3665,7 +3667,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
 }
 
 /**
@@ -3676,11 +3678,10 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
 }
 
-/* Legacy define */
-#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
@@ -3692,7 +3693,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
 }
 
 /**
@@ -3703,11 +3704,10 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
 }
 
-/* Legacy define */
-#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
@@ -3719,7 +3719,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
 }
 
 /**
@@ -3730,7 +3730,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
 }
 
 /**
@@ -3741,7 +3741,7 @@ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
 }
 
 /**
@@ -3752,7 +3752,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
 }
 
 /**
@@ -3765,7 +3765,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
 }
 
 /**
@@ -3778,7 +3778,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
 }
 
 /**
@@ -3791,7 +3791,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
 }
 
 /**
@@ -3819,7 +3819,7 @@ __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
 }
 
 /**
@@ -3832,7 +3832,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
 }
 
 /**
@@ -3845,7 +3845,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
 }
 
 /**
@@ -3858,7 +3858,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
 }
 
 /**
@@ -3871,7 +3871,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
 }
 
 /**
@@ -3884,7 +3884,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
 }
 
 /**
@@ -3893,13 +3893,12 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
@@ -3909,7 +3908,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
 }
@@ -3920,13 +3919,12 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
 }
 
-/* Legacy define */
-#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
 
 /**
   * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
@@ -3936,7 +3934,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
 }
@@ -3947,7 +3945,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
 }
@@ -3958,7 +3956,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
 }
@@ -3969,7 +3967,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
 }
@@ -3982,7 +3980,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
 }
@@ -3995,7 +3993,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
 }
@@ -4008,7 +4006,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
 }
@@ -4021,7 +4019,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
 }
@@ -4032,7 +4030,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
 }
@@ -4045,7 +4043,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
 }
@@ -4058,7 +4056,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
 }
@@ -4071,7 +4069,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
 }
@@ -4084,7 +4082,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
 }
@@ -4097,7 +4095,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
 }
@@ -4118,7 +4116,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
 }
 
 /**
@@ -4129,7 +4127,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
 }
 
 /**
@@ -4138,7 +4136,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
 }
@@ -4151,7 +4149,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
 {
-  SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
 }
 
 /**
@@ -4162,7 +4160,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
   */
 __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
 {
-  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
 }
 
 /**
@@ -4171,7 +4169,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
 }
@@ -4204,7 +4202,7 @@ __STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
 {
   return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
 }
@@ -4219,7 +4217,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx
   *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
   * @retval Address of data register
   */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
 {
   uint32_t data_reg_addr;
 
@@ -4251,7 +4249,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t
   * @param  USARTx USART Instance
   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
   */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
 {
   return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
 }
@@ -4262,7 +4260,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
   * @param  USARTx USART Instance
   * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
   */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
 {
   return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
 }
@@ -4370,10 +4368,10 @@ __STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
 /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
   * @{
   */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
 void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
 void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
 /**
   * @}
@@ -4400,4 +4398,3 @@ void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS
 
 #endif /* STM32H7xx_LL_USART_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c
index 48940661ea..ed2ca0f04a 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c
@@ -11,29 +11,30 @@
   *           + Peripheral Control functions
   *           + Peripheral State functions
   *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                     ##### How to use this driver #####
   ==============================================================================
     [..]
-      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+      (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
 
       (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
 
       (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
 
   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
+
   ******************************************************************************
   */
 
@@ -82,7 +83,6 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
 {
   HAL_StatusTypeDef ret;
-
   if (cfg.phy_itface == USB_OTG_ULPI_PHY)
   {
     USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
@@ -252,21 +252,39 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
   */
 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)
 {
+  uint32_t ms = 0U;
+
   USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
 
   if (mode == USB_HOST_MODE)
   {
     USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+
+    do
+    {
+      HAL_Delay(10U);
+      ms += 10U;
+    } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
   }
   else if (mode == USB_DEVICE_MODE)
   {
     USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+
+    do
+    {
+      HAL_Delay(10U);
+      ms += 10U;
+    } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS));
   }
   else
   {
     return HAL_ERROR;
   }
-  HAL_Delay(50U);
+
+  if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS)
+  {
+    return HAL_ERROR;
+  }
 
   return HAL_OK;
 }
@@ -311,9 +329,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
   /* Restart the Phy Clock */
   USBx_PCGCCTL = 0U;
 
-  /* Device mode configuration */
-  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-
   if (cfg.phy_itface == USB_OTG_ULPI_PHY)
   {
     if (cfg.speed == USBD_HS_SPEED)
@@ -427,7 +442,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
 }
 
 /**
-  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO
+  * @brief  USB_FlushTxFifo Flush a Tx FIFO
   * @param  USBx  Selected device
   * @param  num  FIFO number
   *         This parameter can be a value from 1 to 15
@@ -436,13 +451,28 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf
   */
 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
 {
-  uint32_t count = 0U;
+  __IO uint32_t count = 0U;
 
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Flush TX Fifo */
+  count = 0U;
   USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));
 
   do
   {
-    if (++count > 200000U)
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
     {
       return HAL_TIMEOUT;
     }
@@ -452,19 +482,34 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)
 }
 
 /**
-  * @brief  USB_FlushRxFifo : Flush Rx FIFO
+  * @brief  USB_FlushRxFifo  Flush Rx FIFO
   * @param  USBx  Selected device
   * @retval HAL status
   */
 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint32_t count = 0;
+  __IO uint32_t count = 0U;
 
+  /* Wait for AHB master IDLE state. */
+  do
+  {
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
+    {
+      return HAL_TIMEOUT;
+    }
+  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
+
+  /* Flush RX Fifo */
+  count = 0U;
   USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
 
   do
   {
-    if (++count > 200000U)
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
     {
       return HAL_TIMEOUT;
     }
@@ -484,7 +529,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
   *            @arg USB_OTG_SPEED_FULL: Full speed mode
   * @retval  Hal status
   */
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -500,7 +545,7 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)
   *            @arg USBD_HS_SPEED: High speed mode
   *            @arg USBD_FS_SPEED: Full speed mode
   */
-uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint8_t speed;
@@ -529,7 +574,7 @@ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
   * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t epnum = (uint32_t)ep->num;
@@ -567,7 +612,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTy
   * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t epnum = (uint32_t)ep->num;
@@ -606,7 +651,7 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB
   * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t epnum = (uint32_t)ep->num;
@@ -653,7 +698,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EP
   * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t epnum = (uint32_t)ep->num;
@@ -720,7 +765,22 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
       */
       USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
       USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+
+      if (epnum == 0U)
+      {
+        if (ep->xfer_len > ep->maxpacket)
+        {
+          ep->xfer_len = ep->maxpacket;
+        }
+
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
+      }
+      else
+      {
+        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT &
+                                       (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));
+      }
+
       USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
 
       if (ep->type == EP_TYPE_ISOC)
@@ -789,16 +849,34 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
     USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
     USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
 
-    if (ep->xfer_len == 0U)
+    if (epnum == 0U)
     {
-      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+      if (ep->xfer_len > 0U)
+      {
+        ep->xfer_len = ep->maxpacket;
+      }
+
+      /* Store transfer size, for EP0 this is equal to endpoint max packet size */
+      ep->xfer_size = ep->maxpacket;
+
+      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size);
       USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
     }
     else
     {
-      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
-      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
-      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);
+      if (ep->xfer_len == 0U)
+      {
+        USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
+        USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
+      }
+      else
+      {
+        pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);
+        ep->xfer_size = ep->maxpacket * pktcnt;
+
+        USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);
+        USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size;
+      }
     }
 
     if (dma == 1U)
@@ -827,103 +905,64 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
   return HAL_OK;
 }
 
+
 /**
-  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0
-  * @param  USBx  Selected device
-  * @param  ep pointer to endpoint structure
-  * @param  dma USB dma enabled or disabled
-  *          This parameter can be one of these values:
-  *           0 : DMA feature not used
-  *           1 : DMA feature used
-  * @retval HAL status
-  */
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)
+   * @brief  USB_EPStoptXfer  Stop transfer on an EP
+   * @param  USBx  usb device instance
+   * @param  ep pointer to endpoint structure
+   * @retval HAL status
+   */
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
 {
+  __IO uint32_t count = 0U;
+  HAL_StatusTypeDef ret = HAL_OK;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t epnum = (uint32_t)ep->num;
 
   /* IN endpoint */
   if (ep->is_in == 1U)
   {
-    /* Zero Length Packet? */
-    if (ep->xfer_len == 0U)
+    /* EP enable, IN data in FIFO */
+    if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
     {
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-    }
-    else
-    {
-      /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+      USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK);
+      USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS);
 
-      if (ep->xfer_len > ep->maxpacket)
+      do
       {
-        ep->xfer_len = ep->maxpacket;
-      }
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
-      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-    }
+        count++;
 
-    if (dma == 1U)
-    {
-      if ((uint32_t)ep->dma_addr != 0U)
-      {
-        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);
-      }
-
-      /* EP enable, IN data in FIFO */
-      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-    }
-    else
-    {
-      /* EP enable, IN data in FIFO */
-      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
-      /* Enable the Tx FIFO Empty Interrupt for this EP */
-      if (ep->xfer_len > 0U)
-      {
-        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);
-      }
+        if (count > 10000U)
+        {
+          ret = HAL_ERROR;
+          break;
+        }
+      } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) ==  USB_OTG_DIEPCTL_EPENA);
     }
   }
   else /* OUT endpoint */
   {
-    /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */
-    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
-    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
-    if (ep->xfer_len > 0U)
+    if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
     {
-      ep->xfer_len = ep->maxpacket;
-    }
+      USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK);
+      USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS);
 
-    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
-    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
-
-    if (dma == 1U)
-    {
-      if ((uint32_t)ep->xfer_buff != 0U)
+      do
       {
-        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);
-      }
-    }
+        count++;
 
-    /* EP enable */
-    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+        if (count > 10000U)
+        {
+          ret = HAL_ERROR;
+          break;
+        }
+      } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) ==  USB_OTG_DOEPCTL_EPENA);
+    }
   }
 
-  return HAL_OK;
+  return ret;
 }
 
+
 /**
   * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated
   *         with the EP/channel
@@ -937,12 +976,13 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe
   *           1 : DMA feature used
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
                                   uint8_t ch_ep_num, uint16_t len, uint8_t dma)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint8_t *pSrc = src;
-  uint32_t count32b, i;
+  uint32_t count32b;
+  uint32_t i;
 
   if (dma == 0U)
   {
@@ -967,7 +1007,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
   * @param  len  Number of bytes to read
   * @retval pointer to destination buffer
   */
-void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
+void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint8_t *pDest = dest;
@@ -990,7 +1030,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
   {
     i = 0U;
     __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U));
-	
+
     do
     {
       *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i)));
@@ -1009,7 +1049,7 @@ void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
   * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t epnum = (uint32_t)ep->num;
@@ -1040,7 +1080,7 @@ HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef
   * @param  ep pointer to endpoint structure
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t epnum = (uint32_t)ep->num;
@@ -1110,7 +1150,7 @@ HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
   *          This parameter can be a value from 0 to 255
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1125,7 +1165,7 @@ HAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres
   * @param  USBx  Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1142,7 +1182,7 @@ HAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)
   * @param  USBx  Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1157,9 +1197,9 @@ HAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)
 /**
   * @brief  USB_ReadInterrupts: return the global USB interrupt status
   * @param  USBx  Selected device
-  * @retval HAL status
+  * @retval USB Global Interrupt status
   */
-uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx)
 {
   uint32_t tmpreg;
 
@@ -1169,12 +1209,29 @@ uint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)
   return tmpreg;
 }
 
+/**
+  * @brief  USB_ReadChInterrupts: return USB channel interrupt status
+  * @param  USBx  Selected device
+  * @param  chnum Channel number
+  * @retval USB Channel Interrupt status
+  */
+uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum)
+{
+  uint32_t USBx_BASE = (uint32_t)USBx;
+  uint32_t tmpreg;
+
+  tmpreg = USBx_HC(chnum)->HCINT;
+  tmpreg &= USBx_HC(chnum)->HCINTMSK;
+
+  return tmpreg;
+}
+
 /**
   * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
   * @param  USBx  Selected device
-  * @retval HAL status
+  * @retval USB Device OUT EP interrupt status
   */
-uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t tmpreg;
@@ -1188,9 +1245,9 @@ uint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
 /**
   * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
   * @param  USBx  Selected device
-  * @retval HAL status
+  * @retval USB Device IN EP interrupt status
   */
-uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t tmpreg;
@@ -1208,7 +1265,7 @@ uint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)
   *          This parameter can be a value from 0 to 15
   * @retval Device OUT EP Interrupt register
   */
-uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t tmpreg;
@@ -1226,10 +1283,12 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
   *          This parameter can be a value from 0 to 15
   * @retval Device IN EP Interrupt register
   */
-uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
+uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t tmpreg, msk, emp;
+  uint32_t tmpreg;
+  uint32_t msk;
+  uint32_t emp;
 
   msk = USBx_DEVICE->DIEPMSK;
   emp = USBx_DEVICE->DIEPEMPMSK;
@@ -1247,7 +1306,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)
   */
 void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
 {
-  USBx->GINTSTS |= interrupt;
+  USBx->GINTSTS &= interrupt;
 }
 
 /**
@@ -1258,7 +1317,7 @@ void  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
   *           0 : Host
   *           1 : Device
   */
-uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx)
 {
   return ((USBx->GINTSTS) & 0x1U);
 }
@@ -1268,7 +1327,7 @@ uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
   * @param  USBx  Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1290,10 +1349,10 @@ HAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)
   * @param  psetup  pointer to setup packet
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
+  uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U);
 
   if (gSNPSiD > USB_OTG_CORE_ID_300A)
   {
@@ -1325,12 +1384,14 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin
   */
 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
 {
-  uint32_t count = 0U;
+  __IO uint32_t count = 0U;
 
   /* Wait for AHB master IDLE state. */
   do
   {
-    if (++count > 200000U)
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
     {
       return HAL_TIMEOUT;
     }
@@ -1342,7 +1403,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
 
   do
   {
-    if (++count > 200000U)
+    count++;
+
+    if (count > HAL_USB_TIMEOUT)
     {
       return HAL_TIMEOUT;
     }
@@ -1361,6 +1424,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
   */
 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
 {
+  HAL_StatusTypeDef ret = HAL_OK;
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t i;
 
@@ -1374,7 +1438,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
 
 
-  if ((USBx->CID & (0x1U << 8)) != 0U)
+  if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U)
   {
     if (cfg.speed == USBH_FSLS_SPEED)
     {
@@ -1394,41 +1458,32 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   }
 
   /* Make sure the FIFOs are flushed. */
-  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */
-  (void)USB_FlushRxFifo(USBx);
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
 
   /* Clear all pending HC Interrupts */
   for (i = 0U; i < cfg.Host_channels; i++)
   {
-    USBx_HC(i)->HCINT = 0xFFFFFFFFU;
+    USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK;
     USBx_HC(i)->HCINTMSK = 0U;
   }
 
-  /* Enable VBUS driving */
-  (void)USB_DriveVbus(USBx, 1U);
-
-  HAL_Delay(200U);
-
   /* Disable all interrupts. */
   USBx->GINTMSK = 0U;
 
   /* Clear any pending interrupts */
-  USBx->GINTSTS = 0xFFFFFFFFU;
-
-  if ((USBx->CID & (0x1U << 8)) != 0U)
-  {
-    /* set Rx FIFO size */
-    USBx->GRXFSIZ  = 0x200U;
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
-    USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
-  }
-  else
-  {
-    /* set Rx FIFO size */
-    USBx->GRXFSIZ  = 0x80U;
-    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);
-    USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);
-  }
+  USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
+  /* set Rx FIFO size */
+  USBx->GRXFSIZ  = 0x200U;
+  USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);
+  USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);
 
   /* Enable the common interrupts */
   if (cfg.dma_enable == 0U)
@@ -1441,7 +1496,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
                     USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \
                     USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);
 
-  return HAL_OK;
+  return ret;
 }
 
 /**
@@ -1454,7 +1509,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c
   *           HCFG_6_MHZ : Low Speed 6 MHz Clock
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1463,15 +1518,15 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
 
   if (freq == HCFG_48_MHZ)
   {
-    USBx_HOST->HFIR = 48000U;
+    USBx_HOST->HFIR = HFIR_48_MHZ;
   }
   else if (freq == HCFG_6_MHZ)
   {
-    USBx_HOST->HFIR = 6000U;
+    USBx_HOST->HFIR = HFIR_6_MHZ;
   }
   else
   {
-    /* ... */
+    return HAL_ERROR;
   }
 
   return HAL_OK;
@@ -1484,7 +1539,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)
   * @note (1)The application must wait at least 10 ms
   *   before clearing the reset bit.
   */
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1511,7 +1566,7 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
   *           1 : Activate VBUS
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   __IO uint32_t hprt0 = 0U;
@@ -1541,7 +1596,7 @@ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)
   *            @arg HCD_SPEED_FULL: Full speed mode
   *            @arg HCD_SPEED_LOW: Low speed mode
   */
-uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   __IO uint32_t hprt0 = 0U;
@@ -1555,7 +1610,7 @@ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)
   * @param  USBx  Selected device
   * @retval current frame number
   */
-uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1592,11 +1647,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
 {
   HAL_StatusTypeDef ret = HAL_OK;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t HCcharEpDir, HCcharLowSpeed;
+  uint32_t HCcharEpDir;
+  uint32_t HCcharLowSpeed;
   uint32_t HostCoreSpeed;
 
   /* Clear old interrupt conditions for this host channel. */
-  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;
+  USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK;
 
   /* Enable channel interrupts required for this transfer. */
   switch (ep_type)
@@ -1616,11 +1672,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
       }
       else
       {
-        if ((USBx->CID & (0x1U << 8)) != 0U)
-        {
-          USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
-                                                 USB_OTG_HCINTMSK_ACKM;
-        }
+        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |
+                                               USB_OTG_HCINTMSK_ACKM;
       }
       break;
 
@@ -1657,6 +1710,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
       break;
   }
 
+  /* Clear Hub Start Split transaction */
+  USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
+
+  /* Enable host channel Halt interrupt */
+  USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM;
+
   /* Enable the top level host channel interrupt. */
   USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);
 
@@ -1688,11 +1747,12 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
   USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |
                                       ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |
                                       (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |
-                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;
+                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) |
+                                      USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed;
 
-  if (ep_type == EP_TYPE_INTR)
+  if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC))
   {
-    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
+    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
   }
 
   return ret;
@@ -1716,53 +1776,113 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
   uint8_t  is_oddframe;
   uint16_t len_words;
   uint16_t num_packets;
-  uint16_t max_hc_pkt_count = 256U;
+  uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT;
 
-  if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))
+  /* in DMA mode host Core automatically issues ping in case of NYET/NAK */
+  if (dma == 1U)
   {
-    /* in DMA mode host Core automatically issues ping  in case of NYET/NAK */
-    if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))
+    if ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))
     {
+
       USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |
                                                USB_OTG_HCINTMSK_ACKM |
                                                USB_OTG_HCINTMSK_NAKM);
     }
-
-    if ((dma == 0U) && (hc->do_ping == 1U))
+  }
+  else
+  {
+    if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U))
     {
       (void)USB_DoPing(USBx, hc->ch_num);
       return HAL_OK;
     }
-
   }
 
-  /* Compute the expected number of packets associated to the transfer */
-  if (hc->xfer_len > 0U)
+  if (hc->do_ssplit == 1U)
   {
-    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
+    /* Set number of packet to 1 for Split transaction */
+    num_packets = 1U;
 
-    if (num_packets > max_hc_pkt_count)
+    if (hc->ep_is_in != 0U)
     {
-      num_packets = max_hc_pkt_count;
       hc->XferSize = (uint32_t)num_packets * hc->max_packet;
     }
+    else
+    {
+      if (hc->ep_type == EP_TYPE_ISOC)
+      {
+        if (hc->xfer_len > ISO_SPLT_MPS)
+        {
+          /* Isochrone Max Packet Size for Split mode */
+          hc->XferSize = hc->max_packet;
+          hc->xfer_len = hc->XferSize;
+
+          if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE))
+          {
+            hc->iso_splt_xactPos = HCSPLT_MIDDLE;
+          }
+          else
+          {
+            hc->iso_splt_xactPos = HCSPLT_BEGIN;
+          }
+        }
+        else
+        {
+          hc->XferSize = hc->xfer_len;
+
+          if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE))
+          {
+            hc->iso_splt_xactPos = HCSPLT_FULL;
+          }
+          else
+          {
+            hc->iso_splt_xactPos = HCSPLT_END;
+          }
+        }
+      }
+      else
+      {
+        if ((dma == 1U) && (hc->xfer_len > hc->max_packet))
+        {
+          hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+        }
+        else
+        {
+          hc->XferSize = hc->xfer_len;
+        }
+      }
+    }
   }
   else
   {
-    num_packets = 1U;
-  }
+    /* Compute the expected number of packets associated to the transfer */
+    if (hc->xfer_len > 0U)
+    {
+      num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);
 
-  /*
-   * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
-   * max_packet size.
-   */
-  if (hc->ep_is_in != 0U)
-  {
-    hc->XferSize = (uint32_t)num_packets * hc->max_packet;
-  }
-  else
-  {
-    hc->XferSize = hc->xfer_len;
+      if (num_packets > max_hc_pkt_count)
+      {
+        num_packets = max_hc_pkt_count;
+        hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+      }
+    }
+    else
+    {
+      num_packets = 1U;
+    }
+
+    /*
+    * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of
+    * max_packet size.
+    */
+    if (hc->ep_is_in != 0U)
+    {
+      hc->XferSize = (uint32_t)num_packets * hc->max_packet;
+    }
+    else
+    {
+      hc->XferSize = hc->xfer_len;
+    }
   }
 
   /* Initialize the HCTSIZn register */
@@ -1780,6 +1900,65 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
   USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
   USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;
 
+  if (hc->do_ssplit == 1U)
+  {
+    /* Set Hub start Split transaction */
+    USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) |
+                                        (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN;
+
+    /* unmask ack & nyet for IN/OUT transactions */
+    USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM |
+                                            USB_OTG_HCINTMSK_NYET);
+
+    if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U))
+    {
+      USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+      USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET;
+    }
+
+    if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) &&
+        (hc->do_csplit == 1U) && (hc->ep_is_in == 1U))
+    {
+      USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT;
+    }
+
+    /* Position management for iso out transaction on split mode */
+    if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U))
+    {
+      /* Set data payload position */
+      switch (hc->iso_splt_xactPos)
+      {
+        case HCSPLT_BEGIN:
+          /* First data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1;
+          break;
+
+        case HCSPLT_MIDDLE:
+          /* Middle data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos;
+          break;
+
+        case HCSPLT_END:
+          /* End data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0;
+          break;
+
+        case HCSPLT_FULL:
+          /* Entire data payload for OUT Transaction */
+          USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS;
+          break;
+
+        default:
+          break;
+      }
+    }
+  }
+  else
+  {
+    /* Clear Hub Start Split transaction */
+    USBx_HC((uint32_t)ch_num)->HCSPLT = 0U;
+  }
+
   /* Set host channel enable */
   tmpreg = USBx_HC(ch_num)->HCCHAR;
   tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
@@ -1801,7 +1980,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
     return HAL_OK;
   }
 
-  if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))
+  if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U))
   {
     switch (hc->ep_type)
     {
@@ -1847,7 +2026,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe
   * @param  USBx  Selected device
   * @retval HAL state
   */
-uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
+uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -1861,16 +2040,21 @@ uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)
   *         This parameter can be a value from 1 to 15
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t hcnum = (uint32_t)hc_num;
-  uint32_t count = 0U;
+  __IO uint32_t count = 0U;
   uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;
   uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;
+  uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31;
 
-  if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&
-      (ChannelEna == 0U))
+  /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels.
+     At the end of the next uframe/frame (in the worst case), the core generates a channel halted
+     and disables the channel automatically. */
+
+  if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) &&
+      ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR)))))
   {
     return HAL_OK;
   }
@@ -1886,10 +2070,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
       {
         USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
         USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-        USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
         do
         {
-          if (++count > 1000U)
+          count++;
+
+          if (count > 1000U)
           {
             break;
           }
@@ -1900,6 +2085,10 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
         USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
       }
     }
+    else
+    {
+      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+    }
   }
   else
   {
@@ -1909,10 +2098,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
     {
       USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
       USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
-      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
       do
       {
-        if (++count > 1000U)
+        count++;
+
+        if (count > 1000U)
         {
           break;
         }
@@ -1934,7 +2124,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)
   *         This parameter can be a value from 1 to 15
   * @retval HAL state
   */
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
   uint32_t chnum = (uint32_t)ch_num;
@@ -1960,16 +2150,24 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)
   */
 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
 {
+  HAL_StatusTypeDef ret = HAL_OK;
   uint32_t USBx_BASE = (uint32_t)USBx;
-  uint32_t count = 0U;
+  __IO uint32_t count = 0U;
   uint32_t value;
   uint32_t i;
 
   (void)USB_DisableGlobalInt(USBx);
 
-  /* Flush FIFO */
-  (void)USB_FlushTxFifo(USBx, 0x10U);
-  (void)USB_FlushRxFifo(USBx);
+  /* Flush USB FIFO */
+  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */
+  {
+    ret = HAL_ERROR;
+  }
+
+  if (USB_FlushRxFifo(USBx) != HAL_OK)
+  {
+    ret = HAL_ERROR;
+  }
 
   /* Flush out any leftover queued requests. */
   for (i = 0U; i <= 15U; i++)
@@ -1992,7 +2190,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
 
     do
     {
-      if (++count > 1000U)
+      count++;
+
+      if (count > 1000U)
       {
         break;
       }
@@ -2000,12 +2200,12 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
   }
 
   /* Clear any pending Host interrupts */
-  USBx_HOST->HAINT = 0xFFFFFFFFU;
-  USBx->GINTSTS = 0xFFFFFFFFU;
+  USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK;
+  USBx->GINTSTS = CLEAR_INTERRUPT_MASK;
 
   (void)USB_EnableGlobalInt(USBx);
 
-  return HAL_OK;
+  return ret;
 }
 
 /**
@@ -2013,7 +2213,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
   * @param  USBx Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -2031,7 +2231,7 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
   * @param  USBx Selected device
   * @retval HAL status
   */
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx)
 {
   uint32_t USBx_BASE = (uint32_t)USBx;
 
@@ -2042,7 +2242,6 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
 }
 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
-
 /**
   * @}
   */
@@ -2056,5 +2255,3 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)
 /**
   * @}
   */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h
index 5ee7cf7053..9cfe6a1b73 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -23,7 +22,7 @@
 
 #ifdef __cplusplus
 extern "C" {
-#endif
+#endif /* __cplusplus */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
@@ -38,18 +37,24 @@ extern "C" {
   */
 
 /* Exported types ------------------------------------------------------------*/
+#ifndef HAL_USB_TIMEOUT
+#define HAL_USB_TIMEOUT                                       0xF000000U
+#endif /* define HAL_USB_TIMEOUT */
+
+#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS
+#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS                           200U
+#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */
 
 /**
   * @brief  USB Mode definition
   */
-#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 
 typedef enum
 {
-  USB_DEVICE_MODE  = 0,
-  USB_HOST_MODE    = 1,
-  USB_DRD_MODE     = 2
-} USB_OTG_ModeTypeDef;
+  USB_DEVICE_MODE = 0,
+  USB_HOST_MODE   = 1,
+  USB_DRD_MODE    = 2
+} USB_ModeTypeDef;
 
 /**
   * @brief  URB States definition
@@ -62,7 +67,7 @@ typedef enum
   URB_NYET,
   URB_ERROR,
   URB_STALL
-} USB_OTG_URBStateTypeDef;
+} USB_URBStateTypeDef;
 
 /**
   * @brief  Host channel States  definition
@@ -72,52 +77,56 @@ typedef enum
   HC_IDLE = 0,
   HC_XFRC,
   HC_HALTED,
+  HC_ACK,
   HC_NAK,
   HC_NYET,
   HC_STALL,
   HC_XACTERR,
   HC_BBLERR,
   HC_DATATGLERR
-} USB_OTG_HCStateTypeDef;
+} USB_HCStateTypeDef;
+
 
 /**
   * @brief  USB Instance Initialization Structure definition
   */
 typedef struct
 {
-  uint32_t dev_endpoints;           /*!< Device Endpoints number.
+  uint8_t dev_endpoints;            /*!< Device Endpoints number.
                                          This parameter depends on the used USB core.
                                          This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
 
-  uint32_t Host_channels;           /*!< Host Channels number.
+  uint8_t Host_channels;            /*!< Host Channels number.
                                          This parameter Depends on the used USB core.
                                          This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
 
-  uint32_t speed;                   /*!< USB Core speed.
-                                         This parameter can be any value of @ref USB_Core_Speed                 */
+  uint8_t dma_enable;              /*!< USB DMA state.
+                                         If DMA is not supported this parameter shall be set by default to zero */
 
-  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */
+  uint8_t speed;                   /*!< USB Core speed.
+                                        This parameter can be any value of @ref PCD_Speed/HCD_Speed
+                                                                                (HCD_SPEED_xxx, HCD_SPEED_xxx) */
 
-  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
+  uint8_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */
 
-  uint32_t phy_itface;              /*!< Select the used PHY interface.
-                                         This parameter can be any value of @ref USB_Core_PHY                   */
+  uint8_t phy_itface;              /*!< Select the used PHY interface.
+                                        This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module  */
 
-  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
+  uint8_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */
 
-  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */
+  uint8_t low_power_enable;        /*!< Enable or disable the low Power Mode.                                  */
 
-  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
+  uint8_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */
 
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
+  uint8_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */
 
-  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
+  uint8_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */
 
-  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
+  uint8_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */
 
-  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
+  uint8_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */
 
-} USB_OTG_CfgTypeDef;
+} USB_CfgTypeDef;
 
 typedef struct
 {
@@ -130,29 +139,34 @@ typedef struct
   uint8_t   is_stall;             /*!< Endpoint stall condition
                                        This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
 
+  uint8_t   is_iso_incomplete;    /*!< Endpoint isoc condition
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+
   uint8_t   type;                 /*!< Endpoint type
-                                       This parameter can be any value of @ref USB_EP_Type_                     */
+                                       This parameter can be any value of @ref USB_LL_EP_Type                   */
 
   uint8_t   data_pid_start;       /*!< Initial data PID
                                        This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
 
+  uint32_t  maxpacket;            /*!< Endpoint Max packet size
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
+
+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
+
+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
+
   uint8_t   even_odd_frame;       /*!< IFrame parity
                                        This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
 
   uint16_t  tx_fifo_num;          /*!< Transmission FIFO number
                                        This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
 
-  uint32_t  maxpacket;            /*!< Endpoint Max packet size
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */
-
   uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */
 
-  uint32_t  xfer_len;             /*!< Current transfer length                                                  */
-
-  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */
-} USB_OTG_EPTypeDef;
+  uint32_t  xfer_size;            /*!< requested transfer size                                                  */
+} USB_EPTypeDef;
 
 typedef struct
 {
@@ -168,15 +182,21 @@ typedef struct
   uint8_t   ep_is_in;           /*!< Endpoint direction
                                      This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
 
-  uint8_t   speed;              /*!< USB Host speed.
-                                     This parameter can be any value of @ref USB_Core_Speed_                    */
+  uint8_t   speed;              /*!< USB Host Channel speed.
+                                     This parameter can be any value of @ref HCD_Device_Speed:
+                                                                             (HCD_DEVICE_SPEED_xxx)             */
 
   uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */
+  uint8_t   do_ssplit;          /*!< Enable start split transaction in HS mode.                                 */
+  uint8_t   do_csplit;          /*!< Enable complete split transaction in HS mode.                              */
+  uint8_t   ep_ss_schedule;     /*!< Enable periodic endpoint start split schedule .                            */
+  uint32_t  iso_splt_xactPos;   /*!< iso split transfer transaction position.                                   */
 
-  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */
+  uint8_t   hub_port_nbr;       /*!< USB HUB port number                                                        */
+  uint8_t   hub_addr;           /*!< USB HUB address                                                            */
 
   uint8_t   ep_type;            /*!< Endpoint Type.
-                                     This parameter can be any value of @ref USB_EP_Type_                       */
+                                     This parameter can be any value of @ref USB_LL_EP_Type                     */
 
   uint16_t  max_packet;         /*!< Endpoint Max packet size.
                                      This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
@@ -186,7 +206,7 @@ typedef struct
 
   uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */
 
-  uint32_t  XferSize;             /*!< OTG Channel transfer size.                                                   */
+  uint32_t  XferSize;           /*!< OTG Channel transfer size.                                                 */
 
   uint32_t  xfer_len;           /*!< Current transfer length.                                                   */
 
@@ -201,15 +221,21 @@ typedef struct
   uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */
 
   uint32_t  ErrCnt;             /*!< Host channel error count.                                                  */
+  uint32_t  NyetErrCnt;         /*!< Complete Split NYET Host channel error count.                              */
 
-  USB_OTG_URBStateTypeDef urb_state;  /*!< URB state.
-                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
+  USB_URBStateTypeDef urb_state;  /*!< URB state.
+                                       This parameter can be any value of @ref USB_URBStateTypeDef              */
 
-  USB_OTG_HCStateTypeDef state;       /*!< Host Channel state.
-                                            This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */
-} USB_OTG_HCTypeDef;
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+  USB_HCStateTypeDef state;       /*!< Host Channel state.
+                                       This parameter can be any value of @ref USB_HCStateTypeDef               */
+} USB_HCTypeDef;
 
+typedef USB_ModeTypeDef     USB_OTG_ModeTypeDef;
+typedef USB_CfgTypeDef      USB_OTG_CfgTypeDef;
+typedef USB_EPTypeDef       USB_OTG_EPTypeDef;
+typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef;
+typedef USB_HCStateTypeDef  USB_OTG_HCStateTypeDef;
+typedef USB_HCTypeDef       USB_OTG_HCTypeDef;
 
 /* Exported constants --------------------------------------------------------*/
 
@@ -237,18 +263,6 @@ typedef struct
   * @}
   */
 
-/** @defgroup USB_LL Device Speed
-  * @{
-  */
-#define USBD_HS_SPEED                          0U
-#define USBD_HSINFS_SPEED                      1U
-#define USBH_HS_SPEED                          0U
-#define USBD_FS_SPEED                          2U
-#define USBH_FSLS_SPEED                        1U
-/**
-  * @}
-  */
-
 /** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed
   * @{
   */
@@ -312,24 +326,14 @@ typedef struct
 /**
   * @}
   */
-
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
   * @{
   */
-#define EP_MPS_64                        0U
-#define EP_MPS_32                        1U
-#define EP_MPS_16                        2U
-#define EP_MPS_8                         3U
-/**
-  * @}
-  */
-
-/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
-  * @{
-  */
-#define EP_SPEED_LOW                           0U
-#define EP_SPEED_FULL                          1U
-#define EP_SPEED_HIGH                          2U
+#define EP_MPS_64                              0U
+#define EP_MPS_32                              1U
+#define EP_MPS_16                              2U
+#define EP_MPS_8                               3U
 /**
   * @}
   */
@@ -346,6 +350,40 @@ typedef struct
   * @}
   */
 
+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0U
+#define EP_SPEED_FULL                          1U
+#define EP_SPEED_HIGH                          2U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type
+  * @{
+  */
+#define HC_PID_DATA0                           0U
+#define HC_PID_DATA2                           1U
+#define HC_PID_DATA1                           2U
+#define HC_PID_SETUP                           3U
+/**
+  * @}
+  */
+
+/** @defgroup USB_LL Device Speed
+  * @{
+  */
+#define USBD_HS_SPEED                          0U
+#define USBD_HSINFS_SPEED                      1U
+#define USBH_HS_SPEED                          0U
+#define USBD_FS_SPEED                          2U
+#define USBH_FSLS_SPEED                        1U
+/**
+  * @}
+  */
+
+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
 /** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines
   * @{
   */
@@ -368,6 +406,16 @@ typedef struct
   * @}
   */
 
+/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines
+  * @{
+  */
+#define HFIR_6_MHZ                          6000U
+#define HFIR_60_MHZ                        60000U
+#define HFIR_48_MHZ                        48000U
+/**
+  * @}
+  */
+
 /** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines
   * @{
   */
@@ -383,29 +431,47 @@ typedef struct
 #define HCCHAR_BULK                            2U
 #define HCCHAR_INTR                            3U
 
-#define HC_PID_DATA0                           0U
-#define HC_PID_DATA2                           1U
-#define HC_PID_DATA1                           2U
-#define HC_PID_SETUP                           3U
-
 #define GRXSTS_PKTSTS_IN                       2U
 #define GRXSTS_PKTSTS_IN_XFER_COMP             3U
 #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U
 #define GRXSTS_PKTSTS_CH_HALTED                7U
 
+#define CLEAR_INTERRUPT_MASK          0xFFFFFFFFU
+
+#define HC_MAX_PKT_CNT                       256U
+#define ISO_SPLT_MPS                         188U
+
+#define HCSPLT_BEGIN                           1U
+#define HCSPLT_MIDDLE                          2U
+#define HCSPLT_END                             3U
+#define HCSPLT_FULL                            4U
+
+#define TEST_J                                 1U
+#define TEST_K                                 2U
+#define TEST_SE0_NAK                           3U
+#define TEST_PACKET                            4U
+#define TEST_FORCE_EN                          5U
+
 #define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)
 #define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)
 
 #define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))
-#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
-#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\
+                                                       + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\
+                                                        + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))
+
 #define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))
 
 #define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))
-#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
-#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\
+                                                        + USB_OTG_HOST_CHANNEL_BASE\
+                                                        + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))
+
 
 #define EP_ADDR_MSK                            0xFU
+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 /**
   * @}
   */
@@ -436,54 +502,55 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);
 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);
-HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
+HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed);
 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);
-HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);
-HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
+HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src,
                                   uint8_t ch_ep_num, uint16_t len, uint8_t dma);
 
-void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
-HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
-HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);
-HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);
+void             *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx);
 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
-uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
-uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx);
+uint32_t          USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum);
+uint32_t          USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);
 void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
 
 HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
-HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
-HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);
-uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);
-uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx);
+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx);
 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,
                               uint8_t epnum, uint8_t dev_address, uint8_t speed,
                               uint8_t ep_type, uint16_t mps);
 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,
                                    USB_OTG_HCTypeDef *hc, uint8_t dma);
 
-uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
-HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
+uint32_t          USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);
 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
-HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx);
 #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
 
 /**
@@ -505,9 +572,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);
 
 #ifdef __cplusplus
 }
-#endif
+#endif /* __cplusplus */
 
 
 #endif /* STM32H7xx_LL_USB_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c
index 00c397507e..8117ecb02d 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -251,6 +250,7 @@
 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
 static ErrorStatus UTILS_IsPLLsReady(void);
+static uint32_t    UTILS_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
 /**
   * @}
   */
@@ -523,7 +523,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitS
 
   /* Check VCO Output frequency */
 #ifdef  USE_FULL_ASSERT
-  vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
+  vcooutput_freq = UTILS_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
 #endif
   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
 
@@ -619,7 +619,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa
 
   /* Check VCO output frequency */
 #ifdef  USE_FULL_ASSERT
-  vcooutput_freq = LL_RCC_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
+  vcooutput_freq = UTILS_CalcPLLClockFreq(HSEFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1U);
 #endif
   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
 
@@ -927,7 +927,7 @@ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTIL
   assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
   assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
 
-  pllfreq = LL_RCC_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
+  pllfreq = UTILS_CalcPLLClockFreq(PLL_InputFrequency, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, UTILS_PLLInitStruct->PLLP);
 
   return pllfreq;
 }
@@ -966,6 +966,27 @@ static ErrorStatus UTILS_IsPLLsReady(void)
   return status;
 }
 
+/**
+  * @brief  Helper function to calculate the PLL frequency output
+  * @param  PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/CSI)
+  * @param  M      Between 1 and 63
+  * @param  N      Between 4 and 512
+  * @param  FRACN  Between 0 and 0x1FFF
+  * @param  PQR    VCO output divider (P, Q or R)
+  *                Between 1 and 128, except for PLL1P Odd value not allowed
+  * @retval PLL1 clock frequency (in Hz)
+  */
+static uint32_t UTILS_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR)
+{
+  float_t freq;
+
+  freq = ((float_t)PLLInputFreq / (float_t)M) * ((float_t)N + ((float_t)FRACN / (float_t)0x2000));
+
+  freq = freq / (float_t)PQR;
+
+  return (uint32_t)freq;
+}
+
 /**
   * @brief  Function to enable PLL and switch system clock to PLL
   * @param  SYSCLK_Frequency SYSCLK frequency
@@ -1071,4 +1092,3 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_
   * @}
   */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.h
index 28331487d3..41a5aa4ee8 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.h
@@ -3,6 +3,16 @@
   * @file    stm32h7xx_ll_utils.h
   * @author  MCD Application Team
   * @brief   Header file of UTILS LL module.
+  ******************************************************************************
+  * @attention
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
@@ -16,17 +26,6 @@
 
   @endverbatim
   ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
@@ -346,7 +345,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
   * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  Ticks Number of ticks
+  * @param  Ticks Frequency of Ticks (Hz)
   * @retval None
   */
 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
@@ -400,4 +399,3 @@ ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
 
 #endif /* STM32H7xx_LL_UTILS_H */
 
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_wwdg.h
index 489cf3ec50..eef033dd61 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_wwdg.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_wwdg.h
@@ -6,13 +6,12 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
   *
   ******************************************************************************
   */
@@ -327,5 +326,3 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
 #endif
 
 #endif /* STM32H7xx_LL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h
index afcfc24210..a37776edf7 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h
+++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h
@@ -49,7 +49,11 @@
 #define HAL_DMA2D_MODULE_ENABLED
 #define HAL_DTS_MODULE_ENABLED
 #define HAL_DSI_MODULE_ENABLED
-#define HAL_ETH_MODULE_ENABLED
+
+// Temporary: using legacy Ethernet driver for now
+// #define HAL_ETH_MODULE_ENABLED
+#define HAL_ETH_LEGACY_MODULE_ENABLED
+
 #define HAL_EXTI_MODULE_ENABLED
 #define HAL_FDCAN_MODULE_ENABLED
 #define HAL_FLASH_MODULE_ENABLED
@@ -436,6 +440,10 @@
   #include "stm32h7xx_hal_eth.h"
 #endif /* HAL_ETH_MODULE_ENABLED */
 
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
 #ifdef HAL_EXTI_MODULE_ENABLED
   #include "stm32h7xx_hal_exti.h"
 #endif /* HAL_EXTI_MODULE_ENABLED */
diff --git a/targets/TARGET_STM/TARGET_STM32H7/system_init_files/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/system_init_files/CMakeLists.txt
new file mode 100644
index 0000000000..2075b884f2
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/system_init_files/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Jamie Smith
+# SPDX-License-Identifier: Apache-2.0
+
+# Add correct system init file for each MCU.
+target_sources(mbed-stm32h7a3xiq INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h7b3xiq INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h723xg INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h725xe INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h735xg INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h743xi INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h750xb INTERFACE system_stm32h7xx_singlecore.c)
+target_sources(mbed-stm32h753xi INTERFACE system_stm32h7xx_singlecore.c)
+
+target_sources(mbed-stm32h745xi INTERFACE system_stm32h7xx_dualcore_boot_cm4_cm7.c)
+target_sources(mbed-stm32h747xi INTERFACE system_stm32h7xx_dualcore_boot_cm4_cm7.c)
\ No newline at end of file
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/targets/TARGET_STM/TARGET_STM32H7/system_init_files/system_stm32h7xx_dualcore_boot_cm4_cm7.c
similarity index 80%
rename from targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c
rename to targets/TARGET_STM/TARGET_STM32H7/system_init_files/system_stm32h7xx_dualcore_boot_cm4_cm7.c
index 8e0017de2a..027de42de2 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/system_init_files/system_stm32h7xx_dualcore_boot_cm4_cm7.c
@@ -25,13 +25,10 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * SPDX-License-Identifier: BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -49,9 +46,6 @@
   */
 
 #include "stm32h7xx.h"
-
-#if defined(DUAL_CORE)
-
 #include <math.h>
 
 #if !defined  (HSE_VALUE)
@@ -84,11 +78,48 @@
   */
 
 /************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+#if defined(CORE_CM4)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
-                                      This value must be a multiple of 0x200. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   D2_AXISRAM_BASE   /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BANK2_BASE  /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#elif defined(CORE_CM7)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
+/* #define VECT_TAB_SRAM */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   D1_AXISRAM_BASE   /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BANK1_BASE  /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#else
+#error Please #define CORE_CM4 or CORE_CM7
+#endif /* CORE_CM4 */
+#endif /* USER_VECT_TAB_ADDRESS */
 /******************************************************************************/
 
 /**
@@ -141,7 +172,7 @@
   * @param  None
   * @retval None
   */
-__weak void SystemInit (void)
+void SystemInit (void)
 {
   /* FPU settings ------------------------------------------------------------*/
   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
@@ -152,13 +183,13 @@ __weak void SystemInit (void)
      detectable by the CPU after a WFI/WFE instruction.*/
  SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
 
-#ifdef CORE_CM7
+#if defined(CORE_CM7)
   /* Reset the RCC clock configuration to the default reset state ------------*/
    /* Increasing the CPU frequency */
   if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
   }
 
   /* Set HSION bit */
@@ -167,14 +198,14 @@ __weak void SystemInit (void)
   /* Reset CFGR register */
   RCC->CFGR = 0x00000000;
 
-  /* Reset HSEON, HSECSSON, CSION, RC48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
   RCC->CR &= 0xEAF6ED7FU;
 
    /* Decreasing the number of wait states because of lower CPU frequency */
   if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
   }
 
   /* Reset D1CFGR register */
@@ -217,7 +248,6 @@ __weak void SystemInit (void)
   /* Enable CortexM7 HSEM EXTI line (line 78)*/
   EXTI_D2->EMR3 |= 0x4000UL;
 
-
   if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
   {
     /* if stm32h7 revY*/
@@ -237,9 +267,7 @@ __weak void SystemInit (void)
   SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED
 #endif
 
-#else
-#ifdef CORE_CM7
-
+#elif defined(CORE_CM7)
   /*
    * Disable the FMC bank1 (enabled after reset).
    * This, prevents CPU speculation access on this bank which blocks the use of FMC during
@@ -257,9 +285,7 @@ __weak void SystemInit (void)
 
 #else
 #error Please #define CORE_CM4 or CORE_CM7
-#endif
-#endif
-
+#endif /* CORE_CM4 */
 }
 
 /**
@@ -378,14 +404,13 @@ void SystemCoreClockUpdate (void)
   /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 
-#if defined(DUAL_CORE) && defined(CORE_CM4)
+#if defined(CORE_CM4)
   SystemCoreClock = SystemD2Clock;
 #else
   SystemCoreClock = common_system_clock;
-#endif /* DUAL_CORE && CORE_CM4 */
+#endif /* CORE_CM4 */
 }
 
-#endif   /* DUAL_CORE */
 
 /**
   * @}
@@ -398,4 +423,3 @@ void SystemCoreClockUpdate (void)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c b/targets/TARGET_STM/TARGET_STM32H7/system_init_files/system_stm32h7xx_singlecore.c
similarity index 88%
rename from targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c
rename to targets/TARGET_STM/TARGET_STM32H7/system_init_files/system_stm32h7xx_singlecore.c
index 69f4cea288..9a083df253 100644
--- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c
+++ b/targets/TARGET_STM/TARGET_STM32H7/system_init_files/system_stm32h7xx_singlecore.c
@@ -24,13 +24,10 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
   *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  * SPDX-License-Identifier: BSD-3-Clause
   *
   ******************************************************************************
   */
@@ -48,10 +45,6 @@
   */
 
 #include "stm32h7xx.h"
-
-
-#if !defined(DUAL_CORE)
-
 #include <math.h>
 
 #if !defined  (HSE_VALUE)
@@ -87,11 +80,29 @@
 /*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
 /* #define DATA_IN_D2_SRAM */
 
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
+/* Note: Following vector table addresses must be defined in line with linker
+         configuration. */
+/*!< Uncomment the following line if you need to relocate the vector table
+     anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
+     remap of boot address selected */
+/* #define USER_VECT_TAB_ADDRESS */
+
+#if defined(USER_VECT_TAB_ADDRESS)
+/*!< Uncomment the following line if you need to relocate your vector Table
+     in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
-                                      This value must be a multiple of 0x200. */
+#if defined(VECT_TAB_SRAM)
+#define VECT_TAB_BASE_ADDRESS   D1_AXISRAM_BASE   /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#else
+#define VECT_TAB_BASE_ADDRESS   FLASH_BANK1_BASE  /*!< Vector Table base address field.
+                                                       This value must be a multiple of 0x400. */
+#define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
+                                                       This value must be a multiple of 0x400. */
+#endif /* VECT_TAB_SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
 /******************************************************************************/
 
 /**
@@ -144,7 +155,7 @@
   * @param  None
   * @retval None
   */
-__weak void SystemInit (void)
+void SystemInit (void)
 {
 #if defined (DATA_IN_D2_SRAM)
  __IO uint32_t tmpreg;
@@ -160,7 +171,7 @@ __weak void SystemInit (void)
   if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
   }
 
   /* Set HSION bit */
@@ -176,7 +187,7 @@ __weak void SystemInit (void)
   if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
   {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
   }
 
 #if defined(D3_SRAM_BASE)
@@ -245,6 +256,7 @@ __weak void SystemInit (void)
 #else
   RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
 #endif /* RCC_AHB2ENR_D2SRAM3EN */
+
   tmpreg = RCC->AHB2ENR;
   (void) tmpreg;
 #endif /* DATA_IN_D2_SRAM */
@@ -392,8 +404,6 @@ void SystemCoreClockUpdate (void)
 #endif
 }
 
-#endif
-
 /**
   * @}
   */
@@ -405,4 +415,3 @@ void SystemCoreClockUpdate (void)
 /**
   * @}
   */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c
index e6cea7739d..e5a969f906 100644
--- a/targets/TARGET_STM/stm_spi_api.c
+++ b/targets/TARGET_STM/stm_spi_api.c
@@ -75,14 +75,6 @@
 /* Consider 10ms as the default timeout for sending/receving 1 byte */
 #define TIMEOUT_1_BYTE 10
 
-#if defined(SPI_FLAG_FRLVL) // STM32F0 STM32F3 STM32F7 STM32L4
-#if defined(STM32U5) || defined(STM32H5)
-extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
-#else
-extern HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
-#endif
-#endif
-
 #if defined(SPI_DATASIZE_17BIT) || defined(SPI_DATASIZE_18BIT) || defined(SPI_DATASIZE_19BIT) || defined(SPI_DATASIZE_20BIT) || \
     defined(SPI_DATASIZE_21BIT) || defined(SPI_DATASIZE_22BIT) || defined(SPI_DATASIZE_23BIT) || defined(SPI_DATASIZE_24BIT) || \
     defined(SPI_DATASIZE_25BIT) || defined(SPI_DATASIZE_26BIT) || defined(SPI_DATASIZE_27BIT) || defined(SPI_DATASIZE_28BIT) || \
diff --git a/targets/targets.json5 b/targets/targets.json5
index c37160277a..9a92265c64 100644
--- a/targets/targets.json5
+++ b/targets/targets.json5
@@ -3225,7 +3225,8 @@
         },
         "macros_add": [
             "EXTRA_IDLE_STACK_REQUIRED",
-            "MBED_TICKLESS"
+            "MBED_TICKLESS",
+            "DATA_IN_D2_SRAM" // Flag to HAL Layer to initialize clock for D2 SRAM on boot
         ],
         "overrides": {
             "lpticker_delay_ticks": 0,
diff --git a/targets/upload_method_cfg/NUCLEO_H723ZG.cmake b/targets/upload_method_cfg/NUCLEO_H723ZG.cmake
index 6552c0e385..3b7ad8a865 100644
--- a/targets/upload_method_cfg/NUCLEO_H723ZG.cmake
+++ b/targets/upload_method_cfg/NUCLEO_H723ZG.cmake
@@ -37,7 +37,7 @@ set(PYOCD_CLOCK_SPEED 4000k)
 
 set(OPENOCD_UPLOAD_ENABLED TRUE)
 set(OPENOCD_CHIP_CONFIG_COMMANDS
-    -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/nucleo_h72x.cfg)
+    -f ${CMAKE_CURRENT_LIST_DIR}/openocd_cfgs/stm32h72x.cfg)
 
 # Config options for STM32Cube
 # -------------------------------------------------------------